WO2002009165A1 - Work polishing method - Google Patents
Work polishing method Download PDFInfo
- Publication number
- WO2002009165A1 WO2002009165A1 PCT/JP2001/005971 JP0105971W WO0209165A1 WO 2002009165 A1 WO2002009165 A1 WO 2002009165A1 JP 0105971 W JP0105971 W JP 0105971W WO 0209165 A1 WO0209165 A1 WO 0209165A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- polishing
- wafer
- work
- film
- polished
- Prior art date
Links
- 238000005498 polishing Methods 0.000 title claims abstract description 127
- 238000000034 method Methods 0.000 title claims description 50
- 230000002093 peripheral effect Effects 0.000 claims abstract description 94
- 229920005989 resin Polymers 0.000 claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 23
- 239000004744 fabric Substances 0.000 claims abstract description 10
- 238000007517 polishing process Methods 0.000 claims abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052710 silicon Inorganic materials 0.000 claims description 34
- 239000010703 silicon Substances 0.000 claims description 34
- 238000010438 heat treatment Methods 0.000 claims description 13
- 238000004528 spin coating Methods 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 abstract description 131
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 239000011248 coating agent Substances 0.000 description 35
- 238000000576 coating method Methods 0.000 description 35
- 238000005229 chemical vapour deposition Methods 0.000 description 14
- 238000005530 etching Methods 0.000 description 12
- 238000007665 sagging Methods 0.000 description 10
- 239000003822 epoxy resin Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 239000002994 raw material Substances 0.000 description 5
- 238000006073 displacement reaction Methods 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 2
- IQVNEKKDSLOHHK-FNCQTZNRSA-N (E,E)-hydramethylnon Chemical compound N1CC(C)(C)CNC1=NN=C(/C=C/C=1C=CC(=CC=1)C(F)(F)F)\C=C\C1=CC=C(C(F)(F)F)C=C1 IQVNEKKDSLOHHK-FNCQTZNRSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004587 chromatography analysis Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
Definitions
- the present invention relates to a polishing technique for a circular work requiring a high flatness, and for example, to a polishing method for producing a mirror-polished wafer, which is highly flat to a peripheral portion of the wafer.
- semiconductor wafers used for device fabrication require extremely high flatness.
- a silicon wafer manufacturing method is obtained by a slicing step of slicing a single crystal ingot to obtain a thin disk-shaped wafer, and the slicing process.
- a slicing step of slicing a single crystal ingot to obtain a thin disk-shaped wafer, and the slicing process.
- ⁇ Chamfering process for chamfering the outer periphery to prevent cracking and chipping of the wafer
- ⁇ Rubbing process for flattening the wafer surface
- chamfering and rubbing From the etching process to remove the processing strain remaining on the wafer, the polishing process to make the surface of the wafer mirror, and the cleaning process to clean the polished wafer to remove the abrasive and foreign matter adhering to it. It is configured.
- the above steps show the main steps, and other steps such as a heat treatment step may be added or the order of the steps may be changed.
- the polishing process of mirroring the surface of the wafer is very important because it is the process of determining the final shape of the wafer, that is, the quality of the wafer.
- Some polishing machines are generally designed to combine rotation and orbit so that the momentum around the center of the work (the wafer) is equal to the momentum around the periphery.
- a workpiece W is held on a holding plate 16 attached to a rotating holder 11 by vacuum suction or the like.
- Abrasive cloth 15 is supplied onto polishing cloth 13 attached to surface plate 12 which is rotating from above, and polishing cloth 13 which rotates the surface of workpiece W (surface to be polished) 13 The surface is polished by applying a load to the surface while making sliding contact.
- a method of holding a work a method of providing a backing pad on the holding surface of a holding plate made of metal or the like to fix the work, or a method such as ceramics or glass
- a method of attaching a work to the holding plate via an adhesive or the like is also a method of attaching a work to the holding plate via an adhesive or the like.
- a silicon wafer is polished like this to make it a mirror surface wafer, but when a semiconductor device is manufactured by forming a circuit on the surface of the mirror surface wafer, one piece is used. It is desirable to obtain as many devices as possible from the wafer, and in order to achieve this, the wafer must be as flat as possible over the entire surface, especially near the outer edge. Is required. Specifically, in the current standard, it is sufficient that high flattening is performed in a region excluding a certain area (for example, 3 mm in outer circumference) from the outer edge of the wafer. There is a growing demand for wafers with high flatness in the area of 2 mm or even 1 mm from the part.
- FIG. 5 shows the change in the shape of the periphery of the wafer measured by the inventors after the primary polishing from the outer peripheral edge.
- a jig called a retainer ring that protrudes from the holding surface by the thickness of the eave from the holding surface is provided on the outer periphery of the holding plate.
- a method has been proposed in which a polishing cloth is submerged from the surface, or a method in which excessive polishing is suppressed by floating the peripheral portion of the anode using a small-diameter holding plate. I have. Further, a method in which a retainer ring and a small-diameter holding plate are combined as disclosed in Japanese Patent Application Laid-Open No. 8-257893 has been proposed.
- the peripheral sag can be slightly improved, but for example, the peripheral sag at a position 2 mm from the outer edge can be reduced to 0.2 / It is very difficult to keep it below m.
- the SFQR max of the surface reference is 0 ⁇ 15 / xm or less. ⁇ It was difficult to manufacture wafers stably.
- SFQR Site Frontrons-sQuares Range
- SFQR max represents the maximum value among SFQRs of all sites on the antenna. Disclosure of the invention
- the present invention has been made in view of the above-mentioned problems, and suppresses generation of peripheral sag when polishing a circular work requiring extremely precise flatness such as a semiconductor wafer.
- the surface-based SFQR max is extremely high, less than 0.15 / zm ⁇
- the aim is to produce a stable amount of ewa.
- the work in a method of holding a circular work with a holding plate and bringing the surface of the work into sliding contact with a polishing cloth for polishing, the work is polished by the work.
- a coat film made of a material having a low speed is formed at least on the peripheral portion of the workpiece surface, and the central portion of the workpiece surface is exposed or the workpiece surface is exposed more than the peripheral portion.
- the polishing of the peripheral portion of the work can be substantially delayed, and the peripheral portion can be polished. Can be prevented from being excessively polished and causing peripheral sagging.
- the coating film is formed on the workpiece, the workpiece surface can be stably highly planarized regardless of the structure of the holding plate or the like.
- the polishing method according to the present invention can be suitably applied when the work is a silicon wafer.
- a high flatness including a region within 2 mm from the outer peripheral end can be achieved.
- a wafer having a surface-based SFQR max force of 0.15 im or less can be stably manufactured.
- the coat film is formed on a peripheral portion within 10 mm from the outer peripheral edge of the surface of the wafer.
- the peripheral sag can be reliably suppressed. S can.
- a silicon oxide film, a silicon nitride film, or a resin film is formed as the coating film.
- Such a coating film has a polishing rate more moderate than that of a silicon wafer. Slowly, its speed can be controlled precisely, and it can be formed relatively easily around the wafer surface.
- the formation of the silicon oxide film or the silicon nitride film is performed at least by the CVD (Chemical Vapor Deposition) or thermal treatment. After an oxide film or a nitride film is formed on the surface of the wafer, the peripheral portion of the wafer surface is masked and subjected to an etching process, thereby forming a central portion of the wafer. The oxide film or nitride film can be removed to expose the work surface or make it thinner than the peripheral part.
- CVD Chemical Vapor Deposition
- a desired oxide film or nitride film can be easily formed on the peripheral portion of the wafer surface. .
- the resin film can be formed by applying the resin to a peripheral portion of the wafer surface by spin coating and then performing a heat treatment. .
- a drying heat treatment for evaporating the organic solvent is performed. Apply heat treatment such as curing heat treatment to cure the resin.
- a coat film according to the present invention is formed to form a work surface. By performing the polishing, it is possible to substantially suppress overpolishing of the peripheral portion of the work.
- the present invention is applied to polishing requiring very high flatness, such as a semiconductor wafer, there is no need to improve the structure of the holding plate, and the conventional holding plate can be used.
- ⁇ ⁇ Grinding while holding the wafer causes This achieves extremely high flatness over the entire surface up to the vicinity of the outer peripheral edge of the wafer, and also makes it possible to provide a mirror surface wafer with excellent surface characteristics.
- Such a mirror surface wafer can form a circuit on the entire surface, and can improve the productivity and yield of semiconductor devices.
- FIG. 1 is a schematic sectional view showing an example of a wafer before polishing on which a coating film according to the present invention has been formed.
- FIG. 2 is a schematic view showing a part of a step of forming a thermosetting resin film according to the present invention.
- Figure 3 is a graph showing the polishing rates for silicon wafers and various coating films.
- FIG. 4 is a graph showing the amount of displacement of the thickness of the peripheral portion of the wafer measured in the example and the comparative example.
- FIG. 5 is a schematic view showing an example of a wafer polishing apparatus.
- FIG. 6 is a graph showing the displacement of the thickness of the peripheral portion of the wafer after polishing by the conventional method.
- the polishing method according to the present invention can be applied to any polishing of thin circular workpieces requiring high flatness, but a silicon wafer is a preferred specific example. Will be described.
- silicon wafers are grown from a silicon raw material melt by the Chizoralski method (CZ method), floating zone melting method (FZ method), etc.
- CZ method Chizoralski method
- FZ method floating zone melting method
- the ingot is sliced, and the rough surface of the obtained wafer is removed.
- etching is performed to remove the processing distortion and the like on the wafer surface.
- surface grinding is performed instead of wrapping.
- the wafer that has undergone such a process is subjected to surface polishing in order to make the surface more flat and mirror-finished.
- the wafer is made of a material having a lower polishing rate than the wafer.
- the coating film is formed at least on the peripheral portion of the wafer surface, and is formed so that the wafer surface is exposed or thinner at the central portion of the wafer surface.
- the back surface of the wafer is held and the surface of the wafer is polished.
- a coat film made of a material having a low polishing rate is formed on at least a peripheral portion of the wafer surface, and then the surface is polished.
- the silicon around the wafer can be delayed from being polished.
- the silicon in the central portion is removed to some extent by polishing until the coat film in the peripheral portion of the wafer is removed, the silicon in the peripheral portion is removed. Substantial polishing is started. Therefore, even if the peripheral part of the wafer is removed at a higher polishing rate than the central part after the coat film is polished and removed, overpolishing of the peripheral part is prevented and generation of peripheral sag is suppressed. be able to.
- peripheral sagging can be suitably prevented.
- the coating film gradually thins from the outer edge to the center. It is even more preferable to form it so that it becomes more dense.
- the coating film formed by the present invention is not particularly limited as long as it is made of a work, that is, a silicon wafer or a material having a low polishing rate, but is not particularly limited.
- a silicon nitride film or a resin film is preferred.
- the polishing rate of these coat films is a fraction to several tenths of that of silicon, and polishing of the silicon around the wafer begins. This is advantageous in that it can be effectively delayed and can be formed relatively easily.
- the method of forming the silicon oxide film or the silicon nitride film is not particularly limited, but at least the oxide film or the nitride film is formed on the surface of the wafer by CVD or heat treatment. After the film is formed, the periphery of the wafer surface is masked and etched to form a silicon oxide film or a silicon nitride film on the wafer surface. It can be easily formed on the periphery.
- the raw material is subjected to a heat treatment in an oxidizing atmosphere to form a thermal oxide film on the entire surface of the wafer, and then a tape or a resist is formed around the periphery.
- a tape or a resist is formed around the periphery.
- the oxide film is formed only on the peripheral portion according to the same procedure as above.
- the CVD oxide film may be formed only on the peripheral portion by masking the central portion first and then performing CVD.
- the method for forming the resin film is not particularly limited, either.A resin solution diluted with an organic solvent is applied to the peripheral portion of the wafer surface by spin coating, followed by heat treatment. It can be easily formed.
- the resin is not particularly limited, but may be, for example, a thermosetting resin such as an epoxy resin.
- the wafer W is fixed on the turntable 2 so that the center thereof is located on the rotation axis 3.
- a thermosetting resin such as an epoxy resin dissolved in an appropriate solvent is applied to the periphery of the wafer through the supply nozzle 4 and then applied.
- the epoxy resin coat film 1 can be easily formed only on the periphery of the wafer.
- the resin is not limited to epoxy resin, and any resin can be used as long as it has a lower polishing rate than the work after curing.
- the coating film is formed so that the central portion of the wafer surface is exposed or thinner than the peripheral portion.
- the coating film 1 can be made thinner and the subsequent polishing time can be shortened. It is preferable because you can do it.
- a coating film on the portion other than the peripheral portion of the wafer surface, for example, on the back surface of the wafer, but also on the back surface 6 as shown in FIG. If the wafer W is polished by forming the coat film 1, excessive etching and dirt on the rear surface of the wafer due to an abrasive or the like can be prevented, and the rear surface of the wafer can be prevented. The occurrence of scratches due to holding can also be prevented. Such prevention of dirt and scratches is particularly effective when a resinous coating film is formed.
- the viscosity of the coating solution and the spin conditions are controlled.
- the resin may flow into the surface of the wafer, and this phenomenon can be used to form a coat film only on the peripheral part of the surface of the wafer. is there.
- PVB polyvinyl butyral
- the wafer shown in FIG. 1 is an example in which the coating film according to the present invention is formed, and is formed only on the peripheral portion of the wafer front surface or only on the peripheral portion of the wafer front and back surfaces.
- the coating film may be formed, and the work efficiency can be improved by reducing the portion where the coating film is formed as described above.
- the coat film remaining on the back surface or the chamfered portion is washed and removed using a solution capable of dissolving and removing the coat film. Alternatively, it may be removed by polishing to remove the coating film, etching, mirror polishing, or the like.
- a desired coat film can be easily formed by the above-described method, but the thickness of the coat film formed on the peripheral portion is as follows, for example. It can be determined by a simple method.
- tl TH / Rc
- the amount of the silicon removed in the central part during the time t1 The thickness TH of the coat film can be determined so that the thickness of the coat film coincides with the peripheral sag amount Y.
- the peripheral sag (Y;), the silicon polishing rate (Rsi), and the coating film polishing rate (Rc) are measured in advance, the peripheral part The thickness (TH) of the coating film can be easily determined.
- the polishing rate varies depending on the polishing conditions. However, according to the experiments performed by the present inventors, the polishing rate of the silicon itself was 0.6 to 0.6. When polishing is performed under normal polishing conditions of 7 / xmZ, the respective polishing rates are approximately as follows.
- Epoxy resin film 0.02 to 0.04 / im / min
- polishing conditions such as polishing pressure, or the conditions for forming the coating film.However, experiments should be performed in advance under the same conditions. Can be easily obtained with
- FIG. 3 shows the results of an experiment on the polishing rate performed by the present inventors.
- each coating film has a polishing rate of 1/10 or less as compared to silicon nano-electrode, which is higher than that of silicon. It is hard to be polished. Therefore, it is possible to delay polishing of the silicon in the peripheral portion only by coating thinly on the portion _ around the wafer, thereby effectively preventing peripheral dripping. Is out.
- the above formula for deriving the thickness of the coating film is merely an example, and the thickness of the coating film may be determined after rubbing or as described above.
- the shape of the wafer after polishing (raw material wafer), the overall polishing allowance, the material and manufacturing conditions of the coating film, the polishing conditions such as the abrasive used and the polishing pressure, or the surface of the abrasive to be polished In consideration of the change in hardness due to the doping amount of a dopant element such as boron or an impurity element such as nitrogen, the polishing rate may be determined in advance as appropriate, for example, by confirming the polishing rate by experiments.
- the coat film After the coat film is formed on the peripheral portion, it can be polished using a conventional holding plate as shown in FIG. That is, the wafer W is vacuum-sucked and held through the through-holes in the holding plate 16 provided with a large number of through-holes, and the abrasive 15 is supplied to the polishing cloth 13. Polish the wafer surface by sliding it against the polishing cloth 13 while applying a predetermined pressing force. By performing such polishing, in the initial stage of polishing, the center of the The silicon is directly polished in the part, while the coat film with a low polishing rate is polished in the peripheral part, so that the central part of the wafer becomes thin once.
- the silicon in the peripheral portion is polished at a higher polishing rate than the central portion, so that the thickness of the central portion and the peripheral portion eventually becomes almost equal. It is only necessary to finish polishing when it becomes the same.
- the polishing method of the present invention can be applied at any stage in the polishing process, the peripheral sag is almost always generated by the primary polishing, which has the largest polishing allowance. It can be suitably applied to primary polishing. Therefore, after the primary polishing is performed by the method of the present invention, the secondary polishing is performed as necessary, and the final polishing is further performed, so that a very high flatness is obtained over the entire surface. It is possible to obtain a mirror surface having the following characteristics.
- the present invention is not particularly limited with respect to the type of holding plate, the method of holding the wafer, and the like, and is also applicable to the case of polishing in a patch type. be able to. That is, the back surfaces of a plurality of wafers on which a desired coat film has been formed are adhered to a glass or ceramic plate via an adhesive or a wax. These wafers can be polished simultaneously.
- the silicon wafer polished by the polishing method of the present invention suppresses the generation of peripheral sag, becomes a mirror-finished wafer having excellent flatness over the entire surface of the wafer, and shows a good yield of the wafer. Can be improved. In particular, it has a very high flatness with a SFQR max of 0.15 ⁇ ⁇ or less, including the area within 2 mm from the outer edge. ⁇
- the wafer is stable regardless of the structure of the holding plate etc. It can be manufactured.
- a circuit can be formed over the entire surface, and the productivity and yield of semiconductor devices can be significantly improved. I can do it.
- the silicon wafer after etching (diameter: 8 inches (200 mm)) is formed by CVD to form a CVD oxide film on the surface of the wafer.
- CVD chemical vapor deposition
- the peripheral portion up to 5 mm from the outer peripheral edge of the anode was subjected to masking and etching treatment, and the central portion of the oxide film was removed to leave the CVD oxide film only in the peripheral portion.
- the thickness of the CVD oxide film was calculated by the HU notation formula, and the CVD oxide film was formed based on the calculated value.
- the polishing rate of silicon Rsi 0.6 ⁇ m
- the polishing rate of the coating film (CVD oxide film) Rc 0.1 ⁇ m
- the peripheral sagging Y Approximately 0.3 ⁇ (value obtained by polishing by the conventional method)
- Polishing equipment Vacuum adsorption type single wafer polishing equipment
- a silicon wafer of the same size as the wafer used in the embodiment was used.
- polishing was performed under the same polishing conditions as in Example 1 without forming a coat film.
- the thickness distribution of the peripheral portion was determined using a capacitance-type thickness measuring device with reference to a position 10 mm from the outer peripheral end. Excluded area: 2 mm around) was measured, and the results are shown in Fig. 4.
- the wafer polished in the embodiment achieves extremely high flatness up to the peripheral part, and the displacement amount is less than 0.1 ⁇ even at a position 2 mm from the outer peripheral edge.
- the SFQR max was 0.09 ⁇ , while the wafer polished in the comparative example (without coat film) improved more than the sag around the raw material anode.
- the sagging started around 6 mm from the outer edge of the target, and there was a displacement of about 0.3 m at 2 mm from the outer edge.
- SFQRmax was about 0.20 ⁇ .
- peripheral sagging had already occurred in the periphery of the raw material wafer measured in advance after the etching.
- the peripheral part of the wafer is thinner than the central part, although the polishing pressure is low and the polishing rate is low, if the polishing is further continued, the entire surface of the wafer is substantially polished under the same conditions (polishing rate), or the peripheral portion of the wafer is excessively polished. Therefore, when polishing is performed with a polishing allowance of about 10 ⁇ in the polishing process, a new peripheral sag as shown in FIG. 6 is generated.
- the present invention is not limited to the above embodiment.
- the above embodiment is merely an example, and has substantially the same configuration as the technical idea described in the claims of the present invention, and achieves the same operation and effect. Anything is included in the technical scope of the present invention.
- the object to be polished to which the present invention can be applied is not limited to the silicon wafer, and high flatness of the entire surface is required. It can be applied to the required polishing of circular workpieces.
- the present invention is not particularly limited with respect to the size of the work.
- the method of controlling the thickness of the coat film is controlled so as to attain a high flatness after one step of polishing.
- the final step is performed. It is necessary to have high flatness after perfect finish polishing.
- the present invention is optimally used in primary polishing where peripheral sagging is most likely to occur.
- subsequent polishing such as secondary polishing or finish polishing, may cause some sagging around the periphery. Therefore, the thickness of the coating film must be adjusted so that the first polishing completely achieves high flatness.
- polishing may be performed by controlling the thickness of the film. That is, the present invention may be used so that a wafer with high flatness is obtained in a final product.
- a coat film as in the present invention may be formed and polished at each polishing step.
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
A method of polishing a circular work by bringing the front surface of the work into slidable contact with an abrasive cloth in the state of the work being held by a holding plate, characterized by comprising the steps of forming a coat film formed of a material having a slower polishing rate than that of the material of the work around the periphery of the front surface of the work and forming at the center portion on the front surface of the work so that the front surface of the work is exposed or the coat film is formed thinner than that around the periphery thereof, holding the rear surface of the work, and polishing the front surface of the work, wherein, desirably, a silicon oxide film, a silicon nitride film, or a resin film should be formed as the coat film, whereby, because peripheral sags can be prevented from occurring when the circular work requiring a very precise flatness such as a semiconductor wafer is polished, the wafers having such a very high flatness that the SFQR max. of a surface reference is 0.15 νm or below can be manufactured stably in the areas including an area within 2 mm from the outer peripheral end part thereof.
Description
明 細 書 ワ ー ク の研磨方法 技術分野 Description Workpiece polishing method Technical field
本発明 は、 高い平坦度が要求 され る 円形状ワ ー ク の研磨技術に関 し、 例えば、 鏡面研磨ゥエーハ を製造す る際、 ゥエーハの周辺部分 まで高平坦化する研磨方法に関する。 背景技術 The present invention relates to a polishing technique for a circular work requiring a high flatness, and for example, to a polishing method for producing a mirror-polished wafer, which is highly flat to a peripheral portion of the wafer. Background art
薄い円形状の ワーク の中でも 、 デバイ ス作製に使用 される半導体 ゥエーハは、 非常に高い平坦度が要求されている。 Among thin circular workpieces, semiconductor wafers used for device fabrication require extremely high flatness.
一般にシ リ コ ンゥエーハの製造方法は、 単結晶イ ンゴッ ト をス ラ イ ス し て薄円板状の ゥエーハを得る ス ラ イ ス工程 と 、 該ス ラ イ ス ェ 程に よ っ て得 られた ゥエーハの割れ、 欠 けを防止する ため にその外 周部を面取 り する面取 り 工程と 、 ゥ エーハ表面を平坦化する ラ ツ ビ ング工程と 、 面取 り 及びラ ッ ビ ング されたゥエーハに残留する加工 歪を除去するエ ッチング工程と 、 ゥエーハ表面を鏡面化する研磨ェ 程と 、 研磨 された ゥエーハを洗浄してこれに付着 した研磨剤や異物 を除去する洗浄工程な どか ら構成 さ れている。 上記工程は、 主なェ 程を示 した も の で、 他に熱処理工程等が加わっ た り 、 工程順が入れ 換え られた り する。 In general, a silicon wafer manufacturing method is obtained by a slicing step of slicing a single crystal ingot to obtain a thin disk-shaped wafer, and the slicing process.ゥ Chamfering process for chamfering the outer periphery to prevent cracking and chipping of the wafer; ラ Rubbing process for flattening the wafer surface; chamfering and rubbing. From the etching process to remove the processing strain remaining on the wafer, the polishing process to make the surface of the wafer mirror, and the cleaning process to clean the polished wafer to remove the abrasive and foreign matter adhering to it. It is configured. The above steps show the main steps, and other steps such as a heat treatment step may be added or the order of the steps may be changed.
上記工程の 中でも ゥエーハ表面を鏡面化する研磨工程は、 ゥエー ハの最終形状、 言わば品質を決定す る工程であ る ため非常に重要で あ り 、 通常、 1 次研磨 と仕上げ研磨、 さ ら に必要に応 じて仕上げ研 磨前に 2 次研磨を行 う な ど、 複数の段階に分けて研磨を行っ てい る シ リ コ ンゥエーハの研磨の よ う に円形状ワーク を研磨する際に用
いる研磨装置は、 ワー ク ( ゥエ ーハ) の 中心 と周辺の運動量を同等 にする よ う に一般的に 自 転公転を組み合わせる よ う に設計 されてい る。 Among the above processes, the polishing process of mirroring the surface of the wafer is very important because it is the process of determining the final shape of the wafer, that is, the quality of the wafer. Used for polishing circular workpieces, such as silicon wafers, which are divided into multiple stages, such as secondary polishing before final polishing, if necessary. Some polishing machines are generally designed to combine rotation and orbit so that the momentum around the center of the work (the wafer) is equal to the momentum around the periphery.
例えば図 5 で示 される よ う に、 回転自 在のホルダ 1 1 に取 り 付け られる保持板 1 6 に真空吸着等によ り ワ ー ク Wを保持し、 研磨剤供 給装置 1 4 か ら回転自 在な定盤 1 2 に貼 り 付けた研磨布 1 3 上に研 磨剤 1 5 を供給する と と も に、 ワー ク Wの表面 (被研磨面) を回転 する研磨布 1 3 に対 して荷重を掛けなが ら摺接させる こ と に よ り 表 面研磨が行われる。 For example, as shown in FIG. 5, a workpiece W is held on a holding plate 16 attached to a rotating holder 11 by vacuum suction or the like. Abrasive cloth 15 is supplied onto polishing cloth 13 attached to surface plate 12 which is rotating from above, and polishing cloth 13 which rotates the surface of workpiece W (surface to be polished) 13 The surface is polished by applying a load to the surface while making sliding contact.
なお、 ワーク を保持する方法 と しては、 金属等の保持板の保持面 にバ ッ キ ングパ ッ ト を設けてワ ーク を固定する方法、 あるいはセ ラ ミ ッ ク スやガラ ス等の保持板に接着剤ゃヮ ッ ク ス等を介して ワー ク を.貼 り 付ける方法な ども あ る。 In addition, as a method of holding a work, a method of providing a backing pad on the holding surface of a holding plate made of metal or the like to fix the work, or a method such as ceramics or glass There is also a method of attaching a work to the holding plate via an adhesive or the like.
シ リ コ ンゥエ ー ノヽはこ の よ う に研磨する こ と で鏡面ゥエ ーハ と さ れる が、 鏡面 ゥエ ーハの表面に回路 を形成 させて半導体デバイ ス を 作製する場合、 1 枚の ゥエ ー ハから極力多 く のデバイ スを得る こ と が望ま し く 、 そのため には ゥェ一ハ全面、 特に外周端部近 く ま で極 力フ ラ ッ ト な形状 と する こ と が要求 される。 具体的に言えば、 現状 の規格ではゥエ ー ハ外周端部か ら一定の領域 (例えば外周 3 m m ) を除いた領域で高平坦化がな されていればよ いが、 近年、 外周端部 から 2 m m、 更には 1 m mまでの領域で高平坦度であ る ゥエ ーハが 要望されつつあ る。 A silicon wafer is polished like this to make it a mirror surface wafer, but when a semiconductor device is manufactured by forming a circuit on the surface of the mirror surface wafer, one piece is used. It is desirable to obtain as many devices as possible from the wafer, and in order to achieve this, the wafer must be as flat as possible over the entire surface, especially near the outer edge. Is required. Specifically, in the current standard, it is sufficient that high flattening is performed in a region excluding a certain area (for example, 3 mm in outer circumference) from the outer edge of the wafer. There is a growing demand for wafers with high flatness in the area of 2 mm or even 1 mm from the part.
し力、 しな 力 S ら 、 図 5 に示したよ う にゥエ ーハを研磨した場合、 ゥ ェ ー ハ表面の中央部分よ り も 周辺部分の方が よ り 新 しい研磨剤に触れ る こ と 等の種々 の要因 に よ り 、 ゥエーハ周辺部分が過剰に研磨されて いわゆる周辺ダレが生じる問題があった。 図 6 は、 一次研磨後に本発 明者 ら が測定した ゥエ ーハの周辺部分の形状変化を外周端部か ら 1 When the wafer is polished as shown in Fig. 5, the peripheral part touches the new abrasive more than the central part of the wafer surface. Due to various factors such as these, there was a problem that the periphery of the wafer was excessively polished and so-called peripheral sagging occurred. Figure 6 shows the change in the shape of the periphery of the wafer measured by the inventors after the primary polishing from the outer peripheral edge.
O ra mの位置を基準に して示したグラ フ であ り 、 ゥエ ーハ外周端部
から 6 m m前後の位置から いわゆ る 周辺ダ レが生 じている。 こ の よ う な周辺ダ レは ゥ ユーハの径に よ らず外周端部か ら 6 m m前後の位 置から始ま る こ と が多い。 Graph shown with reference to the Oram position. So-called sagging occurs around 6 mm from the center. Such peripheral sagging often starts at a position about 6 mm from the outer peripheral edge regardless of the diameter of the ハ uha.
周辺ダ レを抑制する方法 と しては、 例 えば、 保持板の外周 に保持 面よ り ゥエーハの厚 さ分だけ突出す る リ テーナ リ ング と 呼ばれる治 具を設け、 研磨中、 ゥエーハ外周部か ら研磨布を沈み込ませた り 、 あるいは ゥエ ー ノヽ ょ り 小径の保持板を用 いて ゥエ ー ノヽの周辺部分を 浮かせる こ と で過剰な研磨を抑 え る方法等が提案 されている。 さ ら に、 特開平 8 — 2 5 7 8 9 3 号の よ う に リ テーナ リ ングと 小径保持 板を組み合わせた方法も提案されている。 As a method of suppressing the peripheral sag, for example, a jig called a retainer ring that protrudes from the holding surface by the thickness of the eave from the holding surface is provided on the outer periphery of the holding plate. For example, a method has been proposed in which a polishing cloth is submerged from the surface, or a method in which excessive polishing is suppressed by floating the peripheral portion of the anode using a small-diameter holding plate. I have. Further, a method in which a retainer ring and a small-diameter holding plate are combined as disclosed in Japanese Patent Application Laid-Open No. 8-257893 has been proposed.
こ の よ う に保持板の構造等を工夫する こ と によ り 周辺ダレは多少 改善される が、 それでも例えば外周端部カゝ ら 2 m mの位置におけ る 周辺ダ レを 0 . 2 / m以下に抑 え る こ と は大変難 しい。 特に、 近年 の半導体デパイ ス の高集積化が進み、 前記 したよ う に ゥエーハ全面 にわたつ て高い平坦度が要求さ れている が、 表面基準の S F Q R m a x が 0 · 1 5 /x m以下の ゥエ ーハを安定して製造する こ と は困難 であっ た。 By devising the structure of the holding plate in this way, the peripheral sag can be slightly improved, but for example, the peripheral sag at a position 2 mm from the outer edge can be reduced to 0.2 / It is very difficult to keep it below m. In particular, as the integration of semiconductor devices in recent years progresses, and as described above, high flatness is required over the entire surface of the wafer, the SFQR max of the surface reference is 0 · 15 / xm or less.ゥ It was difficult to manufacture wafers stably.
なお、 S F Q R ( S i t e F r o n t l e a s t - s Q u a r e s R a n g e ) と は、 平坦度に関 して表面基準の平均平面 を サイ ト毎に算出 し、 その面に対する 凹凸の最大範囲を表 した値であ り 、 S F Q R m a x と は、 ゥエ ー ノヽ上の全サイ ト の S F Q Rの 中の 最大値を表している。 発明の開示 Note that SFQR (Site Frontrons-sQuares Range) is a value that calculates the average plane of the surface reference for each site for flatness and expresses the maximum range of unevenness with respect to that surface. Therefore, SFQR max represents the maximum value among SFQRs of all sites on the antenna. Disclosure of the invention
本発明 は上記問題点に鑑みてな さ れた も の で、 半導体ゥエーハ等 の非常に精密な平坦度が要求さ れる 円形状ワ ー ク を研磨する際、 周 辺ダ レの発生を抑制 し、 特に、 外周端部から 2 m m以内の領域を含 め、 表面基準の S F Q R m a x が 0 . 1 5 /z m以下の非常に高い平
坦度を有す る ゥエーハを安定して製造する こ と を 目 的 とする。 The present invention has been made in view of the above-mentioned problems, and suppresses generation of peripheral sag when polishing a circular work requiring extremely precise flatness such as a semiconductor wafer. In particular, including the area within 2 mm from the outer edge, the surface-based SFQR max is extremely high, less than 0.15 / zm ゥ The aim is to produce a stable amount of ewa.
前記 目 的を達成する ため、 本発明 によ れば、 円形状 ワーク を保持 板で保持 し、 該ワー ク の表面を研磨布に摺接 させて研磨する方法に おいて、 前記ワーク よ り 研磨速度が遅い材質から なる コ ー ト 膜を、 少な く と も 前記ワーク表面の周辺部分に形成 させる と と も に該ヮー ク 表面の 中央部分ではワー ク表面が露出する かま たは周辺部分よ り 薄く な る よ う に形成 させ、 前記ワー ク の裏面 を保持してワー ク 表面 の研磨を行 う こ と を特徴と する ワ ー ク の研磨方法が提供される。 To achieve the above object, according to the present invention, in a method of holding a circular work with a holding plate and bringing the surface of the work into sliding contact with a polishing cloth for polishing, the work is polished by the work. A coat film made of a material having a low speed is formed at least on the peripheral portion of the workpiece surface, and the central portion of the workpiece surface is exposed or the workpiece surface is exposed more than the peripheral portion. There is provided a method of polishing a work, characterized in that the work is polished so as to be thin, and the work surface is polished while holding the back surface of the work.
こ の よ う にコー ト膜を形成 させた上で研磨を行 う こ と に よ り 、 ヮ ーク の周辺部分が研磨 される の を実質的に遅 らせる こ と ができ 、 周 辺部分が過剰に研磨されて周辺ダレが生 じる のを防ぐ こ と ができ る 。 ま た、 ワーク に コー ト膜を形成さ せる の で、 保持板等の構造に関 係.無く 、 安定してヮ "ク表面 を高度に平坦化する こ と ができ る。 By performing the polishing after forming the coating film in this manner, the polishing of the peripheral portion of the work can be substantially delayed, and the peripheral portion can be polished. Can be prevented from being excessively polished and causing peripheral sagging. In addition, since the coating film is formed on the workpiece, the workpiece surface can be stably highly planarized regardless of the structure of the holding plate or the like.
本発明 にかかる研磨方法は、 前記 ワー ク が、 シ リ コ ンゥエーハで あ る場合に好適に適用する こ と ができ る。 The polishing method according to the present invention can be suitably applied when the work is a silicon wafer.
特に高平坦度が要求 される シ リ コ ンゥエーハの研磨工程において 本発明 にかかる研磨方法を適用すれば、 外周端部から 2 m m以内の 領域を含めて高い平坦度を達成する こ と ができ 、 例えば表面基準の S F Q R m a x 力 0 . 1 5 i m以下の ゥェ一ハを安定 して製造する こ と ができ る。 In particular, when the polishing method according to the present invention is applied in a polishing process of a silicon wafer which requires a high flatness, a high flatness including a region within 2 mm from the outer peripheral end can be achieved. For example, a wafer having a surface-based SFQR max force of 0.15 im or less can be stably manufactured.
こ の場合、 コー ト膜を、 ゥエーハの表面の外周端部から 1 0 m m 以内の周辺部分に形成 させる こ と が好ま しい。 In this case, it is preferable that the coat film is formed on a peripheral portion within 10 mm from the outer peripheral edge of the surface of the wafer.
こ の よ う にゥエーノヽの表面の外周端部力、 ら 1 O m m以内の周辺部 分にコ ー ト 膜を形成させて研磨を行えば、 周辺ダ レを確実に抑制す る こ と 力 Sでき る。 As described above, if a coat film is formed on the periphery of the surface of the ゥ NOE ヽ and the peripheral portion within 1 Omm is polished, the peripheral sag can be reliably suppressed. S can.
前記コー ト膜と して、 シ リ コ ン酸化膜、 シ リ コ ン窒化膜ま たは樹 脂膜を形成 させる こ と が好ま しい。 It is preferable that a silicon oxide film, a silicon nitride film, or a resin film is formed as the coating film.
こ の よ う な コー ト膜は、 研磨速度がシ リ コ ンゥェ一ハよ り 適度に
遅 く 、 その速度 も精密にコ ン ト ロールでき る上に、 ゥェ一ハ表面の 周辺部分に比較的容易に形成 させる こ と ができ る。 Such a coating film has a polishing rate more moderate than that of a silicon wafer. Slowly, its speed can be controlled precisely, and it can be formed relatively easily around the wafer surface.
前記シ リ コ ン酸化膜またはシ リ コ ン窒化膜の形成は、 C V D ( C h e m i c a 丄 v a p o r d e p o s i t i o n : ィ匕学的気†目 成長) ま たは熱処理に よ っ て少な く と も 前記 ゥエ ーハ表面に酸化膜 または窒化膜を形成 させた後、 該ゥエ ーハ表面の周辺部分をマ ス キ ング してエ ッチ ング処理する こ と に よ り 該ゥエ ーハの中央部分の酸 化膜ま たは窒化膜を除去し、 ワーク 表面を露出、 又は周辺部分よ り 薄く する こ と 力 sでき る。 The formation of the silicon oxide film or the silicon nitride film is performed at least by the CVD (Chemical Vapor Deposition) or thermal treatment. After an oxide film or a nitride film is formed on the surface of the wafer, the peripheral portion of the wafer surface is masked and subjected to an etching process, thereby forming a central portion of the wafer. The oxide film or nitride film can be removed to expose the work surface or make it thinner than the peripheral part.
こ の よ う に C V D ま たは熱処理 と 、 エ ッチ ング処理を組み合わせ る こ と で ゥエ ーハ表面の周辺部分に所望の酸化膜または窒化膜を容 易に形成 させる こ と ができ る。 By combining the CVD or heat treatment with the etching process, a desired oxide film or nitride film can be easily formed on the peripheral portion of the wafer surface. .
.また、 前記樹脂膜の形成は、 ス ピ ンコ ーテ ィ ングによ っ て前記 ゥ エーハ表面の周辺部分に前記樹脂を塗布 した後、 熱処理する こ と に よ り 行 う こ と カ でき る。 Further, the resin film can be formed by applying the resin to a peripheral portion of the wafer surface by spin coating and then performing a heat treatment. .
つま り 、 有機溶媒に溶解 させた樹脂や熱硬化性樹脂をス ピ ン コ ー テ ィ ングによ っ て ゥエ ーハ表面の周辺部分に塗布 した後、 有機溶媒 を蒸発 さ せる乾燥熱処理や樹脂 を硬化させる硬化熱処理な どの熱処 理を施す。 こ の よ う にス ピ ン コ ーテ ィ ング と熱処理を組み合わせる こ と で、 ゥエーハ表面の周辺部分に所望の樹脂膜を容易に形成 さ せ る こ と カ でき る'。 In other words, after a resin or a thermosetting resin dissolved in an organic solvent is applied to the peripheral portion of the wafer surface by spin coating, a drying heat treatment for evaporating the organic solvent is performed. Apply heat treatment such as curing heat treatment to cure the resin. By combining spin coating and heat treatment in this way, it is possible to easily form a desired resin film on the periphery of the wafer surface '.
以上説明 した よ う に、 半導体 ゥエ ーハ等の非常に高い平坦度が要 求 される 円形状ワーク を研磨す る際、 本発明 に係る コ 一 ト膜を形成 させて力 ら ワー ク表面の研磨を行 う こ と によ り 、 ワーク の周辺部分 の過研磨を実質的に抑制する こ と ができ る。 As described above, when polishing a circular work requiring extremely high flatness, such as a semiconductor wafer, a coat film according to the present invention is formed to form a work surface. By performing the polishing, it is possible to substantially suppress overpolishing of the peripheral portion of the work.
特に、 半導体ゥエ ーハの よ う な非常に高い平坦度が要求 される研 磨に本発明を適用すれば、 保持板の構造等を改良する必要が無 く 、 従来の保持板を用いて ゥエ ーハを保持して研磨する こ と で周辺ダ レ
を防ぎ、 ゥエーハ外周端部近 く まで表面全体にわたっ て非常に高い 平坦度が達成 される上、 表面特性に優れた鏡面ゥエ ーハ とする こ と ができ る。 こ の よ う な鏡面 ゥエ ーハは、 表面全体に回路を形成 さ せ る こ と ができ 、 半導体デパ イ ス の生産性及び歩留 り を向上させる こ と ができ る。 図面の簡単な説明 In particular, if the present invention is applied to polishing requiring very high flatness, such as a semiconductor wafer, there is no need to improve the structure of the holding plate, and the conventional holding plate can be used.周 辺 Grinding while holding the wafer causes This achieves extremely high flatness over the entire surface up to the vicinity of the outer peripheral edge of the wafer, and also makes it possible to provide a mirror surface wafer with excellent surface characteristics. Such a mirror surface wafer can form a circuit on the entire surface, and can improve the productivity and yield of semiconductor devices. BRIEF DESCRIPTION OF THE FIGURES
図 1 は、 本発明に係る コー ト 膜が形成 された研磨前の ゥエーハの 一例を示す概略断面図であ る。 FIG. 1 is a schematic sectional view showing an example of a wafer before polishing on which a coating film according to the present invention has been formed.
図 2 は、 本発明に係る熱硬化樹脂膜を形成 させる工程の一部を示 す概略図であ る。 FIG. 2 is a schematic view showing a part of a step of forming a thermosetting resin film according to the present invention.
図 3 は、 シ リ コ ン ゥエ ーハ と 各種コ ー ト膜の研磨速度を示すグラ フであ る。 Figure 3 is a graph showing the polishing rates for silicon wafers and various coating films.
図 4 は、 実施例、 比較例で測定した ゥエ ーハの周辺部分の厚 さ の 変位量を示すグラ フである。 FIG. 4 is a graph showing the amount of displacement of the thickness of the peripheral portion of the wafer measured in the example and the comparative example.
図 5 は、 ゥエ ーハの研磨装置の一例を示す概略図であ る。 FIG. 5 is a schematic view showing an example of a wafer polishing apparatus.
図 6 は、 従来の方法に よ る研磨後の ゥエ ーハの周辺部分の厚 さ の 変位量を示すグ ラ フ である。 発明を実施するための最良の形態 FIG. 6 is a graph showing the displacement of the thickness of the peripheral portion of the wafer after polishing by the conventional method. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施の形態について図面を参照 しなが ら さ ら に具 体的に説明する が、 本発明 はこれ ら に限定される も の ではない。 Hereinafter, embodiments of the present invention will be described more specifically with reference to the drawings, but the present invention is not limited thereto.
なお、 本発明 に係 る研磨方法は、 高い平坦度が要求 される薄板の 円形状ワーク を研磨する場合であれば全てに適用 でき る が、 好適な 具体例 と してシ リ コ ンゥエ ーハを研磨する場合について説明する。 The polishing method according to the present invention can be applied to any polishing of thin circular workpieces requiring high flatness, but a silicon wafer is a preferred specific example. Will be described.
シ リ コ ン ゥ エ ーハ を製造する場合、 チ ヨ ク ラ ルス キー法 ( C Z 法 )、 浮遊帯域溶融法 ( F Z 法) 等に よ り シ リ コ ン の原料融液か ら 成 長 させたイ ン ゴ ッ ト をス ラ イ ス し、 得られた ゥエーハの粗面取 り と
ラ ッ ビ ングを行っ た後、 ゥエーハ表面の加工歪等を除去する ため、 エ ッチ ングが行われる。 なお、 ラ ッ ピングに代えて平面研削 を行 う 場合も あ る。 When manufacturing silicon wafers, silicon wafers are grown from a silicon raw material melt by the Chizoralski method (CZ method), floating zone melting method (FZ method), etc. The ingot is sliced, and the rough surface of the obtained wafer is removed. After performing the rubbing, etching is performed to remove the processing distortion and the like on the wafer surface. In some cases, surface grinding is performed instead of wrapping.
こ の よ う な工程を経た ゥエーハは、 表面を よ り 平坦化及び鏡面化 する ため に表面研磨が施 さ れる が、 本発明では、 まず、 前記 ゥエー ハよ り 研磨速度が遅い材質から な る コー ト膜を、 少な く と も 前記 ゥ エーハ表面の周辺部分に形成させる と と も に該ゥエーハ表面の中央 部分では ゥエーハ表面が露出する かまたは周辺部分よ り 薄 く な る よ う に形成 させ、 次いで、 前記ゥエーハの裏面 を保持 して ゥエーハ表 面の研磨を行 う 。 The wafer that has undergone such a process is subjected to surface polishing in order to make the surface more flat and mirror-finished. In the present invention, first, the wafer is made of a material having a lower polishing rate than the wafer. The coating film is formed at least on the peripheral portion of the wafer surface, and is formed so that the wafer surface is exposed or thinner at the central portion of the wafer surface. Next, the back surface of the wafer is held and the surface of the wafer is polished.
こ の よ う に ゥエーハ ょ り 研磨速度が遅い材質か ら な る コ ー ト膜を 、 少な く と も ゥエーハ表面の周辺部分に形成 させてか ら表面を研磨 す.れば、 周辺部分の コー ト 膜が研磨 される分、 ゥエーハ周辺のシ リ コ ンが研磨され始め る の を遅 らせる こ と ができ る。 すなわち、 ゥェ ーハの周辺部分の コ ー ト膜が除去 さ れる までの間中央部分の シ リ コ ンが研磨によ り あ る程度除去 された後で、 周辺部分のシ リ コ ンの実 質的な研磨が開始される。 したがっ てコ ー ト 膜が研磨されて除去 さ れた後、 ゥエーハの周辺部分が中央部分よ り 速い研磨速度で除去 さ れて も 、 周辺部分の過研磨を防ぎ、 周辺ダレの発生を抑制する こ と ができ る。 As described above, a coat film made of a material having a low polishing rate is formed on at least a peripheral portion of the wafer surface, and then the surface is polished. As the film is polished, the silicon around the wafer can be delayed from being polished. In other words, after the silicon in the central portion is removed to some extent by polishing until the coat film in the peripheral portion of the wafer is removed, the silicon in the peripheral portion is removed. Substantial polishing is started. Therefore, even if the peripheral part of the wafer is removed at a higher polishing rate than the central part after the coat film is polished and removed, overpolishing of the peripheral part is prevented and generation of peripheral sag is suppressed. be able to.
コー ト膜は、 少な く と も 研磨 され る ウ ^ーハ表面の外周端部か ら 1 0 m m以内の周辺部分に形成 させる こ と で周辺ダ レを好適に防 ぐ こ と ができ る。 前記 した よ う にシ リ コ ン ゥエーハの研磨では、 ゥェ 一ハの径に よ らず外周端部か ら 6 m m前後の位置か ら落ち込みが始 ま り 易いの で、 外周端部か ら 1 5 m m以内、 好ま し く は 1 O m m以 内の周辺部分に形成 させ、 特に外周端部か ら 5 〜 7 m mぐ らいま で コ ー ト 膜を形成 させて研磨すれば、 周辺ダ レ を効果的に防 ぐ こ と が でき る。 また、 外周端部か ら 中央部分にかけて徐々 にコー ト 膜が薄
く な る よ う に形成する と さ ら に好ま しい。 By forming the coating film at least on the peripheral portion within 10 mm from the outer peripheral edge of the wafer surface to be polished, peripheral sagging can be suitably prevented. As described above, in polishing silicon wafers, it is easy to start dropping from a position about 6 mm from the outer peripheral end regardless of the diameter of the wafer, and therefore, from the outer peripheral end. 1 5 mm within, and preferred rather causes formed in the peripheral portion of the 1 O mm or more, if polished, especially to form a co-chromatography preparative membranes or outer edge et 5 ~ 7 m m instrument Lima, peripheral da Can be effectively prevented. In addition, the coating film gradually thins from the outer edge to the center. It is even more preferable to form it so that it becomes more dense.
本発明で形成 させる コー ト膜 と しては、 ワ ーク 、 すなわち シ リ コ ンゥエーハ ょ り 研磨速度が遅い材質から な る も の であれば特に限定 されないが、 シ リ コ ン酸化膜、 シ リ コ ン窒化膜ま たは樹脂膜が好ま しい。 これ ら の コ ー ト 膜の研磨速度は、 シ リ コ ンに比べて数分の 1 か ら数十分の 1 程度であ り 、 ゥエーハ周辺部分の シ リ コ ンの研磨が 始ま る のを効果的に遅 らせる こ と ができ 、 ま た、 比較的容易に形成 させる こ と ができ る 点でも有利であ る。 The coating film formed by the present invention is not particularly limited as long as it is made of a work, that is, a silicon wafer or a material having a low polishing rate, but is not particularly limited. A silicon nitride film or a resin film is preferred. The polishing rate of these coat films is a fraction to several tenths of that of silicon, and polishing of the silicon around the wafer begins. This is advantageous in that it can be effectively delayed and can be formed relatively easily.
シ リ コ ン酸化膜ま たはシ リ コ ン窒化膜の形成方法と しては特に限 定されないが、 C V D また は熱処理によ って少な く と も ゥエーハ表 面に酸化膜ま たは窒化膜を形成 させた後、 該 ゥエーハ表面の周辺部 分をマスキ ング してエ ッチ ング処理する こ と に よ り シ リ コ ン酸化膜 ま.たはシ リ コ ン窒化膜を ゥエーハ表面の周辺部に容易 に形成 させる こ と ができ る。 The method of forming the silicon oxide film or the silicon nitride film is not particularly limited, but at least the oxide film or the nitride film is formed on the surface of the wafer by CVD or heat treatment. After the film is formed, the periphery of the wafer surface is masked and etched to form a silicon oxide film or a silicon nitride film on the wafer surface. It can be easily formed on the periphery.
例えば、 エ ッチング後の原料 ゥエーハに酸化性雰囲気下で熱処理 を施 して ゥエーハの全面に熱酸化膜を形成した後、 周辺部分にテー プの貼着ま たは レ ジス ト形成等によ り 周辺部分をマス ク し、 フ ッ酸 ( H F ) 等でエ ッチ ングす る こ と に よ り 中央部分の熱酸化膜を除去 する こ と ができ る。 For example, after etching, the raw material is subjected to a heat treatment in an oxidizing atmosphere to form a thermal oxide film on the entire surface of the wafer, and then a tape or a resist is formed around the periphery. By masking the peripheral part and etching it with hydrofluoric acid (HF) or the like, the central part of the thermal oxide film can be removed.
また、 熱処理に代えて C V D によ っ て酸化膜 ( C V D酸化膜) を ゥエーハ上に堆積す る こ と によ り 形成 させた後、 上記 と 同様の手順 に従っ て周辺部分にのみ酸化膜を形成 させる こ と も でき る ほか、 最 初に中央部分をマス ク した上で C V D を行 う こ と で、 周辺部分にだ け C V D酸化膜を形成させて も よい。 After forming an oxide film (CVD oxide film) on the wafer by CVD instead of heat treatment, the oxide film is formed only on the peripheral portion according to the same procedure as above. Alternatively, the CVD oxide film may be formed only on the peripheral portion by masking the central portion first and then performing CVD.
樹脂膜の形成方法も特に限定 されないが、 ス ピ ンコ ーテ ィ ングに よ っ て前記ゥエーハ表面の周辺部分に有機溶媒で希釈 した樹脂溶液 を塗布 した後、 熱処理する こ と.で樹脂膜を容易に形成 させる こ と が でき る 。
前記樹脂は特に限定 され る も のではないが、 例 えばエポキシ樹脂 等の熱硬化性樹脂でも 良い。 The method for forming the resin film is not particularly limited, either.A resin solution diluted with an organic solvent is applied to the peripheral portion of the wafer surface by spin coating, followed by heat treatment. It can be easily formed. The resin is not particularly limited, but may be, for example, a thermosetting resin such as an epoxy resin.
例えば、 図 2 に示 さ れる よ う に、 ゥエ ーハ Wを、 その中心が回転 軸 3 上に位置す る よ う に回転テーブル 2 上に固定する。 次いで、 ゥ エ ーハ Wを回転させなが ら 、 適当な溶媒に溶かしたエポキシ樹脂等 の熱硬化性樹脂 を供給ノ ズル 4 を通 じて ゥエ ーハ周辺部分に塗布 し た後、 これを熱硬化処理する こ と に よ り 、 ゥ エ ーハ周辺部分にのみ エポキシ樹脂 コ ー ト 膜 1 を容易 に形成 させる こ と ができ る。 なお、 樹脂 と してはエポキシ樹脂に限定されず、 硬化後 ワーク よ り 研磨速 度が遅いも の であれば全て使用する こ と ができ る。 For example, as shown in FIG. 2, the wafer W is fixed on the turntable 2 so that the center thereof is located on the rotation axis 3. Next, while rotating the wafer W, a thermosetting resin such as an epoxy resin dissolved in an appropriate solvent is applied to the periphery of the wafer through the supply nozzle 4 and then applied. By subjecting the epoxy resin to heat curing, the epoxy resin coat film 1 can be easily formed only on the periphery of the wafer. The resin is not limited to epoxy resin, and any resin can be used as long as it has a lower polishing rate than the work after curing.
いずれの コ ー ト膜を形成 させる場合で も 、 ゥエ ーハ表面の中央部 分では ゥエ ーハ表面が露出する かま たは周辺部分よ り 薄く な る よ う にコ一 ト膜を形成 させるが、 中央部分ではゥエ ーハ表面 5 が露出す る よ う に コー ト膜 1 を形成 させれば、 コ ー ト 膜 1 は よ り 薄く て良 く 、 その後の研磨時間 も短縮する こ と ができ る ので好ま しい。 Regardless of which coating film is formed, the coating film is formed so that the central portion of the wafer surface is exposed or thinner than the peripheral portion. However, if the coating film 1 is formed so that the wafer surface 5 is exposed in the center portion, the coating film 1 can be made thinner and the subsequent polishing time can be shortened. It is preferable because you can do it.
ま た、 ゥエ ーハ表面の周辺部分以外、 例えばゥエ ーハの裏面に関 してはコー ト膜の形成は必須ではないが、 図 1 で示 されるよ う に裏 面 6 に も コ ー ト膜 1 を形成 させて ゥエ ーハ Wの研磨を行えば、 研磨 剤等に よ る ゥエ ーハ裏面の過剰なエ ッ チングや汚れを防止する こ と ができ 、 また裏面の保持に よ る傷の発生も防止でき る。 こ の よ う な 汚れ、 傷の防止は、 樹脂性の コー ト 膜を形成 させた場合に特に有効 と な る。 In addition, it is not essential to form a coating film on the portion other than the peripheral portion of the wafer surface, for example, on the back surface of the wafer, but also on the back surface 6 as shown in FIG. If the wafer W is polished by forming the coat film 1, excessive etching and dirt on the rear surface of the wafer due to an abrasive or the like can be prevented, and the rear surface of the wafer can be prevented. The occurrence of scratches due to holding can also be prevented. Such prevention of dirt and scratches is particularly effective when a resinous coating film is formed.
なお、 ス ピンコ ーテ ィ ング法によ っ て ゥエ ーハ裏面に樹脂の コ ー ト膜を形成する と き に、 塗布溶液の粘度 と ス ピ ンの条件を制御する こ と に よ っ て ゥエ ー ノ、表面側に樹脂の回 り 込みが発生するが、 こ の 現象を利用 して ゥエ ーハ表面側の周辺部のみにコ ー ト膜を形成す る こ と が可能であ る。 こ の場合、 榭脂 と しては P V B (ポ リ ビニルブ チラール) を用いる こ と が可能であ る。
図 1 の ゥエ ーハは、 本発明に係る コー ト膜を形成させた一例であ つて、 ゥエ ーハ表面の周辺部分のみ、 あ るいはゥエ ーハ表裏面の周 辺部分のみに コ ー ト 膜を形成 させて も よ く 、 こ の よ う にコ ー ト 膜を 形成する部分を少な く する こ と で作業効率を向上 させる こ と ができ る。 When a resin coating film is formed on the backside of the wafer by the spin coating method, the viscosity of the coating solution and the spin conditions are controlled. In this case, the resin may flow into the surface of the wafer, and this phenomenon can be used to form a coat film only on the peripheral part of the surface of the wafer. is there. In this case, PVB (polyvinyl butyral) can be used as the resin. The wafer shown in FIG. 1 is an example in which the coating film according to the present invention is formed, and is formed only on the peripheral portion of the wafer front surface or only on the peripheral portion of the wafer front and back surfaces. The coating film may be formed, and the work efficiency can be improved by reducing the portion where the coating film is formed as described above.
なお、 表面の研磨後、 裏面や面取 り 部に残留 してい る コ ー ト 膜は 、 コ ー ト 膜を溶解除去可能な溶液を用い洗浄除去する。 ま たは、 コ 一ト膜を取 り 除 く 研磨や、 エ ッ チン グ、 鏡面面取 り 等によ り 除去す れば良い。 After the polishing of the front surface, the coat film remaining on the back surface or the chamfered portion is washed and removed using a solution capable of dissolving and removing the coat film. Alternatively, it may be removed by polishing to remove the coating film, etching, mirror polishing, or the like.
上記の よ う な方法に よ り 所望の コ ー ト 膜を容易 に形成させる こ と ができ る が、 周辺部分に形成させる コー ト膜の厚 さ に関しては、 一 例 と して以下の よ う な簡易的な方法に よ り 決定する こ と ができ る。 A desired coat film can be easily formed by the above-described method, but the thickness of the coat film formed on the peripheral portion is as follows, for example. It can be determined by a simple method.
従来の研磨方法で研磨した場合の周辺ダレ量 : Y、 Peripheral sag when polished by conventional polishing method: Y,
シ リ コ ン の研磨速度 : R s i Polishing rate of silicon: R s i
コー ト膜の研磨速度 : R c Polishing rate of coat film: R c
周辺部分の コ ー ト 膜の膜厚 : T H Thickness of coat film in peripheral part: T H
とする と 、 コ ー ト膜が除去 されるま での時間 : t l は、 t l = T H / R c と して表 され、 時間 t 1 の間 に中央部分の シ リ コ ンが除去 さ れる量が周辺ダ レ量 Y と一致する よ う に コ ー ト膜の膜厚 T Hを決定 する こ と ができ る。 Then, the time until the coat film is removed: tl is expressed as tl = TH / Rc, and the amount of the silicon removed in the central part during the time t1 The thickness TH of the coat film can be determined so that the thickness of the coat film coincides with the peripheral sag amount Y.
従っ て、 Therefore,
Y = R s i X ( T H / R c ) と な り 、 これを さ ら に変形する と 、 Y = R s i X (TH / R c), and when this is further transformed,
T H = Y X ( R c / R s i ) T H = Y X (R c / R s i)
と な る ので、 周辺ダ レ量 ( Y;)、 シ リ コ ン の研磨速度 ( R s i )、 及 びコー ト膜の研磨速度 ( R c ) さ え予め測定しておけば、 周辺部分 のコー ト膜の厚 さ ( T H ) を簡易的に決定する こ と ができ る。 Therefore, if the peripheral sag (Y;), the silicon polishing rate (Rsi), and the coating film polishing rate (Rc) are measured in advance, the peripheral part The thickness (TH) of the coating film can be easily determined.
研磨速度については研磨条件によ っ て違っ て く るが、 本発明者 ら の実験に よれば、 シ リ コ ン ゥエ ー ノヽ 自 体の研磨速度が 0 · 6 〜 0 ·
7 /x m Z分 と な る通常の研磨条件で研磨を行 う 場合、 各研磨速度は およそ以下の通 り と なる。 The polishing rate varies depending on the polishing conditions. However, according to the experiments performed by the present inventors, the polishing rate of the silicon itself was 0.6 to 0.6. When polishing is performed under normal polishing conditions of 7 / xmZ, the respective polishing rates are approximately as follows.
熱酸化膜 : 0 . 0 1 〜 0 · 0 2 μ πι /分 Thermal oxide film: 0.01 to 0 · 0 2 μπι / min
C V D酸ィ匕膜 : 0 . 0 4 〜 0 . 0 6 /x m Z分 C V D oxidation film: 0.04 to 0.06 / xmZ min
エポキシ樹脂膜 : 0 . 0 2 〜 0 . 0 4 /i m / /分 Epoxy resin film: 0.02 to 0.04 / im / min
これ ら は、 使用 した研磨剤や、 研磨圧力等の研磨条件、 あ る いは コ ー ト 膜作製条件等で値が変わっ て く る が、 予め 同条件で実験を行 つ てお く こ と で容易に求め る こ と ができ る。 These values vary depending on the polishing agent used, polishing conditions such as polishing pressure, or the conditions for forming the coating film.However, experiments should be performed in advance under the same conditions. Can be easily obtained with
図 3 は、 本発明者 らが行っ た研磨速度に関する 実験の結果を示 し たも のであ る。 こ の グラ フ 力、 ら も明 らかな よ う に、 各コー ト 膜はシ リ コ ンゥエ ー ノヽ と 比べてその研磨速度が 1 0 分の 1 以下であ り 、 シ リ コ ンよ り かな り 研磨され難い こ と が分力ゝる。 従って、 ゥエーハ周 辺 _部分に薄 く コ ー トするだけで周辺部分のシ リ コ ンが研磨 される の を遅 らせる こ と ができ、 ひいて は周辺ダ レを効果的に防ぐ こ と がで さ る。 FIG. 3 shows the results of an experiment on the polishing rate performed by the present inventors. As is evident from this graphing force, each coating film has a polishing rate of 1/10 or less as compared to silicon nano-electrode, which is higher than that of silicon. It is hard to be polished. Therefore, it is possible to delay polishing of the silicon in the peripheral portion only by coating thinly on the portion _ around the wafer, thereby effectively preventing peripheral dripping. Is out.
なお、 コ ー ト 膜の厚さ を導 く ため の上記計算式は一例であっ て、 コ ー ト 膜の厚 さ に関 しては、 上述の よ う にラ ッ ビング後あ る いはェ ツチング後の ゥエーハ (原料ゥエーハ) の形状、 全体の研磨代、 コ 一 ト膜の材質や作製条件、 使用 した研磨剤や研磨圧力等の研磨条件 、 あ るいは研磨 される ゥエ ー ノヽのボ ロ ン等の ドーパン ト元素や窒素 等の不純物元素の ドープ量に よ る硬度の変化等を考慮 し、 予め研磨 速度を実験に よ り 確認する な ど して適宜決めれば良い。 The above formula for deriving the thickness of the coating film is merely an example, and the thickness of the coating film may be determined after rubbing or as described above. The shape of the wafer after polishing (raw material wafer), the overall polishing allowance, the material and manufacturing conditions of the coating film, the polishing conditions such as the abrasive used and the polishing pressure, or the surface of the abrasive to be polished In consideration of the change in hardness due to the doping amount of a dopant element such as boron or an impurity element such as nitrogen, the polishing rate may be determined in advance as appropriate, for example, by confirming the polishing rate by experiments.
周辺部分に コ ー ト膜を形成 させた後、 図 5 に示 される よ う な従来 の保持板等を用 いて研磨す る こ と ができ る。 すなわち、 多数の貫通 孔が設け られた保持板 1 6 に貫通孔を通 じて ゥエ ーハ Wを真空吸着 保持し、 研磨布 1 3 に研磨剤 1 5 を供給する と と も に、 ゥエ ーハ表 面を研磨布 1 3 に所定の押圧力 を掛なが ら摺接させて研磨する。 こ の よ う な研磨を行 う こ と で、 研磨初期においては、 ゥエ ー ノヽの中央
部分では シ リ コ ンが直接研磨 さ れる一方、 周辺部分では研磨速度が 遅い コ ー ト膜が研磨 される ため、 ゥエーハの 中央部分が一旦薄 く な る。 そ の後、 周辺部分の コ ー ト 膜が除去 される と 、 周辺部分の シ リ コ ンが中央部分よ り も速い研磨速度で研磨される ので、 やがて中央 部分 と 周辺部分の厚 さ がほぼ同 じ と なっ た と き に研磨を終了すれば 良い。 After the coat film is formed on the peripheral portion, it can be polished using a conventional holding plate as shown in FIG. That is, the wafer W is vacuum-sucked and held through the through-holes in the holding plate 16 provided with a large number of through-holes, and the abrasive 15 is supplied to the polishing cloth 13. Polish the wafer surface by sliding it against the polishing cloth 13 while applying a predetermined pressing force. By performing such polishing, in the initial stage of polishing, the center of the The silicon is directly polished in the part, while the coat film with a low polishing rate is polished in the peripheral part, so that the central part of the wafer becomes thin once. Thereafter, when the coat film in the peripheral portion is removed, the silicon in the peripheral portion is polished at a higher polishing rate than the central portion, so that the thickness of the central portion and the peripheral portion eventually becomes almost equal. It is only necessary to finish polishing when it becomes the same.
なお、 本発明 の研磨方法は研磨工程におけ るいずれの段階におい て も適用でき る が、 周辺ダ レは研磨代が一番多い 1 次研磨で生 じ る こ と がほ と ん どなので、 1 次研磨に好適に適用す る こ と ができ る 。 従っ て、 本発明の方法によ り 1 次研磨を行っ た後、 必要に応 じて 2 次研磨を行い、 さ ら に仕上げ研磨を行 う こ と で表面全体にわたっ て 非常に高い平坦度を有する鏡面 ゥエーハを得る こ と ができ る。 Although the polishing method of the present invention can be applied at any stage in the polishing process, the peripheral sag is almost always generated by the primary polishing, which has the largest polishing allowance. It can be suitably applied to primary polishing. Therefore, after the primary polishing is performed by the method of the present invention, the secondary polishing is performed as necessary, and the final polishing is further performed, so that a very high flatness is obtained over the entire surface. It is possible to obtain a mirror surface having the following characteristics.
_上記研磨方法では、 枚葉式に研磨する場合について説明 したが、 本発明 は保持板の種類、 ゥエーハの保持方法等については特に限定 されず、 パ ッチ式に研磨する場合に も適用する こ と ができ る。 すな わち、 所望の コ ー ト膜を形成 した複数枚の ゥエーハの裏面を接着剤 または ワ ッ ク ス等を介 してガラ スやセラ ミ ッ ク製のプ レー ト に貼 り 付け、 これ ら複数枚の ゥエーハを同時に研磨する こ と もでき る。 _ In the above polishing method, a description has been given of the case of single-wafer polishing, but the present invention is not particularly limited with respect to the type of holding plate, the method of holding the wafer, and the like, and is also applicable to the case of polishing in a patch type. be able to. That is, the back surfaces of a plurality of wafers on which a desired coat film has been formed are adhered to a glass or ceramic plate via an adhesive or a wax. These wafers can be polished simultaneously.
本発明の研磨方法に よ り 研磨 されたシ リ コ ンゥエーハは、 周辺ダ レの発生が抑制 され、 ゥエーハ表面全体にわたっ て平坦度に優れた 鏡面 ゥエーハ と な り 、 ゥエーハ の良品率を著し く 向上 させる こ と が でき る。 特に、 外周端部か ら 2 m m以内の領域を含め、 表面基準の S F Q R m a x が 0 . 1 5 ^ πι以下の非常に高い平坦度を有する ゥ エーハを保持板等の構造に関係無く 安定 して製造する こ と ができ る 。 ま た、 こ の よ う な ゥェ一ノヽを用い る こ と で表面全体に回路を形成 させる こ と ができ 、 半導体デバ イ ス の生産性及び歩留 り を著し く 向 上 させる こ と カ でき る。 The silicon wafer polished by the polishing method of the present invention suppresses the generation of peripheral sag, becomes a mirror-finished wafer having excellent flatness over the entire surface of the wafer, and shows a good yield of the wafer. Can be improved. In particular, it has a very high flatness with a SFQR max of 0.15 ^ πι or less, including the area within 2 mm from the outer edge. 部 The wafer is stable regardless of the structure of the holding plate etc. It can be manufactured. In addition, by using such a semiconductor, a circuit can be formed over the entire surface, and the productivity and yield of semiconductor devices can be significantly improved. I can do it.
以下、 実施例及び比較例 を示 して本発明を よ り 具体的に説明す る
が、 本発明 はこれ ら に限定 される も の ではない Hereinafter, the present invention will be described more specifically with reference to Examples and Comparative Examples. However, the present invention is not limited to these.
(実施例 ) (Example )
エ ツ チ ン グ後 の シ リ コ ン ゥ エ ーハ (径 : 8 イ ンチ ( 2 0 0 m m ) ) を C V D に よ り 成膜処理 し て ゥエ ーハ の表面に C V D酸化膜を形 成 させた。 次いで ゥエ ー ノヽ外周端部から 5 m mま での周辺部分をマ スキングしてエ ッチング処理し、 中央部分の酸化膜を除去する こ と に よ り 周辺部分のみ C V D酸化膜を残存 させた。 なお、 C V D酸化 膜の膜厚は HU記計 式に よ り 算出 し、 そ の値をも と に C V D酸化膜 を形成 させた。 すなわち、 シ リ コ ンの研磨速度 R s i : 0 . 6 μ m ノ分、 コ ー ト 膜 ( C V D酸化膜) の研磨速度 R c : 0 . Ό Ό μ m. 分、 周辺ダ レ量 Y : 約 0 . 3 μ πι (従来の方法に よ る研磨で得 られ た.値) と して、 コー ト 膜の厚 さ T H = Y X ( R c / R s i ) = 0 . The silicon wafer after etching (diameter: 8 inches (200 mm)) is formed by CVD to form a CVD oxide film on the surface of the wafer. Was completed. Next, the peripheral portion up to 5 mm from the outer peripheral edge of the anode was subjected to masking and etching treatment, and the central portion of the oxide film was removed to leave the CVD oxide film only in the peripheral portion. The thickness of the CVD oxide film was calculated by the HU notation formula, and the CVD oxide film was formed based on the calculated value. That is, the polishing rate of silicon Rsi: 0.6 μm, the polishing rate of the coating film (CVD oxide film) Rc: 0.1 μm, the peripheral sagging Y: Approximately 0.3 μπι (value obtained by polishing by the conventional method), the thickness of the coating film TH = YX (Rc / Rsi) = 0.
3 μ m X ( 0 . 0 6 / 0 . 6 ) = 3 0 n m と した。 3 μm X (0.06 / 0.6) = 30 nm.
こ の よ う にコ ー ト 膜を形成 させた ゥエーノ、を用い、 以下の研磨条 件で一次研磨を行っ た。 Primary polishing was performed under the following polishing conditions, using ENO, on which the coating film was formed as described above.
研磨装置 真空吸着タイ プ枚葉研磨装置 Polishing equipment Vacuum adsorption type single wafer polishing equipment
研磨布 S U B A 6 0 0 (口デール社製商品名) Abrasive cloth S U B A 600 (product name made by Kuchi Dale)
研磨剤 コ ロ イ ダルシ リ カ研磨剤 Abrasive Abrasives
研磨荷重 3 0 0 g f / c m Polishing load 300 g f / cm
相対速度 5 0 m / m i n Relative speed 50 m / min
研磨代 1 0 μ m Polishing allowance 10 μm
(比較例) (Comparative example)
実施例で用いた ゥエーハ と 同 じサイ ズのシ リ コ ン ゥエーハを用い A silicon wafer of the same size as the wafer used in the embodiment was used.
、 コ ー ト膜を形成せずに実施例 1 と 同様の研磨条件で研磨を行っ た
実施例及び比較例で研磨 した ゥエ ーハに対 し、 静電容量式厚 さ測 定器を用い、 外周端部か ら 1 0 m mの位置を基準 と して周辺部分の 厚 さ分布 (除外領域 : 周辺 2 m m ) を測定し、 その結果を図 4 に示 した。 Polishing was performed under the same polishing conditions as in Example 1 without forming a coat film. For the wafers polished in the examples and comparative examples, the thickness distribution of the peripheral portion was determined using a capacitance-type thickness measuring device with reference to a position 10 mm from the outer peripheral end. Excluded area: 2 mm around) was measured, and the results are shown in Fig. 4.
実施例 (コー ト 膜有 り ) で研磨したゥエ ーハは、 周辺部分まで非 常に高い平坦度が達成 され、 外周端部か ら 2 m mの位置でも 変位量 は 0 . Ι μ ιη以下であ り 、 S F Q R m a x は 0 . 0 9 μ πιであっ た 一方、 比較例 (コ ー ト膜無 し) で研磨 された ゥエ ーハは、 原料 ゥ エ ー ノヽの周辺ダ レ よ り は改善されている も の の外周端部力 ら 6 m m 付近で周辺ダ レが始ま り 、 外周端部か ら 2 m mの位置で約 0 . 3 mの変位があっ た。 ま た、 S F Q R m a x は 0 . 2 0 μ ιη程度であ つ.た。 The wafer polished in the embodiment (with a coating film) achieves extremely high flatness up to the peripheral part, and the displacement amount is less than 0.1 μμηη even at a position 2 mm from the outer peripheral edge. In contrast, the SFQR max was 0.09 μπι, while the wafer polished in the comparative example (without coat film) improved more than the sag around the raw material anode. The sagging started around 6 mm from the outer edge of the target, and there was a displacement of about 0.3 m at 2 mm from the outer edge. In addition, SFQRmax was about 0.20 μιη.
なお、 図 4 に示 され る よ う に、 エ ッチ ング後に予め測定した原料 ゥエ ーハの周辺部分には、 既に周辺ダレが生 じていた。 通常、 エ ツ チング工程で周辺ダ レが生 じた ゥエ ーハを研磨する と 、 研磨の極初 期段階では、 ゥエ ーハの周辺部分は、 中心部分よ り 厚 さが薄い分、 研磨圧力が低く 研磨速度が遅く な る が、 さ ら に研磨を続け る と 、 ゥ エーハ全面がほぼ同 じ条件 (研磨速度) で、 あ るいは ゥエーハ周辺 部分が過剰に研磨 される。 従っ て、 研磨工程で 1 0 μ πι程度の研磨 代で研磨する と 、 図 6 に示 した よ う な新たな周辺ダレが生 じ る こ と にな る。 しかし、 実施例では、 ゥエ ーハ周辺部分にコー ト膜を形成 させたため、 上記の よ う な研磨工程での周辺ダ レを防止する こ と が でき た。 なお、 本発明 は、 上記実施形態に限定 される も のではない。 上記 実施形態は単な る例示であ り 、, 本発明 の特許請求の範囲に記載さ れ た技術的思想 と 実質的に同一な構成を有 し、 同様な作用効果を奏す
る も の は、 いかな る も のであっ ても 本発明の技術的範囲に包含 さ れ る。 As shown in FIG. 4, peripheral sagging had already occurred in the periphery of the raw material wafer measured in advance after the etching. Normally, when polishing wafers where peripheral dripping has occurred in the etching process, at the very initial stage of polishing, the peripheral part of the wafer is thinner than the central part, Although the polishing pressure is low and the polishing rate is low, if the polishing is further continued, the entire surface of the wafer is substantially polished under the same conditions (polishing rate), or the peripheral portion of the wafer is excessively polished. Therefore, when polishing is performed with a polishing allowance of about 10 μπι in the polishing process, a new peripheral sag as shown in FIG. 6 is generated. However, in the example, since the coat film was formed around the wafer, it was possible to prevent the peripheral sag in the polishing process as described above. Note that the present invention is not limited to the above embodiment. The above embodiment is merely an example, and has substantially the same configuration as the technical idea described in the claims of the present invention, and achieves the same operation and effect. Anything is included in the technical scope of the present invention.
例えば、 前記実施の形態ではシ リ コ ン ゥエーハ を研磨する場合を 例に説明 したが、 本発明が適用 でき る被研磨物はシ リ コ ン ゥエーハ に限定 されず、 表面全体の高い平坦度が要求 され る 円形状ワーク の 研磨に適用 でき る。 ま た、 周辺ダ レは、 ワーク の径にかかわ らず発 生する ので、 本発明は ワーク の大き さ に関 しても 特に限定 される も の ではない。 For example, in the above embodiment, the case where the silicon wafer is polished has been described as an example, but the object to be polished to which the present invention can be applied is not limited to the silicon wafer, and high flatness of the entire surface is required. It can be applied to the required polishing of circular workpieces. In addition, since peripheral sag occurs regardless of the diameter of the work, the present invention is not particularly limited with respect to the size of the work.
また、 コ ー ト 膜の厚 さの制御の仕方も 、 実施例では 1 段の研磨後 に高平坦度にな る よ う に制御 してい る が、 研磨を複数段で行 う 場合 、 最終的な仕上げ研磨後に高平坦度であ る必要が ある。 本発明 は、 先に も述べた よ う に周辺ダ レが最も発生する可能性がある 1 次研磨 で.用いる こ と が最適である。 しかし、 2 次研磨や仕上げ研磨な ど、 その後の研磨で も若干周辺ダレが起こ る こ と があ るので、 1 次研磨 で完全に高平坦度にな る よ う に コ ー ト膜の厚さ を決め る の ではな く 、 2 次、 仕上げ研磨でのダ レ量を考慮して、 1 次研磨では外周部分 が若干跳ね上が る (若干周辺部分が厚く な る) よ う にコー ト膜の厚 さ を制御 し研磨 して も 良い。 つま り 最終的な製品で高平坦度な ゥェ ーハが得 られる よ う に本発明を利用すれば良い。 も ち ろん、 各研磨 段階で本発明の よ う な コー ト膜を形成し研磨 して も構わない。
Also, in the embodiment, the method of controlling the thickness of the coat film is controlled so as to attain a high flatness after one step of polishing. However, when polishing is performed in a plurality of steps, the final step is performed. It is necessary to have high flatness after perfect finish polishing. As described above, the present invention is optimally used in primary polishing where peripheral sagging is most likely to occur. However, subsequent polishing, such as secondary polishing or finish polishing, may cause some sagging around the periphery. Therefore, the thickness of the coating film must be adjusted so that the first polishing completely achieves high flatness. Instead of deciding the amount, consider the amount of sag in the secondary and final polishing, and coat in such a way that the outer peripheral part will jump up slightly (the peripheral part will be slightly thicker) in the primary polishing. Polishing may be performed by controlling the thickness of the film. That is, the present invention may be used so that a wafer with high flatness is obtained in a final product. Of course, a coat film as in the present invention may be formed and polished at each polishing step.
Claims
1 . 円形状ワーク を保持板で保持 し、 該ワー ク の表面を研磨布 に 摺接させて研磨する方法において、 前記ワー ク よ り 研磨速度が遅い 材質か ら な る コ ー ト膜を、 少な く と も前記ワ ーク 表面の周辺部分に 形成 させる と と も に該ワー ク表面の 中央部分では ワーク表面が露出 する かま たは周辺部分よ り 薄く なる よ う に形成させ、 前記ワ ー ク の 裏面を保持 して ワーク表面の研磨を行 う こ と を特徴と する ワー ク の 研磨方法。 1. In a method in which a circular work is held by a holding plate and the surface of the work is slid in contact with a polishing cloth and polished, a coat film made of a material having a lower polishing rate than the work is removed. It is formed at least in the peripheral part of the work surface, and is formed so that the work surface is exposed or thinner in the central part of the work surface than in the peripheral part. A method of polishing a work, characterized in that the work surface is polished while holding the back surface of the work.
2 . 前記ワーク が、 シ リ コ ン ゥエーハであ る こ と を特徴とする 請 求項 1 に記載の研磨方法。 2. The polishing method according to claim 1, wherein the workpiece is a silicon wafer.
3 . 前記 コ ー ト膜を、 前記ゥエーハの表面の外周端部から 1 O m m以内の周辺部分に形成さ せる こ と を特徴と する請求項 2 に記載の 研磨方法。 3. The polishing method according to claim 2, wherein the coat film is formed on a peripheral portion within 1 Om m from an outer peripheral end of the surface of the wafer.
4 . 前記コ ー ト膜と して 、 シ リ コ ン酸化膜、 シ リ コ ン窒化膜ま た は樹脂膜を形成 させる こ と を特徴と する請求項 1 ない し請求項 3 の いずれか 1 項に記載の研磨方法。 4. The method according to any one of claims 1 to 3, wherein a silicon oxide film, a silicon nitride film, or a resin film is formed as the coat film. The polishing method according to the above item.
5 . 前記シ リ コ ン酸化膜またはシ リ コ ン窒化膜の形成は、 C V D または熱処理に よ っ て少な く と も前記ゥエーハ表面に酸化膜ま たは 窒化膜を形成 させた後、 該 ゥエーハ表面の周辺部分をマスキ ング し てエ ッ チ ング処理する こ と に よ り 行 う こ と を特徴 と する請求項 4 に 記載の研磨方法。 前記樹脂膜の形成は、 ス ピ ン コ ーティ ングに よ っ て前記 ゥェ
ー ハ表面の周辺部分に前記樹脂 を塗布 した後、 熱処理する こ と に よ り 行 う こ と を特徴とする請求項 4 に記載の研磨方法。
5. The silicon oxide film or the silicon nitride film is formed by forming at least an oxide film or a nitride film on the surface of the wafer by CVD or heat treatment. 5. The polishing method according to claim 4, wherein the peripheral portion of the surface is masked and etched. The resin film is formed by spin coating by spin coating. 5. The polishing method according to claim 4, wherein the heat treatment is performed after applying the resin to a peripheral portion of the surface of the wafer.
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JP2006237055A (en) * | 2005-02-22 | 2006-09-07 | Shin Etsu Handotai Co Ltd | Method of manufacturing semiconductor wafer and method of specularly chamfering semiconductor wafer |
US8952496B2 (en) | 2009-12-24 | 2015-02-10 | Sumco Corporation | Semiconductor wafer and method of producing same |
JP5423384B2 (en) * | 2009-12-24 | 2014-02-19 | 株式会社Sumco | Semiconductor wafer and manufacturing method thereof |
JP2013110322A (en) * | 2011-11-22 | 2013-06-06 | Shin Etsu Handotai Co Ltd | Formation method and formation apparatus of silicon oxide film and silicon wafer polishing method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS61292922A (en) * | 1985-06-21 | 1986-12-23 | Hitachi Hokkai Semiconductor Ltd | Manufacture of semiconductor device |
JPH07335845A (en) * | 1994-06-15 | 1995-12-22 | Toshiba Corp | Manufacture of soi substrate and polisher |
-
2000
- 2000-07-21 JP JP2000220821A patent/JP2002043257A/en active Pending
-
2001
- 2001-07-10 WO PCT/JP2001/005971 patent/WO2002009165A1/en active Application Filing
- 2001-07-18 TW TW90117559A patent/TW544368B/en active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61292922A (en) * | 1985-06-21 | 1986-12-23 | Hitachi Hokkai Semiconductor Ltd | Manufacture of semiconductor device |
JPH07335845A (en) * | 1994-06-15 | 1995-12-22 | Toshiba Corp | Manufacture of soi substrate and polisher |
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JP2002043257A (en) | 2002-02-08 |
TW544368B (en) | 2003-08-01 |
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