WO2001009683A1

WO2001009683A1 - Reduction of resist poisoning

Info

Publication number: WO2001009683A1
Application number: PCT/US2000/020383
Authority: WO
Inventors: Gill Yong Lee
Original assignee: Infineon Technologies North America Corp.
Priority date: 1999-08-02
Filing date: 2000-07-26
Publication date: 2001-02-08
Also published as: TW480583B

Abstract

A silicon-rich layer is provided beneath a resist to prevent resist poisoning by an underlying device layer.

Description

REDUCTION OF RESIST POISONING

Field of the Invention

The invention relates generally to fabrication of devices such as integrated circuits. More particularly, the invention relates to the improving critical dimension control during patterning.

Background of the Invention

In the fabrication of devices such as integrated circuits (ICs), features are formed on a substrate. The features, for example, correspond to components such as transistors, capacitors, and resistors. These components are then interconnected to achieve the desired electrical function.

To form the devices, layers are repeatedly deposited on the substrate and selectively patterned. Lithographic techniques are used to pattern the device layer or layers. Such techniques typically use an exposure source to project a light image from a mask onto a photoresist (resist) layer formed on the surface of the substrate. The light illuminates the resist layer, exposing it with the desired pattern. Depending on whether a positive or negative tone resist is used, the exposed or unexposed portions of the resist layer are removed. The portions not protected by the resist are then, for example, etched to form the features in the substrate.

The imaging mechanism of photoresist is a photo-acid generator, which produces an acid to catalyze a chemical reaction in the resist when exposed to light. The chemical reaction changes the resist solubility, enabling exposed or unexposed portions to be removed by a developer .

The dimensions of the features depend on the resolution capability of the lithographic systems. The minimum feature size (F) achieved by a given generation of lithographic systems is referred to as the lithographic groundrule (GR) . Critical dimension (CD) is defined as the minimum feature size that must be controlled. This includes, for example, linewidths, spacings, and contact widths.

Due to the variations of light or reflectance into the resist layer, variations in CD occur. Controlling the variations in CD (CD control) becomes a critical issue, particularly with deep ultra-violet lithography (DUV) . CD control is facilitated by the use of an antireflective coating (ARC) beneath the resist to reduce reflectance variations into the resist caused by underlying layers .

Inorganic ARCs, such as dielectric ARCs (DARCs), are attractive candidates for improving lithographic process window for DUV lithography. This is because inorganic ARCs possess desirable characteristics such as tunable properties, low defect levels, good conformality, high etch selectivity to resist, and small swing ratio.

However, the use of inorganic ARCs has been limited due to "resist poisoning." Resist poisoning refers to the contamination of the resist by, for example, amine radicals from the inorganic ARC, neutralizing the acid- generators which makes the contaminated portions of the resist insoluble by the developer. As a result, a foot in the resist profile is formed after development. A conventional technique to prevent resist poisoning is to provide an oxide layer between the ARC and the resist layer. The oxide layer can be deposited on the ARC or formed by plasma treating the surface of the ARC. However, the oxide layer is ineffective in preventing resist poisoning with certain resist chemistry such as JSR TM 399 from JSR Microelectronics. In fact, the oxide layer seems to exacerbate the resist poisoning problem.

As evident from the above discussion, it is desirable to effectively reduce resist poisoning to improve the lithographic process window.

Description of the Drawings

Fig. 1 shows an illustrative embodiment of the invention; and

Figs. 2-3 show the resist profile with and without silicon treatment in accordance with the invention.

Summary of the Invention

The invention relates to reducing resist poisoning. In one embodiment, a cap layer is provided beneath the resist. In one embodiment, the cap layer comprises a silicon-rich layer. Preferably, the cap layer comprises an amorphous silicon layer. Alternatively, excess dangling bonds can be created on a device layer beneath the resist layer to reduce resist poisoning. By reducing resist poisoning, the lithographic process window can be improved.

Description of the Invention

The invention relates to the fabrication of devices, such as integrated circuits (ICs) . In particular, the invention relates to reducing resist poisoning in order to improve the lithographic process window. In accordance with the invention, resist poisoning is reduced by providing a cap layer comprising silicon beneath the resist.

Fig. 1 shows one embodiment of the present invention for reducing resist poisoning. As shown, a substrate 110 is provided. The substrate comprises, for example, a semiconductor substrate such as a silicon wafer. Other types of substrates such as those comprising gallium arsenide, germanium, silicon-on-insulator, or other semiconductor materials are also useful. Non- semiconductor substrates can also be used. The substrate can be at various stages of the process flow. For example, the substrate can be at the beginning of the process flow or partially processed to include features (not shown) . The features are used to form, for example, integrated circuits (ICs) such as dynamic random access memories (DRAMs) or other types of ICs. The features can also be used to form electromechanical or mechanical devices. For purposes of discussion, the term "substrate" is used to refer to a substrate which can be at any stage in the process flow.

A device layer 130 is formed above the substrate. The device layer, in one embodiment, comprises an ARC layer. In one embodiment, the ARC layer comprises an inorganic ARC layer. The inorganic ARC layer comprises, for example, a DARC, such as silicon nitride (Si_xN_y) , silicon oxynitride, (SiN_xO_y) , hydrogenated silicon oxynitride, or other types of dielectric antireflective materials. In a preferred embodiment, the DARC comprises silicon oxynitride. Metallic ARCs or other inorganic antireflective materials are also useful. The inorganic ARC layer is deposited using conventional techniques such as, for example, chemical vapor deposition (CVD) .

In another embodiment, a multi-layer ARC stack utilizing absorption and destructive interference properties can be provided. Multi-lyaer ARC stacks are described in copending US patent application USSN (attorney docket number 98P 7982 US) titled "Improved CD Control", which is herein incorporated by reference for all purposes. An ARC layer comprising a graded refractive index is also useful. Graded refractive index ARC layers are described in copending US patent application USSN 09/276,026 (attorney docket number 98P 7982 USOl) titled "Arc for improving CD control" , and which is also herein incorporated by reference for all purposes.

Alternatively, the device layer 110 comprises a dielectric layer. Dielectric material such as silicon oxide, silicon nitride, or doped silicate glass such as boron-phosphorus-silicate glass, can be useful to serve as the device layer. Other types of dielectric materials are also useful. The dielectric layer can be formed using conventional techniques.

A thin cap layer 140 is formed over the device layer to reduce resist poisoning between the ARC and the subsequently formed resist. In accordance with one embodiment of the invention, the cap layer comprises silicon. Preferably, the cap layer comprises a thin amorphous silicon layer. The silicon comprising layer is sufficiently thin to avoid causing standing waves and interference in the resist. The cap layer, in one embodiment, is less than about 3θA thick, preferably less than about lOA thick, and more preferably less than about 3A thick. The thickness of the cap layer can be optimized to produce the desired resist profile.

Alternatively, the cap layer comprises a mono-atomic layer that alters the surface morphology of the device layer. The mono-atomic layer, in one embodiment, comprises excess silicon dangling bonds on the surface of the device layer. In such a case, the cap layer comprises a silicon-rich layer. The composition of the cap layer depends on the underlying device layer. For example, the cap layer would comprise a silicon-rich oxide or silicon-rich oxynitride if the underlying device layer comprised a silicon oxide or an oxynitride layer.

The resist layer 170 comprises, for example, any conventional resist used in lithography. Such resist can either be positive or negative tone resist. In one embodiment, the resist comprises JSR TM 399. The resist is formed by conventional techniques. The thickness of the resist is, for example, sufficiently thick to serve as an etch mask for the ARC open process. Typically, the thickness of the resist layer is about 0.2 - 10 μm.

As described, the invention provides a silicon comprising cap layer underneath the resist to prevent resist poisoning. The high mismatch in the refractive indices of silicon and resist can cause stancing waves or interference. However, since the cap layer is very thin (in some cases the thickness may not be measurable as in the case of a mono-atomic layer) , the impact of standing waves or interference is reduced or minimized.

In one embodiment, the silicon cap layer is formed by chemical vapor deposition (CVD) , such as low pressure CVD (LPCVD) , plasma enhanced CVD (PECVD), high density plasma CVD (CVD), electron cyclotron resonance (ECR) CVD. Other types of plasma processes such as PVD are also useful. A silicon precursor gas and a dilute gas or gas mixture are introduced into the chamber containing the substrate with the device layer. In one embodiment, a silicon precursor gas comprising SiH₄ is employed. Other types of silicon precursors such as TEOS and Si₂H₆ are also useful. Dilute gas can include, for example, helium (He) , argon (Ar) , or Neon (Ne) . The gases react in the chamber, depositing the silicon cap layer on the device layer .

The process parameters of forming the cap layer are as follows:

RF plasma power : about 10 - 5,000 watts chamber pressure : about 0.1 mTorr to 20 Torr spacing between showerhead and wafer: about 10 - 5000 mils silicon precursor flow rate (SiH₄) : about 0 - 100 seem The deposition process forms a thin cap layer comprising silicon on the surface of the device layer. Preferably, the cap layer comprises a thin amorphous silicon layer. The deposition process can also be used to alter the surface morphology of the device layer by creating excess silicon dangling bonds thereon. The silicon comprising cap layer, in one embodiment, is less than about 30A thick, preferably less than about lOA thick, and more preferably less than about 3A thick. Typically, the process duration is about a range of 0.1 to 120 sec.

The process for forming the cap can be performed in the same process as the formation of the device layer (i.e., in-situ) . For in-situ processes, the flow of gases that are not needed for forming the cap layer into the chamber are turned off. The reactor power remains on and the flow of gases that are needed such as the silicon precursor and dilute (e.g., He) gases remain on or are turned on. For example, after forming a silicon oxynitride device layer by PECVD, the oxygen gas sources such as N₂0 or 0₂ are turned off while the RF plasma power, silicon precursor gas and dilute gas remain on to form the cap layer. The duration of the process is typically about 0.1 - 120 sec.

The gas flow rates, power settings, pressure, and other parameters can be gradually adjusted after the end of the formation of the device layer to the desired levels for forming the cap layer. A stabilization step can be performed prior to the commencement of the formation of the cap layer to stabilize gas flow rates. This is particularly useful when the gas flow regimes are different for the different processes.

Examples

Fig. 2 shows a SEM of a resist layer 270 formed over a silicon oxynitride ARC 230 without the silicon comprising cap layer as described. The resist was patterned to form openings 210. As seen from the SEM, the resist profile narrows at the bottom of the opening. This phenomenon is referred to as footing. Footing occurs as a result of resist poisoning from the oxynitride ARC. Footing is undesirable as it distorts the dimensions of the features that are to be formed.

Referring to Fig. 3, a silicon comprising cap layer 320 in accordance with one embodiment of the invention is provided between a resist layer 370 and a silicon oxynitride ARC 370. Openings 310 were formed in the resist. The resist profile shows that the dimensions at the top and bottom of the openings are about the same, indicating that resist poisoning is avoided by the use of the silicon cap layer.

While the invention has been particularly shown and described with reference to various embodiments, it will be recognized by those skilled in the art that modifications and changes may be made to the present invention without departing from its scope. The scope of the invention should therefore be determined not with reference to the above description but with reference to the appended claims along with their full scope of equivalents .

Claims

What is claimed is:

1. In the fabrication of devices, a method for reducing resist poisoning comprising: providing a substrate with a device layer; depositing a cap layer comprising silicon on the device layer; and depositing a resist layer over the cap layer.

2. The method of claim 1 wherein the device layer comprises an anti-reflective coating (ARC) .

3. The method of claim 2 wherein the device layer comprises an inorganic ARC.

4. The method of claim 4 wherein the inorganic ARC comprises a dielectric ARC.

5. The method of claim 4 wherein the dielectric ARC is selected from a group consisting of

6. The method of claim 3 wherein the inorganic ARC is selected from a group consisting

7. The method of claim 1 wherein the device layer comprises a dielectric layer.

8. The method of claim 7 wherein the device layer is selected from a group consisting of

9. The method of claim 1, 2, 3, 4, 5, 6, 7, or 8 wherein the cap layer comprises a silicon-rich layer.

10. The method of claim 9 wherein the cap layer comprises an amorphous silicon layer.

11. The method of claim 10 wherein the cap layer is thin to avoid interference.

12. The method of claim 11 wherein the cap layer comprises a thickness of less than about 30A

13. The method of claim 11 wherein the cap layer comprises a thickness of less than about lOA

14. The method of claim 11 wherein the cap layer comprises a thickness of less than about 3A

15. The method of claim 1, 2, 3, 4, 5, 6, 7, or 8 wherein forming the cap layer comprises forming excess dangling silicon bonds on the surface of the device layer.

16. The method of claim 15 wherein the excess dangling silicon bonds are formed by altering the surface morphology of the device layer.

17. The method of claim 15 wherein the cap layer is formed with in-situ process.

18. The method of claim 17 further comprises a stabilization step prior to forming the cap layer to stabilize flow of gases into a reaction chamber.

19. The method of claim 18 wherein forming the cap layer comprises leaving the reactor power and flow of silicon precursor and dilute gases while turning off flow of other gases after formation of the device layer.

20. The method of claim 17 wherein forming the cap layer comprises leaving the reactor power and flow of silicon precursor and dilute gases while turning off flow of other gases after formation of the device layer.

21. The method of claim 15 wherein forming the cap layer comprises : introducing silicon precursor and dilute gases into a reaction chamber; and causing a reaction to form the silicon cap layer.

22. The method of claim 1 wherein the cap layer is formed with in-situ process.

23. The method of claim 22 further comprises a stabilization step prior to forming the cap layer to stabilize flow of gases into a reaction chamber.

24. The method of claim 23 wherein forming the cap layer comprises leaving the reactor power and flow of silicon precursor and dilute gases while turning off flow of other gases after formation of the device layer.

25. The method of claim 22 wherein forming the cap layer comprises leaving the reactor power and flow of silicon precursor and dilute gases while turning off flow of other gases after formation of the device layer.

26. The method of claim 1 wherein forming the cap layer comprises : introducing silicon precursor and dilute gases into a reaction chamber; and causing a reaction to form the silicon cap layer.

27. The method of claim 9 wherein the cap layer is formed with in-situ process.

28. The method of claim 27 further comprises a stabilization step prior to forming the cap layer to stabilize flow of gases into a reaction chamber.

29. The method of claim 28 wherein forming the cap layer comprises leaving the reactor power and flow of silicon precursor and dilute gases while turning off flow of other gases after formation of the device layer.

30. The method of claim 27 wherein forming the cap layer c3omprises leaving the reactor power and flow of silicon precursor and dilute gases while turning off flow of other gases after formation of the device layer.

31. The method of claim 9 wherein forming the cap layer comprises : introducing silicon precursor and dilute gases into a reaction chamber; and causing a reaction to form the silicon cap layer.

32. The method of claim 10 wherein the cap layer is formed with in-situ process.

33. The method of claim 32 further comprises a stabilization step prior to forming the cap layer to stabilize flow of gases into a reaction chamber.

34. The method of claim 33 wherein forming the cap layer comprises leaving the reactor power and flow of silicon precursor and dilute gases while turning off flow of other gases after formation of the device layer.

35. The method of claim 32 wherein forming the cap layer comprises leaving the reactor power and flow of silicon precursor and dilute gases while turning off flow of other gases after formation of the device layer.

36. The method of claim 10 wherein forming the cap layer comprises : introducing silicon precursor and dilute gases into a reaction chamber; and causing a reaction to form the silicon cap layer.

37. The method of claim 11 wherein the cap layer is formed with in-situ process.

38. The method of claim 37 further comprises a stabilization step prior to forming the cap layer to stabilize flow of gases into a reaction chamber.

39. The method of claim 38 wherein forming the cap layer comprises leaving the reactor power and flow of silicon precursor and dilute gases while turning off flow of other gases after formation of the device layer.

40. The method of claim 37 wherein forming the cap layer comprises leaving the reactor power and flow of silicon precursor and dilute gases while turning off flow of other gases after formation of the device layer.

41. The method of claim 11 wherein forming the cap layer comprises : introducing silicon precursor and dilute gases into a reaction chamber; and causing a reaction to form the silicon cap layer.

42. The method of claim 1 wherein the device comprises an integrated circuit.

43. The method of claim 1 wherein the device comprises memory integrated circuit.