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WO1999048145A1 - Semiconductor device, method for manufacturing the same, and mounting structure of the same - Google Patents

Semiconductor device, method for manufacturing the same, and mounting structure of the same Download PDF

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Publication number
WO1999048145A1
WO1999048145A1 PCT/JP1998/001182 JP9801182W WO9948145A1 WO 1999048145 A1 WO1999048145 A1 WO 1999048145A1 JP 9801182 W JP9801182 W JP 9801182W WO 9948145 A1 WO9948145 A1 WO 9948145A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor chip
wiring board
semiconductor device
lead
main surface
Prior art date
Application number
PCT/JP1998/001182
Other languages
French (fr)
Japanese (ja)
Inventor
Ltd. Hitachi Yonezawa Electronics Co.
Noriyuki Takahashi
Seiichi Ichihara
Chuichi Miyazaki
Original Assignee
Hitachi, Ltd.
Hitachi Microcomputer System, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Microcomputer System, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1998/001182 priority Critical patent/WO1999048145A1/en
Priority to KR1020007007869A priority patent/KR20010034214A/en
Priority to US09/381,232 priority patent/US20020149027A1/en
Publication of WO1999048145A1 publication Critical patent/WO1999048145A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73269—Layer and TAB connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Definitions

  • the present invention relates to a semiconductor device, a method of manufacturing the same, and a mounting structure of the semiconductor device.
  • the present invention relates to a semiconductor device, a manufacturing method thereof, and a mounting structure of the semiconductor device, and is applied to a BGA (Ba 11 Grid Array) type semiconductor device using a tape technology, a manufacturing method thereof, and a mounting structure of the semiconductor device. And effective technology.
  • BGA Bit 11 Grid Array
  • the latest logic devices are required to have higher speed and more functions by increasing the operating frequency and increasing the number of bits of signals.
  • the package size of an existing package such as a package using a lead frame
  • the package size increases.
  • the ratio of the area occupied by the package to the mounting board increases.
  • many multimedia devices such as communication devices, notebook computers, camera-integrated VTRs, and digital cameras, have overwhelming devices that pursue smaller size and lighter weight while having many functions. Often.
  • a through hole is provided in a base film member supporting a semiconductor chip inside, and an external connection electrically connected to a lead on the base film at the position of the through hole.
  • the connecting electrode member 54 is provided so as to project vertically from the front and back surfaces of the base film.
  • a semiconductor device is characterized in that a metal plate 55 is mounted on the upper external connection electrode member 54 and the lower external connection electrode member is used for connection to a mounting substrate.
  • the planar dimensions of the package are reduced, but the thickness of the package is not reduced in thickness.
  • the present inventors have pointed out that the BGA type packages shown in the first to third technologies are not enough to improve the thickness of the package.
  • An object of the present invention is to provide a semiconductor device having a thin package structure having a multi-pin compatible package and a method of manufacturing the same.
  • Another object of the present invention is to provide a semiconductor device having a package structure that is thin and has good heat dissipation characteristics and that is compatible with multiple pins and a method of manufacturing the same.
  • Another object of the present invention is to provide a semiconductor device mounting structure that can be reduced in size and weight.
  • a semiconductor device characterized by the above-mentioned.
  • a semiconductor chip a wiring board provided to surround the semiconductor chip, a lead projecting from the wiring board and connected to the semiconductor chip, and a reinforcement provided on one main surface of the wiring board and surrounding the semiconductor chip.
  • a member, a plurality of bumps provided along a peripheral edge of the wiring substrate on another main surface of the wiring substrate opposite to the one main surface on which the reinforcing member is provided, and the semiconductor chip and the lead.
  • a semiconductor device comprising a resin, wherein the semiconductor chip and a lead connected thereto are accommodated in a total thickness of the wiring board, the reinforcing member, and a plurality of bumps.
  • a semiconductor device characterized by the above-mentioned.
  • a strip-shaped tape having a resin substrate, a device hole provided in the substrate, and a lead of a copper foil protruding from the device hole and being bent; and connected to one main surface of the tape so as to surround the device hole. Connecting the bent lead projecting into the device hole of the tape to the main surface of the semiconductor chip, and sealing the semiconductor chip and the lead with a resin.
  • a method of manufacturing a semiconductor device comprising: connecting a plurality of bumps to another main surface of the tape opposite to the one main surface to which the reinforcing member is connected.
  • a printed circuit board having one main surface and another main surface facing the one main surface, and a mounting structure for mounting a plurality of semiconductor devices on one main surface and the other main surface of the print substrate,
  • a semiconductor chip a wiring board provided to surround the semiconductor chip, a lead projecting from the wiring board and connected to the semiconductor chip, and a main surface provided on one main surface of the wiring board.
  • a reinforcing member surrounding the semiconductor chip a plurality of bumps provided along a periphery of the wiring substrate on another main surface of the wiring substrate opposite to the one main surface on which the reinforcing member is provided; And a resin covering the leads, wherein the semiconductor chip and the resin are accommodated in a total thickness of the wiring board, the reinforcing member, and the plurality of bumps.
  • Semiconductor equipment Mounting structure characterized in that it is so.
  • the position of the semiconductor chip when the semiconductor device is viewed from the side can be arranged as close to the center of the semiconductor device as possible. A device can be obtained.
  • a semiconductor device that is thin and has a high heat dissipation characteristic and that can handle a large number of pins can be obtained. Further, according to the above-described mounting structure, a mounting structure that can be reduced in size, weight, and thickness can be obtained.
  • FIG. 1 is a plan view (front side) of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1 taken along the line AA ′.
  • FIG. 3 is a plan view showing a wiring board used in the semiconductor device of Embodiment 1 of the present invention.
  • FIG. 4 is an enlarged view of a portion A of the wiring board of FIG.
  • FIG. 5 is a cross-sectional view of the wiring board of FIG. 4 taken along the line BB ′.
  • FIG. 6 is an enlarged sectional view of a main part of FIG.
  • FIG. 7 is an enlarged sectional view of a main part showing a first other example of the semiconductor device of FIG.
  • FIG. 8 is an enlarged sectional view of a main part showing a second other example of the semiconductor device of FIG.
  • FIG. 9 is a plan view (back side) of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 10 is an enlarged view of a mouth portion of the semiconductor device of FIG.
  • FIG. 11 is a cross-sectional view taken along line CC ′ of FIG.
  • FIG. 12 is a cross-sectional flow chart showing one example of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 13 is a plan view showing an example of a tape used in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 14 is a plan view of the tape of FIG. 13, (a) is an enlarged plan view of a main part, and (b) is a cross-sectional view taken along the line D-D 'of (a).
  • FIG. 15 is a partially enlarged view showing a first other example of the tape used in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 16 is a partially enlarged view showing a second other example of the tape used in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIGS. 17 (a) and 17 (b) are partial cross-sectional views showing an example of offset processing.
  • FIGS. 18A and 18B are partial cross-sectional views illustrating an example of the lead bonding method.
  • FIG. 19 is a conceptual diagram showing an example of the potting method.
  • FIG. 20 is a plan view showing the tape after the sealing step has been completed.
  • FIGS. 21A and 21B are plan views showing an example in which the semiconductor device of the first embodiment is mounted on a printed circuit board for a memory card, and FIG. 21A is a plan view of one surface side.
  • Replacement form (Rule 26) (B) is a plan view of the other side opposite thereto.
  • FIG. 22 is a partially transparent plan view showing a memory card in which the printed circuit board for memory card of FIG. 21 is housed in a case.
  • FIG. 23 is a cross-sectional view of the memory card of FIG. 22 taken along the line EE ′.
  • FIG. 24 is a cross-sectional view of the memory card of FIG. 22 taken along the line FF ′.
  • FIG. 25 is a plan view showing an example in which the semiconductor device of the first embodiment is mounted on a printed circuit board for a multimedia device.
  • FIG. 26 is a plan view showing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 27 is a cross-sectional view of the semiconductor device of FIG. 26 taken along the line GG ′.
  • FIG. 28 is an enlarged sectional view of a main part of FIG.
  • FIG. 29 is a cross-sectional view showing an example in which the semiconductor device of the second embodiment is mounted on a printed circuit board together with another semiconductor device.
  • FIG. 30 is a cross-sectional flowchart showing an example of the method for manufacturing a semiconductor device in the second embodiment.
  • FIG. 31 is a plan view showing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 32 is a cross-sectional view of the semiconductor device of FIG.
  • FIG. 33 is an enlarged sectional view of a main part of FIG.
  • FIG. 34 is a cross-sectional view showing an example of the semiconductor device according to the third embodiment in which heat radiation fins are mounted on the heat radiation plate.
  • FIG. 35 is a cross-sectional flowchart showing an example of the method for manufacturing a semiconductor device of the third embodiment.
  • FIG. 36 is a cross-sectional view showing a first conventional technique.
  • FIG. 37 is a sectional view showing a second conventional technique.
  • FIG. 38 is a flowchart showing an assembling process of the third conventional technique.
  • the semiconductor device includes, as external terminals of the semiconductor device, a plurality of ball-shaped solder bumps arranged on one main surface (hereinafter, referred to as a back surface) of the semiconductor device.
  • This is a BGA type semiconductor device that uses tape technology to connect to external terminals.
  • the semiconductor device 1 includes a plurality of aligned ball-shaped solder bumps as external terminals for connection to a mounting board (not shown). It has nine.
  • the ball-shaped solder bumps 9 are formed on a frame-shaped wiring board 4 having a base material 10 made of polyimide resin and leads 7 which are copper foil wirings formed thereon.
  • a base material 10 made of polyimide resin and leads 7 which are copper foil wirings formed thereon.
  • the material of the base material 10 polyimide resin, glass epoxy, BT (Bismaleimide-Triazine) resin, PET (Polyetehylenenetterphthatal), or the like is used.
  • a semiconductor chip is provided in a plane to improve the mechanical strength of the semiconductor device 1.
  • a frame-shaped reinforcing member with a hole that can be accommodated and having a thickness of about 200 ⁇ m (hereinafter referred to as “stiffener 3”) 1S Adhesive made of epoxy resin and having a thickness of about 50 ⁇ along the periphery of the wiring board 4 1 Connected by 1.
  • a polyimide resin may be used in addition to the epoxy resin.
  • the material of the stiffener 3 preferably has a thermal expansion coefficient close to that of the mounting substrate on which the semiconductor device 1 is mounted.
  • a thermal expansion coefficient close to that of the mounting substrate on which the semiconductor device 1 is mounted.
  • Cu or a Cu alloy containing Cu as a main component, or an 81-1 alloy, or an iron-based material Alloys and ceramics are good.
  • the shape is not limited, as long as it can surround the semiconductor chip 2 as shown in FIG.
  • the semiconductor chip 2 includes, for example, a predetermined integrated circuit such as a microcomputer and an AS IC and terminals for external connection of these circuits on one main surface of a semiconductor substrate such as silicon having a thickness of about 400 to 550 ⁇ m.
  • a pad (not shown) made of a material such as A1 is provided.
  • a passivation film for protecting the integrated circuit is formed on the uppermost layer of the integrated circuit formation surface.
  • the passivation film is made of, for example, a polyimide resin having a thickness of about 2 to 10 m.
  • An opening is formed in the passivation film, and an Au bump 8 connected to the pad is formed in the opening.
  • the diameter of the Au bump 8 is about 14 to 35 / zm.
  • the Au bumps 8 are formed by plating bumps or wire bumps. Note that the Au bump 8 may be formed on the lead 7 side of the wiring board 4.
  • Such a semiconductor chip 2 is arranged with the main surface on which the integrated circuit and the Au bump 8 are formed facing the back side of the semiconductor device 1, that is, the side on which the solder bump 9 is formed, as shown in FIG.
  • the lead 7 which is protruded from the wiring board 4 and connected to the back surface of the semiconductor device 1, that is, the side on which the solder bump 9 is formed, has been bent (offset) in advance.
  • the main surface, side surfaces and leads 7 on which the integrated circuits of the semiconductor chip 2 are formed are intended to protect the semiconductor device 1, improve the moisture resistance, and improve the reliability of the joint between the lead 7 and the semiconductor chip 2. It is sealed with a sealing resin 5 for the purpose.
  • a sealing resin 5 for the purpose.
  • the resin 5 a silicone resin, an epoxy resin, or the like is used.
  • the total thickness t 1 of the solder bump 9, the wiring board 4, and the reinforcing material 3 is larger than the total thickness t 2 of the semiconductor chip 2 and the sealing resin 5. (T 1> t 2).
  • the total thickness t 1 of the solder bump 9, the wiring board 4, and the reinforcing material 3 includes the total thickness t 2 of the semiconductor chip 2 and the sealing lug 5. ing.
  • the above-mentioned wiring board 4 is a member for electrically connecting the Au bumps 8 and the solder bumps 9 of the semiconductor chip 2, and the wiring board 4 is provided at the center as shown in the plan view of FIG. A penetrating device hole 14 is provided, and a device hole 14 having a structure capable of accommodating the semiconductor chip 2 is used.
  • the wiring board 4 has a thickness of 50 to: about 125 ⁇ m, preferably 75 ⁇ 8 ⁇ , and a base 10 having a thickness of 12 to A lead 7 of an arbitrary wiring pattern and a bumper having a circular planar shape formed of copper foil of about 30 ⁇ m, preferably 18 ⁇ 2 ⁇ m
  • the lead 7 and the bump land 12 are adhered to the substrate 10 with an adhesive (not shown) having a thickness of about 12 ⁇ 4 ⁇ m. .
  • the leads 7 and the bump lands 12 are covered with a light-sensitive insulating film 6 such as a solder resist.
  • the photosensitive insulating film 6 is, for example, an insulating film having a thickness of about 5 to 30 ⁇ m, preferably 20 ⁇ m, and is made of a material such as melamine, acrylic, polystyrene, polyimide, polyurethane, and silicone. It has the heat resistance to withstand the soldering temperature, does not wet the solder, prevents the deterioration of the wiring board due to moisture and contamination, and has the property to withstand exposure to flux and cleaning liquid. Is preferred.
  • the bump land portions 12 are regularly arranged along the outer edge of the wiring board 4.
  • the bump lands having a diameter of 310 / im are arranged at a pitch of 500 / xm (interval) along the periphery of the wiring board 4, and the rows on the peripheral side and the rows on the inner side thereof. Are arranged in two rows.
  • the diameter, pitch, and arrangement of the bump land portions differ depending on the product, and are not necessarily limited thereto.
  • the diameter is 300 to 500 ⁇
  • the pitch is 500 to 800 / zm.
  • the arrangement pattern may be regularly arranged in two rows, three rows, or irregularly. As shown in FIGS.
  • solder bump is connected to 1 2.
  • fine processing can be performed, a small opening can be formed, and the solder bump can be reduced in size.
  • the opening in the photosensitive insulating film 6 on the base material 10 may be formed by a mechanical processing method such as a punch.
  • a mechanical processing method such as a punch.
  • the diameter of the opening is limited. Therefore, it is not suitable for fine processing.
  • the photosensitive insulating film is omitted for convenience.
  • a part of a lead 7 which is a wiring pattern formed of a copper foil projects from the device hole 14 of the wiring board 4.
  • the positions of the protruding leads are substantially in the same plane, and this plane is referred to as a lead protruding plane.
  • the semiconductor chip 2 has a main surface on which an integrated circuit and Au bumps 8 are formed, and a semiconductor device.
  • the leads 7 and A are arranged in the device hole 14 with the lead 7 facing the back surface side of 1, that is, the side on which the solder bump 9 is formed (hereinafter referred to as “face-down”).
  • u Bump 8 is electrically connected.
  • FIG. 6 is an enlarged cross-sectional view of a main part of FIG. 2.
  • each lead 7 protruding into the device hole 14 is connected to the back side of the semiconductor device 1, namely, the solder bump 9.
  • a second bent portion 16 bent so as to provide a region parallel to the element formation surface is referred to as an offset structure.
  • the offset amount (the distance between the first bent portion 15 and the second bent portion 16, in other words, the lead 7 on the base material 10) Let T be the distance between the position and the position of the lead 7 displaced by the first bent portion 15.
  • connection between each of the leads 7 and the Au bump 8 is performed in a region from the second bent portion 16 to the tip of the lead 7.
  • the offset structure and the offset amount T are set to 125 m so that the semiconductor device 1 has the thinnest structure in consideration of the thickness of the semiconductor chip and the diameter of the solder bump.
  • the offset amount T and the offset structure depend on the thickness of the semiconductor chip, the diameter of the solder ball, and the like, and vary depending on the product, and are not necessarily limited to these.
  • the second bent portion 16 gradually approach the element forming surface of the semiconductor chip, in other words, the second bent portion from the connection portion with the Au bump 8. It may be configured so as to have an inclination K that gradually moves away from the element formation surface of the semiconductor chip toward the portion 16. By doing so, it is possible to prevent contact (hereinafter referred to as edge short) between the lead and the peripheral portion of the element formation surface of the semiconductor chip on which the passivation film is not easily applied.
  • a first bent portion 15 is formed by bending the vicinity of the wiring board from the lead protruding direction to the back side of the semiconductor device, and a semiconductor chip is provided on the lead end side from the first bent portion 15. Folded so as to have a first region parallel to the element formation surface of
  • the second, third, and fourth bent portions are formed so as not to reach the position of the lead 7 on the base material 10 so that the offset amount is secured. You.
  • such a semiconductor device has bump bumps 12 exposed through openings formed in the solder resist of the wiring board 4 as terminals for connection with the mounting board.
  • the solder bump 9 is connected.
  • the solder bump 9 is a ball-shaped bump made of a material such as an alloy containing Pb—Sn, Pb—Sn, etc. as a main component and having a diameter of about 300 // m.
  • a position corresponding to the land portion 12 it is arranged at a pitch of 500 along the periphery of the wiring board 4 over two rows of a row on the peripheral side and a row on the inner side.
  • the opening of the solder resist can be formed small, and the balls of the solder bumps 9 can be made small, so that the semiconductor device can be made thin.
  • the material, diameter, pitch, and arrangement pattern of the solder bumps differ depending on the product, and are not necessarily limited to this.
  • the diameter is 300 to 5001
  • the pitch is 500 to 800.
  • the arrangement pattern may be arranged regularly in two or three rows, or even irregularly.
  • a base material 10 made of polyimide resin and an arbitrary wiring pattern formed of copper foil on one main surface of the base material 10 are formed.
  • a tape obtained by processing the tape 19 and cutting it into pieces is called a wiring board 4) and a stiffener 3 having a hole capable of receiving a semiconductor chip in a plane.
  • FIG. 14 (a) is an enlarged plan view of a main part of FIG. 13, and FIG. 14 (b) is a cross-sectional view taken along the line DD ′ in FIG. 14 (a).
  • the lead before processing is formed by integrally connecting the tips on the same plane as the wiring on the base material 10.
  • a lead 7 projecting from the base material 10 of the tape 19 to the device hole 14 is placed on the side of the tape 19 where the solder bumps 9 are formed. Bend it.
  • the lead 7 before processing is formed such that its tips are integrally connected to the same plane as the wiring on the base material 10. As a result, it is possible to suppress variations in the lead end.
  • the tips of the leads connected integrally may be reinforced with a fixing member 21 such as a tape.
  • the base material 10 extends to near the tip of the protruding lead, and the extended base material 10 has four cuts so that the lead can be bent.
  • a shape provided with 22 may be used.
  • the leads are made longer so that semiconductor chips with different external dimensions can be connected. In this way, even if it is necessary to change the leading end position of the lead in accordance with the external dimensions of the semiconductor chip, it is possible to sufficiently cope with the situation. There is no need to prepare a pump.
  • this lead is performed as follows. First, as shown in FIG. 17 (a), it is inserted between a die 24, which is a lead forming jig, and a punch 23 in a state where they are aligned in a plane. Thereafter, as shown in FIG. 17 (b), the die 24 and the punch 23 are vertically dropped with respect to the lead 7 while maintaining the alignment state, and are pressed into a predetermined shape, and the lead is formed. The tip of 7 is cut by a cutting punch 25 into a length suitable for a semiconductor chip. The leading ends of the connected leads are divided into individual parts.
  • this processing is referred to as offset processing, and this step is referred to as a lead offset step.
  • a tape may be prepared in which the leads have been offset-processed in advance (step a).
  • step finner 3 is epoxied along the periphery of the device hole on the base material 10 of the strip-shaped tape 19 processed in the lead offset process. Adhesively bond through the adhesive 1 1 Hereinafter, this step is referred to as a stiffener bonding step (step b).
  • Au bumps 8 are formed on the pads formed on one main surface of the semiconductor chip 2 by, for example, a ball bonding method.
  • the bumps may be formed by plating.
  • this step is referred to as an Au bump formation step (step c).
  • the Au bumps 8 on the semiconductor chip 2 and the leads 7 are electrically connected.
  • the semiconductor chip 2 is mounted on the bonding stage 27 so that the surface of the semiconductor chip 2 on which the Au bumps 8 are formed faces upward.
  • the tape 19 is positioned on the semiconductor chip 2 such that the leads 7 projecting from the base material 10 of the tape 19 and the Au bumps 8 of the semiconductor chip 2 face each other.
  • the semiconductor chip 2 and the tape 19 are aligned so that the positions of the bumps 8 and the connection portions near the ends of the leads 7 of the tape 19 match. At this time, it is preferable that the distance between each lead 7 and the Au bump 8 be as close as possible.
  • the tape 19 is aligned so that the surface on which the stiffener 3 is formed is on the semiconductor chip 2 side.
  • the bonding tool 26 is fixed to the semiconductor chip 2 with the tape 19 fixed by a tape guide (not shown) while maintaining the above positional relationship.
  • the lead 7 and the Au bump 8 are pressed and joined by vertically falling down on the main surface side of the substrate (hereinafter, referred to as a collective bonding method).
  • the pressing amount by the tool is equal to or smaller than the diameter of the Au bump. In this batch bonding method, bonding can be performed in a single operation even when the number of pins is large, so that the time required for bonding is short regardless of the number of pins.
  • the leads 7 and the Au bumps 8 are uniformly heated and pressed. For that purpose, the flatness of the lead 7 must be ensured.
  • the tip of each lead 7 is formed integrally, and the lead offset is added.
  • step d By dividing each lead together with the lead, it is possible to suppress variations in each lead and maintain flatness.
  • this step is referred to as a lead bonding step (step d).
  • step e the main surface, side surfaces, and the leads 7 on which the integrated circuits of the semiconductor chip 2 are formed are sealed with a liquid resin 5 by a potting method.
  • the sealing resin 5 is dropped by a possible dispenser 28 to seal the main surface, the side surfaces, and the leads 7 of the semiconductor chip 2.
  • this step e this step is referred to as a sealing step (step e).
  • a bump land portion exposed through an opening formed in the photosensitive insulating film of the tape 19 is formed of a material such as Pb—Sn.
  • the ball-shaped solder bump 9 is connected.
  • the solder bumps are aligned with the bump land portion in a planar manner, and are adsorbed by a mounting jig (not shown).
  • a flux is applied to the solder bumps adsorbed by the mounting jig, and the mounting jig is mounted.
  • the solder bumps 9 to which the flux has been applied are collectively connected to the bump lands of the semiconductor device.
  • this step is referred to as a solder bump mounting step (step f).
  • Step g the strip-shaped tape 19 as shown in FIG. 20 where the solder bump mounting process is completed is cut at a position slightly outside the peripheral edge of each stiffener 3. As a result, the semiconductor device is punched into individual pieces. Hereinafter, this step is referred to as a cutting step. (Step g)
  • the method of connecting the leads 7 and the Au bumps 8 in the lead bonding step (step d) is not limited to the batch bonding method.
  • the semiconductor chip is mounted on a bonding stage heated by a heater. Heating, applying ultrasonic waves and weight to the bonding tool, and connecting the leads and Au bumps of the semiconductor chip one point at a time (hereinafter, single point bonding method) may be used.
  • the bonding rules are different for each type of semiconductor chip,
  • the sealing method in the sealing step (step e) is not limited to the potting method, and may be performed by transfer molding.
  • the transfer molding method first, a tape in which a semiconductor chip is connected to an offset-processed lead is formed between a first mold and a second mold for molding, and the semiconductor chip is formed on each mold surface. The first mold and the second mold are then clamped, and the sealing resin is poured into the cavity via a gate to seal the semiconductor chip and leads. Is the way.
  • the resin plays a role of a stiffener which is a reinforcing member of a semiconductor device. Therefore, the manufacturing cost of the semiconductor device is reduced.
  • Figure 21 is a plan view of a case of mounting the semiconductor device 1 of the first embodiment on the printed board 29 for a small memory force one de, of FIG (a) is a plan view of one side, (b) is a plan view of the other surface on the opposite side.
  • the semiconductor device 1 of the first embodiment of the present invention As shown in (a) of the figure, on one surface of the printed circuit board 29, the semiconductor device 1 of the first embodiment of the present invention and a tape carrier package (TCP) or a thin small output device (TSOP) are provided.
  • the memory 30 using a thin package such as a line package is mounted.
  • a plurality of memories 30 using the same thin package as described above are mounted on the other surface of the printed circuit board 29.
  • a crystal oscillator 33 and a plurality of chip components 32 such as a chip capacitor and a chip resistor are mounted.
  • the printed circuit board 29 is connected to the printed circuit board socket 34 through the external terminals 31, and the printed circuit board socket 34 and the printed circuit board 29 are housed in the case 35 and a small memory capacity is provided.
  • FIG. 23 is a cross-sectional view of the memory card 36 of FIG. 22 taken along the line EE ′
  • FIG. 24 is a cross-sectional view of the memory card 36 of FIG. 22 taken along the line FF ′.
  • the semiconductor device 1 of the first embodiment used for the small memory card 36 is an integrated circuit (microcomputer) for controlling the memory 30 and controlling the exchange of data between the host microcomputer and the memory 30. And an integrated circuit having functions such as a gateway).
  • the memory 30 formed on one side of the printed circuit board 29 and the other side is a non-volatile memory for semi-permanently storing data and a volatile memory used for storing a control program for a memory card.
  • the non-volatile memory include a flash memory, an E-PROM (Ele c t r i c a l l y y E r a s a b l e a n d
  • ProgrammabLeReadOnLyMemory ProgrammabLeReadOnLyMemory
  • EPR ⁇ M ErasablEndAmProgRammamBleEReDOn1yMemory
  • a mask ROM and the like are used.
  • the volatile memory DRAM, SRAM, or the like is used.
  • the solder bumps 9 on the back surface of the semiconductor device 1 of the first embodiment are electrically connected to wiring (not shown) on the printed circuit board 29. Further, the leads of the TCP or TSOP type memory 30 are electrically connected to the wiring on the printed circuit board 29.
  • two semiconductor devices 1 of the first embodiment are used, one is a microcomputer having one function, and the other is a microcomputer having a function of a gate. Alternatively, two semiconductor devices 1 of the first embodiment may be mounted. In this case, one of the plurality of memories 30 mounted on the other surface of the printed circuit board 29 is a non-volatile memory, and the other is a volatile memory.
  • Such a memory card 36 is implemented as a control-type semiconductor device (a microcomputer single-gate array or a device having both of these functions), which is a high-performance and multi-pin semiconductor device that has conventionally been difficult to reduce in thickness.
  • the memory card 36 can be reduced in size and weight and can be significantly reduced in thickness.
  • the semiconductor device 1 of the first embodiment is a surface mount type, other surface mount type semiconductor devices such as a TCP type, a TSOP type, and a UT SOP type.
  • Replacement form (Rule 26) In addition, it can be mounted on the same mounting board and reflowed collectively, which facilitates mounting.
  • Such a small memory card 36 is very useful if used as, for example, a compact memory card used in digital cameras and the like.
  • FIG. 25 is a plan view showing an example in which the semiconductor device 1 of the first embodiment is mounted on a printed circuit board 39 for multimedia equipment.
  • the semiconductor device 1 according to the first embodiment is one in which an integrated circuit such as a microcomputer or a gate array is formed.
  • the solder bumps 9 on the back surface of the semiconductor device of the first embodiment are electrically connected to the wiring on the printed circuit board 38.
  • the leads of the semiconductor device 37 of the QFP, TCP or TSP type are electrically connected to the wiring on the printed circuit board 39.
  • the printed circuit board 39 by using a plurality of the semiconductor devices 1 of the first embodiment, the mounting density is improved, and the area and the weight of the printed circuit board 39 can be reduced.
  • Such a small printed circuit board 39 is incorporated in devices such as a camera-integrated VTR and a notebook computer, and greatly contributes to high performance, portability, and weight reduction of products.
  • the semiconductor device 1 of the first embodiment is a surface mount type, it can be mounted on a mounting board together with another surface mount type semiconductor device such as a QFP, TCP type, or TSOP type and reflowed collectively. Easy to implement.
  • the position of the semiconductor chip can be arranged as close to the center of the semiconductor device 1 as possible. That is, the total thickness of the solder bump 9, the wiring board 4, the lead 7 on the wiring board 4, the stiffener 3, and the adhesive 11
  • the semiconductor device 1 can be configured so that the semiconductor chip 2 and the Au bumps 8 and the leads 7 connected to the Au bumps 8 can be accommodated therein, and the semiconductor device 1 can be made thinner.
  • diameter of solder bump 9 300 ⁇
  • wiring board 4 87 ⁇
  • thickness of lead 7 18 Mm
  • stiffener 3 200 / im
  • adhesive 1 1 50 ⁇ m
  • the thickness of the semiconductor chip 2 400 / zm
  • the height of the Au bump 35 ⁇ m
  • the thickness of the semiconductor device 1 is 655.5 ⁇ m.
  • the semiconductor device of the first embodiment since the thickness of the final structure of the semiconductor device can be made extremely thin by setting the leads to the offset structure, the thin and multi-pin structure is achieved. Accordingly, it is possible to obtain a semiconductor device compatible with the chemical conversion.
  • a tape 19 having a lead 7 of a wiring pattern formed on a base material 10 such as polyimide resin is used. There is an advantage that it can be performed at low cost.
  • solder bumps 9 for connection between the semiconductor device 1 and the mounting board are connected to the lead 7 forming surface side of the wiring board 4, there is no need to form through holes and multilayer wiring, and the Manufacturing can be performed at low cost.
  • solder bumps 9 for connecting the semiconductor device 1 to the mounting board are arranged two-dimensionally on the back surface of the semiconductor device 1, the number of pins can be increased without increasing the area of the semiconductor device. It becomes possible.
  • the lead 7 can be offset-processed with high accuracy by offsetting the lead 7 in a member state.
  • the length of the lead 7 of the wiring board 4 is made longer and the tip is cut according to the outer dimensions of the semiconductor chip 2, so that semiconductor chips with different outer dimensions can be supported. The manufacturing cost of the semiconductor device 1 is reduced.
  • the mounting structure for mounting a semiconductor device on a printed circuit board can be reduced in size, weight, and thickness.
  • the semiconductor device of the second embodiment is a BGA type semiconductor device in which the lead 7 of the wiring board 4 is offset-processed as in the first embodiment, but the difference from the first embodiment is that the lead 7 This is the difference between the offset direction and the direction of the element forming surface of the semiconductor chip 2.
  • the surface opposite to the element forming surface of the semiconductor chip 2 is on the back surface side of the semiconductor device 1, It is incorporated into the semiconductor device 1 in a state facing the solder bump 9 side (hereinafter, referred to as face-up).
  • the lead 7 protruding into the device hole of the wiring board 4 is bent on the front side of the semiconductor device 1 (the side on which the stiffener 3 of the wiring board 4 is formed).
  • the first bent portion 15 and the second bent portion 16 which is bent so that a connection portion parallel to the element forming surface of the semiconductor chip 2 is formed on the lead tip side of the first bent portion 15.
  • the connection surface between the lead 7 and the semiconductor chip 2 is shifted from the surface of the semiconductor device 1 from the projecting plane of the lead 7, that is, from the side where the stiffener 3 is formed, in other words, from the connection portion between the semiconductor chip and the lead.
  • the semiconductor chip 2 is connected face-up to the lead 7 of the semiconductor chip 2 in a direction away from it.
  • the offset amount of the lead 7 is controlled so that the position of the non-element forming surface of the semiconductor chip 2 connected to the lead 7 is not lower than the lowest point of the solder bump 9 as shown in FIG. It is important to configure.
  • FIG. 1 An example in which the semiconductor device 1 of the second embodiment is mounted on a printed circuit board is shown in FIG.
  • the semiconductor device 1 according to the second embodiment is mounted on the surface of the printed circuit board 40 together with the QFP semiconductor device.
  • a tape 19 Prior to the manufacture of the semiconductor device, a tape 19, a stepper 3, a semiconductor chip 2, a sealing resin, a flux, a solder bump, and the like are prepared as in the first embodiment.
  • the lead 7 of the tape 19 is pressed and formed into a predetermined shape by a die and a punch as in the first embodiment, and cut into a length suitable for a semiconductor chip by a cutting punch ( Step a ).
  • the stepper 9 is thermocompressed around the device hole on the base material 10 of the strip-shaped tape 19 processed in the lead offset step via an adhesive 11 such as an epoxy resin. (Step b).
  • the Au bump 8 is formed on a pad formed on one main surface of the semiconductor chip 2 by a method such as a ball bonding method.
  • the bump may be formed by plating (step c).
  • the semiconductor chip 2 is mounted on the bonding stage with the main surface of the semiconductor chip 2 and the surface of the tape 19 facing the photosensitive insulating film facing each other, and a bonding tool is mounted on the main surface of the semiconductor chip 2.
  • step e the main surface, side surfaces, and the leads 7 on which the integrated circuits of the semiconductor chip 2 are formed are sealed with a sealing resin 5 (step e).
  • a ball-shaped bump made of a material such as Pb—Sn is placed on the bump land portion exposed through the opening formed in the photosensitive insulating film of the tape 19.
  • the connection forms a solder bump which is an external electrode of the semiconductor device (step f).
  • the semiconductor device 1 is punched into individual pieces by cutting the belt-shaped tape 19 at a position slightly outside the peripheral edge of the stiffener 3 (step g). After that, a predetermined inspection is performed on the semiconductor device 1 to determine the quality. Thus, the manufacturing process of the semiconductor device 1 is completed.
  • the same effect as the effect (1) described in the first embodiment that is, the position of the semiconductor chip 2 when the semiconductor device 1 is viewed from the side can be set as far as possible.
  • 1 can be placed on the center side of the semiconductor chip 2, Au in the total thickness of solder bump 9, wiring board 4, lead 7 on wiring board 4, stepper 3, adhesive 1 1, Bump 8 and lead 7 connected to Au bump 8
  • a semiconductor device 1 having a complete structure can be configured. Therefore, a thin semiconductor device capable of increasing the number of pins can be obtained.
  • the semiconductor device of the third embodiment is a BGA type semiconductor device in which the leads 7 of the tape wiring board 4 are offset-processed, as in the first and second embodiments.
  • the features of the third embodiment are as follows. The point is that a heat sink 41 for improving thermal characteristics is mounted on the semiconductor device 1.
  • the wiring board 4 is the same as that of the first embodiment, and a device hole penetrating the wiring board 4 is formed in the center thereof, and the semiconductor chip can be accommodated in the device hole. It has become.
  • a plurality of wiring leads 7 made of copper foil protrude from the device hole.
  • Each of the leads 7 is connected to a first bent portion 15 bent on the back side of the semiconductor device 1, that is, on the side on which the solder bump 9 is formed.
  • a second bent portion 16 which is bent so that a connection portion parallel to the element formation surface of the semiconductor chip 2 is formed on the tip end side of the lead from the first bent portion 15.
  • the semiconductor chip 2 is connected to the connection portion of each offset-processed lead 7 by face down.
  • a heat radiating plate 41 for improving heat radiating characteristics is mounted on the upper surface of the stiffener 3 of the wiring board 4 and the non-element forming surface of the semiconductor chip.
  • the offset amount of the lead 7 is set to 125 ⁇ m in consideration of the diameter of the solder bump 9 so that the position of the semiconductor chip 2 is as close to the center of the semiconductor device 1 as possible.
  • This offset amount is not necessarily limited to this, and may be such that the non-element formation surface of the semiconductor chip 2 is located substantially in the same plane as the upper surface of the stepper 3 as shown in FIGS. 32 and 33. What is necessary is just an offset amount.
  • the radiator plate is adhered to the non-element forming surface of the semiconductor chip 2 and the upper surface of the stepper 3 with an epoxy resin adhesive.
  • the material of the heat sink is preferably copper tungsten (Cu-W), which has a coefficient of thermal expansion close to that of the semiconductor chip 2, but Fe-based alloy, mullite, and aluminum nitride, which satisfy the same conditions.
  • a carbon-based material such as diamond may be used.
  • the heat radiating plate 41 greatly contributes to efficiently radiating the heat generated in the semiconductor chip 2 to the outside of the semiconductor device, and can improve the operation reliability and the life of the semiconductor device 1.
  • radiating fins 42 can be mounted on the heat radiating plate 41 to cope with further high heat generation semiconductor devices.
  • the material of the heat radiation fins 42 is preferably aluminum, and the shape is preferably a shape having a large surface area and improving heat radiation characteristics.
  • the material and shape are not necessarily limited to these, and may be selected in consideration of the appropriateness of the semiconductor chip.
  • the main surface, side surfaces and leads on which the integrated circuit of the semiconductor chip is formed are resin for sealing for the purpose of protecting and improving the moisture resistance of the semiconductor device and the reliability of the joint between the lead and the semiconductor chip. Sealed.
  • this resin a silicone resin, an epoxy resin or the like is used.
  • ball-shaped solder bumps 9 are mounted along the outer edge of the tape wiring board 4 as terminals for connection with the mounting board over two rows, an outer row and an inner row. .
  • a tape, a stepper, a semiconductor chip, a sealing resin, a flux, a solder ball, a heat sink, and the like are prepared.
  • the leads of the tape 19 are pressed and formed into a predetermined shape by a die and a punch in the same manner as in the first embodiment, and are cut to a length suitable for the outer shape of the semiconductor chip by a cutting punch (step). a).
  • a stiffener 3 is applied to the band-shaped tape 19 processed in the lead offset process around the device holes on the base material 10 by epoxy resin.
  • Thermocompression bonding is performed via an adhesive 11 such as a fat (step b).
  • an Au bump 8 is formed on the pad formed on one main surface of the semiconductor chip by a method such as a ball bonding method.
  • the bump may be formed by plating (step c).
  • the semiconductor chip main surface and the leads 7 of the tape 19 are mounted on the bonding stage in correspondence with each other, and the bonding tool is dropped vertically to the main surface side of the semiconductor chip 2.
  • the Au bumps 8 of the semiconductor chip and the leads 7 of the tape 19 are heated and pressed to join them (step d).
  • a heat sink is bonded to the non-element forming surface of the semiconductor chip 2 and the upper surface of the stiffener 3 via an adhesive such as an epoxy resin (step e).
  • step f the main surface, side surface and lead of the semiconductor chip on which the integrated circuit is formed are sealed with a sealing resin.
  • solder bump forming step a spherical bump made of a material such as Pb-Sn is connected to the bump land exposed through the opening formed in the solder resist of the tape 19. As a result, solder bumps, which are external electrodes of the semiconductor device, are formed (step g).
  • the band-shaped tape 19 is cut at a position slightly outside the periphery of the stiffener 3, whereby the semiconductor device 1 is punched into a single piece (step h). After that, a predetermined inspection is performed on the semiconductor device 1 to determine the quality. Thus, the assembling process of the semiconductor device is completed.
  • the heat resistance becomes about 1 Z 2 compared to a case where no heat radiating plate or heat radiating fin is mounted, and the heat radiation characteristics of the semiconductor device can be greatly improved.
  • the semiconductor device according to the present invention is useful when applied to a BGA type semiconductor device, and a portable device such as a small memory card or a handy type personal computer using the BGA type semiconductor device, and It is useful when applied to small information communication equipment.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A semiconductor device composed of a semiconductor chip, a wiring board which is provided so as to surround the semiconductor chip, leads which protrude from the wiring board and are connected to the semiconductor chip, a reinforcing member which is provided on one main surface of the wiring board and surrounds the semiconductor chip, a plurality of bumps which are provided along the peripheral edge of the wiring board on the other main surface of the board on the opposite side of the reinforcing member, and a resin which covers the semiconductor chip and the leads. The leads connected to the semiconductor chip are bent toward the surface of the reinforcing member or the surface of the bumps and connected to the semiconductor chip so that the surface opposite to the surface of the semiconductor chip connecting to the leads may be positioned on the side opposite to the side on which the leads are bent.

Description

明細書 半導体装置及びその製造方法並びに半導体装置の実装構造 技術分野  TECHNICAL FIELD The present invention relates to a semiconductor device, a method of manufacturing the same, and a mounting structure of the semiconductor device.
本発明は、 半導体装置とその製造方法並びに半導体装置の実装構造に係わり、 テープ技術を用いた B G A ( B a 1 1 G r i d A r r a y ) 型半導体装置及 びその製造方法並びに半導体装置の実装構造に適用して有効な技術に関する。 背景技術  The present invention relates to a semiconductor device, a manufacturing method thereof, and a mounting structure of the semiconductor device, and is applied to a BGA (Ba 11 Grid Array) type semiconductor device using a tape technology, a manufacturing method thereof, and a mounting structure of the semiconductor device. And effective technology. Background art
最先端のロジックデバイスには、 動作周波数の高周波数化、 信号の多ビット化 により高速化及び多機能化が要求されている。 しかし、 高速化及び多機能化によ り端子数が増加すると、既存のパッケージ例えばリードフレームを用いるパッケ ージではリ一ドフレームの加工の限界により制約をうけパッケージサイズが大 きくなる。 そうすると、 パッケージを実装基板に実装する際に、 実装基板に対し てのパッケージが占領する面積の割合が増加する。 しかし、 近年、 通信機器、 ノ —ト型 .パソコン、 カメラ一体型 V T R、 デジタル.カメラなどのマルチメディ ァ機器の多くは、 多くの機能を持ち併せながら、 小型 ·軽量化を追求した機器が 圧倒的に多い。  The latest logic devices are required to have higher speed and more functions by increasing the operating frequency and increasing the number of bits of signals. However, as the number of terminals increases due to the increase in speed and the number of functions, the package size of an existing package, such as a package using a lead frame, is limited by the limitations of the lead frame, and the package size increases. Then, when the package is mounted on the mounting board, the ratio of the area occupied by the package to the mounting board increases. However, in recent years, many multimedia devices, such as communication devices, notebook computers, camera-integrated VTRs, and digital cameras, have overwhelming devices that pursue smaller size and lighter weight while having many functions. Often.
こうした時代のニーズから、 L S I実装技術の向上、 すなわち、 多ピン化に対 応し、 さらに小型化されたパッケージの開発が重要な技術課題となっている。 こ の課題の特に平面寸法の小型化に対処しうる技術として、パッケージの裏面に外 部接続用の端子であるボール状のはんだが、格子状に整列されて並ぶ B G A型パ ッケージ技術が提案されてきており、 その第 1の技術として、 特開平 8— 8 8 2 4 5号公報に開示される技術がある。 この技術は、 図 3 6に示すように、 スルー ホール 4 5が形成されたベースフィルム 4 6と、その上に形成されている透孔 4 4が形成された銅箔配線 4 8と、 この銅箔配線 4 8に連続しているインナ一リ一 ド 4 7と、 インナーリードにボンディングされる半導体チップと、 半導体チップ を封止する封止樹脂と、上記透孔 4 4の部分に形成された半田ボールとを有する  Given the needs of such an era, the development of LSI packaging technology, that is, the development of a more compact package that can accommodate the increasing number of pins has become an important technical issue. As a technology that can cope with this problem, especially miniaturization of planar dimensions, a BGA type package technology in which ball-shaped solder, which is a terminal for external connection, is arranged in a grid pattern on the back of the package has been proposed. As a first technique, there is a technique disclosed in Japanese Patent Application Laid-Open No. 8-82845. As shown in FIG. 36, this technique involves, as shown in FIG. 36, a base film 46 having through holes 45 formed therein, a copper foil wiring 48 having through holes 44 formed thereon, and An inner lead 47 connected to the foil wiring 48, a semiconductor chip to be bonded to the inner lead, a sealing resin for sealing the semiconductor chip, and the through hole 44 With solder balls
1 1
差替え用紙 （規則 26) ことを特徴とする T A B方式の B G Aである。 また、 第 2の技術として、 特開平 8 - 8 8 2 4 3号公報に開示される技術がある。 この技術は、 図 3 7に示すよう に、 バイァホール 5 0を形成した絶縁フィルム 5 2の片面に、 上記バイァホール を覆う配線パターン 5 3が形成され、該配線パターン 5 3のインナーリードに半 導体チップが接続した T A Bテープにおいて、上記配線パターン側と反対側から 上記ホール 5 0内に上記配線パターン 5 3と接続される金属ボール 5 1を設け たことを特徴とする B G A型半導体装置である。 さらに、 第 3の技術として、 特 開平 8— 1 1 1 4 3 3号公報に開示される技術がある。 この技術は、 図 3 8に示 すように、半導体チップを内側に支持したベースフィルム部材に貫通孔を設け、 この貫通孔の位置にベースフィルム上のリードと電気体的に接続された外部接 続電極部材 5 4をべ一スフイルムの表裏面から上下に突出するように設ける。 こ の上部の外部接続用電極部材 5 4上に金属板 5 5を取り付け、 下部の外部接続用 電極部材を実装基板との接続用とすることを特徴する半導体装置である。 Replacement form (Rule 26) This is a TAB BGA. Further, as a second technique, there is a technique disclosed in Japanese Patent Application Laid-Open No. 8-82843. In this technique, as shown in FIG. 37, a wiring pattern 53 covering the via hole is formed on one surface of an insulating film 52 having a via hole 50 formed thereon, and a semiconductor chip is attached to an inner lead of the wiring pattern 53. In the BGA type semiconductor device, a metal ball 51 connected to the wiring pattern 53 is provided in the hole 50 from a side opposite to the wiring pattern side in the TAB tape to which the wiring pattern is connected. Further, as a third technique, there is a technique disclosed in Japanese Patent Application Laid-Open No. HEI 8-111433. In this technique, as shown in Fig. 38, a through hole is provided in a base film member supporting a semiconductor chip inside, and an external connection electrically connected to a lead on the base film at the position of the through hole. The connecting electrode member 54 is provided so as to project vertically from the front and back surfaces of the base film. A semiconductor device is characterized in that a metal plate 55 is mounted on the upper external connection electrode member 54 and the lower external connection electrode member is used for connection to a mounting substrate.
これら第 1の技術から第 3の技術によれば、パッケージの平面寸法は小型化さ れるが、 パッケージの厚さ寸法の薄型化は達成されていない。  According to these first to third technologies, the planar dimensions of the package are reduced, but the thickness of the package is not reduced in thickness.
すなわち、 半導体チップの端子数が増加すると、 パッケージの平面寸法が大き くなる。 よって、 端子数が増加してもパッケージの平面寸法が大きくならないよ うにするためにはパッケージの裏面に格子状に外部端子を設けるのが有効な手 段である。 し力 し、 パッケージの裏面に多数の外部端子を設けただけでは、 パッ ケージの平面寸法は小型化されるが、 薄型化は向上されない。 すなわち、 上記第 That is, as the number of terminals of the semiconductor chip increases, the planar dimension of the package increases. Therefore, it is an effective means to provide external terminals in a lattice pattern on the back surface of the package so that the planar dimensions of the package do not increase even if the number of terminals increases. However, simply providing a large number of external terminals on the back surface of the package reduces the package's planar dimensions, but does not improve the thickness. That is,
1の技術から第 3の技術に示される B G A型パッケージでは、パッケージの薄型 化の向上については不十分であることが本発明者によって指摘された。 The present inventors have pointed out that the BGA type packages shown in the first to third technologies are not enough to improve the thickness of the package.
本発明の目的は、薄型で多ピン化対応のパッケージ構造を有する半導体装置及 びその製造方法を提供することにある。  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a thin package structure having a multi-pin compatible package and a method of manufacturing the same.
本発明の他の目的は、薄型で放熱特性の良い多ピン化対応のパッケージ構造を 有する半導体装置及びその製造方法を提供することにある。  Another object of the present invention is to provide a semiconductor device having a package structure that is thin and has good heat dissipation characteristics and that is compatible with multiple pins and a method of manufacturing the same.
本発明の他の目的は、 小型化、 軽量化のできる半導体装置の実装構造を提供す ることにある。  Another object of the present invention is to provide a semiconductor device mounting structure that can be reduced in size and weight.
なお、 本発明の上記並びにその他の目的と、 新規な特徴は、 本明細書の記述及  The above and other objects and novel features of the present invention will be described in the present specification.
2 Two
差替え用紙 （規則 26) び添付図面から明らかになるであろう。 発明の開示 Replacement form (Rule 26) And the accompanying drawings. Disclosure of the invention
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、 下記の通りである。  The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
半導体チップと、 この半導体チップを囲むように設けられた配線基板と、 この 配線基板から突出して上記半導体チップに接続されたリードと、 上記配線基板の 一主面に設けられ上記半導体チップを囲む補強部材と、 上記配線基板の上記補強 部材が設けられる一主面と反対の他の主面に上記配線基板の周縁に沿って設けら れた複数のバンプと、 上記半導体チップとリードとを覆う樹脂とから成る半導体 装置であって、 上記半導体チップに接続されたリードは上記配線基板の補強部材 が設けられる側又は複数のバンプが設けられる側に折り曲げ加工され、 上記半導 体チップの上記リードと接続される面とは反対の面が上記リ一ドが折り曲げ加工 される側とは反対の側に位置するように上記リードと上記半導体チップとが接続 されていることを特徴とする半導体装置。  A semiconductor chip, a wiring board provided to surround the semiconductor chip, a lead projecting from the wiring board and connected to the semiconductor chip, and a reinforcement provided on one main surface of the wiring board and surrounding the semiconductor chip. A member, a plurality of bumps provided along the periphery of the wiring substrate on another main surface of the wiring substrate opposite to the one main surface on which the reinforcing member is provided, and a resin covering the semiconductor chip and the leads Wherein the lead connected to the semiconductor chip is bent to a side of the wiring board on which a reinforcing member is provided or a side on which a plurality of bumps are provided, and the lead of the semiconductor chip is The leads and the semiconductor chip are connected such that a surface opposite to a surface to be connected is located on a side opposite to a side on which the lead is bent. A semiconductor device characterized by the above-mentioned.
半導体チップと、 この半導体チップを囲むように設けられた配線基板と、 この 配線基板から突出して上記半導体チップに接続されたリードと、 上記配線基板の 一主面に設けられ上記半導体チップを囲む補強部材と、 上記配線基板の上記補強 部材が設けられた一主面と反対の他の主面に上記配線基板の周縁に沿って設けら れた複数のバンプと、 上記半導体チップとリードとを覆う樹脂とから成る半導体 装置であって、 上記配線基板と、 補強部材と、 複数のバンプとの合計厚さの中に 上記半導体チップとそれに接続されたリードとが収納されるように構成されたこ とを特徴とする半導体装置。  A semiconductor chip, a wiring board provided to surround the semiconductor chip, a lead projecting from the wiring board and connected to the semiconductor chip, and a reinforcement provided on one main surface of the wiring board and surrounding the semiconductor chip. A member, a plurality of bumps provided along a peripheral edge of the wiring substrate on another main surface of the wiring substrate opposite to the one main surface on which the reinforcing member is provided, and the semiconductor chip and the lead. A semiconductor device comprising a resin, wherein the semiconductor chip and a lead connected thereto are accommodated in a total thickness of the wiring board, the reinforcing member, and a plurality of bumps. A semiconductor device characterized by the above-mentioned.
半導体チップと、 この半導体チップを囲むように設けられた配線基板と、 上記 配線基板の一主面に設けられ上記半導体チップを囲む補強部材と、 上記配線基板 の上記補強部材が設けられた一主面と反対の他の主面に上記配線基板の周縁に沿 つて設けられた複数のバンプと、 上記配線基板から突出して上記半導体チップに 接続されたリードと、 上記半導体チップとリードとを覆う樹脂とから成る半導体 装置であって、 上記リードは上記複数のバンプが設けられた側に折り曲げ加工さ  A semiconductor chip, a wiring board provided to surround the semiconductor chip, a reinforcing member provided on one main surface of the wiring board and surrounding the semiconductor chip, and a wiring board provided with the reinforcing member of the wiring board. A plurality of bumps provided on the other main surface opposite to the surface along the periphery of the wiring board; a lead projecting from the wiring board and connected to the semiconductor chip; and a resin covering the semiconductor chip and the lead. Wherein the lead is bent on the side on which the plurality of bumps are provided.
3 Three
差替え用紙 （規則 26) れ、 上記半導体チップの上記リードと接続された面とは反対の他の面が上記補強 部材が設けられた側に位置し、 上記半導体チップの他の面と上記補強部材の表面 に放熱板が接続されていることを特徴とする半導体装置。 Replacement form (Rule 26) The other surface of the semiconductor chip opposite to the surface connected to the leads is located on the side on which the reinforcing member is provided, and a heat sink is provided on the other surface of the semiconductor chip and the surface of the reinforcing member. A semiconductor device which is connected.
樹脂基板とこの基板に設けられたデバイスホールとこのデバイスホールに突出 しかつ折り曲げ加工された銅箔のリードとを有する帯状のテープと、 上記デバィ スホールを囲むように上記テープの一主面に接続された補強部材とを準備するェ 程、 上記テープのデバイスホール内に突出する折り曲げ加工された上記リードを 半導体チップのー主面に接続する工程、 上記半導体チップ及びリ一ドを樹脂で封 止する工程、 上記テープの上記補強部材が接続された一主面と反対側の他の一主 面に複数のバンプを接続する工程を有することを特徴とする半導体装置の製造方 法。  A strip-shaped tape having a resin substrate, a device hole provided in the substrate, and a lead of a copper foil protruding from the device hole and being bent; and connected to one main surface of the tape so as to surround the device hole. Connecting the bent lead projecting into the device hole of the tape to the main surface of the semiconductor chip, and sealing the semiconductor chip and the lead with a resin. A method of manufacturing a semiconductor device, comprising: connecting a plurality of bumps to another main surface of the tape opposite to the one main surface to which the reinforcing member is connected.
一主面及びこの一主面に対向する他の主面を有するプリント基板と、 このプリ ント基板の一主面及び他の主面に複数の半導体装置を実装する実装構造であって、 前記一主面には、 半導体チップと、 この半導体チップを囲むように設けられた配 線基板と、 この配線基板から突出して上記半導体チップに接続されたリードと、 上記配線基板の一主面に設けられ上記半導体チップを囲む補強部材と、 上記配線 基板の上記補強部材が設けられた一主面と反対の他の主面に上記配線基板の周縁 に沿つて設けられた複数のバンプと、 上記半導体チップとリードとを覆う樹脂と から成る半導体装置であって、 上記配線基板と、 補強部材と、 複数のバンプとの 合計厚さの中に上記半導体チップと樹脂とが収納されるように構成された半導体 装置が実装されていることを特徴とする実装構造。  A printed circuit board having one main surface and another main surface facing the one main surface, and a mounting structure for mounting a plurality of semiconductor devices on one main surface and the other main surface of the print substrate, A semiconductor chip, a wiring board provided to surround the semiconductor chip, a lead projecting from the wiring board and connected to the semiconductor chip, and a main surface provided on one main surface of the wiring board. A reinforcing member surrounding the semiconductor chip; a plurality of bumps provided along a periphery of the wiring substrate on another main surface of the wiring substrate opposite to the one main surface on which the reinforcing member is provided; And a resin covering the leads, wherein the semiconductor chip and the resin are accommodated in a total thickness of the wiring board, the reinforcing member, and the plurality of bumps. Semiconductor equipment Mounting structure characterized in that it is so.
前記した半導体装置及びその製造方法によれば、 半導体装置を側面方向から見 た場合の半導体チップの位置を可能な限り半導体装置の中央部側へ配置すること ができ薄型で多ピン化対応の半導体装置を得ることができる。  According to the above-described semiconductor device and the method of manufacturing the same, the position of the semiconductor chip when the semiconductor device is viewed from the side can be arranged as close to the center of the semiconductor device as possible. A device can be obtained.
又、 薄型で放熱特性の良い多ピン化対応の半導体装置も得ることができる。 さらに、 前記した実装構造によれば、 小型化、 軽量化、 薄型化が可能な実装構 造を得ることができる。 図面の簡単な説明  In addition, a semiconductor device that is thin and has a high heat dissipation characteristic and that can handle a large number of pins can be obtained. Further, according to the above-described mounting structure, a mounting structure that can be reduced in size, weight, and thickness can be obtained. BRIEF DESCRIPTION OF THE FIGURES
4 Four
差替え用紙 （規則 26) 図 1は、 本発明の実施の形態 1における半導体装置の平面図 （表面側） である。 図 2は、 図 1の半導体装置の A— A' 切断線における断面図である。 Replacement form (Rule 26) FIG. 1 is a plan view (front side) of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1 taken along the line AA ′.
図 3は、 本発明の実施形態 1の半導体装置に用いられる配線基板を示す平面図 である。  FIG. 3 is a plan view showing a wiring board used in the semiconductor device of Embodiment 1 of the present invention.
図 4は、 図 3の配線基板のィの部分の拡大図である。  FIG. 4 is an enlarged view of a portion A of the wiring board of FIG.
図 5は、 図 4の配線基板の B— B' 切断線における断面図である。  FIG. 5 is a cross-sectional view of the wiring board of FIG. 4 taken along the line BB ′.
図 6は、 図 2の要部拡大断面図である。  FIG. 6 is an enlarged sectional view of a main part of FIG.
図 7は、 図 1の半導体装置の第 1のその他の例を示す要部拡大断面図である。 図 8は、 図 1の半導体装置の第 2のその他の例を示す要部拡大断面図である。 図 9は、 本発明の実施の形態 1における半導体装置の平面図 （裏面側） である。 図 10は、 図 9の半導体装置の口の部分の拡大図である。  FIG. 7 is an enlarged sectional view of a main part showing a first other example of the semiconductor device of FIG. FIG. 8 is an enlarged sectional view of a main part showing a second other example of the semiconductor device of FIG. FIG. 9 is a plan view (back side) of the semiconductor device according to the first embodiment of the present invention. FIG. 10 is an enlarged view of a mouth portion of the semiconductor device of FIG.
図 1 1は、 図 10の C— C' 切断線における断面図である。  FIG. 11 is a cross-sectional view taken along line CC ′ of FIG.
図 1 2は、 本発明の実施の形態 1における半導体装置の製造方法の一例を示す 断面フロー図である。  FIG. 12 is a cross-sectional flow chart showing one example of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
図 13は、 本発明の実施の形態 1における半導体装置の製造方法に使用される テープの一例を示す平面図である。  FIG. 13 is a plan view showing an example of a tape used in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
図 14は、 図 1 3のテープの平面図であり、 （a) は要部拡大平面図 （b) は、 (a) の D— D' 切断線における断面図である。  14 is a plan view of the tape of FIG. 13, (a) is an enlarged plan view of a main part, and (b) is a cross-sectional view taken along the line D-D 'of (a).
図 1 5は、 本発明の実施の形態 1における半導体装置の製造方法に使用される テープの第 1のその他の例を示す部分拡大図である。  FIG. 15 is a partially enlarged view showing a first other example of the tape used in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
図 16は、 本発明の実施の形態 1における半導体装置の製造方法に使用される テープの第 2のその他の例を示す部分拡大図である。  FIG. 16 is a partially enlarged view showing a second other example of the tape used in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
図 1 7 (a) 、 (b) は、 オフセッ ト加工の一例を示す部分断面図である。 図 18 (a) 、 (b) は、 リードボンディング方法の一例を示す部分断面図で ある。  FIGS. 17 (a) and 17 (b) are partial cross-sectional views showing an example of offset processing. FIGS. 18A and 18B are partial cross-sectional views illustrating an example of the lead bonding method.
図 1 9は、 ポッティング方法の一例を示す概念図である。  FIG. 19 is a conceptual diagram showing an example of the potting method.
図 20は、 封止工程が終了した状態のテープを示す平面図である。  FIG. 20 is a plan view showing the tape after the sealing step has been completed.
図 21 (a) 、 （b) は、 実施の形態 1の半導体装置をメモリカード用のプリ ント実装基板に実装した一例を示す平面図であり、 （a) は一面側の平面図であ δ 差替え用紙 （規則 26) り、 （b ) は、 それと反対の他の一面側の平面図である。 FIGS. 21A and 21B are plan views showing an example in which the semiconductor device of the first embodiment is mounted on a printed circuit board for a memory card, and FIG. 21A is a plan view of one surface side. Replacement form (Rule 26) (B) is a plan view of the other side opposite thereto.
図 2 2は、 図 2 1のメモリ力一ド用のプリント基板をケースに収容したメモリ カードを示す部分透過平面図である。  FIG. 22 is a partially transparent plan view showing a memory card in which the printed circuit board for memory card of FIG. 21 is housed in a case.
図 2 3は、 図 2 2のメモリカードの E— E ' 切断線における断面図である。 図 2 4は、 図 2 2のメモリカードの F— F ' 切断線における断面図である。 図 2 5は、 実施の形態 1の半導体装置をマルチメディア機器用のプリント基板 に実装した一例を示す平面図である。  FIG. 23 is a cross-sectional view of the memory card of FIG. 22 taken along the line EE ′. FIG. 24 is a cross-sectional view of the memory card of FIG. 22 taken along the line FF ′. FIG. 25 is a plan view showing an example in which the semiconductor device of the first embodiment is mounted on a printed circuit board for a multimedia device.
図 2 6は、 本発明の実施の形態 2の半導体装置を示す平面図である。  FIG. 26 is a plan view showing a semiconductor device according to the second embodiment of the present invention.
図 2 7は、 図 2 6の半導体装置の G— G ' 切断線における断面図である。  FIG. 27 is a cross-sectional view of the semiconductor device of FIG. 26 taken along the line GG ′.
図 2 8は、 図 2 7の要部拡大断面図である。  FIG. 28 is an enlarged sectional view of a main part of FIG.
図 2 9は、 実施の形態 2の半導体装置を他の半導体装置と共にプリント基板に 実装した一例を示す断面図である。  FIG. 29 is a cross-sectional view showing an example in which the semiconductor device of the second embodiment is mounted on a printed circuit board together with another semiconductor device.
図 3 0は、 実施の形態 2における半導体装置の製造方法の一例を示す断面フロ 一図である。  FIG. 30 is a cross-sectional flowchart showing an example of the method for manufacturing a semiconductor device in the second embodiment.
図 3 1は、 本発明の実施の形態 3における半導体装置を示す平面図である。 図 3 2は、 図 3 1の半導体装置の H— H， 切断線における断面図である。  FIG. 31 is a plan view showing a semiconductor device according to the third embodiment of the present invention. FIG. 32 is a cross-sectional view of the semiconductor device of FIG.
図 3 3は、 図 3 2の要部拡大断面図である。  FIG. 33 is an enlarged sectional view of a main part of FIG.
図 3 4は、 実施の形態 3の半導体装置の放熱板に放熱フィンを搭載した一例を 示す断面図である。  FIG. 34 is a cross-sectional view showing an example of the semiconductor device according to the third embodiment in which heat radiation fins are mounted on the heat radiation plate.
図 3 5は、 実施の形態 3の半導体装置の製造方法の一例を示す断面フロー図で ある。  FIG. 35 is a cross-sectional flowchart showing an example of the method for manufacturing a semiconductor device of the third embodiment.
図 3 6は、 第 1の従来技術を示す断面図である。  FIG. 36 is a cross-sectional view showing a first conventional technique.
図 3 7は、 第 2の従来技術を示す断面図である。  FIG. 37 is a sectional view showing a second conventional technique.
図 3 8は、 第 3の従来技術の組立工程を示すフローチャートである。 発明を実施するための最良の形態  FIG. 38 is a flowchart showing an assembling process of the third conventional technique. BEST MODE FOR CARRYING OUT THE INVENTION
以下図面を参照して本発明の実施の形態を説明する。  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
なお、 本発明の実施の形態を説明するための全図において、 同一機能を有するも のは同一符号をつけ、 その繰り返しの説明は省略する。 In all the drawings for describing the embodiments of the present invention, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.
6 6
差替え用紙 （規則 26) 本発明に係わる半導体装置は、 半導体装置の外部端子として、 半導体装置の一 主面 （以下、 裏面と称する） に整列された複数のボール状のはんだバンプを備え ており、 半導体チップのパッドと上記外部端子との接続にテープ技術を用いた B GA型の半導体装置である。 Replacement form (Rule 26) The semiconductor device according to the present invention includes, as external terminals of the semiconductor device, a plurality of ball-shaped solder bumps arranged on one main surface (hereinafter, referred to as a back surface) of the semiconductor device. This is a BGA type semiconductor device that uses tape technology to connect to external terminals.
(実施の形態 1 )  (Embodiment 1)
まず、 図 1〜 1 1を用いて、 本発明の実施の形態 1の半導体装置の構造を説明 する。  First, the structure of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.
本実施の形態 1の半導体装置 1は、 図 1、 図 2、 図 9に示すように、 実装基板 (図示せず） への接続用の外部端子として、 複数の整列されたボール状のはんだ バンプ 9を備えている。 このボール状のはんだバンプ 9は、 ポリイミ ド系樹脂か ら成る基材 1 0と、 この上に形成された銅箔の配線であるリード 7とを有する枠 状の配線基板 4に形成されている。 上記基材 1 0の材料としては、 ポリイミ ド系 樹脂や、 ガラスエポキシ、 BT (B i s ma l e i m i d e— T r i a z i n e) レジン、 又は P E T (P o l y e t h y l e n e t e r p h t h a l a t e) 等が用いられる。  As shown in FIGS. 1, 2, and 9, the semiconductor device 1 according to the first embodiment includes a plurality of aligned ball-shaped solder bumps as external terminals for connection to a mounting board (not shown). It has nine. The ball-shaped solder bumps 9 are formed on a frame-shaped wiring board 4 having a base material 10 made of polyimide resin and leads 7 which are copper foil wirings formed thereon. . As the material of the base material 10, polyimide resin, glass epoxy, BT (Bismaleimide-Triazine) resin, PET (Polyetehylenenetterphthatal), or the like is used.
そして、 この配線基板 4の上記基材 1 0のリード 7が形成される面とは反対側 の他の面には、 半導体装置 1の機械的強度を向上させるために、 平面内において 半導体チップが収容可能なホールを有する厚さ 200 μ m程度の枠状の補強部材 (以下、 ステフイナ 3と称する） 1S 配線基板 4の周縁部に沿って、 エポキシ樹 脂からなる厚さ 50 μπι程度の接着剤 1 1により接続されている。 この接着剤 1 1には、 エポキシ樹脂の他にポリイミ ド系樹脂を用いても良い。  On the other surface of the wiring substrate 4 opposite to the surface on which the leads 7 of the base material 10 are formed, a semiconductor chip is provided in a plane to improve the mechanical strength of the semiconductor device 1. A frame-shaped reinforcing member with a hole that can be accommodated and having a thickness of about 200 μm (hereinafter referred to as “stiffener 3”) 1S Adhesive made of epoxy resin and having a thickness of about 50 μπι along the periphery of the wiring board 4 1 Connected by 1. As the adhesive 11, a polyimide resin may be used in addition to the epoxy resin.
ステフイナ 3の材料は、 半導体装置 1が実装される実装基板に近い熱膨張係数 を有するものが好ましく、 例えば、 Cuや Cuを主成分とする Cu合金、 または、 八 1ゃ 1合金、 あるいは鉄系合金やセラミックス等が良い。 その形状は限定さ れるものではなく、 図 1に示すように半導体チップ 2の周囲を囲むことが可能な ものであればよレ、。  The material of the stiffener 3 preferably has a thermal expansion coefficient close to that of the mounting substrate on which the semiconductor device 1 is mounted. For example, Cu or a Cu alloy containing Cu as a main component, or an 81-1 alloy, or an iron-based material Alloys and ceramics are good. The shape is not limited, as long as it can surround the semiconductor chip 2 as shown in FIG.
半導体チップ 2は、 例えば、 厚さ 400~5 5 0 μ m程度のシリコンなどの半 導体基板の一主面にマイコン、 AS I C等の所定の集積回路及びこれら回路の外 部接続用の端子となる A 1などの材料からなるパッド （図示せず） が設けられ、  The semiconductor chip 2 includes, for example, a predetermined integrated circuit such as a microcomputer and an AS IC and terminals for external connection of these circuits on one main surface of a semiconductor substrate such as silicon having a thickness of about 400 to 550 μm. A pad (not shown) made of a material such as A1 is provided.
7 7
差替え用紙 （規則 26) そして、 上記集積回路形成面の最上層には、 上記集積回路を保護するためのパッ シべ一シヨン膜が形成されている。 このパッシベーシヨン膜は例えば、 厚さ 2〜 1 0 m程度のポリイミ ド樹脂からなる。 Replacement form (Rule 26) A passivation film for protecting the integrated circuit is formed on the uppermost layer of the integrated circuit formation surface. The passivation film is made of, for example, a polyimide resin having a thickness of about 2 to 10 m.
上記パッシベーシヨン膜には開口部が形成され、 この開口部に上記パッドと接 続される A uバンプ 8が形成されている。 A uバンプ 8の直径は 1 4〜3 5 /z m 程度である。 この A uバンプ 8は、 メツキバンプ又はワイヤバンプにより形成さ れる。 尚、 この A uバンプ 8は、 配線基板 4のリード 7側に形成しても良い。 このような半導体チップ 2は、 図 2に示すように集積回路及び A uバンプ 8が 形成された主面を半導体装置 1の裏面側すなわちはんだバンプ 9が形成される側 に向けた状態で配置され、 配線基板 4から突出して半導体装置 1の裏面側すなわ ちはんだバンプ 9が形成される側にあらかじめ折り曲げ加工 （オフセット加工） されているリード 7と接続されている。 そして、 上記半導体チップ 2の集積回路 が形成された主面、 側面及びリード 7は半導体装置 1の保護、 耐湿性の向上、 リ ード 7と半導体チップ 2との接合部の信頼性の向上を目的に封止用の樹脂 5によ り封止されている。 この樹脂 5は、 シリコーン樹脂、 エポキシ樹脂等が用いられ る。  An opening is formed in the passivation film, and an Au bump 8 connected to the pad is formed in the opening. The diameter of the Au bump 8 is about 14 to 35 / zm. The Au bumps 8 are formed by plating bumps or wire bumps. Note that the Au bump 8 may be formed on the lead 7 side of the wiring board 4. Such a semiconductor chip 2 is arranged with the main surface on which the integrated circuit and the Au bump 8 are formed facing the back side of the semiconductor device 1, that is, the side on which the solder bump 9 is formed, as shown in FIG. The lead 7 which is protruded from the wiring board 4 and connected to the back surface of the semiconductor device 1, that is, the side on which the solder bump 9 is formed, has been bent (offset) in advance. The main surface, side surfaces and leads 7 on which the integrated circuits of the semiconductor chip 2 are formed are intended to protect the semiconductor device 1, improve the moisture resistance, and improve the reliability of the joint between the lead 7 and the semiconductor chip 2. It is sealed with a sealing resin 5 for the purpose. As the resin 5, a silicone resin, an epoxy resin, or the like is used.
このような半導体装置 1は図 2に示されるように、 はんだバンプ 9、 配線基板 4、 補強材 3の合計厚さ t 1 が半導体チップ 2と封止用樹脂 5との合計厚さ t 2 よりも厚くなるように （ t 1〉 t 2 ) 構成されている。 言い換えると、 はんだバ ンプ 9、 配線基板 4、 補強材 3の合計厚さ t 1 の中に半導体チップ 2と封止用樹 月旨 5との合計厚さ t 2が含まれる厚さ関係となっている。  In such a semiconductor device 1, as shown in FIG. 2, the total thickness t 1 of the solder bump 9, the wiring board 4, and the reinforcing material 3 is larger than the total thickness t 2 of the semiconductor chip 2 and the sealing resin 5. (T 1> t 2). In other words, the total thickness t 1 of the solder bump 9, the wiring board 4, and the reinforcing material 3 includes the total thickness t 2 of the semiconductor chip 2 and the sealing lug 5. ing.
次に上記した半導体装置 1の詳細を図 3〜図 1 1に基づき説明する。  Next, details of the above-described semiconductor device 1 will be described with reference to FIGS.
上記した配線基板 4は、 半導体チップ 2の A uバンプ 8とはんだバンプ 9とを 電気的に接続するための部材であり、 図 3の平面図に示されるように中央部に、 配線基板 4を貫通するデバイスホール 1 4が設けられ、 このデバイスホール 1 4 内に半導体チップ 2が収容可能な構造となっているものが用いられる。 この配線 基板 4は、 厚さ 5 0〜： 1 2 5 μ m程度、 好ましくは 7 5 ± 8 μ ιηの基材 1 0と、 この基材 1 0の一主面に、 厚さ 1 2〜3 0 μ m程度、 好ましくは 1 8 ± 2 μ mの 銅箔で形成された、 任意の配線パターンのリード 7と平面形状が円形のバンブラ  The above-mentioned wiring board 4 is a member for electrically connecting the Au bumps 8 and the solder bumps 9 of the semiconductor chip 2, and the wiring board 4 is provided at the center as shown in the plan view of FIG. A penetrating device hole 14 is provided, and a device hole 14 having a structure capable of accommodating the semiconductor chip 2 is used. The wiring board 4 has a thickness of 50 to: about 125 μm, preferably 75 ± 8 μιη, and a base 10 having a thickness of 12 to A lead 7 of an arbitrary wiring pattern and a bumper having a circular planar shape formed of copper foil of about 30 μm, preferably 18 ± 2 μm
8 8
差替え用紙 （規則 26) ンド部 1 2とが設けられており、 これらリード 7及びバンプランド部 1 2は、 厚 さ 1 2 ± 4 μ m程度の接着剤 （図示せず） により上記基材 1 0に接着されている。 又、 これらリード 7及びバンプランド部 1 2は、 ソルダーレジスト等のような感 光性絶縁膜 6により被覆されている。 この感光性絶縁膜 6は、 例えば、 厚さ 5 ~ 3 0 μ m程度、 好ましくは 2 0 μ mの絶縁膜であり、 メラミン、 アクリル、 ポリ スチロール、 ポリイミ ド、 ポリウレタン、 シリコーン等の材料からなり、 はんだ 付け温度に耐える耐熱性があり、 はんだに濡れない性質を有し、 また、 湿気や汚 染による配線基板の劣化を防ぎ、 さらに、 フラックスや洗浄液にさらされること に耐えうる性質をもつのが好ましい。 Replacement form (Rule 26) The lead 7 and the bump land 12 are adhered to the substrate 10 with an adhesive (not shown) having a thickness of about 12 ± 4 μm. . The leads 7 and the bump lands 12 are covered with a light-sensitive insulating film 6 such as a solder resist. The photosensitive insulating film 6 is, for example, an insulating film having a thickness of about 5 to 30 μm, preferably 20 μm, and is made of a material such as melamine, acrylic, polystyrene, polyimide, polyurethane, and silicone. It has the heat resistance to withstand the soldering temperature, does not wet the solder, prevents the deterioration of the wiring board due to moisture and contamination, and has the property to withstand exposure to flux and cleaning liquid. Is preferred.
上記バンプランド部 1 2は、 配線基板 4の外縁に沿って規則的に配置される。 例えば、 本実施の形態 1では、 直径が 3 1 0 /i mのバンプランド部を 5 0 0 /x m ピッチ （間隔） で、 配線基板 4の周縁に沿って、 周縁側の列及びその内側の列の 2列にわたり配置される。 しかし、 バンプランド部の直径及びピッチ、 配置は製 品により異なり、 必ずしもこれに限定されるものではなく、 例えば、 直径 3 0 0 〜5 0 0 μ ιη、 ピッチ 5 0 0〜8 0 0 /z m、 配置パターンは規則的に 2列配置や 3列配置、 不規則的に配置しても良い。 また、 図 4、 図 5に示すように、 バンプ ランド部 1 2の一部は、 感光性絶縁膜 6にフォトリソグラフィ技術によって形成 された開口部 1 3を通じて露出され、 その露出されたバンプランド部 1 2にはん だバンプが接続される。 このようなフォトリソグラフィ技術によって開口部を形 成する場合は、 微細加工が可能であり、 小さな開口部の形成が可能となり、 はん だバンプの小ボ一ル化に対応することができる。  The bump land portions 12 are regularly arranged along the outer edge of the wiring board 4. For example, in the first embodiment, the bump lands having a diameter of 310 / im are arranged at a pitch of 500 / xm (interval) along the periphery of the wiring board 4, and the rows on the peripheral side and the rows on the inner side thereof. Are arranged in two rows. However, the diameter, pitch, and arrangement of the bump land portions differ depending on the product, and are not necessarily limited thereto. For example, the diameter is 300 to 500 μιη, and the pitch is 500 to 800 / zm. However, the arrangement pattern may be regularly arranged in two rows, three rows, or irregularly. As shown in FIGS. 4 and 5, a part of the bump land portion 12 is exposed through an opening 13 formed in the photosensitive insulating film 6 by photolithography, and the exposed bump land portion is exposed. The solder bump is connected to 1 2. When an opening is formed by such a photolithography technique, fine processing can be performed, a small opening can be formed, and the solder bump can be reduced in size.
上記基材 1 0上の感光性絶縁膜 6への開口部形成は、 パンチ等のような機械的 な加工方法で形成しても良い、 ただし、 この場合は、 開口部の直径に制限がある ので、 微細加工には不向きである。  The opening in the photosensitive insulating film 6 on the base material 10 may be formed by a mechanical processing method such as a punch. However, in this case, the diameter of the opening is limited. Therefore, it is not suitable for fine processing.
図 3において、 便宜上感光性絶縁膜は省略する。  In FIG. 3, the photosensitive insulating film is omitted for convenience.
配線基板 4のデバイスホール 1 4には、 銅箔で形成された配線パターンである リード 7の一部が突出している。 配線基板 4を側面方向から見た場合上記突出す る各リードの位置はほぼ同一平面内にあり、この平面をリ一ド突出平面と称する。 半導体チップ 2は、 集積回路及び A uバンプ 8が形成された主面を半導体装置  A part of a lead 7 which is a wiring pattern formed of a copper foil projects from the device hole 14 of the wiring board 4. When the wiring board 4 is viewed from the side, the positions of the protruding leads are substantially in the same plane, and this plane is referred to as a lead protruding plane. The semiconductor chip 2 has a main surface on which an integrated circuit and Au bumps 8 are formed, and a semiconductor device.
9 9
差替え用紙 （規則 26) 1の裏面側すなわちはんだバンプ 9が形成される側に向けた状態 （以下、 フェイ スダウンと称する） で、 デバイスホール 1 4内に配置され、 上記デバイスホール 1 4内に突出されたリード 7と A uバンプ 8とが電気的に接続されている。 Replacement form (Rule 26) The leads 7 and A are arranged in the device hole 14 with the lead 7 facing the back surface side of 1, that is, the side on which the solder bump 9 is formed (hereinafter referred to as “face-down”). u Bump 8 is electrically connected.
図 6は、 図 2の要部拡大断面図であり、 同図に示すように、 上記デバイスホー ル 1 4内に突出された各リード 7は、 半導体装置 1の裏面側すなわちはんだバン プ 9が形成される側又は半導体チップ 2のリード 7と接続される側から遠ざかる 方向に折り曲げ加工した第 1の折り曲げ部 1 5と、 第 1の折り曲げ部 1 5よりリ ―ド先端側に半導体チップ 2の素子形成面と平行となる領域を設けるように折り 曲げ加工した第 2の折り曲げ部 1 6とを有している。 このような折り曲げ加工さ れたリード構造をオフセット構造と称し、 そのオフセット量 （第 1の折り曲げ部 1 5と第 2の折り曲げ部 1 6との距離、 言い替えると基材 1 0上のリード 7の位 置と第 1の折り曲げ部 1 5によって変位したリード 7の位置との距離） を Tとす る。  FIG. 6 is an enlarged cross-sectional view of a main part of FIG. 2. As shown in FIG. 6, each lead 7 protruding into the device hole 14 is connected to the back side of the semiconductor device 1, namely, the solder bump 9. A first bent portion 15 bent in a direction away from the side to be formed or the side connected to the lead 7 of the semiconductor chip 2, and the semiconductor chip 2 closer to the leading end of the lead from the first bent portion 15 And a second bent portion 16 bent so as to provide a region parallel to the element formation surface. Such a bent lead structure is referred to as an offset structure. The offset amount (the distance between the first bent portion 15 and the second bent portion 16, in other words, the lead 7 on the base material 10) Let T be the distance between the position and the position of the lead 7 displaced by the first bent portion 15.
上記各リード 7と A uバンプ 8との接続は上記第 2の折り曲げ部 1 6からリー ド 7の先端にかけての領域で行われる。  The connection between each of the leads 7 and the Au bump 8 is performed in a region from the second bent portion 16 to the tip of the lead 7.
実施の形態 1では、 半導体チップの厚さ及びはんだバンプの径を考慮して半導 体装置 1が最も薄型構造となるように上記オフセット構造及びオフセット量 Tを 1 2 5 mとした。 しかし、 このオフセット量 T及びオフセット構造は半導体チ ップの厚さ、 はんだボールの径などに依存するものであり、 製品により異なるの で必ずしもこれに限定されるものではない。  In the first embodiment, the offset structure and the offset amount T are set to 125 m so that the semiconductor device 1 has the thinnest structure in consideration of the thickness of the semiconductor chip and the diameter of the solder bump. However, the offset amount T and the offset structure depend on the thickness of the semiconductor chip, the diameter of the solder ball, and the like, and vary depending on the product, and are not necessarily limited to these.
例えば、図 7に示すように、第 2の折り曲げ部 1 6からリード先端にかけて徐々 に半導体チップの素子形成面に近ずくように、 言い換えると A uバンプ 8との接 続部から第 2の折り曲げ部 1 6に向かって半導体チップの素子形成面から徐々に 遠ざかるような傾斜 Kを有するように構成しても良い。 このようにすることによ り、 パッシベ一ション膜が塗布されにくい半導体チップの素子形成面の周縁部と リードとの接触 （以下、 エッジショートと称する） を防止することができる。 ま た、 図 8に示すように、 配線基板近傍をリード突出方向から半導体装置の裏面側 に折り曲げ加工した第 1の折り曲げ部 1 5と、 第 1の折り曲げ部 1 5よりリード 先端側に半導体チップの素子形成面と平行となる第 1の領域を有するように折り  For example, as shown in FIG. 7, from the second bent portion 16 to the tip of the lead, gradually approach the element forming surface of the semiconductor chip, in other words, the second bent portion from the connection portion with the Au bump 8. It may be configured so as to have an inclination K that gradually moves away from the element formation surface of the semiconductor chip toward the portion 16. By doing so, it is possible to prevent contact (hereinafter referred to as edge short) between the lead and the peripheral portion of the element formation surface of the semiconductor chip on which the passivation film is not easily applied. Further, as shown in FIG. 8, a first bent portion 15 is formed by bending the vicinity of the wiring board from the lead protruding direction to the back side of the semiconductor device, and a semiconductor chip is provided on the lead end side from the first bent portion 15. Folded so as to have a first region parallel to the element formation surface of
10 Ten
差替え用紙 （規則 26) 曲げ加工した第 2の折り曲げ部 1 6と、 第 2の折り曲げ部 1 6よりリード先端側 に、 上記第 1の領域より半導体チップ 2側であって、 半導体チップの素子形成面 と平行となる第 2の領域が形成されるように折り曲げ加工した第 3の折り曲げ部 1 7及び第 4の折り曲げ部 1 8とを有するように構成してもよい。 このようにす ることにより、 半導体チップの素子形成面の周緣部とリードとのエッジショート 及び半導体チップの素子形成面とリード先端部との接触を防止することができる。 ただし、 上記図 7および図 8の構造とも上記オフセット量が確保されるように、 基材 1 0上のリード 7の位置に達しない範囲で第 2、 第 3、 第 4の折り曲げ部が 形成される。 Replacement form (Rule 26) A bent second bent portion 16; a second bent portion 16 closer to the lead end than the second bent portion 16; and a semiconductor chip 2 closer to the semiconductor chip 2 than the first region and parallel to the element forming surface of the semiconductor chip. It may be configured to have a third bent portion 17 and a fourth bent portion 18 which are bent so as to form the second region. By doing so, it is possible to prevent an edge short between the peripheral portion of the element forming surface of the semiconductor chip and the lead and a contact between the element forming surface of the semiconductor chip and the tip of the lead. However, in the structures of FIGS. 7 and 8 described above, the second, third, and fourth bent portions are formed so as not to reach the position of the lead 7 on the base material 10 so that the offset amount is secured. You.
このような半導体装置は、 実装基板との接続用端子として、 図 9〜 1 1に示す ように、 配線基板 4のソルダ一レジストに形成された開口部を通じて露出されて いるバンプランド部 1 2に、 はんだバンプ 9が接続されている。 このはんだバン プ 9は、 P b—S n、 P b— S n等を主成分とする合金などの材料から構成され た径が 3 0 0 // m程度のボール状のバンプであり、 バンプランド部 1 2と対応す る位置に、 5 0 0 ピッチで、 配線基板 4の周縁に沿って、 周縁側の列及びそ の内側の列の 2列にわたり配置される。 上述したようにソルダーレジス卜の開口 部は、 小さく形成することができ、 はんだバンプ 9の小ボール化が可能となるの で、 半導体装置を薄型化できる。 しかし、 はんだバンプの材料、 径及びピッチ、 配置パターンは製品により異なり、 必ずしもこれに限定されるものではなく、 例 えば、 径は3 0 0〜5 0 0 111、 ピッチは 5 0 0〜8 0 0 μ m、 配置パターンは 規則的に 2列配置や 3列配置、 さらに、 不規則的に配置しても良い。  As shown in FIGS. 9 to 11, such a semiconductor device has bump bumps 12 exposed through openings formed in the solder resist of the wiring board 4 as terminals for connection with the mounting board. The solder bump 9 is connected. The solder bump 9 is a ball-shaped bump made of a material such as an alloy containing Pb—Sn, Pb—Sn, etc. as a main component and having a diameter of about 300 // m. At a position corresponding to the land portion 12, it is arranged at a pitch of 500 along the periphery of the wiring board 4 over two rows of a row on the peripheral side and a row on the inner side. As described above, the opening of the solder resist can be formed small, and the balls of the solder bumps 9 can be made small, so that the semiconductor device can be made thin. However, the material, diameter, pitch, and arrangement pattern of the solder bumps differ depending on the product, and are not necessarily limited to this.For example, the diameter is 300 to 5001, and the pitch is 500 to 800. 0 μm, the arrangement pattern may be arranged regularly in two or three rows, or even irregularly.
次に、 図 1 2の断面フロー図及び図 1 3〜2 0を用いて本実施の形態 1の半導 体装置の製造方法の一例を説明する。  Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to a cross-sectional flow diagram of FIG. 12 and FIGS.
半導体装置の製造に先立って、 図 1 3に示すような、 例えばポリイミ ド系樹脂 からなる基材 1 0とその基材 1 0の一主面に銅箔で形成された任意の配線パター ンのリード 7と、 その配線を被覆する感光性絶縁膜 6と、 基材 1 0を貫通する複 数のデバイスホール 1 4とデバイスホール 1 4に突出するリード 7とを有する帯 状のテープ 1 9 (このテープ 1 9を加工し個片に切断したものを配線基板 4とい う） と、 平面内において半導体チップが収容可能なホールを有するステフイナ 3  Prior to the manufacture of the semiconductor device, as shown in FIG. 13, for example, a base material 10 made of polyimide resin and an arbitrary wiring pattern formed of copper foil on one main surface of the base material 10 are formed. A strip-shaped tape 19 having leads 7, a photosensitive insulating film 6 covering the wiring, a plurality of device holes 14 penetrating the base material 10, and leads 7 protruding from the device holes 14 ( A tape obtained by processing the tape 19 and cutting it into pieces is called a wiring board 4) and a stiffener 3 having a hole capable of receiving a semiconductor chip in a plane.
11 11
差替え用紙 （規則 26) と、一主面に集積回路とパッドが形成された半導体チップ 2と、封止用の樹脂と、 フラックス、 はんだボール等の半導体装置を構成する各部材を準備する。 Replacement form (Rule 26) Then, a semiconductor chip 2 having an integrated circuit and a pad formed on one main surface, a sealing resin, flux, solder balls, and other members constituting a semiconductor device are prepared.
図 1 4 ( a ) は、 図 1 3の要部拡大平面図であり、 図 1 4 ( b ) は、 （a ) の D - D ' 切断線における断面図である。 これらの図からわかるように、 加工前 のリードは、 基材 1 0上の配線と同一平面にその先端部が一体的に繋がれて形成 されている。  FIG. 14 (a) is an enlarged plan view of a main part of FIG. 13, and FIG. 14 (b) is a cross-sectional view taken along the line DD ′ in FIG. 14 (a). As can be seen from these drawings, the lead before processing is formed by integrally connecting the tips on the same plane as the wiring on the base material 10.
最初に、 図 1 2の （a ) に示すように、 テープ 1 9の基材 1 0からデバイスホ ール 1 4に突出するリ一ド 7をテープ 1 9のはんだバンプ 9が形成される側に折 り曲げ加工する。 先に述べたように、 加工前のリード 7は、 基材 1 0上の配線と 同一平面にその先端部が一体的に繋がれて形成されている。 これによりリード先 端のばらつきを抑制することができる。 図 1 5に示すように、 その一体的に繋が れたリードの先端をテープ等の固定部材 2 1で補強してもよい。 また、 図 1 6に 示すように、 突出するリード先端近くまで基材 1 0が延在し、 その延在された基 材 1 0に、 リードの折り曲げ加工が可能となるように 4本の切り込み 2 2を設け た形状としても良い。  First, as shown in FIG. 12A, a lead 7 projecting from the base material 10 of the tape 19 to the device hole 14 is placed on the side of the tape 19 where the solder bumps 9 are formed. Bend it. As described above, the lead 7 before processing is formed such that its tips are integrally connected to the same plane as the wiring on the base material 10. As a result, it is possible to suppress variations in the lead end. As shown in FIG. 15, the tips of the leads connected integrally may be reinforced with a fixing member 21 such as a tape. Also, as shown in FIG. 16, the base material 10 extends to near the tip of the protruding lead, and the extended base material 10 has four cuts so that the lead can be bent. A shape provided with 22 may be used.
加工前のリードは、 外形寸法の異なる半導体チップを接続することが可能なよ うに、 リードの長さを長めに形成している。 このようにすることにより、 半導体 チップの外形寸法に合わせてリ一ドの先端位置を変更する必要がある場合でも十 分対応することができるので半導体チップの外形寸法が変わる毎に、 異なるテ一 プを用意する必要がない。  Before processing, the leads are made longer so that semiconductor chips with different external dimensions can be connected. In this way, even if it is necessary to change the leading end position of the lead in accordance with the external dimensions of the semiconductor chip, it is possible to sufficiently cope with the situation. There is no need to prepare a pump.
このリードの加工は次のように行う。 まず、 図 1 7 ( a ) に示すように、 リ一 ド成形治具であるダイ 2 4とパンチ 2 3との間に、 平面的な位置合わせをした状 態で挿入する。 その後、 図 1 7 ( b ) に示すように、 その位置合わせをした状態 を保ったままダイ 2 4及びパンチ 2 3をリード 7に対して垂直に打ち下ろし所定 の形状に押圧成形すると共に、 リード 7の先端部を切断パンチ 2 5により、 半導 体チップに適した長さに切断する。 なお、 繋がれていたリードの先端部はそれぞ れに分割される。 以下、 この加工をオフセット加工、 この工程をリードオフセッ ト工程と称する。 また、 半導体装置の構成部材を準備する工程で、 予め、 リード がオフセット加工されたテープを準備しても良い （工程 a ) 。  The processing of this lead is performed as follows. First, as shown in FIG. 17 (a), it is inserted between a die 24, which is a lead forming jig, and a punch 23 in a state where they are aligned in a plane. Thereafter, as shown in FIG. 17 (b), the die 24 and the punch 23 are vertically dropped with respect to the lead 7 while maintaining the alignment state, and are pressed into a predetermined shape, and the lead is formed. The tip of 7 is cut by a cutting punch 25 into a length suitable for a semiconductor chip. The leading ends of the connected leads are divided into individual parts. Hereinafter, this processing is referred to as offset processing, and this step is referred to as a lead offset step. Further, in the step of preparing the components of the semiconductor device, a tape may be prepared in which the leads have been offset-processed in advance (step a).
12 12
差替え用紙 （規則 26) 次に、 図 1 2の （b ) に示すように、 リードオフセッ ト工程で加工された帯状 のテープ 1 9の基材 1 0上のデバイスホールの周囲に沿ってステフイナ 3をェポ キシ樹脂等の接着剤 1 1を介して熟圧着する。 以下、 この工程をステフイナ接着 工程と称する （工程 b )。 Replacement form (Rule 26) Next, as shown in FIG. 12 (b), the step finner 3 is epoxied along the periphery of the device hole on the base material 10 of the strip-shaped tape 19 processed in the lead offset process. Adhesively bond through the adhesive 1 1 Hereinafter, this step is referred to as a stiffener bonding step (step b).
次に、 図 1 2の （c ) に示すように、 半導体チップ 2の一主面に形成されたパ ッド上に、 例えばボールボンディング法で A uバンプ 8を形成する。 バンプの形 成方法は、 めっき法で行ってもかまわない。 以下、 この工程を A uバンプ形成ェ 程と称する （工程 c ) 。  Next, as shown in (c) of FIG. 12, Au bumps 8 are formed on the pads formed on one main surface of the semiconductor chip 2 by, for example, a ball bonding method. The bumps may be formed by plating. Hereinafter, this step is referred to as an Au bump formation step (step c).
次に、 図 1 2の （d ) に示すように、 半導体チップ 2上の A uバンプ 8とリ一 ド 7とを電気的に接続する。 この工程は、 図 1 8 ( a ) に示すように、 ボンディ ングステージ 2 7上に、 半導体チップ 2の A uバンプ 8が形成された面が上にな るように搭載する。 そして、 テープ 1 9の基材 1 0から突出するリード 7と半導 体チップ 2の A uバンプ 8が対向するように上記半導体チップ 2上にテープ 1 9 を位置させ、 半導体チップ 2の A uバンプ 8とテープ 1 9のリ一ド 7先端近傍の 接続部との位置が一致するように、 半導体チップ 2とテープ 1 9との位置合わせ を行う。 この時、 各リード 7と A uバンプ 8との間隔はできるだけ接近させてお くことが好ましい。 又、 テープ 1 9はステフイナ 3が形成された面が半導体チッ プ 2側になるように位置合わせする。  Next, as shown in FIG. 12D, the Au bumps 8 on the semiconductor chip 2 and the leads 7 are electrically connected. In this step, as shown in FIG. 18 (a), the semiconductor chip 2 is mounted on the bonding stage 27 so that the surface of the semiconductor chip 2 on which the Au bumps 8 are formed faces upward. Then, the tape 19 is positioned on the semiconductor chip 2 such that the leads 7 projecting from the base material 10 of the tape 19 and the Au bumps 8 of the semiconductor chip 2 face each other. The semiconductor chip 2 and the tape 19 are aligned so that the positions of the bumps 8 and the connection portions near the ends of the leads 7 of the tape 19 match. At this time, it is preferable that the distance between each lead 7 and the Au bump 8 be as close as possible. The tape 19 is aligned so that the surface on which the stiffener 3 is formed is on the semiconductor chip 2 side.
その後、 図 1 8 ( b ) に示すように、 上記の位置関係を確保したまま、 テープ 1 9をテープガイド （図示しない） により動かないように固定した状態でボンデ イングツール 2 6を半導体チップ 2の主面側に垂直に打ち下ろすことにより、 リ 一ド 7と A uバンプ 8とを押圧し接合する （以下、一括ボンディング法と称する）。 この時、テープ 1 9との位置関係が変わらないように接合することが重要となる。 例えば、 ツールによる押圧する量を A uバンプの径以下とするのが好ましい。 こ の一括ボンディング法は、 ピン数が多くても 1回でボンディングが行えるので、 ボンディングに要する時間はピン数に依存せず短時間で済む。 このボンディング で重要なのは、 リード 7と A uバンプ 8が均一に加熱加圧されることである。 そ のためには、 リード 7の平坦性を確保しなければならない。 本実施の形態 1では、 前述したように、 各リード 7の先端を一体的に形成しておきリードオフセット加  Then, as shown in FIG. 18 (b), the bonding tool 26 is fixed to the semiconductor chip 2 with the tape 19 fixed by a tape guide (not shown) while maintaining the above positional relationship. The lead 7 and the Au bump 8 are pressed and joined by vertically falling down on the main surface side of the substrate (hereinafter, referred to as a collective bonding method). At this time, it is important to join them so that the positional relationship with the tape 19 does not change. For example, it is preferable that the pressing amount by the tool is equal to or smaller than the diameter of the Au bump. In this batch bonding method, bonding can be performed in a single operation even when the number of pins is large, so that the time required for bonding is short regardless of the number of pins. What is important in this bonding is that the leads 7 and the Au bumps 8 are uniformly heated and pressed. For that purpose, the flatness of the lead 7 must be ensured. In the first embodiment, as described above, the tip of each lead 7 is formed integrally, and the lead offset is added.
13 13
差替え用紙 （規則 26) ェと共にリード毎に分割することで各リードのばらつきを抑えて平坦性を保つこ とが可能となる。 以下、 この工程をリードボンディング工程と称する （工程 d ) 。 次に、 図 1 2の （e ) に示すように、 半導体チップ 2の集積回路が形成された 主面、 側面及びリード 7をポッティング法により液状の樹脂 5で封止する。 図 1 9に示すように半導体チップ 2の集積回路が形成された主面を上向きにした状態 で、 半導体チップ 2の主面、 リード 7上に、 図 1 9に付したループで示すように 移動可能なデイスペンサ 2 8により封止用樹脂 5を滴下させ、 半導体チップ 2の 主面、 側面及びリード 7を封止する。 このとき、 リード 7の隙間及び半導体チッ プ 2の側面は樹脂の表面張力によって充填される。 以下、 この工程を封止工程と 称する （工程 e ) 。 Replacement form (Rule 26) By dividing each lead together with the lead, it is possible to suppress variations in each lead and maintain flatness. Hereinafter, this step is referred to as a lead bonding step (step d). Next, as shown in (e) of FIG. 12, the main surface, side surfaces, and the leads 7 on which the integrated circuits of the semiconductor chip 2 are formed are sealed with a liquid resin 5 by a potting method. With the main surface of the semiconductor chip 2 on which the integrated circuit is formed facing upward as shown in FIG. 19, the semiconductor chip 2 is moved on the main surface of the semiconductor chip 2 and on the lead 7 as shown by the loop attached to FIG. The sealing resin 5 is dropped by a possible dispenser 28 to seal the main surface, the side surfaces, and the leads 7 of the semiconductor chip 2. At this time, the gap between the leads 7 and the side surfaces of the semiconductor chip 2 are filled by the surface tension of the resin. Hereinafter, this step is referred to as a sealing step (step e).
次に、 図 1 2の （ f ) に示すように、 テープ 1 9の感光性絶縁膜に形成された 開口部を通じて露出されているバンプランド部に、 P b— S nなどの材料から構 成されたボール状のはんだバンプ 9を接続する。 まず、 はんだバンプをバンプラ ンド部との平面的な位置合わせをして搭載治具 （図示しない） で吸着し、 その後、 搭載治具に吸着された状態のはんだバンプにフラックスを塗布し、 搭載治具によ り、 フラックスを塗布したはんだバンプ 9を半導体装置のバンプランド部に一括 で接続する。 以下、 この工程をはんだバンプ搭載工程と称する （工程 f ) 。  Next, as shown in (f) of FIG. 12, a bump land portion exposed through an opening formed in the photosensitive insulating film of the tape 19 is formed of a material such as Pb—Sn. The ball-shaped solder bump 9 is connected. First, the solder bumps are aligned with the bump land portion in a planar manner, and are adsorbed by a mounting jig (not shown). Then, a flux is applied to the solder bumps adsorbed by the mounting jig, and the mounting jig is mounted. The solder bumps 9 to which the flux has been applied are collectively connected to the bump lands of the semiconductor device. Hereinafter, this step is referred to as a solder bump mounting step (step f).
次に、 図 1 2の （g ) に示すように、 はんだバンプ搭載工程が完了した図 2 0 に示すような帯状のテープ 1 9を、 各ステフイナ 3の周縁よりやや外側の位置で 切断することにより半導体装置が個片に打ち抜かれる。 以下、 この工程を切断ェ 程と称する。 （工程 g )  Next, as shown in (g) of FIG. 12, the strip-shaped tape 19 as shown in FIG. 20 where the solder bump mounting process is completed is cut at a position slightly outside the peripheral edge of each stiffener 3. As a result, the semiconductor device is punched into individual pieces. Hereinafter, this step is referred to as a cutting step. (Step g)
その後、 この半導体装置に対し所定の検査を行い良否を判定する。 このように して、 半導体装置の製造工程が完了する。  Thereafter, a predetermined inspection is performed on the semiconductor device to judge the quality. Thus, the manufacturing process of the semiconductor device is completed.
なお、 リードボンディング工程 （工程 d ) でのリード 7と A uバンプ 8との接 続方法は、 一括ボンディング法に限定されるものではなく、 例えば、 ヒータで加 熱したボンディングステージ上で半導体チップを加熱し、 ボンディングツールに 超音波と加重を加えて、 リードと半導体チップの A uバンプとを 1点ずつ接続す る方法 （以下、 シングルポイントボンディング法） で行っても良い。 一括ボンデ ィング法は半導体チップの種類ごとにボンデイングッ一ルが異なり、 品種交換を  The method of connecting the leads 7 and the Au bumps 8 in the lead bonding step (step d) is not limited to the batch bonding method. For example, the semiconductor chip is mounted on a bonding stage heated by a heater. Heating, applying ultrasonic waves and weight to the bonding tool, and connecting the leads and Au bumps of the semiconductor chip one point at a time (hereinafter, single point bonding method) may be used. In the batch bonding method, the bonding rules are different for each type of semiconductor chip,
14 14
差替え用紙 （規則 26) 頻繁に行う必要がある場合作業効率が悪い。 しかし、 シングルポイントボンディ ング法は、 ボンディングツールの交換が必要なく品種交換が容易に行え、 AS I Cのような少量多品種製品への適用が適している。 Replacement form (Rule 26) The work efficiency is poor when it is necessary to perform it frequently. However, the single-point bonding method allows easy product change without the need to change the bonding tool, and is suitable for application to small-quantity multi-product products such as AS ICs.
又、 封止工程 （工程 e) の封止方法は、 ポッティング法に限定されるものでは なく トランスファモールドで行っても良い。 トランスファモールド法は、 まずォ フセット加工されたリードに半導体チップを接続した状態のテープを成型用の第 1の金型と第 2の金型との間に半導体チップが各金型表面に形成されているキヤ ビティに収まるように搭載し、 その後、 第 1の金型及び第 2の金型を型締めし、 キヤビティ内へゲートを介し、 封止用樹脂を流し込み半導体チップ及びリードを 封止する方法である。 このようなトランスファモールド法の場合、 樹脂が半導体 装置の補強部材であるステフィナの役割を果たすので、 ステフィナは必要なレ、。 したがって、 半導体装置の製造コストが低減される。  Further, the sealing method in the sealing step (step e) is not limited to the potting method, and may be performed by transfer molding. In the transfer molding method, first, a tape in which a semiconductor chip is connected to an offset-processed lead is formed between a first mold and a second mold for molding, and the semiconductor chip is formed on each mold surface. The first mold and the second mold are then clamped, and the sealing resin is poured into the cavity via a gate to seal the semiconductor chip and leads. Is the way. In the case of such a transfer molding method, the resin plays a role of a stiffener which is a reinforcing member of a semiconductor device. Therefore, the manufacturing cost of the semiconductor device is reduced.
次に、 本実施の形態 1の半導体装置 1を実装基板に実装した例を説明する。 まず、 図 21〜24を用いて、 本発明の実施の形態 1の半導体装置 1を小型の メモリカードに適用した例を説明する。  Next, an example in which the semiconductor device 1 of the first embodiment is mounted on a mounting board will be described. First, an example in which the semiconductor device 1 according to the first embodiment of the present invention is applied to a small-sized memory card will be described with reference to FIGS.
図 21は、 実施の形態 1の半導体装置 1を小型のメモリ力一ド用のプリント基 板 29に実装した場合の平面図であり、 同図の （a) は一面側の平面図であり、 (b) は、 それと反対側の他の一面側の平面図である。 Figure 21 is a plan view of a case of mounting the semiconductor device 1 of the first embodiment on the printed board 29 for a small memory force one de, of FIG (a) is a plan view of one side, (b) is a plan view of the other surface on the opposite side.
同図の （a) に示されるように、 プリント基板 29の一面には本発明の実施の 形態 1の半導体装置 1及び T C P (T a p e C a r r i e r P a c k a g e) や TSOP (Th i n Sma l l Ou t— l i n e P a c k a g e) 等の薄型パッケージを用いたメモリ 30が実装される。 又、 同図の （b) に示さ れるように、 プリント基板 29の他の一面にも前記と同様の薄型パッケージを用 いた複数のメモリ 30が実装される。 また、 プリント基板 29の他の一面には、 水晶発振子 33や、 チップコンデンサ及びチップ抵抗などの複数のチップ部品 3 2も実装される。  As shown in (a) of the figure, on one surface of the printed circuit board 29, the semiconductor device 1 of the first embodiment of the present invention and a tape carrier package (TCP) or a thin small output device (TSOP) are provided. The memory 30 using a thin package such as a line package is mounted. Further, as shown in FIG. 2B, a plurality of memories 30 using the same thin package as described above are mounted on the other surface of the printed circuit board 29. On the other surface of the printed circuit board 29, a crystal oscillator 33 and a plurality of chip components 32 such as a chip capacitor and a chip resistor are mounted.
そして、 このプリント実装基板 29は図 22に示されるように、 外部端子 3 1 を通じてプリント基板用ソケット 34に接続され、 プリント基板用ソケット 34 とプリント基板 29とがケース 35に収容され小型のメモリ力一ド 36を構成す  Then, as shown in FIG. 22, the printed circuit board 29 is connected to the printed circuit board socket 34 through the external terminals 31, and the printed circuit board socket 34 and the printed circuit board 29 are housed in the case 35 and a small memory capacity is provided. Make up 36
15 Fifteen
差替え用紙 （規則 26) るものである。 Replacement form (Rule 26) Things.
図 23は、 図 22のメモリカード 36の E— E'切断線における断面図であり、 図 24は、 図 22のメモリカード 36の F— F' 切断線における断面図である。 この小型のメモリカード 36に用いられる実施の形態 1の半導体装置 1は、 上 記メモリ 30の制御やホストマイコンとメモリ 30とのデータ一のやり取りの制 御等を行うための集積回路 （マイクロコンピューター及びゲ一トァレ一等の機能 を有する集積回路） が形成されている。  FIG. 23 is a cross-sectional view of the memory card 36 of FIG. 22 taken along the line EE ′, and FIG. 24 is a cross-sectional view of the memory card 36 of FIG. 22 taken along the line FF ′. The semiconductor device 1 of the first embodiment used for the small memory card 36 is an integrated circuit (microcomputer) for controlling the memory 30 and controlling the exchange of data between the host microcomputer and the memory 30. And an integrated circuit having functions such as a gateway).
又、 プリント基板 29の一面及び他の一面に形成されるメモリ 30は、 データ を半永久的に保存する不揮発性メモリやメモリ力一ドの制御用プログラムの格納 等に用いられる揮発性メモリである。 上記不揮発性メモリとしては、 フラッシュ メモリ、 EE P ROM (E l e c t r i c a l l y E r a s a b l e a n d The memory 30 formed on one side of the printed circuit board 29 and the other side is a non-volatile memory for semi-permanently storing data and a volatile memory used for storing a control program for a memory card. Examples of the non-volatile memory include a flash memory, an E-PROM (Ele c t r i c a l l y y E r a s a b l e a n d
P r o g r amma b l e Re a d On l y Memo r y) 、 EPR〇 M( E r a s a b l e a n d P r o g r amma b l e Re a d O n 1 y Memo r y ) , マスク ROM、 等が用いられる。 又、 上記揮発性メモリと しては DRAMや S RAMなどが用いられる。 For example, ProgrammabLeReadOnLyMemory), EPR〇M (ErasablEndAmProgRammamBleEReDOn1yMemory), a mask ROM, and the like are used. Also, as the volatile memory, DRAM, SRAM, or the like is used.
実施の形態 1の半導体装置 1の裏面のはんだバンプ 9はプリント基板 29上の 配線 （図示せず） と電気的に接続されている。 また、 TCPや TSOP型のメモ リ 30のリード部が、 プリント基板 29上の配線と電気的に接続されている。 又、 実施の形態 1の半導体装置 1を二つ用い、 一つは、 マイクロコンピュータ 一の機能を有するものとし、他の一つはゲ一トァレ一の機能を有するものとして、 プリント基板 29の一面に実施の形態 1の半導体装置 1を二つ実装しても良い。 この場合、 プリント基板 29の他の一面に実装される複数のメモリ 30は、 一つ が不揮発性メモリであり、 他の一つは揮発性メモリとなる。  The solder bumps 9 on the back surface of the semiconductor device 1 of the first embodiment are electrically connected to wiring (not shown) on the printed circuit board 29. Further, the leads of the TCP or TSOP type memory 30 are electrically connected to the wiring on the printed circuit board 29. Also, two semiconductor devices 1 of the first embodiment are used, one is a microcomputer having one function, and the other is a microcomputer having a function of a gate. Alternatively, two semiconductor devices 1 of the first embodiment may be mounted. In this case, one of the plurality of memories 30 mounted on the other surface of the printed circuit board 29 is a non-volatile memory, and the other is a volatile memory.
このようなメモリカード 36では、 従来薄型化が困難とされていた高性能且つ 多ピンの半導体装置である制御系の半導体装置 （マイクロコンピュータ一ゃゲー トアレーまたはこれら両者の機能を有するもの） として実施の形態 1のような薄 型の半導体装置 1を用いたことで、 メモリカード 36の小型、 軽量化に加え、 大 幅な薄型化が可能となる。 また、 実施の形態 1の半導体装置 1は表面実装型であ るので、 TCP型、 TSOP型、 UT SOP型等の他の表面実装型の半導体装置  Such a memory card 36 is implemented as a control-type semiconductor device (a microcomputer single-gate array or a device having both of these functions), which is a high-performance and multi-pin semiconductor device that has conventionally been difficult to reduce in thickness. By using the thin semiconductor device 1 as in the first embodiment, the memory card 36 can be reduced in size and weight and can be significantly reduced in thickness. In addition, since the semiconductor device 1 of the first embodiment is a surface mount type, other surface mount type semiconductor devices such as a TCP type, a TSOP type, and a UT SOP type.
16 16
差替え用紙 （規則 26) と共に同一の実装基板に搭載して一括でリフローすることができ実装が容易であ る。 Replacement form (Rule 26) In addition, it can be mounted on the same mounting board and reflowed collectively, which facilitates mounting.
このような小型のメモリカード 36は、 例えば、 デジタルカメラなどに用いら れるコンパク トメモリカードとして用いれば大変有益である。  Such a small memory card 36 is very useful if used as, for example, a compact memory card used in digital cameras and the like.
次に、 図 25を用いて、 本実施の形態 1の半導体装置 1をマルチメディア機器 用のプリント基板 39に適用した例を説明する。 図 25は、 実施の形態 1の半導 体装置 1をマルチメディア機器用のプリント基板 39に実装した一例を示す平面 図である。  Next, an example in which the semiconductor device 1 of the first embodiment is applied to a printed circuit board 39 for a multimedia device will be described with reference to FIG. FIG. 25 is a plan view showing an example in which the semiconductor device 1 of the first embodiment is mounted on a printed circuit board 39 for multimedia equipment.
図 25に示すように、 上記プリント基板 39の表面には、 複数の実施の形態 1 の半導体装置 1と共に複数の QF P (Qu a d F l a t P a c k a g e) 型 の半導体装置 38や、 丁。？型又は丁3〇？型の半導体装置37が実装されてい る。 実施の形態 1の半導体装置 1は、 例えばマイクロコンピューターやゲートァ レー等の集積回路が形成されたものである。  As shown in FIG. 25, on the surface of the printed circuit board 39, a plurality of QFP (QuadFlatPaccage) type semiconductor devices 38 together with the plurality of semiconductor devices 1 of the first embodiment and a plurality of semiconductor devices 1 are provided. ? Type or 3 丁? Type semiconductor device 37 is mounted. The semiconductor device 1 according to the first embodiment is one in which an integrated circuit such as a microcomputer or a gate array is formed.
実施の形態 1の半導体装置の裏面のはんだバンプ 9はプリント基板 38上の配 線と電気的に接続されている。 また、 QFP、 TC P型又は T S〇 P型の半導体 装置 37のリード部は、 プリント基板 39上の配線と電気的に接続されている。 このプリント基板 39においては、 実施の形態 1の半導体装置 1を複数採用す ることで実装密度が向上され、 プリント基板 39の面積の小型化、 軽量化を向上 することができる。 このような小型のプリント基板 39は、 カメラ一体型 VTR、 ノート型パソコン等の機器に組み込まれ、 製品の高性能、 携帯性、 軽量化に大き く貢献する。 また、 実施の形態 1の半導体装置 1は表面実装型であるので、 QF P、 TCP型又は TSOP型等の他の表面実装型の半導体装置と共に実装基板に 搭載して一括でリフローすることができ実装が容易である。  The solder bumps 9 on the back surface of the semiconductor device of the first embodiment are electrically connected to the wiring on the printed circuit board 38. In addition, the leads of the semiconductor device 37 of the QFP, TCP or TSP type are electrically connected to the wiring on the printed circuit board 39. In the printed circuit board 39, by using a plurality of the semiconductor devices 1 of the first embodiment, the mounting density is improved, and the area and the weight of the printed circuit board 39 can be reduced. Such a small printed circuit board 39 is incorporated in devices such as a camera-integrated VTR and a notebook computer, and greatly contributes to high performance, portability, and weight reduction of products. In addition, since the semiconductor device 1 of the first embodiment is a surface mount type, it can be mounted on a mounting board together with another surface mount type semiconductor device such as a QFP, TCP type, or TSOP type and reflowed collectively. Easy to implement.
次に、 上述した本実施の形態 1の効果について下記する。  Next, effects of the above-described first embodiment will be described below.
上述した本実施の形態 1の半導体装置 1によれば、 次のような効果を得ること ができる。  According to the semiconductor device 1 of the first embodiment described above, the following effects can be obtained.
(1) 半導体装置 1を側面方向から見た場合の半導体チップの位置を可能な限 り半導体装置 1の中央部側へ配置することができる。 すなわち、 はんだバンプ 9、 配線基板 4、 配線基板 4上のリード 7、 ステフイナ 3、 接着剤 1 1、 の合計厚さ  (1) When the semiconductor device 1 is viewed from the side, the position of the semiconductor chip can be arranged as close to the center of the semiconductor device 1 as possible. That is, the total thickness of the solder bump 9, the wiring board 4, the lead 7 on the wiring board 4, the stiffener 3, and the adhesive 11
17 17
差替え用紙 （規則 26) の中に半導体チップ 2と Auバンプ 8及び Auバンプ 8に接続されるリード 7と が収まるように半導体装置 1を構成することができ、 半導体装置 1の薄型化を達 成できる。 Replacement form (Rule 26) The semiconductor device 1 can be configured so that the semiconductor chip 2 and the Au bumps 8 and the leads 7 connected to the Au bumps 8 can be accommodated therein, and the semiconductor device 1 can be made thinner.
例えば、 はんだバンプ 9の直径 = 3 0 0 μ πι、 配線基板 4 = 8 7 μ τη 、 リード 7の厚さ = 1 8 Mm, ステフイナ 3 = 2 0 0 /i m 、 接着剤 1 1 = 5 0 μ m、 半導 体チップ 2の厚さ = 4 0 0 /z m、 A uバンプの高さ = 3 5 μ mの半導体装置 1の 厚さは 6 5 5 μ mとなる。  For example, diameter of solder bump 9 = 300 μπι, wiring board 4 = 87 μτη, thickness of lead 7 = 18 Mm, stiffener 3 = 200 / im, adhesive 1 1 = 50 μ m, the thickness of the semiconductor chip 2 = 400 / zm, and the height of the Au bump = 35 μm, the thickness of the semiconductor device 1 is 655.5 μm.
以上のように、 本実施の形態 1の半導体装置によれば、 リードをオフセット構 造とすることで半導体装置の最終構造の厚さを極めて薄型の構造とすることがで きるので薄型で多ピン化対応の半導体装置を得ることができる。  As described above, according to the semiconductor device of the first embodiment, since the thickness of the final structure of the semiconductor device can be made extremely thin by setting the leads to the offset structure, the thin and multi-pin structure is achieved. Accordingly, it is possible to obtain a semiconductor device compatible with the chemical conversion.
(2) 半導体チップ 2との接続手段として、 ポリイミ ド樹脂等の基材 1 0に配 線パターンのリード 7を形成したテープ 1 9を用いているので、 生産性が高く、 半導体装置の組立が低コストで行えるというメリットがある。  (2) As a means for connecting to the semiconductor chip 2, a tape 19 having a lead 7 of a wiring pattern formed on a base material 10 such as polyimide resin is used. There is an advantage that it can be performed at low cost.
(3) 半導体装置 1と実装基板との接続用のはんだバンプ 9を配線基板 4のリ —ド 7形成面側に接続しているのでスルーホールゃ多層配線を形成する必要がな く半導体装置の製造が低コストで行える。  (3) Since the solder bumps 9 for connection between the semiconductor device 1 and the mounting board are connected to the lead 7 forming surface side of the wiring board 4, there is no need to form through holes and multilayer wiring, and the Manufacturing can be performed at low cost.
(4) 半導体装置 1と実装基板との接続用のはんだバンプ 9を、 半導体装置 1 の裏面に 2次元に整列されて配置する構造なので、 半導体装置の面積を大きくす ることなく多ピン化が可能となる。  (4) Since the solder bumps 9 for connecting the semiconductor device 1 to the mounting board are arranged two-dimensionally on the back surface of the semiconductor device 1, the number of pins can be increased without increasing the area of the semiconductor device. It becomes possible.
(5) リード 7を部材状態でオフセッ ト加工することで、 リード 7が精度良く オフセット加工できる。  (5) The lead 7 can be offset-processed with high accuracy by offsetting the lead 7 in a member state.
(6) 配線基板 4のリード 7の長さを長めに形成しておき、 半導体チップ 2の 外形寸法に合わせて先端を切断するようにしたので異なった外形寸法の半導体チ ップに対応可能となり、 半導体装置 1の製造コストが低減される。  (6) The length of the lead 7 of the wiring board 4 is made longer and the tip is cut according to the outer dimensions of the semiconductor chip 2, so that semiconductor chips with different outer dimensions can be supported. The manufacturing cost of the semiconductor device 1 is reduced.
(7) 表面実装型の半導体装置 1であるので、 QF P、 T S OP, UT SO P、 TC P型等の他の表面実装型の半導体装置と共に同一の実装基板に搭載し て一括でリフローすることができ実装が容易となる。  (7) Since it is a surface-mount type semiconductor device 1, it is mounted on the same mounting board together with other surface-mount type semiconductor devices such as QFP, TSOP, UT SOP, and TCP, and reflowed collectively. Can be easily mounted.
(8) 半導体装置をプリント基板に実装する実装構造を小型化、 軽量化及び薄 型化することができる。  (8) The mounting structure for mounting a semiconductor device on a printed circuit board can be reduced in size, weight, and thickness.
18 18
差替え用紙 （規則 26) (実施の形態 2 ) Replacement form (Rule 26) (Embodiment 2)
まず、 図 2 6〜 2 8を用いて、 実施の形態 2の半導体装置の構造を説明する。 本実施の形態 2の半導体装置は、 実施の形態 1と同様に、 配線基板 4のリード 7 をオフセット加工した B G A型の半導体装置であるが、 実施の形態 1との相違点 は、 リード 7のオフセッ ト方向と半導体チップ 2の素子形成面の向きの違いであ る。 図 2 7及び図 2 8に示すように実施の形態 2の半導体チップ 2は、 半導体チ ップ 2の素子形成面と対向する反対の面 （非素子形成面） が半導体装置 1の裏面 側すなわちはんだバンプ 9側を向いた状態 （以下、 フェイスアップと称する） で 半導体装置 1内に組み込まれる。  First, the structure of the semiconductor device of the second embodiment will be described with reference to FIGS. The semiconductor device of the second embodiment is a BGA type semiconductor device in which the lead 7 of the wiring board 4 is offset-processed as in the first embodiment, but the difference from the first embodiment is that the lead 7 This is the difference between the offset direction and the direction of the element forming surface of the semiconductor chip 2. As shown in FIGS. 27 and 28, in the semiconductor chip 2 of the second embodiment, the surface opposite to the element forming surface of the semiconductor chip 2 (non-element forming surface) is on the back surface side of the semiconductor device 1, It is incorporated into the semiconductor device 1 in a state facing the solder bump 9 side (hereinafter, referred to as face-up).
すなわち、 実施の形態 2の半導体装置 1は、 配線基板 4のデバイスホールに突 出するリード 7に、 半導体装置 1の表面側 （配線基板 4のステフイナ 3が形成さ れる側） に折り曲げ加工した第 1の折り曲げ部 1 5と、 第 1の折り曲げ部 1 5よ りリード先端側に半導体チップ 2の素子形成面と平行な接続部が形成されるよう に折り曲げ加工した第 2の折り曲げ部 1 6とを設けることにより、 リード 7と半 導体チップ 2との接続面をリード 7突出平面より半導体装置 1の表面側すなわち、 ステフイナ 3が形成される側、 言い替えると半導体チップとリードとの接続部か ら遠ざかる方向に位置させ、 そのリード 7に半導体チップ 2をフェイスアップで 接続した構造である。  That is, in the semiconductor device 1 of the second embodiment, the lead 7 protruding into the device hole of the wiring board 4 is bent on the front side of the semiconductor device 1 (the side on which the stiffener 3 of the wiring board 4 is formed). The first bent portion 15 and the second bent portion 16 which is bent so that a connection portion parallel to the element forming surface of the semiconductor chip 2 is formed on the lead tip side of the first bent portion 15. By providing the lead, the connection surface between the lead 7 and the semiconductor chip 2 is shifted from the surface of the semiconductor device 1 from the projecting plane of the lead 7, that is, from the side where the stiffener 3 is formed, in other words, from the connection portion between the semiconductor chip and the lead. In this structure, the semiconductor chip 2 is connected face-up to the lead 7 of the semiconductor chip 2 in a direction away from it.
この時、 リード 7に接続した半導体チップ 2の非素子形成面の位置が図 2 7に 示すように、 はんだバンプ 9の最下点より低くならないようにリード 7のオフセ ット量を制御して構成することが重要である。  At this time, the offset amount of the lead 7 is controlled so that the position of the non-element forming surface of the semiconductor chip 2 connected to the lead 7 is not lower than the lowest point of the solder bump 9 as shown in FIG. It is important to configure.
次に、 本実施の形態 2の半導体装置 1を、 プリント基板に実装した一例を図 2 9に示す。 プリント基板 4 0の表面に、 Q F P型の半導体装置と共に、 実施の形 態 2の半導体装置 1が実装される。  Next, an example in which the semiconductor device 1 of the second embodiment is mounted on a printed circuit board is shown in FIG. The semiconductor device 1 according to the second embodiment is mounted on the surface of the printed circuit board 40 together with the QFP semiconductor device.
次に、 図 3 0のフローチャートに沿って、 本実施の形態 2の半導体装置の製造 方法の一例を説明する。  Next, an example of the method of manufacturing the semiconductor device of the second embodiment will be described with reference to the flowchart of FIG.
まず、 半導体装置の製造に先立って、 実施の形態 1と同様にテープ 1 9と、 ス テフイナ 3と、 半導体チップ 2と、 封止榭脂と、 フラックス、 はんだバンプ等を 準備する。  First, prior to the manufacture of the semiconductor device, a tape 19, a stepper 3, a semiconductor chip 2, a sealing resin, a flux, a solder bump, and the like are prepared as in the first embodiment.
19 19
差替え用紙 （規則 26) 次に、 リードオフセット工程において、 テープ 1 9のリード 7を、 実施の形態 1と同様ダイ及びパンチにより所定の形状に押圧成形すると共に、 切断パンチに より半導体チップに適した長さに切断する （工程 a ) 。 Replacement form (Rule 26) Next, in the lead offset step, the lead 7 of the tape 19 is pressed and formed into a predetermined shape by a die and a punch as in the first embodiment, and cut into a length suitable for a semiconductor chip by a cutting punch ( Step a ).
次に、 ステフイナ 3接着工程において、 リードオフセット工程で加工された帯 状のテープ 1 9の基材 1 0上のデバイスホールの周囲にステフイナ 9をエポキシ 樹脂等の接着剤 1 1を介して熱圧着する （工程 b ) 。  Next, in the stepper 3 bonding step, the stepper 9 is thermocompressed around the device hole on the base material 10 of the strip-shaped tape 19 processed in the lead offset step via an adhesive 11 such as an epoxy resin. (Step b).
次に、 A uバンプ 8形成工程において、 半導体チップ 2の一主面に形成された パッド上に、例えばボ一ルボンディング法などの方法で A uバンプ 8を形成する。 バンプの形成方法は、 めっき法で行ってもかまわない （工程 c ) 。  Next, in the Au bump 8 forming step, the Au bump 8 is formed on a pad formed on one main surface of the semiconductor chip 2 by a method such as a ball bonding method. The bump may be formed by plating (step c).
次に、 リードボンディング工程において、 ボンディングステージ上に、 半導体 チップ 2主面とテープ 1 9の感光性絶縁膜側の面とを対向させた状態で搭載し、 ボンディングツールを半導体チップ 2の主面側に垂直に打ち下ろすことにより、 半導体チップ 2の A uバンプ 8とテープ 1 9のリード 7と加熱加圧し接合する Next, in the lead bonding step, the semiconductor chip 2 is mounted on the bonding stage with the main surface of the semiconductor chip 2 and the surface of the tape 19 facing the photosensitive insulating film facing each other, and a bonding tool is mounted on the main surface of the semiconductor chip 2. By applying heat and pressure to the Au bumps 8 on the semiconductor chip 2 and the leads 7 on the tape 19
(工程 d ) 。 (Step d).
次に、 樹脂封止工程において、 半導体チップ 2の集積回路が形成された主面、 側面及びリード 7を封止用の樹脂 5により封止する （工程 e ) 。  Next, in the resin sealing step, the main surface, side surfaces, and the leads 7 on which the integrated circuits of the semiconductor chip 2 are formed are sealed with a sealing resin 5 (step e).
次に、 はんだバンプ形成工程において、 テープ 1 9の感光性絶縁膜に形成され た開口部を通じて露出されているバンプランド部に、 P b— S nなどの材料から 構成されたボール状のバンプを接続することで半導体装置の外部電極であるはん だバンプを形成する （工程 f ) 。  Next, in a solder bump forming step, a ball-shaped bump made of a material such as Pb—Sn is placed on the bump land portion exposed through the opening formed in the photosensitive insulating film of the tape 19. The connection forms a solder bump which is an external electrode of the semiconductor device (step f).
次に、 切断工程において、 帯状のテープ 1 9を、 ステフイナ 3の周縁よりやや 外側の位置で切断することにより半導体装置 1が個片に打ち抜かれる （工程 g ) 。 その後、 この半導体装置 1に対し所定の検査を行い良否を判定する。 このよう にして、 半導体装置 1の製造工程が完了する。  Next, in the cutting step, the semiconductor device 1 is punched into individual pieces by cutting the belt-shaped tape 19 at a position slightly outside the peripheral edge of the stiffener 3 (step g). After that, a predetermined inspection is performed on the semiconductor device 1 to determine the quality. Thus, the manufacturing process of the semiconductor device 1 is completed.
このような実施の形態 2によれば、 実施の形態 1で述べた効果 （1 ) と同様な 効果すなわち、 半導体装置 1を側面方向から見た場合の半導体チップ 2の位置を 可能な限り半導体装置 1の中央部側へ配置することができ、 はんだバンプ 9、 配 線基板 4、 配線基板 4上のリード 7、 ステフイナ 3、 接着剤 1 1、 の合計厚さの 中に半導体チップ 2、 A uバンプ 8及び A uバンプ 8に接続されるリード 7が収  According to such a second embodiment, the same effect as the effect (1) described in the first embodiment, that is, the position of the semiconductor chip 2 when the semiconductor device 1 is viewed from the side can be set as far as possible. 1 can be placed on the center side of the semiconductor chip 2, Au in the total thickness of solder bump 9, wiring board 4, lead 7 on wiring board 4, stepper 3, adhesive 1 1, Bump 8 and lead 7 connected to Au bump 8
20 20
差替え用紙 （規則 26) まる構造の半導体装置 1を構成することができる。 従って、 薄型で多ピン化対応 の半導体装置を得ることができる。 Replacement form (Rule 26) A semiconductor device 1 having a complete structure can be configured. Therefore, a thin semiconductor device capable of increasing the number of pins can be obtained.
その他実施形態 1で述べた効果 （2 ) 〜 （8 ) と同様な効果も得ることができ る。  Other effects similar to the effects (2) to (8) described in the first embodiment can also be obtained.
(実施の形態 3 )  (Embodiment 3)
図 3 1〜3 5を用いて、 実施の形態 3の半導体装置の構造その製造方法を説明 する。 本実施の形態 3の半導体装置は、 実施の形態 1および実施の形態 2と同様 に、 テープ配線基板 4のリード 7をオフセット加工した B G A型の半導体装置で あり、 実施の形態 3の特徴は、 半導体装置 1に熱特性向上のための放熱板 4 1を 搭載した点である。  The structure of the semiconductor device according to the third embodiment and a method for manufacturing the same will be described with reference to FIGS. The semiconductor device of the third embodiment is a BGA type semiconductor device in which the leads 7 of the tape wiring board 4 are offset-processed, as in the first and second embodiments. The features of the third embodiment are as follows. The point is that a heat sink 41 for improving thermal characteristics is mounted on the semiconductor device 1.
すなわち、 配線基板 4は、 実施の形態 1と同様のものであり、 その中央部には、 配線基板 4を貫通するデバイスホールが形成され、 そのデバイスホール内に半導 体チップが収容可能な構造となっている。 また、 デバイスホールには、 銅箔の配 線リード 7が複数突出され、 この各リード 7は、 半導体装置 1の裏面側すなわち はんだバンプ 9形成側に折り曲げ加工された第 1の折り曲げ部 1 5と、 第 1の折 り曲げ部 1 5よりリードの先端側に半導体チップ 2の素子形成面と平行な接続部 が形成されるように折り曲げ加工された第 2の折り曲げ部 1 6とを有する。  That is, the wiring board 4 is the same as that of the first embodiment, and a device hole penetrating the wiring board 4 is formed in the center thereof, and the semiconductor chip can be accommodated in the device hole. It has become. A plurality of wiring leads 7 made of copper foil protrude from the device hole. Each of the leads 7 is connected to a first bent portion 15 bent on the back side of the semiconductor device 1, that is, on the side on which the solder bump 9 is formed. And a second bent portion 16 which is bent so that a connection portion parallel to the element formation surface of the semiconductor chip 2 is formed on the tip end side of the lead from the first bent portion 15.
オフセット加工された各リード 7の接続部には、 半導体チップ 2がフェイスダ ゥンで接続されている。  The semiconductor chip 2 is connected to the connection portion of each offset-processed lead 7 by face down.
上記配線基板 4のステフイナ 3上面および半導体チップの非素子形成面には、 放熱特性を向上させるための放熱板 4 1が搭載されている。 このように、 放熱板 4 1を搭載するためには、 半導体チップ 2の非素子形成面とステフイナ 3の上面 が同一平面内に位置する必要がある。 例えば、 実施の形態 3では、 はんだバンプ 9の径を考慮して、 半導体チップ 2の位置が可能な限り半導体装置 1の中央部と なるようにリード 7のオフセット量を 1 2 5 μ mとした。 このような構造にする ことにより、 薄型化の達成とともに放熱特性の向上も図ることができる。 このォ フセット量は、 必ずしもこれに限定されるものではなく、 図 3 2、 図 3 3に示す ように半導体チップ 2の非素子形成面がステフイナ 3の上面とほぼ同一平面内に 位置するようなオフセット量であれば良い。  On the upper surface of the stiffener 3 of the wiring board 4 and the non-element forming surface of the semiconductor chip, a heat radiating plate 41 for improving heat radiating characteristics is mounted. As described above, in order to mount the heat sink 41, the non-element forming surface of the semiconductor chip 2 and the upper surface of the stepper 3 need to be located on the same plane. For example, in the third embodiment, the offset amount of the lead 7 is set to 125 μm in consideration of the diameter of the solder bump 9 so that the position of the semiconductor chip 2 is as close to the center of the semiconductor device 1 as possible. . With such a structure, it is possible to achieve a reduction in thickness and an improvement in heat radiation characteristics. This offset amount is not necessarily limited to this, and may be such that the non-element formation surface of the semiconductor chip 2 is located substantially in the same plane as the upper surface of the stepper 3 as shown in FIGS. 32 and 33. What is necessary is just an offset amount.
21 twenty one
差替え用紙 （規則 26) 上記放熱板は、 半導体チップ 2の非素子形成面及びステフイナ 3の上面にェポ キシ系樹脂の接着剤により接着される。 また、 放熱板の材料は、 半導体チップ 2 と熱膨張係数が近い材料である銅タングステン （C u— W) が好ましいが、 同様 の条件を満たす材料である F e系合金、 ムライ ト、 窒化アルミニウム、 炭素系の 材料例えばダイヤモンドなどを用いても良い。 Replacement form (Rule 26) The radiator plate is adhered to the non-element forming surface of the semiconductor chip 2 and the upper surface of the stepper 3 with an epoxy resin adhesive. The material of the heat sink is preferably copper tungsten (Cu-W), which has a coefficient of thermal expansion close to that of the semiconductor chip 2, but Fe-based alloy, mullite, and aluminum nitride, which satisfy the same conditions. Alternatively, a carbon-based material such as diamond may be used.
前記放熱板 4 1は、 半導体チップ 2で生じた熱を高効率に半導体装置の外部へ の放熱させるのに大きく寄与し、 半導体装置 1の動作信頼性及び寿命を向上させ ることができる。  The heat radiating plate 41 greatly contributes to efficiently radiating the heat generated in the semiconductor chip 2 to the outside of the semiconductor device, and can improve the operation reliability and the life of the semiconductor device 1.
また、 この放熱板 4 1には、 図 3 4に示すように、 さらなる高熱発生半導体装 置に対応するための放熱用のフィン 4 2を搭載することができる。 放熱フィン 4 2の材料はアルミニウム、 形状は表面積を広くし放熱特性を向上する形状が好ま しい。 材料、 形状は必ずしもこれに限定されるものではなく、 半導体チップの適 化を考慮して選択すれば良い。  Further, as shown in FIG. 34, radiating fins 42 can be mounted on the heat radiating plate 41 to cope with further high heat generation semiconductor devices. The material of the heat radiation fins 42 is preferably aluminum, and the shape is preferably a shape having a large surface area and improving heat radiation characteristics. The material and shape are not necessarily limited to these, and may be selected in consideration of the appropriateness of the semiconductor chip.
上記半導体チップの集積回路が形成された主面、 側面及びリードは保護及び半 導体装置の耐湿性の向上、 リードと半導体チップとの接合部の信頼性の向上を目 的に封止用の樹脂により封止される。 この樹脂は、 シリコーン樹脂、 エポキシ樹 脂等が用いられる。  The main surface, side surfaces and leads on which the integrated circuit of the semiconductor chip is formed are resin for sealing for the purpose of protecting and improving the moisture resistance of the semiconductor device and the reliability of the joint between the lead and the semiconductor chip. Sealed. As this resin, a silicone resin, an epoxy resin or the like is used.
半導体装置 1の裏面には、 実装基板との接続用端子として、 ボール状のはんだ バンプ 9がテープ配線基板 4の外縁に沿つて、 外縁側の列及びその内側の列の 2 列にわたり搭載される。  On the back surface of the semiconductor device 1, ball-shaped solder bumps 9 are mounted along the outer edge of the tape wiring board 4 as terminals for connection with the mounting board over two rows, an outer row and an inner row. .
以下、 図 3 5のフローチャートに沿って、 本実施の形態 3の半導体装置の製造 方法を説明する。  Hereinafter, the method of manufacturing the semiconductor device of the third embodiment will be described with reference to the flowchart of FIG.
まず、 半導体装置の製造に先立って、 テープと、 ステフイナと、 半導体チップ と、 封止樹脂と、 フラックス、 はんだボールと放熱板等を準備する。  First, before manufacturing a semiconductor device, a tape, a stepper, a semiconductor chip, a sealing resin, a flux, a solder ball, a heat sink, and the like are prepared.
次に、 リードオフセット工程において、 テープ 1 9のリードを実施の形態 1と 同様ダイ及びパンチにより所定の形状に押圧成形すると共に切断パンチにより半 導体チップの外形に適した長さに切断する （工程 a ) 。  Next, in the lead offset step, the leads of the tape 19 are pressed and formed into a predetermined shape by a die and a punch in the same manner as in the first embodiment, and are cut to a length suitable for the outer shape of the semiconductor chip by a cutting punch (step). a).
次に、 ステフイナ接着工程において、 リードオフセット工程で加工された帯状 のテープ 1 9の基材 1 0上のデバイスホールの周囲にステフイナ 3をエポキシ樹  Next, in a stiffener bonding process, a stiffener 3 is applied to the band-shaped tape 19 processed in the lead offset process around the device holes on the base material 10 by epoxy resin.
22 twenty two
差替え用紙 （規則 26) 脂等の接着剤 1 1をを介して熱圧着する （工程 b ) 。 Replacement form (Rule 26) Thermocompression bonding is performed via an adhesive 11 such as a fat (step b).
次に、 A uバンプ形成工程において、 半導体チップの一主面に形成されたパッ ド上に、 例えばボールボンディング法などの方法で A uバンプ 8を形成する。 バ ンプの形成方法は、 めっき法で行ってもかまわない （工程 c ) 。  Next, in an Au bump formation step, an Au bump 8 is formed on the pad formed on one main surface of the semiconductor chip by a method such as a ball bonding method. The bump may be formed by plating (step c).
次に、 リードボンディング工程において、 ボンディングステージ上に、 半導体 チップ主面とテープ 1 9のリード 7とを対応させた状態で搭載し、 ボンディング ツールを半導体チップ 2の主面側に垂直に打ち下ろすことにより、 半導体チップ の A uバンプ 8とテープ 1 9のリード 7とを加熱加圧し接合する （工程 d ) 。 次に、 半導体チップ 2の非素子形成面及びステフイナ 3の上面にエポキシ系樹 脂等の接着剤を介して放熱板を接着する （工程 e ) 。  Next, in the lead bonding process, the semiconductor chip main surface and the leads 7 of the tape 19 are mounted on the bonding stage in correspondence with each other, and the bonding tool is dropped vertically to the main surface side of the semiconductor chip 2. Thus, the Au bumps 8 of the semiconductor chip and the leads 7 of the tape 19 are heated and pressed to join them (step d). Next, a heat sink is bonded to the non-element forming surface of the semiconductor chip 2 and the upper surface of the stiffener 3 via an adhesive such as an epoxy resin (step e).
次に、 樹脂封止工程において、 半導体チップの集積回路が形成された主面、 側 面及びリ一ドを封止用の樹脂により封止する （工程 f ) 。  Next, in the resin sealing step, the main surface, side surface and lead of the semiconductor chip on which the integrated circuit is formed are sealed with a sealing resin (step f).
次に、 はんだバンプ形成工程において、 テープ 1 9のソルダ一レジストに形成 された開口部を通じて露出されているバンプランド部に、 P b— S nなどの材料 から構成された球形のバンプを接続することで半導体装置の外部電極であるはん だバンプを形成する （工程 g ) 。  Next, in the solder bump forming step, a spherical bump made of a material such as Pb-Sn is connected to the bump land exposed through the opening formed in the solder resist of the tape 19. As a result, solder bumps, which are external electrodes of the semiconductor device, are formed (step g).
次に、 切断工程において、 帯状のテープ 1 9を、 ステフイナ 3の周縁よりやや 外側の位置で切断することにより半導体装置 1が単体に打ち抜かれる （工程 h ) 。 その後、 この半導体装置 1に対し所定の検査を行い良否を判定する。 このように して、 半導体装置の組立工程が完了する。  Next, in a cutting step, the band-shaped tape 19 is cut at a position slightly outside the periphery of the stiffener 3, whereby the semiconductor device 1 is punched into a single piece (step h). After that, a predetermined inspection is performed on the semiconductor device 1 to determine the quality. Thus, the assembling process of the semiconductor device is completed.
このような実施の形態 3の半導体装置によれば、 実施の形態 1で説明した効果 ( 1 ) 〜 （7 ) と同様な効果を得ることができる。  According to such a semiconductor device of the third embodiment, effects similar to the effects (1) to (7) described in the first embodiment can be obtained.
さらに、 効果 （8 ) として、 放熱板や放熱フィンを搭載することにより、 それ を搭載しない場合に比べ熱抵抗が約 1 Z 2となり、 半導体装置の放熱特性を大幅 に向上することができる。  Further, as an effect (8), by mounting a heat radiating plate or a heat radiating fin, the heat resistance becomes about 1 Z 2 compared to a case where no heat radiating plate or heat radiating fin is mounted, and the heat radiation characteristics of the semiconductor device can be greatly improved.
以上、 本発明者によってなされた発明を実施の形態に基づき説明したが、 本発 明は前記実施の形態に限定されるものではなく、 その要旨を逸脱しない範囲で 種々変更可能であることはいうまでもない。  As described above, the invention made by the inventor has been described based on the embodiment. However, the present invention is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even.
23 twenty three
差替え用紙 （規則 26) 産業上の利用可能性 Replacement form (Rule 26) Industrial applicability
以上のように、 本発明に係わる半導体装置は、 B G A型半導体装置に適用して 有益であり、 又、 この B G A型半導体装置を用いる小型のメモリカードやハンデ イタイプのパーソナルコンピューターなどの携帯機器、 および小型の情報通信機 器等に適用して有用である。  As described above, the semiconductor device according to the present invention is useful when applied to a BGA type semiconductor device, and a portable device such as a small memory card or a handy type personal computer using the BGA type semiconductor device, and It is useful when applied to small information communication equipment.
24 twenty four
差替え用紙 （規則 26)  Replacement form (Rule 26)

Claims

請 求 の 範 囲 The scope of the claims
1 . 半導体チップと、 この半導体チップを囲むように設けられた配線基板と、 こ の配線基板から突出して上記半導体チップに接続されたリードと、 上記配線基板 の一主面に設けられ上記半導体チップを囲む補強部材と、 上記配線基板の上記補 強部材が設けられる一主面と反対の他の主面に上記配線基板の周縁に沿って設け られた複数のバンプと、 上記半導体チップとリードとを覆う樹脂とから成る半導 体装置であって、 上記半導体チップに接続されたリードは上記配線基板の補強部 材が設けられる側又は複数のバンプが設けられる側に折り曲げ加工され、 上記半 導体チップの上記リードと接続される面とは反対の面が上記リードが折り曲げ加 ェされる側とは反対の側に位置するように上記リードと上記半導体チップとが接 続されていることを特徴とする半導体装置。  1. A semiconductor chip, a wiring board provided so as to surround the semiconductor chip, a lead projecting from the wiring board and connected to the semiconductor chip, and a semiconductor chip provided on one main surface of the wiring board. A plurality of bumps provided along the periphery of the wiring board on the other main surface of the wiring board opposite to the one main surface on which the reinforcing member is provided, and the semiconductor chip and the lead. A lead that is connected to the semiconductor chip and is bent to a side on which the reinforcing member of the wiring board is provided or a side on which a plurality of bumps are provided; The lead and the semiconductor chip are connected so that the surface of the chip opposite to the surface to be connected to the lead is located on the side opposite to the side on which the lead is bent and added. Wherein a Rukoto.
2 . 上記リードは上記複数のバンプが設けられる側に折り曲げ加工されているこ とを特徴とする請求項 1に記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the lead is bent on a side on which the plurality of bumps are provided.
3 . 上記リードは上記配線基板の補強部材が設けられる側に折り曲げ加工されて いることを特徴とする請求項 1に記載の半導体装置。  3. The semiconductor device according to claim 1, wherein the lead is bent on a side of the wiring substrate on which a reinforcing member is provided.
4 . 上記リードの折り曲げ加工は、 上記半導体チップのリードと接続される面か ら遠ざかる方向に折り曲げ加工した第 1の折り曲げ加工部と、 この第 1の折り曲 げ加工部よりリード先端側で折り曲げ加工された第 2の折り曲げ加工部とを有す ることを特徴とする請求項 1乃至請求項 3のいずれか 1項に記載の半導体装置。 4. The lead is bent at a first bent portion bent in a direction away from a surface of the semiconductor chip to be connected to the lead, and at a lead tip side of the first bent portion. The semiconductor device according to any one of claims 1 to 3, further comprising a processed second bent portion.
5 . 上記配線基板の複数のバンプが設けられる側には感光性絶縁膜が形成 されていることを特徴とする請求項 1乃至請求項 4のいずれか 1項に記載の半導 体装置。 5. The semiconductor device according to any one of claims 1 to 4, wherein a photosensitive insulating film is formed on a side of the wiring board on which the plurality of bumps are provided.
6 . 上記複数のバンプは複数列に整列されて設けられていることを特徴とする請 求項 1乃至請求項 5のいずれか 1項に記載の半導体装置。  6. The semiconductor device according to claim 1, wherein the plurality of bumps are provided in a plurality of rows.
7 . 半導体チップと、 この半導体チップを囲むように設けられた配線基板と、 こ の配線基板から突出して上記半導体チップに接続されたリードと、 上記配線基板 の一主面に設けられ上記半導体チッブを囲む補強部材と、 上記配線基板の上記補 強部材が設けられた一主面と反対の他の主面に上記配線基板の周縁に沿って設け  7. A semiconductor chip, a wiring board provided so as to surround the semiconductor chip, leads protruding from the wiring board and connected to the semiconductor chip, and a semiconductor chip provided on one main surface of the wiring board. A reinforcing member surrounding the wiring board on the other main surface of the wiring board opposite to the main surface on which the reinforcing member is provided.
25 twenty five
差替え用紙 （規則 26) られた複数のバンプと、 上記半導体チップとリードとを覆う樹脂とから成る半導 体装置であって、 上記配線基板と、 補強部材と、 複数のバンプとの合計厚さの中 に上記半導体チップと樹脂とが収納されるように構成されたことを特徴とする半 導体装置。 Replacement form (Rule 26) A semiconductor device comprising a plurality of bumps provided and a resin covering the semiconductor chip and the leads, wherein the semiconductor chip is included in a total thickness of the wiring board, the reinforcing member, and the plurality of bumps. And a resin.
8 . 上記半導体チップの上記リードと接続された面が上記複数のバンプが設けら れた側に向いていることを特徴とする請求項 7に記載の半導体装置。  8. The semiconductor device according to claim 7, wherein a surface of the semiconductor chip connected to the leads faces a side on which the plurality of bumps are provided.
9 . 上記半導体チップの上記リードと接続された面が上記補強部材が設けられた 側に向いていることを特徴とする請求項 7に記載の半導体装置。  9. The semiconductor device according to claim 7, wherein a surface of the semiconductor chip connected to the lead faces a side on which the reinforcing member is provided.
1 0 . 半導体チップと、 この半導体チップを囲むように設けられた配線基板と、 上記配線基板の一主面に設けられ上記半導体チップを囲む補強部材と、 上記配線 基板の上記補強部材が設けられた一主面と反対の他の主面に上記配線基板の周縁 に沿って設けられた複数のバンプと、 上記配線基板から突出して上記半導体チッ プに接続されたリードと、 上記半導体チップとリードとを覆う樹脂とから成る半 導体装置であって、 上記リードは上記複数のバンプが設けられた側に折り曲げ加 ェされ、 上記半導体チップの上記リードと接続された面とは反対の他の面が上記 補強部材が設けられた側に位置し、 上記半導体チップの他の面と上記補強部材の 表面に放熱板が接続されていることを特徴とする半導体装置。  10. A semiconductor chip, a wiring board provided so as to surround the semiconductor chip, a reinforcing member provided on one main surface of the wiring board and surrounding the semiconductor chip, and the reinforcing member of the wiring board are provided. A plurality of bumps provided along the periphery of the wiring substrate on the other main surface opposite to the one main surface; a lead projecting from the wiring substrate and connected to the semiconductor chip; A lead that is bent and added to the side on which the plurality of bumps are provided, and the other surface of the semiconductor chip opposite to the surface connected to the leads. Is located on the side where the reinforcing member is provided, and a heat sink is connected to the other surface of the semiconductor chip and the surface of the reinforcing member.
1 1 . 上記放熱板の上に放熱フィンが接続されていることを特徴とする請求項 1 0に記載の半導体装置。  11. The semiconductor device according to claim 10, wherein a radiation fin is connected to the heat radiation plate.
1 2 . 枠状の配線基板と、 この配線基板の一方の面に形成された複数のバンプと、 上記配線基板の他方の面に形成された補強部材と、 上記配線基板から突出して上 記複数のバンプが形成される側にオフセット加工された複数のリードと、 上記複 数のリードがオフセット加工された方向とは反対の方向に非素子形成面が位置す るように上記複数のリードに接続された半導体チップと、 上記半導体チップと複 数のリードとを覆う樹脂とから成ることを特徴とする半導体装置。  12. A frame-shaped wiring board, a plurality of bumps formed on one surface of the wiring board, a reinforcing member formed on the other surface of the wiring board, and the plurality of protrusions protruding from the wiring board. A plurality of leads that are offset-processed on the side where the bumps are formed, and are connected to the plurality of leads such that the non-element formation surface is located in a direction opposite to the direction in which the plurality of leads are offset-processed. A semiconductor device, comprising: a semiconductor chip formed as described above; and a resin covering the semiconductor chip and a plurality of leads.
1 3 . 枠状の配線基板と、 この配線基板の一方の面に形成された複数のバンプと、 上記配線基板の他方の面に形成された補強部材と、 上記配線基板から突出して上 記補強部材が形成される側にオフセット加工された複数のリードと、 上記複数の リ一ドがオフセット加工された方向とは反対の方向に非素子形成面が位置するよ  13. A frame-shaped wiring board, a plurality of bumps formed on one surface of the wiring board, a reinforcing member formed on the other surface of the wiring board, and the above-mentioned reinforcing member protruding from the wiring board. A plurality of leads that are offset-processed on the side where the member is formed, and the non-element formation surface is located in a direction opposite to the direction in which the plurality of leads are offset-processed.
26 26
差替え用紙 （規則 26) うに上記複数のリードに接続された半導体チップと、 上記半導体チップと複数の リードとを覆う樹脂とから成ることを特徴とする半導体装置。 Replacement form (Rule 26) A semiconductor device comprising: a semiconductor chip connected to the plurality of leads; and a resin covering the semiconductor chip and the plurality of leads.
1 4 . 樹脂基板とこの基板に設けられたデバイスホールとこのデバイスホールに 突出しかつ折り曲げ加工された銅箔のリードとを有する帯状のテープと、 上記デ バイスホールを囲むように上記テープの一主面に接続された補強部材とを準備す る工程、 上記テープのデバイスホール内に突出する折り曲げ加工された上記リー ドを半導体チップの一主面に接続する工程、 上記半導体チップ及びリードを樹脂 で封止する工程、 上記テープの上記補強部材が接続された一主面と反対側の他の 一主面に複数のバンプを接続する工程を有することを特徴とする半導体装置の製 造方法。  14. A band-shaped tape having a resin substrate, a device hole provided in the substrate, and a lead of a copper foil protruding from the device hole and being bent, and a main part of the tape surrounding the device hole. A step of preparing a reinforcing member connected to the surface; a step of connecting the bent lead projecting into a device hole of the tape to one main surface of the semiconductor chip; and a step of connecting the semiconductor chip and the lead with a resin. A method of manufacturing a semiconductor device, comprising: a sealing step; and a step of connecting a plurality of bumps to another main surface of the tape opposite to the one main surface to which the reinforcing member is connected.
1 5 . 上記テープは上記補強部材側に折り曲げ加工されたリ―ドを有し、 上記半 導体チップは、 上記リードとの接続面とは反対側の面が上記複数のバンプ側に位 置するように上記リードに接続されることを特徴とする請求項 1 4に記載の半導 体装置の製造方法。  15. The tape has a lead bent toward the reinforcing member, and the semiconductor chip has a surface opposite to a surface connected to the lead positioned on the plurality of bumps. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the semiconductor device is connected to the lead as described above.
1 6 . 上記テープは上記複数のバンプ側に折り曲げ加工されたリードを有し、 上 記半導体チップは、 上記リードとの接続面とは反対側の面が上記補強部材側に位 置するように上記リ一ドに接続されることを特徴とする請求項 1 4に記載の半導 体装置の製造方法。  16. The tape has leads bent on the plurality of bumps, and the semiconductor chip is arranged such that the surface opposite to the connection surface with the leads is located on the reinforcing member side. 15. The method according to claim 14, wherein the semiconductor device is connected to the lead.
1 7 . —主面及びこの一主面に対向する他の主面を有するプリント基板と、 この プリント基板の一主面及び他の主面に複数の半導体装置を実装する実装構造であ つて、 前記一主面には、 半導体チップと、 この半導体チップを囲むように設けら れた配線基板と、 この配線基板から突出して上記半導体チップに接続されたリー ドと、 上記配線基板の一主面に設けられ上記半導体チップを囲む補強部材と、 上 記配線基板の上記補強部材が設けられた一主面と反対の他の主面に上記配線基板 の周縁に沿って設けられた複数のバンプと、 上記半導体チップとリードとを覆う 樹脂とから成る半導体装置であって、 上記配線基板と、 補強部材と、 複数のバン プとの合計厚さの中に上記半導体チップと樹脂とが収納されるように構成された 半導体装置が実装されていることを特徴とする実装構造。  17. A printed circuit board having a main surface and another main surface facing the one main surface, and a mounting structure for mounting a plurality of semiconductor devices on one main surface and the other main surface of the printed circuit board, A semiconductor chip, a wiring board provided so as to surround the semiconductor chip, a lead projecting from the wiring board and connected to the semiconductor chip, and one main face of the wiring board A reinforcing member provided around the semiconductor chip, and a plurality of bumps provided along the periphery of the wiring board on the other main surface of the wiring board opposite to the one main surface on which the reinforcing member is provided. A semiconductor device comprising a resin covering the semiconductor chip and a lead, wherein the semiconductor chip and the resin are accommodated in a total thickness of the wiring board, a reinforcing member, and a plurality of bumps. Semiconductors configured as Mounting structure characterized in that location has been implemented.
1 8 . 上記半導体装置は、 マイクロコンピューター及び又はゲ一トァレ一の機能  18. The semiconductor device has the functions of a microcomputer and / or a gateway.
27 27
差替え用紙 （規則 26) を有する半導体装置であることを特徴とする請求項 1 7に記載の実装構造。 Replacement form (Rule 26) 18. The mounting structure according to claim 17, wherein the mounting structure is a semiconductor device having:
1 9 . 上記ブリント基板に実装される他の半導体装置は、 T C P型または T S O P型または U T S O P型のいづれかであることを特徴とする請求項 1 7に記載の 実装構造。 19. The mounting structure according to claim 17, wherein the other semiconductor device mounted on the printed board is one of a TCP type, a TSOP type, and a UTSOP type.
2 0 . 上記他の半導体装置は、 メモリであることを特徴とする請求項 1 9に記載 の実装構造。  20. The mounting structure according to claim 19, wherein the other semiconductor device is a memory.
2 1 . 上記実装構造は、 メモリカードに用いられることを特徴とする請求項 1 7 に記載の実装構造。  21. The mounting structure according to claim 17, wherein the mounting structure is used for a memory card.
2 2 . —主面を有するプリント基板と、 このプリント基板の一主面に実装される 複数の半導体装置とを有し、 前記複数の半導体装置の一部の半導体装置は、 半導 体チップと、 この半導体チップを囲むように設けられた配線基板と、 この配線基 板から突出して上記半導体チップに接続されたリードと、 上記配線基板の一主面 に設けられ上記半導体チップを囲む補強部材と、 上記配線基板の上記補強部材が 設けられた一主面と反対の他の主面に上記配線基板の周縁に沿って設けられた複 数のバンプと、 上記半導体チップとリードとを覆う樹脂とから成る半導体装置で あって、 上記配線基板と、 補強部材と、 複数のバンプとの合計厚さの中に上記半 導体チップと樹脂とが収納されるように構成された半導体装置であり、 他の半導 体装置は、 Q F P型の半導体装置であることを特徴とする実装構造。  2 2. A printed circuit board having a main surface, and a plurality of semiconductor devices mounted on one main surface of the printed circuit board. Some of the plurality of semiconductor devices include a semiconductor chip and a semiconductor chip. A wiring board provided to surround the semiconductor chip, a lead projecting from the wiring board and connected to the semiconductor chip, and a reinforcing member provided on one main surface of the wiring board and surrounding the semiconductor chip. A plurality of bumps provided along the periphery of the wiring substrate on another main surface of the wiring substrate opposite to the one main surface on which the reinforcing member is provided; and a resin covering the semiconductor chip and the lead. A semiconductor device comprising: the semiconductor chip and the resin accommodated in a total thickness of the wiring board, the reinforcing member, and the plurality of bumps. Semiconductor device , Mounting structure, which is a Q F P-type semiconductor device.
2 3 . 上記他の半導体装置は、 T C P型及び又は T S O P型であることを特徴と する請求項 2 2に記載の実装構造。  23. The mounting structure according to claim 22, wherein the other semiconductor device is a TCP type and / or a TSOP type.
2 4 . 上記実装構造は、 マルチメディア機器に用いられることを特徴とする請求 項 2 2に記載の実装構造。  24. The mounting structure according to claim 22, wherein the mounting structure is used for a multimedia device.
28 28
差替え用紙 （規則 26)  Replacement form (Rule 26)
PCT/JP1998/001182 1998-03-19 1998-03-19 Semiconductor device, method for manufacturing the same, and mounting structure of the same WO1999048145A1 (en)

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KR1020007007869A KR20010034214A (en) 1998-03-19 1998-03-19 Semiconductor device, method for manufacturing the same, and mounting structure of the same
US09/381,232 US20020149027A1 (en) 1998-03-19 1998-03-19 Semiconductor device and its manufacture, and semiconductor device packaging structure

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