Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
  • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
  • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
  • H03M1/0687—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using fault-tolerant coding, e.g. parity check, error correcting codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
  • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
  • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
  • H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
  • H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
  • H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/34—Analogue value compared with reference values
  • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
  • H03M1/40—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
  • H03M1/403—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type using switched capacitors
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/66—Digital/analogue converters
  • H03M1/667—Recirculation type

Definitions

• the present invention generally relates to analog-to-digital conversion, and more specifically to cyclic analog-to-digital conversion.
• An analog-to-digital (A/D) converter is a circuit on the borderline between the analog domain and the digital domain which acts as an intermediary in the exchange of information between the two domains.
• an A/D-converter converts or transforms analog input signals to digital output signals.
• An A/D-converter could be used for converting analog information such as audio signals or measurements of physical variables into numbers consisting of two-level digits or bits,- a form suitable for digital processing.
• A/D-converters are found in numerous applications of all modern technologies . They are widely used in different fields of electronics and communication.
• A/D-converter naturally determines to what extent the digital output signal truly represents the analog input signal.
• the performance evaluation of an A/D-converter with regard to accuracy and distortion is normally based on the magnitude of the error generated in the A/D-conversion.
• all A/D-converters suffer from offset errors due to imperfections in the circuit realizations of the converters. These offset errors will influence the behavior and performance of the A/D-converter.
• a particular type of A/D-converter is the cyclic A/D-converter which utilizes the same functional blocks cyclically for bit-wise generation of all the bits of a digital output value.
• cyclic A/D-converters are constructed to generate digital output signals of regular binary code.
• the offset errors propagate and accumulate in a strictly increasing manner during a conversion, thus limiting the accuracy of the converter and increasing the distortion. Relatively large differential and integral non-linearities will be introduced, and in the worst case scenario some output codes might be missing.
• the present invention reduces these and other drawbacks of the prior art .
• cyclic A/D- conversion of an analog input signal is performed according to an inventive recursive algorithm which generates a Gray coded digital output signal.
• the output bits are generated cyclically, one by one.
• the inventive Gray coding algorithm in each bit decision cycle, the digital information obtained from the previous bit decision determines whether or not the cyclic signal is inverted.
• the accumulation of offset errors will generally be very low.
• the fact that the signal inversion is digitally controlled enables high precision implementations which further improve the performance of the inventive cyclic A/D-converter.
• Gray code cyclic A/D-conversion offers the following advantages over conventional binary code cyclic A/D-conversion:
• Fig. 1 is a schematic diagram illustrating the basic principle of a conventional binary code cyclic A/D- converter (prior art) ;
• Fig. 2 is a schematic diagram illustrating the principle of a cyclic A/D-converter according to the invention
• Fig. 3 is a schematic flow diagram of a method for cyclically converting an analog input signal into a digital output signal in accordance with a preferred embodiment of the invention
• Fig. 4 is a schematic diagram illustrating the transformation of Gray coded bits into bits of binary code
• Fig. 5 is a circuit diagram of a fully differential realization of a cyclic A/D-converter in accordance with a currently most preferred embodiment of the invention
• Fig. 6 is a timing diagram illustrating clock pulses that are utilized in the differential implementation of Fig. 5;
• Fig. 7A-D are circuit diagrams of the fully differential implementation of Fig. 5 at different clock phases,-
• Fig. 8 illustrates a transfer curve of a 5-bit cyclic A/D- converter based on binary coding
• Fig. 9 illustrates a transfer curve of a 5 -bit cyclic A/D- converter based on the Gray coding algorithm according to the invention.
• Fig. 10 is a circuit diagram of a fully differential realization of a cyclic D/A-converter in accordance with the invention.
• a cyclic A/D-converter utilizes the same functional blocks cyclically to generate a digital output value, bit by bit.
• the analog signal circulates in a signal transforming loop from which the signal is recurrently sent to a comparator for bi -wise generation of the digital output bits.
• MSB most significant bit
• SB least significant bit
• Fig. 1 is a schematic diagram illustrating the basic principle of a conventional cyclic A/D-converter which is based on binary code.
• the binary code cyclic A/D-converter shown in Fig. 1 comprises the following functional blocks: a first switch 4, a comparator 5, a sample/hold amplifier 6 with a gain factor of 2, a second switch 7 and an adder/subtractor 8.
• clock signals are utilized to control the operation of the cyclic A/D- converter, i.e. functional blocks thereof. These clock signals are generated by a clock signal generator (not shown) .
• the A/D-conversion starts by connecting the first switch 4 to an input voltage, hereinafter referred to as the input signal, V ⁇ n or V 0 (l) . Accordingly, the input signal V ⁇ n is connected to the comparator 5 and the sample/hold amplifier 6.
• a first code bit b the most significant bit (MSB) of the digital output value, is generated depending on the sign of the input signal.
• the input signal is sampled and held by the sample/hold amplifier 6 which also amplifies the signal by a factor of 2.
• the generated code bit, in this case b ⁇ determines whether a reference voltage Vr, hereinafter referred to as the reference signal, is added to or subtracted from the amplified output signal of the sample/hold amplifier 6.
• the generated bit controls a second switch 7 such that either the reference signal or its inverse will be switched into connection with the adder/subtractor 8 and added to the output signal of the sample/hold amplifier 6.
• the first switch 4 is then connected to the output of the adder/subtractor 8, thus closing the loop and initiating signal circulation.
• the next code bit b 2 is determined by comparing the current output signal, in this case V 0 (2), of the adder/subtractor 8 with a zero level in the comparator 5.
• the 2-nd MSB, b 2 determines whether the reference voltage Vr or its inverse is added to the current output signal of the sample/hold amplifier 6.
• the first switch 4 is still connected to the output of the adder/subtractor 8 and the 3-rd MSB, b 3 , is generated in the comparator 5. The operation continues until the least significant bit (LSB) has been generated, at which time the loop is opened. A new A/D-conversion starts by once again connecting the first switch 4 to an input signal .
• LSB least significant bit
• Cyclic A/D-converters are also known as algorithmic A/D- converters, and the operation of the conventional binary code cyclic A/D-converter can be summarized by a recursive algorithm which is defined by the following equations :
• v (i) 2 • v n (i - l) + (-1) V r , (2 ⁇ i ⁇ n) ;
• b 1 denotes the i-th binary output bit
• i is an integer value ranging from 1 to n (n represents the number of bits of the digital output value) .
• h x is the MSB
• b n is the LSB of the digital output value.
• the resulting digital output value will have 4 bits, and hence the 4-th MSB is the SB.
• the A/D-conversion is completed. Accordingly, with a reference voltage of 1.0 V corresponding to the binary coded value of 1111, an input voltage of +0.49 V was converted into the binary coded output value 1011.
• V Q (i) 2 • v 0 (i - 1) + (-l) ⁇ - 1 • v r + ⁇ v e (i - 1) ; 2 ⁇ i ⁇ n
• V 0 (n) 2 11 - 1 • V in + ⁇ .n-l
• ⁇ v e (j) represents the error voltage produced when generating the (j+l)-th MSB. Since errors due to offset generally have the same sign, these errors are truly accumulated, limiting the accuracy and increasing the distortion of the conventional binary code cyclic A/D-converter.
• Cyclic A/D-conversion according to the invention
• the general idea according to the present invention is to perform cyclic A/D-conversion of an analog input signal into a digital output signal according to an inventive recursive Gray coding algorithm.
• the particular recursive algorithm used by the invention will be described below.
• the generated digital output signal is in the form of Gray code.
• a cyclic A/D-converter architecture based on the recursive Gray coding algorithm according to the invention the accumulation of errors during a cyclic conversion will be substantially reduced, compared to a conventional binary code cyclic A/D-converter.
• Gray code is known as a sequence of bit patterns in which adjacent patterns differ in only a single bit.
• the Gray code structure is most easily understood by studying table I given below.
• Table .1 illustrates 4-bit Gray code to the left, 4- bit binary code in the middle, and corresponding decimal numbers to the right .
• Gray code In both types of code, Gray code and binary code, the rightmost bit is the least significant bit (LSB) . It should however be realized that in Gray code, no specific bit weights can be assigned to the bits of the coded values. Gray code is sometimes described as a reflection code, because all the positions of a Gray code value except for the leftmost bit position (MSB) appear as a reflection around a reflection line, whereas the leftmost position changes logical state.
• MSB leftmost bit position
• Gray coding is often used for representing quantized signal levels and in phase shift keying.
• Gray coding has also been used in connection with A/D-converters in the prior art :
• Gray coding is used in folding-type A/D-converters .
• a folding-type A/D-converter comprises a plurality of parallel stages, and converts all bits in parallel, as opposed to a cyclic A/D- converter which uses a single stage to cyclically generate the output codes bit by bit. Since a folding-type converter determines all bits in parallel, there is no error accumulation as in cyclic converters. Instead Gray coding is used for reducing the number of comparators in the circuit realization.
• the stage- by- stage encoder of Waldhauer generates Gray code words by using an all-analog folding technique.
• the PCM- encoder has a plurality of cascaded encoder circuits .
• Each encoder circuit comprises a full wave rectifier, a sensing circuit for determining the instantaneous polarity of the signal and a sampling network for sampling the signal polarity at a suitable rate.
• Fig. 2 schematically illustrates an example of a cyclic A/D-converter according to the invention.
• the cyclic A/D-converter comprises the following functional blocks: a first switch 14, a comparator 15, a sample/hold amplifier 16, signal inverting means 17, a second switch 18 and an adder 19.
• the operation of the cyclic A/D- converter according to the invention is preferably controlled by appropriate clock signals.
• the clock signals are generated by a clock signal generator (not shown) . For reasons of simplicity and clarity, the clock signals are not shown in the schematic diagram of Fig. 2.
• the cyclic A/D-conversion starts by connecting the first switch 14 to the input voltage, hereinafter referred to as the input signal, V ⁇ n or V 0 (l) . Accordingly, the input signal V in is connected to the comparator 15 and the sample/hold amplifier 16. In the comparator 15, a first output bit b ⁇ (MSB) , in the form of Gray code, of the digital output signal, is generated depending on the sign of the input signal. The input signal V in is sampled and held by the sample/hold amplifier 16 which also amplifies the signal by a factor of 2.
• MSB first output bit b ⁇
• the generated Gray code bit in this case b 1( determines whether the output signal of the sample/hold amplifier 16 or its inverse is added to a reference voltage Vr, hereinafter referred to as the reference signal .
• the signal inversion is carried out by the signal inverting means 17.
• the second switch 18, which is controlled by the generated Gray code bit, determines if the output signal of the amplifier 16 or its inverse is connected to the adder 19.
• the adding is executed in the adder 19.
• the first switch 14 is then connected to the output of the adder 19, thus closing the signal loop and initiating signal circulation.
• the next Gray code bit b 2 is determined by comparing the current output signal of the adder 19, in this case V 0 (2), with a zero level in the comparator 15.
• the 2-nd MSB, b 2 determines whether the current output signal of the sample/hold amplifier 16 or its inverse is added to the reference signal Vr.
• the first switch 14 is still connected to the output of the adder 19 and the 3-rd MSB, b 3 , is generated. The operation continues until the least significant bit (LSB) have been generated, at which time the loop is opened.
• LSB least significant bit
• V r denotes a predetermined reference signal.
• ⁇ V r
• equations (2.1) and (2.2) give a precise definition of a preferred embodiment of the present invention.
• the resulting digital output value should have 4 bits in this particular example, the 4-th MSB is the LSB, and when the LSB has been generated the A/D-conversion is completed. Accordingly, with a reference voltage of 1.0 V corresponding to the Gray code value of 1000, an input voltage of +0.49 V was converted into the Gray code output value 1110.
• the Gray code value 1110 corresponds to the binary code value 1011, which is the same binary code value as that generated in the example of a conventional binary code cyclic A/D-conversion of a +0.49 V input voltage above. Consequently, the resulting digital output value of the Gray code converter according to the invention and the resulting digital output value of the conventional binary code converter are consistent with each other, although they are generated in different types of code.
• V 0 (i) 2 (-D V 0 (i - 1) + V r + ⁇ v e (i - 1) (2 .3 !
• equation (3.3) shows that the total accumulated error in an n-bit Gray code cyclic A/D- conversion according to the invention is smaller than or equal to the total accumulated error in an n-bit binary code cyclic A/D- conversion.
• the Gray code accumulated error will almost always be smaller than the binary code accumulated error. It is useful to give a brief and intuitive explanation of this fact.
• the error ⁇ v ⁇ (j) will propagate through the loop of the A/D-converter.
• the cyclic signal is selectively subjected to an inversion, depending on the most recently generated Gray code output bit. Since the generated Gray code output bits vary between the discrete states 0 and 1 more or less randomly, depending on the particular application, the error associated with a generated output bit will sometimes be added to and sometimes subtracted from the total error accumulated up until that point. Consequently, the offset errors generated during an A/D-conversion will not necessarily accumulate in an increasing manner, and the total accumulated error will lie substantially closer to zero in a Gray code conversion based on the algorithm according to the invention than in a conventional binary code conversion.
• the cyclic A/D-converter based on the Gray coding algorithm according to the invention has a significant advantage over its binary code counterpart .
• the error accumulation for an exemplary resulting 4 -bit binary code value, 0110, generated conventionally, and the error accumulation for the corresponding resulting 4-bit Gray code value 0101, generated in accordance with the invention will be compared in the following. Since a 4- bit value is considered in this particular example, n is equal to 4. The offset error in generating each bit is assumed to be +0.02 V.
• Gray code error accumulation is generally considerably lower than the binary code error accumulation, because the sign associated with the errors are positive as well as negative. This is a property directly related to the term (-if 1 - 1 of the inventive
• Gray coding algorithm defined above in equations (2.1) and (2.2) .
• the accumulated error in a cyclic A/D- conversion according to the invention is reduced in the majority of cases .
• Fig. 3 is a schematic flow diagram of a method for cyclically converting an analog input signal into a digital output signal according to a preferred embodiment of the invention. It is assumed that the resulting digital output signal has a predetermined number, n, of output bits b 1( where i is an integer ranging from 1 to n.
• the updated analog signal is circulated, and the procedure continues with step 32.
• the circulated or cyclic updated analog signal V c (2) is compared to a zero level to generate the second Gray code output bit b 2 .
• the procedure continues in accordance with the flow diagram shown in Fig. 3 until all n output bits have been generated.
• a new A/D-conversion is initiated by once again inputting an analog input signal in step 31.
• the specific order of the amplification by two, and the selective signal inversion in step 35 generally is not critical for the cyclic A/D-conversion according to the invention. It is possible to selectively, in dependence on the generated output bit b 1( invert the sampled and held signal before amplifying it by two. This also holds true for the Gray code cyclic A/D-converter shown in Fig. 2.
• the digital output signal of the Gray code cyclic A/D- converter according to the invention is in the form of Gray code.
• the inventive cyclic A/D-converter generating Gray coded signals further incorporates, as a final stage, means for digitally transforming or converting the Gray coded output signal into an output signal of regular binary code.
• FIG. 4 is a schematic diagram illustrating an illustrative transformation of 4 bits of Gray code into 4 bits of regular binary code by using simple digital gates XOR-1, XOR-2, XOR-3.
• the Gray code bits, here denoted G(i) are transformed into bits, here denoted B(i), of regular binary code according to the following known relations:
• n is the number of bits of the code values .
• n is equal to 4.
• the Gray code MSB, G(l) transforms into the binary code MSB, B(l) without any change.
• the remaining Gray code bits are transformed into binary code bits by using the corresponding digital XOR-gates .
• This digital transformation does not introduce any offset errors. Accordingly, by using the inventive Gray code cyclic A/D-conversion in combination with the above digital Gray code-to-binary code transformation, it is possible to perform a cyclic A/D-conversion, of which the final output signal is in the form of regular binary code, and still maintain low accumulation of offset errors .
• Fig. 5 is a circuit diagram of an exemplary fully differential switched-capacitor realization of a cyclic A/D-converter in accordance with a currently most preferred embodiment of the invention.
• a differential input signal having a positive part
• the cyclic A/D-converter 40 basically comprises a first operational amplifier (OPAMP) 41, a switch arrangement 42, a second operational amplifier (OPAMP) 43, a comparator 44, a clock signal generator 45, capacitors C, Cl, C2 and C3 , and switches S to S 13 .
• OPAMP first operational amplifier
• OPAMP second operational amplifier
• comparator 44 a comparator
• clock signal generator 45 capacitors C, Cl, C2 and C3 , and switches S to S 13 .
• Each one of the OPAMPs 41, 43 has two input terminals and two output terminals, and operates with an internal common mode feedback function.
• the first OPAMP 41 has an associated front capacitor C connected to each of its input terminals .
• the second OPAMP 43 has two associated front capacitors C3 , and two associated parallel capacitors C2.
• the capacitors C3 has a capacitance of 2C, and the capacitors C2 has a capacitance equal to C.
• the first OPAMP 41 and the second OPAMP 43 has switches S 8 and S 3 , respectively, connected in parallel over the corresponding OPAMP. When closed, switches S g and S 3 short-circuit or reset the first OPAMP 41 and the second OPAMP 43, respectively. Switches S 9 are connected in parallel over the first OPAMP 41 and its associated front capacitors C.
• On each side of the second OPAMP 43 there is an input capacitor Cl which is connected to the second OPAMP 43 to contribute, when being discharged, to the voltage over the capacitor C2 thereof.
• Each one of the input capacitors Cl is connected to three switches S 1# S 2 and S ⁇ .
• the capacitors Cl and the switches S 1( S 2 and S 1X constitute switch-capacitor units.
• Switch Si selectively connects a respective part of the differential input signal to the input capacitor Cl .
• Switch S l ⁇ selectively connects a respective part of the differential reference signal, preferably supplied from a conventional signal source, to the input capacitor Cl .
• Switch S 2 selectively connects the input capacitor Cl to ground.
• the capacitors C, C2 and C3 are selectively connected to ground by switches S 7 , S 4 and S 10 , respectively.
• the switch arrangement 42 has two input terminals and two output terminals and comprises four switches S 12 , S 13 .
• the comparator 44 has two input terminals and an output terminal. Preferably, the comparator 44 is a latched comparator, the output signal of which is held for an appropriate part of the conversion cycle.
• the output terminals of the first OPAMP 41 are connected to the input terminals of the switch arrangement 42.
• the output terminals of the switch arrangement 42 are connected to the associated capacitors C3 of the second OPAMP 43.
• the output terminals of the second OPAMP 43 are connected to the input terminals of the comparator 44.
• the output terminals of the second OPAMP 43 are also connected to the front capacitors C of the first OPAMP 41, via switches S e .
• the clock signal generator 45 generates a first set of clock signals, ⁇ ⁇ n , ⁇ 1( ⁇ 2 , ⁇ 3 and ⁇ 4 , of predetermined timing and predetermined signal values, and a second set of clock signals ⁇ S12 and ⁇ S13 , with signal values that depend on the generated output bits b...
• the output terminal of the comparator 44 is connected to the clock signal generator 45 for providing the generated output bit thereto.
• the clock signals ⁇ S12 and ⁇ S13 are generated according to the following relations:
• Fig. 6 is an example of a timing diagram illustrating the predetermined timing of the clock signals ⁇ ⁇ n , ⁇ lf ⁇ 2 , ⁇ 3 and ⁇ 4 utilized in the fully differential realization of Fig. 5.
• the operation of the cyclic A/D-converter 40 is controlled by these clock signals, and the clock signals ⁇ S12 and ⁇ 313 defined above.
• ⁇ 2 triggers the latched comparator 44.
• a switch is turned on when the corresponding clock signal goes high, and turned off when the corresponding clock signal goes low.
• the clock signals are also described in Table II.
• the input signal is forwarded to and sampled by the capacitors C of the first OPAMP 41.
• the output of the first OPAMP 41 is passed to the switch arrangement 42 and selectively inverted thereby in dependence on the generated output bit b ( ⁇ S12 and ⁇ ⁇ 13 depends on b ⁇ as explained above) .
• the selectively inverted output of the switch arrangement 42 is transferred to and sampled by the associated front capacitors C3 of the second OPAMP 43.
• the differential reference signal is sampled by the input capacitors Cl.
• the second OPAMP 43 is in the amplify phase and the selectively inverted signal is amplified by two.
• the reference signal previously sampled by the input capacitors Cl is transferred to the associated capacitors C2 of the second OPAMP 43 such that the voltage of the reference signal will contribute to the output of the second OPAMP 43.
• the output of the second OPAMP 43 is quantized in the comparator 44, thus generating the second output bit b 2 (2-nd MSB) .
• the output of the second OPAMP 43 is sampled by the front capacitors C of the first OPAMP 41.
• the operation of the cyclic A/D-converter 40 continues, in the next clock phase, with the selective inversion in dependence on the generated output bit b 2 , the sampling of the selectively inverted signal, and the sampling of the reference signal.
• the cyclic A/D- conversion will alternate between the operations of clock phases in which ⁇ 2 and ⁇ 3 are high, and the operations of the clock phases in which ⁇ ⁇ and ⁇ 4 are high, until all output bits b have been generated.
• the first OPAMP 41 with its associated front capacitors C acts as a unity gain memory buffer of sample-and-hold type.
• the output of the second OPAMP 43 is quantized in the comparator 44, thus generating a digital output bit.
• the output of the second OPAMP 43 is sampled by the associated front capacitors C of the first OPAMP 41, i.e. the unity gain memory buffer. Because of the hold operation of the unity gain buffer, and the non-overlapping timing of the clock signals that control the comparator 44 and the switch arrangement 42, respectively, the bit decision of the comparator 44 and the selective inversion of the switch arrangement 42 are separated in time. This separation in time enables the feed-forward of the generated digital output to the switch arrangement 42 which, in the subsequent clock phase when ⁇ - and ⁇ 4 are high, selectively inverts the signal held by the first memory buffer in dependence on the forwarded output bit.
• the signal inversion executed in the switch arrangement 42 utilizes the digital information from the previous bit decision in the comparator 44, and decides whether or not the input to the switch arrangement 42 should be inverted based on this information.
• the signal inversion is preferably implemented as a digitally controlled polarity shift. In the fully differential realization of Fig. 5 the inversion is performed by interchanging the polarity of the differential signal by using the digitally controlled switch arrangement 42. In this way, the signal inversion is realized with very high accuracy. The high precision of the signal inversion further improves the accuracy of the cyclic A/D-converter according to the invention.
• Table II summarizes the states (on/off) of the switches S x to S 13 at consecutive clock phases, expressed in terms of high phases of the clock signals ⁇ x and ⁇ 2 .
• a switch that is turned on is represented by a "1”
• a switch that is turned off is represented by a "0”.
• the switches S 12 and S 13 depend on the previously generated digital output.
• ⁇ 2 is high
• switch S x is turned off .
• Figs. 7A-D are circuit diagrams of the fully differential realization of the cyclic A/D-converter 40 at consecutive clock phases .
• the circuit diagrams have been reduced to illustrate only those parts of the cyclic A/D-converter 40 that are pertinent at the considered clock phase. Open switches and unconnected elements will generally not be illustrated.
• Fig. 7A illustrates the cyclic A/D-converter 40 at the first clock phase ⁇ ⁇ for the MSB.
• the switches S ⁇ ; S 3 , S 4 , S 7 , S 8 and S 10 are turned on.
• the differential input signal ( V ⁇ n , V . ) is sampled by the input capacitors Cl .
• the capacitors C, C2 and C3 are all connected to ground, and the first OPAMP 41 and the second OPAMP 43 are reset to enable suppression of the DC-offset in the OPAMPs .
• the switch arrangement 42 is open. The circuit is initialized.
• Fig. 7B illustrates the cyclic A/D-converter 40 during the second clock phase ⁇ 2 for the MSB.
• the switches S 2 , S 5 , S 6 , S 8 and S 10 are turned on.
• the input capacitors Cl are connected to ground to force the charge thereover onto the associated parallel capacitors C2 of the second OPAMP 43.
• the voltage over the parallel capacitors C2 constitute the output of the second OPAMP 43 :
• ⁇ V ⁇ (0) represents an error voltage in sampling and holding the input signal.
• ⁇ v e (0) is referred to the negative side.
• ⁇ V ⁇ (0) indicates the quality of the input to the cyclic comversion rather than the quality of the cyclic conversion itself.
• the output of the second OPAMP 43 is passed to the comparator 44, and the first output bit b x of the comparator 44 is generated according to the following relations:
• the input to the comparator 44 is differential and the output is digital. Furthermore, the output of the second OPAMP 43 is sampled by the associated front capacitors C of the first OPAMP 41, acting as a unity gain buffer.
• the front capacitors C of the first OPAMP 41 act as a memory element in that it holds the output of the second OPAMP 43 until the next clock phase.
• the first OPAMP 41 itself is short-circuited.
• the switches S 3 , S 4/ ⁇ 9 and S 1X are turned on.
• the switches S 12 and the switches S 13 depend on the previously generated output bit b x . If b is equal to 0, the switches S 12 are turned on and the switches S 13 are turned off. If b t is equal to 1, the switches S 12 are turned off and the switches S 13 are turned on.
• the signal sampled by the associated front capacitors C of the first OPAMP 41, corresponding to the output signal of the second OPAMP 43 in the previous clock phase, is passed to the switch arrangement 42.
• the output of the switch arrangement 42 is transferred to the associated front capacitors C3 of the second OPAMP 43.
• the differential reference signal is sampled by the input capacitors Cl .
• the second OPAMP 43 itself is short- circuited, and the capacitors C2 are connected to ground.
• the switches S 2 , S 5 , S G , S 8 and S 10 are turned on.
• the second OPAMP 43 is in the amplify phase and the selectively inverted signal sampled by the associated front capacitors C3 of the second OPAMP 43 is amplified by two.
• the input capacitors Cl are connected to ground to force the charge thereover onto the associated parallel capacitors C2 of the second OPAMP 43. This means that the voltage of the reference signal will contribute to the output of the second OPAMP 43.
• the output of the second OPAMP 43 will be:
• ⁇ V ⁇ (l) represents the error voltage in generating the second output bit b 2 . It represents all errors introduced to the signal when performing a complete bit-conversion cycle, starting at V (l) and ending at V (2) .
• This error voltage is representative of a number of different types of errors .
• Switches provided at high impedance nodes normally inject a small charge, a so called clock induced charge, which gives rise to a DC-offset error voltage. In a differential realization, these offset errors will ideally exclude each other. However, asymmetric switch pairs in regard to clock induced charge injection will generate a DC- offset. In general, there is a DC-offset inherent in each OPAMP.
• the output of the second OPAMP 43 is sampled by the associated front capacitors of the first OPAMP 41.
• the operation of the cyclic A/D-converter continues, alternating between the circuit configuration of Fig. 7C and the circuit configuration of Fig. 7D, until all output bits have been generated .
• ⁇ V ⁇ (j) represents the error voltage in generating the (j+l)-th output bit.
• the i-th MSB is generated according to
• n clock periods are required.
• the last output bit, the LSB is generated according to 1, if V (n) - V 0 n (n) > 0 b, (5.10) 0, if V (n) - V n n (n) ⁇ 0
• V°(n) represents the total accumulated error generated in an n-bit cyclic A/D-conversion according to the invention:
• the expression (5.12) is in correspondence with expression (2.5) given above .
• Fig. 8 there is illustrated a transfer curve of a 5-bit cyclic A/D-converter based on binary coding.
• Fig. 9 illustrates a transfer curve of a 5-bit cyclic A/D-converter based on the Gray coding algorithm according to the invention.
• the magnitude of introduced offset errors is assumed to be 1.5 LSB.
• the simulated offset errors gives the transfer curve for the binary code A/D-converter apparent nonlinear characteristics.
• the transfer curve departs from the ideal stepped transfer curve, and missing codes, such as code 16, are introduced in the binary code cyclic A/D-converter.
• the proposed Gray code architecture of cyclic A/D- converters also turns out to improve the operation performance in comparison to conventional binary code cyclic A/D-converters in several other ways.
• the integral non-linearity and the differential non-linearity of the inventive Gray code A/D- converter are much smaller than their binary code counterparts .
• the signal-to-noise-and-distortion ratio (SNDR) and the spurious- free dynamic range (SFDR) are improved significantly by the proposed Gray code conversion.
• the inverse of the principles utilized for cyclic A/D-conversion is used for cyclic D/A-conversion. Accordingly, the second aspect of the invention relates to the conversion of digital input signals into analog output signals.
• a cyclic D/A-converter the bits are applied to the same circuit which cyclically generates the analog output signal .
• a Gray coded digital signal is converted into an analog output signals according to a recursive algorithm defined by the following equation:
• the output quantity of the D/A-converter is V gout which is equal to V g (l) .
• V r denotes a predetermined reference quantity. The D/A-conversion starts from the LSB.
• the intermediate quantities, the reference quantity and the output quantity can be charges, voltages or currents depending on the particular circuit realization.
• the total accumulated error in a D/A-conversion according to the invention is considerably lower than that in conventional D/A- conversion ⁇ .
• a corresponding improvement as that between cyclic A/D-conversion according to the invention and conventional binary code cyclic A/D-conversion is obtained.
• Fig. 10 is a circuit diagram of a fully differential realization of a cyclic D/A-converter in accordance with the invention.
• the circuit implementation of Fig. 10 realizes the recursive algorithm given by equation (6.1) .
• the fully differential A/D-converter realization of Fig. 5 the realization of Fig. 10 is of switched-capacitor type with digitally controlled switches. Since a D/A-conversion is the inverse of an A/D-conversion, reference is made to the description in connection with the A/D- converter of Fig. 5, 6 and 7A-D for a more detailed understanding of the D/A-converter of Fig. 10.

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• 1996
  • 1996-12-16 SE SE9604617A patent/SE9604617L/ not_active Application Discontinuation
• 1997
  • 1997-12-05 AU AU54227/98A patent/AU5422798A/en not_active Abandoned
  • 1997-12-05 CA CA002275645A patent/CA2275645A1/en not_active Abandoned
  • 1997-12-05 WO PCT/SE1997/002038 patent/WO1998027654A2/en active Application Filing
  • 1997-12-05 DE DE19782152T patent/DE19782152T1/de not_active Withdrawn
  • 1997-12-15 US US08/990,335 patent/US5995035A/en not_active Expired - Fee Related
  • 1997-12-15 TW TW086118908A patent/TW388146B/zh not_active IP Right Cessation

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