WO1994023388A1

WO1994023388A1 - Method for solving asynchronisms in digital logic simulators

Info

Publication number: WO1994023388A1
Application number: PCT/EP1994/000985
Authority: WO
Inventors: Jose Luis Merino Gonzalez; Fernando Ortiz Saenz; Maria Del Mar Gutierrez Serratosa; Rafael Sanz Gomez
Original assignee: Alcatel N.V.
Priority date: 1993-03-31
Filing date: 1994-03-29
Publication date: 1994-10-13
Also published as: AU6537294A

Abstract

The method resolves situations of uncertainty produced by asynchronisms in digital logic simulators arising when a first flip-flop in an input stage receives an incoming signal that can switch inthe time of uncertainty defined by the set-up and hold times associated with an active clock edge. The method consists of a stage of evaluation (1) of the output state of the first flip-flop generated by the digital logic simulator itself; a stage of asynchronism indication (2), which indicates if there is asynchronism or not; a stage or reassignment (3) which, when there has been no asynchronism, assignes the flip-flop with the same state as it had in the previous clock cycle; a stage of assignment (4) of a valid output state when asynchronism has been recognised; and a stage of detection (5) indicating end of simulation in order to return to the first stage of evaluation (1) or to proceed to a finalisation stage (6) of the process.

Description

METHOD FOR SOLVING ASYNCHRONISMS IN DIGITAL LOGIC

SIMULATORS

OBTECT OF THE INVENTION

This invention, as stated in the title of this document, refers to a method that solves the situations of uncertainty in the output state of flip- flops, due to asynchronisms, arising in digital system simulation.

It is of special application in simulators of asynchronous systems for the design of digital integrated circuits. BACKGROUND TO THE INVENTION At present, digital circuits are designed according to the needs of the customer. For this reason, the integrated circuit manufacturers provide a series of design tools which, in addition, simulate the behaviour of the integrated circuit to be made in as faithful a manner possible, considering therefore the actual side effects of the design and manufacture of digital circuits.

One such effect for consideration is that deriving from the requirements of input data transition set-up times in the flip-flops of the system being designed.

This effect arises when a transition appears in the input of a flip-flop inside the uncertainty zone of the active clock edge. This phenomenon is termed metastability.

This region of uncertainty is defined by the duration of the set- up time (prior to the active clock edge) and the hold time (after the active clock edge). In these situations it is not possible to determine the state of the flip- flop, consequently the simulation of it cannot establish an output value for this flip-flop.

Normally, as happens with the LSI-Logic simulator, when this situation arises, the simulator sets an output termed "X", this meaning an undetermined value, which, in addition, can be propagated, as in fact occurs, to other gates and flip-flops that receive at their inputs the signal coming from the output of this flip-flop.

These problems may occur particularly in asynchronous systems and as yet no kind of solution is available for them though, to prevent them to arise, simulator designers indicate that the uncertainty zones already mentioned must be respected by avoiding flip-flop input signal transitions in them, and, should such asynchronisms arise, the simulation must be repeated changing the instants of input data transition to avoid these situations. TECHNICAL PROBLEM TO OVERCOME

Consequently the technical problem to be overcome consists in solving the states of asynchromism in digital logic simulators, avoiding the need to repeat lengthy simulations if these should arise. CHARACTERISATION OF THE INVENTION The method proposed for overcoming asynchronisms in digital logic simulators of the data received in asynchronous form by an input stage is characterised in that it comprises a first stage of evaluation of the output state of the first flip-flop generated by the digital logic simulator, as well as a second stage of asynchromism indication in which indication is given of whether there have been violations or not of the uncertainty times, comprising the set-up and hold times, in the incoming data transitions.

If no asynchronism is indicated, a third stage comprises the reassignment of the same state to the flip-flop under examination.

If asynchronism is indicated, a fourth stage of assignment is made of a valid state to the flip-flop under examination in such a way that the state of ambiguity indicated by the digital logic simulator is solved.

In addition, a fifth stage takes place which comprises the detection of the indication of the end of simulation whereby, in the event that this end-of- simulation indication is not found, the system returns to the first, initial stage of evaluation; if it is detected, the system proceeds to a sixth finalisation stage of the process.

As a consequence of incorporating the method of the invention, the digital logic simulator eliminates the possibility of undefined states appearing, which would oblige the repetition of the simulation after changing the signals that produced these situations of uncertainty. BRIEF FOOTNOTES TO THE FIGURES

A more detailed explanation of the invention is made on a basis of the following figures, in which:

- figure 1 shows the timing diagram of a flip-flop that produces asynchronisms, and a type D flip-flop on which the previous timing signals are defined,

- figure 2.1 shows the most commonly employed input stage for asynchronous digital systems, on the simulation of which the method according to the invention is applied, - figures 2.2 and 2.3 show the timing diagrams of simulated signals present at various points in the circuit of figure 2.1 according to the invention, and

- figure 3 is a flowchart of the method according to the invention, for solving the problem explained above. DESCRIPTION OF THE INVENTION

In asynchronous digital systems, the incoming digital signals do not behave according to the transitions of a system clock that would force the transitions of all present signals to occur in accordance with the active edges of this clock. Instead, the incoming signals to this system can switch at any moment, whereby it is not possible to ensure that, when an incoming signal to a flip-flop switches in coincidence with the active clock edge, this flip-flop has correctly recognised the new incoming signal, and even a state of metastability may arise, in which the output signal of a flip-flop in a situation like that described above, switches repeatedly between one state and the other for a considerable length of time before stabilising itself in one of the two possible states.

To avoid this occurrence it is normal practice to connect another flip- flop 22 in cascade with the first flip-flop 21 as is illustrated in figure 2.1, in such a way that, regardless of the result, the second flip-flop 22 makes the correct reading, but delayed by one clock cycle.

However, though the problem is usually resolved in practice in the input circuit 20, the same does not happen with digital logic simulators for the design of these digital circuits.

Figure 1 shows the problem with simulation, in which the incoming data item DAT_I switches with the active edge of the clock CK_I within the unpermitted uncertainty interval Ti comprising the time needed for setting up te and the hold time tr.

In this case the output data item from the flip-flop obtained by the simulator would be that indicated by DAT_0. The flow chart of figure 3 shows the method according to the invention for solving the problem mentioned above; in it, a first stage of evaluation 1 of the simulated state of the first flip-flop 21 is carried out in each instant of simulation.

Subsequently there is a stage of asynchronism indication 2 in the simulation instant after the evaluation 1 of the preceding stage. The result of this is positive if a transition of the incoming data occurs during the uncertainty period of the active clock edge.

In the case of there being no asynchronism, the method performs a reassignment 3 of the first flip-flop 21 to the state it had before; if, however, asynchronism is indicated, an assignment 4 is made to a valid state of the flip-flop 21, solving the indetermined state indicated with an "X" by the digital logic simulator as shown in the figure 2.2, assigning a valid state SI, which is the opposite of the state established in the last asynchronism resolution made SO (not shown). Thus, at the next clock edge, the right input value is read which, in the case of figure 2.2, is a "1". In this way, at the output of the second flip-flop 22 of the input stage 20 that is being simulated, indicated as DAT_0, all uncertainty disappears; and the output data transition can be performed with a difference of one clock period, depending on whether SI corresponds to a logical "1" or a logical "0". Once all the foregoing has been done there is a stage of detection 5 of end-of-simulation indication, in order to return to the first stage in the next instant of simulation in the event of not detection of the end-of-simulation indication; if this indication is detected, finalisation 6 of the process takes place. Figure 2.3 shows a variant on the previous solution in which the stage of evaluation 1 takes place only on the not active edges of the clock CK_I and, in addition, the output state DAT NT of the first flip-flop 21 in the event of asynchronism is resolved by always assigning a value of "1" or "0" (previously defined); thus, at the output of the second flip-flop 22, and therefore of the input stage 20, the uncertainty disappears by assigning a fixed value each time this occurs. In this case the transition of the output data is brought forward by one clock period when the previously defined fixed value is the same as the new input data value DAT_I with respect to when the previously defined fixed value is the opposite of the new value of the input data item DAT_I. It is also possible to solve the asynchronism by always assigning a previously determined fixed value, "1" or "0", in the case where the stage of evaluation 1 of the simulated state of the first flip-flop 21 takes place in each instant of simulation.

In the same way, it is possible to resolve the asynchronism by assigning a valid state SI, the opposite of that established in the previous resolution SO in the case where the stage of evaluation 1 of the simulated state of the first flip-flop 21 only works on the not active edges of the clock.

Claims

1.- METHOD FOR SOLVING ASYNCHRONISMS IN DIGITAL LOGIC SIMULATORS for the simulation of the data received by an input stage (20) characterised in that it comprises the following stages: - evaluation (1) of the output state of the first flip-flop (21),

- indication (2) of asynchronism in this first flip-flop (21) in the event that a transition occurs in the incoming data during the uncertainty period of the active clock edge,

- reassignment (3) of the state of the first flip-flop with the value detected at its output, in the case of no indication of asynchronism,

- assignment (4) of a valid state of the first flip-flop (21), in the case of indication of asynchronism,

- detection (5) of end-of-simulation indication, returning to the first stage of evaluation (1) in the case that this indication of end- of-simulation is not detected,

- finalisation (6) of the process in the case of detection of the end-of- simulation indication.

2.- METHOD according to claim 1, characterised in that the stage of evaluation (1) of the output state of the first flip-flop (21) takes place once for each simulation period of the digital logic simulator.

3.- METHOD according to claim 1, characterised in that the stage of evaluation (1) of the output state of the first flip-flop (21) takes place only during the not active clock edges (CK_I) of the digital logic simulator.

4.- METHOD according to claim 2 or 3, characterised in that in the case of asynchronism being indicated, the stage of assignment (4) of a valid state of the first flip-flop establishes as the valid state, the opposite of that established in the last asynchronism resolution carried out.

5.- METHOD according to claim 2 or 3, characterised in that in the case of asynchronism being indicated, the stage of assignment (4) of a valid state of the first flip-flop establishes as the valid state a fixed value, "1" or "0", which has been previously defined.