WO1993007565A1

WO1993007565A1 - Memory write protection method and apparatus

Info

Publication number: WO1993007565A1
Application number: PCT/US1992/006455
Authority: WO
Inventors: Francesco Rago; Terrie Frane; Lawrence D. Cepuran; Dale Bengston
Original assignee: Motorola, Inc.
Priority date: 1991-10-01
Filing date: 1992-08-03
Publication date: 1993-04-15
Also published as: IT1258856B; CA2097308A1; MX9205634A; ITRM920707A1; ITRM920707A0; FR2681965A1

Abstract

A write protection apparatus is disclosed. The write protection apparatus couples a data supplying device (121) to the data input of a memory device (127). The memory protection device generates a first signal (211) which triggers generation of a second signal (215). The second signal (215) is active for a first predetermined time and is coupled to the input of the memory device (127). At any time during this first predetermined time, a third signal (209) may be generated. The third signal (209) inactivates the second signal. This third signal (209) may be triggered by numerous events including: generation of a read signal, generation of a chip select signal, or indication that the end of the data to be written to the memory device (127) has occurred.

Description

MEMORY WRITE PROTECTION METHOD AND APPARATUS

Field of the Invention

This invention generally relates to the infrastructure of systems, and more specifically, to accessing a memory device contained within the microprocessing system.

Background of the Invention

Typically, a microprocessing system contains a memory, a data bus, a microprocessor and peripheral devices. The memory contains a data bus input, an address bus input, a chip select input and a write enable input. Generally, there are three systems for writing data to an external memory in a microprocessor environment.

In the first system, a controlling device is used to create the address on the address bus. The chip select and the write enable lines are directly coupled between the controlling device and the memory device. During a power-up or a data transfer, the write enable signal may be activated for too long or falsely triggered. This may allow extraneous data to be written into the memory device; corrupting the data contained in the memory, which may seriously effect the operation of the microprocessor system. Additionally, the controlling device may execute the wrong code during a write cycle, causing unpredictable results within the memory device.

In the second system, an attempt is made to protect the memory from corrupt data. The controlling device triggers a logic device and the logic device creates the write enable signal for the memory device for a predetermined amount of time. This predetermined amount of time is typically fixed for the amount of time required to write the largest block of data to the memory device,- such that it does not limit the amount of data that is written to the memory location of the memory device. This system leaves a window of opportunity for corrupt data to be written into the data device when blocks of data, smaller than the largest block of data, are written to the memory device or a write enable signal is falsely triggered. Again, the controlling device may execute the wrong code during a write cycle and cause unpredictable results within the memory device.

The third system has a protection device built into the memory. The memory requires the controller to write a byte of data to three specific addresses prior to writing the desired data to the memory device. This implementation is discussed in the data sheets X28C64, from the XICOR Data Book, Second Edition, 1990. After the three byte sequence is written to the proper addresses, the page write window is open, allowing the controller to write from 1 to 64 bytes of data to the memory device. This protection device protects the memory from false triggering, but allows corruption of the memory device during the invariable page write window. Again, the controlling device may execute the wrong code during a write cycle and cause unpredictable results within the memory device.

Therefore, a need exists for an adaptive data protection device which varies the duration of the write enable signal depending upon the size of the data block to be written to the memory device or the activity monitored within the controlling device, and eliminates false triggering of the write enable signal.

Summary of the Invention

The present invention encompasses a write protection apparatus for protecting a memory device from receiving corrupted data while writing a block of data from a data supplying device to the memory device. The memory device has a write enable input and a data input. The write protection apparatus couples the data supplying device to the data input of the memory device. The memory. protection device generates a first signal which triggers generation of a second signal. The second signal is active for a first predetermined time and is coupled to the input of the memory device, thereby allowing the data device to write data to the memory device during this first predetermined time. A third signal may be generated disabling said second signal.

Brief Description of the Drawings FIG. 1 is a block diagram of radiotelephone communication system which may employ the present invention. FIG. 2 is a circuit diagram of the present invention.

FIG. 3 is a timing diagram of the present invention.

FIG. 4 is a process flow chart of the method of the present invention.

Detailed Description of the Preferred Embodiment

The present invention encompasses a microprocessor system incorporated into a digital radiotelephone, such as the Japan Digital Cellular Telephone. In the preferred embodiment, an electronically erasable PROM (EEPROM) is used as the memory device in the radiotelephone to store permanent information necessary for operating the radiotelephone, although the invention may be used to protect any type of non-volatile memory device. Various sizes of data blocks are written to the EEPROM from different devices. In the past, when radiotelephones were returned for maintenance problems, the EEPROM contained corrupted data which disabled or impaired the operation of the radiotelephone. By implementing the present invention, the corrupt data written to the EEPROM is minimized.

Essentially, the invention encompasses a method and apparatus of writing data blocks to the EEPROM without corrupting the data stored within the memory device. FIG. 1 is a block diagram of a radiotelephone communications system. Within this system there is a fixed- site transceiver 103 which sends and receives radio frequency (RF) signals to and from mobile and portable radiotelephones located in the geographic area serviced by the fixed site transceiver 103. Radiotelephone 101 is one such radiotelephone served by the fixed site transceiver 103.

Upon reception of radio frequency signals, radiotelephone antennas 105, 107 convert the radio frequency signals into electrical radio frequency signals where then they are transmitted to the receivers 111, 113 respectively. The receivers 111, 113 convert the electrical radio frequency signals into usable data for use by other parts of the radiotelephone 101. Upon transmission of radio frequency signals, the microprocessor 121 inputs the data into the transmitter 109. The transmitter takes the data and converts it into the electrical radio frequency signals and transmits it through antenna 105 which converts its radio frequency signals and transmits those back to the fixed-site transceiver 103. In order for the radiotelephone 101 to operate properly, many parameters need to be stored in a permanent memory 127. This permanent memory is EEPROM 127. The EEPROM 127 is accessed via the microprocessor 121.

During the original programming of the radiotelephone in the factory the EEPROM 127 is programmed with essential operating parameters including: received signal strength information (RSSI), identification information and power level information.

The RSSI information is necessary to calibrate the current received signal strengths. The calibrated received signal strengths are used to select the appropriate fixed site transceiver 103. The current received signal strength recovered from the receivers 111,113 is used to reference the RSSI value stored in the EEPROM 127. If the RSSI values are corrupted, then the wrong fixed site transceiver may be selected, resulting in reduced performance quality of the radiotelephone 101.

The identification information includes a unique serial number and phone number. This information is stored in the EEPROM 127 during the original programming procedure. This information must be protected to insure the communication system's integrity. If the serial number is changed or corrupted, then the phone may be identified as someone else's or phone calls may be made and the charges applied to another's phone bill.

The power level table is loaded into the EEPROM 127 in the factory. The output power levels are measured for a given input, the output power fluctuate from radio to radio depending upon component and hybrid variations. The transmit output power is tuned such that it meets the FCC specification or equivalent Japanese specifications at five predetermined levels. The information necessary to excite the power amplifier to the desired output level is stored in the EEPROM 127 and is retrieved whenever the power amplifier needs to be tuned to a predetermined power output. If this information is corrupted the power amplifier contained in the transmitter 109 will not operate within the specifications and may cause serious performance problems for the radiotelephone 101. After the information is loaded into the EEPROM 127, the radiotelephone 101 is ready to operate. While the radiotelephone 101 is in use, some user feature data and various parameters are stored in the EEPROM 127 to assist in maintenance procedures when the phone is returned to a dealer for service. First, a timer is used to store the amount of elapsed time the radio is in use from the beginning of time. In order for the radiotelephone 101 to maintain this counter the radiotelephone 101 stores the counter in the

EEPROM 127. When power is turned off or lost, the timer does not reset. Second, the radiotelephone 101 contains an error monitor which utilizes a set of error codes to describe problems within the radiotelephone 101 during operation. If such an error occurs while operating the radiotelephone 101, the error code and the time of occurrence is stored in the EEPROM 127 to assist in maintenance of the radiotelephone 101 at a later point in time. Additionally, the EEPROM 127 is used to store phone numbers and preferences such as ringer volume. The preceding operations are controlled by the microprocessor 121 while operating the radiotelephone 101.

FIG. 2 is a block diagram employing the invention. The write cycle of data from the microprocessor 121 begins by sending a known bit pattern to a predetermined address. The predetermined address corresponds to the data verifier 207.

The data verifier 207 receives the known byte of data from the microprocessor 121 and checks it against its known byte of data. Upon verification, the microprocessor 121 then changes the address to the EEPROM 127 and begins to load the desired data onto the data bus 217. Simultaneously, data verifier 207 generates a write_enable_trigger signal 211 which is input into the one-shot 203. The one-shot 203 generates a write.ok signal 213 for a predetermined time. The predetermined time is equal to the time required to write the largest data block from the microprocessor 121 to the EEPROM 127. In the preferred embodiment, the one-shot time is set to 50 uS. The write.ok signal 213 and the read write signal 219 are input into the AND gate 205. This ensures that in case of a false trigger from the one-shot the EEPROM's write_enable_signal 215 is not falsely enabled, protecting the EEPROM 127 from corrupted data. The AND gate 205 and the data verifier 207 in the preferred embodiment are implemented in a programmable logic array (PLA) model number PAL16V8, available from Advanced Micro Devices. Upon successful ANDing of the three signals 211, 213, and 219 the AND gate 205 outputs a write_enable_signal 215 to the write enable input of the EEPROM 127. This allows the data on the data bus 217 to be written into the EEPROM 127 at addresses determined by the microprocessor 121. The one-shot reset signal 209 may be used to shorten the duration of the one-shot write enable signal, thus creating a variable duration write enable signal. There are several reasons this variable write enable signal duration is desirable. First, if the data block which is to be written to the EEPROM 127 is of shorter duration than the largest block of data, then, the one shot reset signal 209 may be triggered by microprocessor 121, subsequently, disabling the write_ok signal 213 to the EEPROM 127 at the end of the shorter data block has been written. The duration of the write enable signal is equal to the length of the data block to be written to the

EEPROM 127, thus, substantially eliminating the possibility of writing corrupt data to the EEPROM 127. Alternatively, the reset signal 209 may be used to discontinue a write cycle to the EEPROM 127 upon determining a problem within the radio. In the preferred embodiment, the reset signal 209 is used to discontinue a write cycle when the radiotelephone detects a read request signal or a chip select signal to a device other than the EEPROM 127. Problems are particular to the system within which the invention is employed and equally sufficient criteria for disabling the write cycle may be employed by one of average skill in the art.

Note that a one-shot 203 is particular to this embodiment. Other embodiments may employ equally sufficient timing devices, including digital timers, shift registers and resistor/capacitor (RC) circuits, in place of the one-shot.

Likewise, any memory device may be substituted in for the EEPROM 127 by one of average skill in the art.

FIG. 3 reveals the timing of all the essential signals included in the block diagram of FIG. 2. The microprocessor 121 sets the data bus 305 to a known bit pattern, and the address bus 307 to the data verifier 207. After the data verifier 207 receives the known bit pattern, the microprocessor 121 sets the address bus 307 to a memory location within the EEPROM 127 and begins transferring desired data onto the data bus 307. Upon verification of the known bit pattern, the data verifier 207 creates the write_enable_trigger signal (211) 313. This signal is input into the one shot 203. The one-shot 203 subsequently creates a write_ok_signal 311(213) which endures for 50 microseconds (uS) and is input into the logic AND device 205. The logic AND device 205 uses inputs of the microprocessor's

RD/WR signal 309 (219), the write_enable_trigger signal (211) 313, and the write.ok.signal 311 to create the EEPROM's write_enable__signal 315. The duration of the write_enable_signal 315 may be shortened by the microprocessor 121 enabling the reset signal 317 (209). The reset signal 317 (209) will reset the one-shot 203, subsequently inactivating the write_enable_signal 315 (215).

FIG. 4 is a process flow chart of the method employed by this embodiment to reduce the opportunity of writing corrupt data to the EEPROM 127. The flow chart starts at 401. At 403, the microprocessor 121 generates a known bit pattern onto the data bus 217 and it sets the address on the bus 217 to the data verifier 207. At 405, the microprocessor 121 sets the address bus 217 to an address located within the EEPROM 127 and begins transferring desired data onto the data bus 217. At 407, the data verifier 207 upon verifying the known received bit pattern, generates a write.enable.trigger signal 207, which is coupled to both the input of a one-shot 203 and to the AND gate 205. At 409, the one-shot 203 generates, responsive to the write_enable_trigger signal 313, the write_ok_signal 311 for the time required to transfer the largest block of desired data to the EEPROM 127. In the preferred embodiment, the time is 50 uS.

At 411, if a data block sent by microprocessor 121 is shorter than the largest data block sent, then the reset signal 317(209) is generated by microprocessor 121 and input into the one-shot reset input, thereby disabling the write_enable_signal 315 to the EEPROM 127. The reset signal 317(209) functions as a variable window for the write_enable_signal 315 which is adjusted to fit the length of data block written to the EEPROM

127. Alternatively, the reset signal 317(209) may be generated in response to problem in the radiotelephone 101, thereby cancelling the remainder of the write cyde to avoid any further damage to the EEPROM 127. In the preferred embodiment, the reset signal 317(209) is triggered in response to an attempted read or an additional chip select executed by the microprocessor 121. These signals indicate that the microprocessor 121 may be executing the wrong code.

In the aforementioned description we have described an apparatus and method of minimizing data corruption of a memory device with a simple variable window write enable circuit. What is claimed is:

Claims

1. A write protection apparatus for protecting a memory device from receiving corrupted data while writing a block of data from a data supplying device to the memory device , the memory device having a write enable input and a data input, the write protection apparatus comprising:

means for coupling the data supplying device to the data input of the memory device ;

means for generating a first signal;

means, responsive to said means for generating a first signal, for generating a second signal for a first predetermined time, said second signal coupled to the write enable input of the memory device , thereby allowing the data supplying device to write data to the data input of the memory device only during said first predetermined time; and

means for generating a reset signal a second predetermined time after said means for generating said first signal, thereby deactivating said second signal, said second predetermined time is less than or equal to said first predetermined time.

2. A write protection apparatus in accordance with claim 1 wherein said first predetermined time is equal to the amount of time necessary to write the largest block of data from the data supplying device to the memory device .

3. A radiotelephone induding inter alia a user interface, a central processing unit (CPU), a data bus, an address bus and a memory, the data bus carrying data between the user interface and the memory, the memory including a write enable input and a data input, the radiotelephone comprising:

means for protecting the memory from accepting incorrect data from the user interface, said means for protecting comprising: the CPU generating a first signal for a first predetermined time, and a timing device, in response to the CPU generating said first signal, generating a second signal for a second predetermined time, said second predetermined time less than or equal to said first predetermined time, said second signal coupled to the write enable input of the memory, whereby writing to the memory can only occur during said second predetermined time, and the CPU generating, in response to a first condition, a third signal a third predetermined time after said generating said second signal, said third signal coupled to a reset input of said timing device, thereby inactivating said second signal, said second predetermined time is less than or equal to said first predetermined time.

4. A radiotelephone in accordance with claim 3 wherein said first condition is an indication of an error by the CPU.

5. A method of writing data into a memory device contained in a system while reducing corruption of the memory device , the memory device having a data input and a write enable input, the method comprising the steps of:

writing a predetermined bit pattern to logic device;

determining said predetermined bit pattern is correct;

coupling a data generating device to the data input of the memory device ;

generating, in response to said determining said predetermined bit pattern is correct, a first signal; and

generating, in response to said generating said first signal, a second signal for a first predetermined time, said second signal coupled to the write enable input of the memory device , whereby the memory device may only accept data during said first predetermined time.

6. A method of writing data into a memory device in accordance with claim 5, further comprises generating a reset signal for a second predetermined time after said generating said write enable signal, said second predetermined time is less than or equal to said first predetermined time, thereby, degenerating said second signal.

7. A method of writing data into a memory device in accordance with claim 5, wherein said first predetermined time is equal to the amount of time necessary to write the largest block of data to the memory device .

8. A method of writing data into a memory device in accordance with claim 7, wherein said second predetermined time is equal to an amount of time necessary to write a block of data to the memory device , wherein said block of data is smaller than said largest block of data.

9. A method of writing data into a memory device in accordance with claim 5, wherein said write protection apparatus further comprises comparing said second signal with said first signal and creating a third signal, said third signal activated in response to said first and said second signal being generated, said third signal coupled to the write enable input of the memory device .

10. A method of writing data into a memory device in accordance with claim 5 wherein the data generating device further comprises a microprocessor.