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USRE48380E1 - Vertical power transistor device - Google Patents

Vertical power transistor device Download PDF

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USRE48380E1
USRE48380E1 US15/970,148 US201815970148A USRE48380E US RE48380 E1 USRE48380 E1 US RE48380E1 US 201815970148 A US201815970148 A US 201815970148A US RE48380 E USRE48380 E US RE48380E
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layer
transistor device
spreading layer
approximately
drift layer
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Vipindas Pala
Anant Kumar Agarwal
Lin Cheng
Daniel Jenner Lichtenwalner
John Williams Palmour
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Wolfspeed Inc
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Cree Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present disclosure relates to power transistor devices, and in particular to power metal-oxide-semiconductor field-effect transistor (MOSFET) devices.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • a power metal-oxide-semiconductor field-effect transistor is a type of transistor that is adapted for use in high power applications.
  • a power MOSFET device has a vertical structure, wherein a source and gate contact are located on a first surface of the MOSFET device that is separated from a drain contact by a drift layer formed on a substrate.
  • Vertical MOSFETS are sometimes referred to as vertical diffused MOSFETs (VDMOSFETs) or double-diffused MOSFETs (DMOSFETs). Due to their vertical structure, the voltage rating of a power MOSFET is a function of the doping and thickness of the drift layer. Accordingly, high voltage power MOSFETs may be achieved with a relatively small footprint.
  • FIG. 1 shows a conventional power MOSFET device 10 .
  • the conventional power MOSFET device 10 includes a substrate 12 , a drift layer 14 formed over the substrate 12 , one or more junction implants 16 in the surface of the drift layer 14 opposite the substrate, and a junction gate field effect transistor (JFET) region 18 between each one of the junction implants 16 .
  • Each one of the junction implants 16 is formed by an ion implantation process, and includes a deep well region 20 , a base region 22 , and a source region 24 .
  • Each deep well region 20 extends from a corner of the drift layer 14 opposite the substrate 12 downwards towards the substrate 12 and inwards towards the center of the drift layer 14 .
  • the deep well region 20 may be formed uniformly or include one or more protruding regions, as shown in FIG. 1 .
  • Each base region 22 is formed vertically from the surface of the drift layer 14 opposite the substrate 12 down towards the substrate 12 along a portion of the inner edge of each one of the deep well regions 20 .
  • Each source region 24 is formed in a shallow portion on the surface of the drift layer 14 opposite the substrate 12 , and extends laterally to overlap a portion of the deep well region 20 and the base region 22 , without extending over either.
  • the JFET region 18 defines a channel width 26 between each one of the junction implants 16 .
  • a gate oxide layer 28 is positioned on the surface of the drift layer 14 opposite the substrate 12 , and extends laterally between a portion of the surface of each source region 24 , such that the gate oxide layer 28 partially overlaps and runs between the surface of each source region 24 in the junction implants 16 .
  • a gate contact 30 is positioned on top of the gate oxide layer 28 .
  • Two source contacts 32 are each positioned on the surface of the drift layer 14 opposite the substrate 12 such that each one of the source contacts 32 partially overlaps both the source region 24 and the deep well region 20 of one of the junction implants 16 , respectively, and does not contact the gate oxide layer 28 or the gate contact 30 .
  • a drain contact 34 is located on the surface of the substrate 12 opposite the drift layer 14 .
  • FIG. 2 shows operation of the conventional power MOSFET 10 when the device is in an ON state.
  • a positive bias is applied to the gate contact 30 of the conventional power MOSFET 10 , an inversion layer channel 36 is formed at the surface of the drift layer 14 underneath the gate contact 30 , thereby placing the conventional power MOSFET 10 in an ON state.
  • current shown by the shaded region in FIG. 2
  • current is allowed to flow from each one of the source contacts 32 through the inversion layer channel 36 and into the JFET region 18 of the drift layer 14 . Once in the JFET region 18 , current flows downward through the drift layer 14 towards the drain contact 34 .
  • the JFET channel width 40 and the spreading distance 42 determine the internal resistance of the power MOSFET 10 , thereby dictating the performance of the device.
  • a conventional power MOSFET 10 generally requires a channel width 26 of 3 microns or wider in order to sustain an adequate JFET channel width and 40 spreading distance 42 for proper operation of the device.
  • the electric field formed by the junctions between the deep well region 20 , the base region 22 , and the drift layer 14 radiates through the gate oxide layer 28 , thereby physically degrading the gate oxide layer 28 over time. Eventually, the electric field will cause the gate oxide layer 28 to break down, and the conventional power MOSFET 10 will cease to function.
  • a power MOSFET is needed that is capable of handling high voltages in the OFF state while maintaining a low ON state resistance and having an improved longevity.
  • the present disclosure relates to a transistor device including a substrate, a drift layer over the substrate, and a spreading layer over the drift layer.
  • the spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. Each one of the junction implants may include a deep well region, a base region, and a source region.
  • the transistor device further includes a gate oxide layer, a gate contact, a pair of source contacts, and a drain contact.
  • the gate oxide layer is on a portion of the spreading layer such that the gate oxide layer partially overlaps and runs between each source region of each junction implant.
  • the gate contact is on top of the gate oxide layer.
  • Each one of the source contacts are on a portion of the spreading layer such that each source contact partially overlaps both the source region and the deep well region of each junction implant, respectively.
  • the drain contact is on the surface of the substrate opposite the drift layer.
  • the spreading layer has a graded doping profile, such that the doping concentration of the spreading layer decreases in proportion to the distance of the point in the spreading layer from the JFET region.
  • the spreading layer includes multiple layers, each having a different doping concentration that progressively decreases in proportion to the distance of the layer from the JFET region.
  • the space between each junction implant, or length of the JFET region can be reduced while simultaneously maintaining or reducing the ON resistance of the device.
  • reducing the space between each junction implant a larger portion of the electric field generated during reverse bias of the transistor device is terminated by each one of the junction implants, thereby reducing the electric field seen by the gate oxide layer and increasing the longevity of the device.
  • FIG. 1 shows a schematic representation of a conventional power MOSFET device.
  • FIG. 2 shows details of the operation of the conventional power MOSFET device shown in FIG. 1 .
  • FIG. 3 shows a power MOSFET device according to one embodiment of the present disclosure.
  • FIG. 4 shows details of the operation of the power MOSFET device shown in FIG. 3 according to one embodiment of the present disclosure.
  • FIG. 5 shows an alternative embodiment of the power MOSFET device shown in FIG. 3 .
  • FIGS. 6-15 illustrate a process for manufacturing the power MOSFET device shown in FIG. 3 .
  • FIG. 16 shows a graph indicating performance improvements achieved by the power MOSFET device shown in FIG. 3 .
  • FIG. 17 shows a graph indicating longevity improvements achieved by the power MOSFET device shown in FIG. 3 .
  • the power MOSFET device 44 includes a substrate 46 , a drift layer 48 formed over the substrate 46 , a spreading layer 50 formed over the drift layer 48 , one or more junction implants 52 in the surface of the spreading layer 50 opposite the drift layer 48 , and a junction gate field effect transistor (JFET) region 54 between each one of the junction implants 52 .
  • Each one of the junction implants 52 may be formed by an ion implantation process, and may include a deep well region 56 , a base region 58 , and a source region 60 .
  • Each deep well region 56 extends from a corner of the spreading layer 50 opposite the drift layer 48 downwards towards the drift layer 48 and inwards towards the center of the spreading layer 50 .
  • the deep well region 56 may be formed uniformly or include one or more protruding regions.
  • Each base region 58 is formed vertically from the surface of the spreading layer 50 opposite the drift layer 48 downwards towards the drift layer 48 along a portion of the inner edge of each one of the deep well regions 56 .
  • Each source region 60 is formed in a shallow portion on the surface of the spreading layer 50 opposite the drift layer 48 , and extends laterally to overlap a portion of the deep well region 56 and the base region 58 , without extending over either.
  • the JFET region 54 defines a channel width 62 between each one of the junction implants 52 .
  • a gate oxide layer 64 is positioned on the surface of the spreading layer 50 opposite the drift layer 48 , and extends laterally between a portion of the surface of each source region 60 , such that the gate oxide layer 64 partially overlaps and runs between the surface of each source region 60 in the junction implants 52 .
  • a gate contact 66 is positioned on top of the gate oxide layer 64 .
  • Two source contacts 68 are each positioned on the surface of the spreading layer 50 opposite the drift layer 48 such that each one of the source contacts 68 partially overlaps both the source region 60 and the deep well region 56 of the junction implants 52 , respectively, and does not contact the gate oxide layer 64 or the gate contact 66 .
  • a drain contact 70 is located on the surface of the substrate 46 opposite the drift layer 48 .
  • FIG. 4 shows the operation of the power MOSFET 44 when the device is in an ON state.
  • a positive bias is applied to the gate contact 66 of the power MOSFET 44 , an inversion layer channel 72 is formed at the surface of the spreading layer 50 underneath the gate contact 66 , thereby placing the power MOSFET 44 in an ON state.
  • current shown by the shaded region in FIG. 4
  • current is allowed to flow from each one of the source contacts 68 through the inversion layer channel 72 and into the JFET region 54 .
  • Once in the JFET region 54 current flows downward through the spreading layer 50 towards the drain contact 70 .
  • An electric field presented by the junctions formed between the deep well region 56 , the base region 58 , and the spreading layer 50 constricts current flow in the JFET region 54 into a JFET channel 74 having a JFET channel width 76 .
  • the spreading layer 50 is doped in such a way to decrease resistance in the spreading layer 50 , thereby mitigating the effects of the electric field by increasing the JFET channel width 76 and decreasing the spreading distance 78 .
  • the spreading layer 50 significantly reduces the ON resistance of the power MOSFET 44 .
  • the ON resistance of the power MOSFET 44 may be about 2.2 m ⁇ /cm 2 when the device is rated to handle 1200V and about 1.8 m ⁇ /cm 2 when the device is rated to handle 600V.
  • the spreading layer 50 allows for a reduction of the channel width 62 between each one of the junction implants 52 . Reducing the channel width 62 of the power MOSFET 44 not only improves the footprint of the device, but also the longevity. As each one of the junction implants 52 is moved closer to one another, a larger portion of the electric field generated by the junctions between the deep well region 56 , the base region 58 , and the spreading layer 50 is terminated by the opposite junction implant 52 . Accordingly, the electric field seen by the gate oxide layer 64 is significantly reduced, thereby resulting in improved longevity of the power MOSFET 44 . According to one embodiment, the channel width 62 of the power MOSFET 44 is less than 3 microns.
  • the power MOSFET 44 may be, for example, a silicon carbide (SiC), gallium arsenide (GaAs), or gallium nitride (GaN) device.
  • SiC silicon carbide
  • GaAs gallium arsenide
  • GaN gallium nitride
  • the substrate 46 of the power MOSFET 44 may be about 180-350 microns thick.
  • the drift layer 48 may be about 3.5-12 microns thick, depending upon the voltage rating of the power MOSFET 44 .
  • the spreading layer 50 may be about 1.0-2.5 microns thick.
  • Each one of the junction implants 52 may be about 1.0-2.0 microns thick.
  • the JFET region 54 may be about 0.75-1.5 microns thick.
  • the spreading layer 50 is an N-doped layer with a doping concentration from about 2 ⁇ 10 17 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 .
  • the spreading layer 50 may be graded, such that the portion of the spreading layer 50 closest to the drift layer 48 has a doping concentration about 5 ⁇ 10 16 cm ⁇ 3 that is graduated as the spreading layer 50 extends upwards to a doping concentration of about 2 ⁇ 10 17 cm ⁇ 3 .
  • the spreading layer 50 may comprise multiple layers.
  • the layer of the spreading layer 50 closest to the drift layer 48 may have a doping concentration about 5 ⁇ 10 16 cm ⁇ 3 .
  • the doping concentration of each additional layer in the spreading layer may decrease in proportion to the distance of the layer from the JFET region 54 .
  • the layer of the spreading layer 50 closest to the drift layer 48 may have a doping concentration about 2 ⁇ 10 17 cm ⁇ 3 .
  • the JFET region 54 may be an N-doped layer with a doping concentration from about 1 ⁇ 10 16 cm ⁇ 3 to 2 ⁇ 10 17 cm ⁇ 3 .
  • the drift layer 48 may be an N-doped layer with a doping concentration from about 6 ⁇ 10 15 cm ⁇ 3 to 1.5 ⁇ 10 16 cm ⁇ 3 .
  • the deep well region 56 may be a heavily P-doped region with a doping concentration from about 5 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the base region 58 may be a P-doped region with a doping concentration from about 5 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the source region 60 may be an N-doped region with a doping concentration from about 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the N doping agent may be nitrogen, phosphorous, or any other suitable element, as will be appreciated by those of ordinary skill in the art.
  • the P doping agent may be aluminum, boron, or any other suitable element, as will be appreciated by those of ordinary skill in the art.
  • the gate contact 66 , the source contacts 68 , and the drain contact 70 may be comprised of multiple layers.
  • each one of the contacts may include a first layer of nickel or nickel-aluminum, a second layer of titanium over the first layer, a third layer of titanium-nickel over the second layer, and a fourth layer of aluminum over the third layer.
  • the gate contact 66 , the source contacts 68 , and the drain contact 70 may be formed of any suitable material.
  • FIG. 5 shows the power MOSFET 44 according to an additional embodiment of the present disclosure.
  • the power MOSFET 44 shown in FIG. 5 is substantially similar to that of FIG. 3 , but further includes a channel Re-growth layer 80 between the gate oxide layer 64 and the spreading layer 50 .
  • the channel re-growth layer 80 is provided to lower the threshold voltage of the power MOSFET 44 .
  • the deep well region 56 due to a heavy level of doping, may raise the threshold voltage of the power MOSFET 44 to a level that inhibits optimum performance.
  • the channel re-growth layer 80 may offset the effects of the deep well region 56 in order to lower the threshold voltage of the power MOSFET 44 .
  • the channel re-growth layer 80 may be an N-doped region with a doping concentration from about 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3
  • FIGS. 6-15 illustrate a process for manufacturing the power MOSFET 44 shown in FIG. 3 .
  • the drift layer 48 is grown on top of the substrate 46 .
  • any suitable growth process may be used to produce the drift layer 48 without departing from the principles of the present disclosure.
  • a chemical vapor deposition process may be used to form the drift layer 48 .
  • the spreading layer 50 is grown on top of the drift layer 48 .
  • any suitable growth process may be used to create the spreading layer 50 without departing from the principles of the present disclosure.
  • the spreading layer 50 is grown such that it includes a graded doping profile.
  • the deep well region 56 of each one of the junction implants 52 is implanted in the spreading layer 50 .
  • the deep well regions 56 may be implanted by any suitable implantation process.
  • an ion implantation process may be used to form the deep well regions 56 .
  • the base regions 58 are then implanted, as illustrated by FIG. 9 , followed by the source regions 60 , as illustrated by FIG. 10 .
  • the JFET region 54 is implanted. As discussed above, any suitable implantation process may be used to create the JFET region 54 without departing from the principles of the present disclosure. Additionally, although not illustrated, the JFET region 54 may alternatively be created by a growth process.
  • the gate oxide layer 64 is formed on top of the spreading layer 50 , such that the gate oxide layer 64 partially overlaps and runs between the surface of each source region 60 in the junction implants 52 .
  • the gate contact 66 is formed on top of the gate oxide layer 64 .
  • the source contacts 68 are then formed on the surface of the spreading layer 50 such that each one of the source contacts 68 partially overlaps both the source region 60 and the deep well region 56 of the junction implants 52 , respectively, and does not contact the gate oxide layer 64 or the gate contact 66 , as illustrated by FIG. 14 .
  • the drain contact 70 is provided on the surface of the substrate 46 opposite the drift layer 48 .
  • FIG. 16 is a chart depicting the effect of the spreading layer 50 on the ON resistance of the power MOSFET 44 . As shown, the spreading layer provides about a 20 % decrease in the ON resistance of the device.
  • FIG. 17 is a chart depicting the effect of the spreading layer 50 on the electric field seen by the gate oxide layer 64 . Because the spreading layer 50 allows a reduction in channel width 62 without impeding the performance of the power MOSFET 44 , up to 26% of the electric field seen by the gate oxide layer 64 may be terminated by the opposing junction implants 52 , thereby significantly increasing the longevity of the device.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

Description

RELATED APPLICATIONS
The present application is a reissue of U.S. Pat. No. 9,331,197, issued May 3, 2016, and entitled VERTICAL POWER TRANSISTOR DEVICE. The disclosure of which is incorporated herein by reference in its entirety.
FIELD OF THE DISCLOSURE
The present disclosure relates to power transistor devices, and in particular to power metal-oxide-semiconductor field-effect transistor (MOSFET) devices.
BACKGROUND
A power metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of transistor that is adapted for use in high power applications. Generally, a power MOSFET device has a vertical structure, wherein a source and gate contact are located on a first surface of the MOSFET device that is separated from a drain contact by a drift layer formed on a substrate. Vertical MOSFETS are sometimes referred to as vertical diffused MOSFETs (VDMOSFETs) or double-diffused MOSFETs (DMOSFETs). Due to their vertical structure, the voltage rating of a power MOSFET is a function of the doping and thickness of the drift layer. Accordingly, high voltage power MOSFETs may be achieved with a relatively small footprint.
FIG. 1 shows a conventional power MOSFET device 10. The conventional power MOSFET device 10 includes a substrate 12, a drift layer 14 formed over the substrate 12, one or more junction implants 16 in the surface of the drift layer 14 opposite the substrate, and a junction gate field effect transistor (JFET) region 18 between each one of the junction implants 16. Each one of the junction implants 16 is formed by an ion implantation process, and includes a deep well region 20, a base region 22, and a source region 24. Each deep well region 20 extends from a corner of the drift layer 14 opposite the substrate 12 downwards towards the substrate 12 and inwards towards the center of the drift layer 14. The deep well region 20 may be formed uniformly or include one or more protruding regions, as shown in FIG. 1. Each base region 22 is formed vertically from the surface of the drift layer 14 opposite the substrate 12 down towards the substrate 12 along a portion of the inner edge of each one of the deep well regions 20. Each source region 24 is formed in a shallow portion on the surface of the drift layer 14 opposite the substrate 12, and extends laterally to overlap a portion of the deep well region 20 and the base region 22, without extending over either. The JFET region 18 defines a channel width 26 between each one of the junction implants 16.
A gate oxide layer 28 is positioned on the surface of the drift layer 14 opposite the substrate 12, and extends laterally between a portion of the surface of each source region 24, such that the gate oxide layer 28 partially overlaps and runs between the surface of each source region 24 in the junction implants 16. A gate contact 30 is positioned on top of the gate oxide layer 28. Two source contacts 32 are each positioned on the surface of the drift layer 14 opposite the substrate 12 such that each one of the source contacts 32 partially overlaps both the source region 24 and the deep well region 20 of one of the junction implants 16, respectively, and does not contact the gate oxide layer 28 or the gate contact 30. A drain contact 34 is located on the surface of the substrate 12 opposite the drift layer 14.
In operation, when a biasing voltage is not applied to the gate contact 30 and the drain contact 34 is positively biased, a junction between each deep well region 20 and the drift layer 14 is reverse biased, thereby placing the conventional power MOSFET 10 in an OFF state. In the OFF state of the conventional power MOSFET 10, any voltage between the source and drain contact is supported by the drift layer 14. Due to the vertical structure of the conventional power MOSFET 10, large voltages may be placed between the source contacts 32 and the drain contact 34 without damaging the device.
FIG. 2 shows operation of the conventional power MOSFET 10 when the device is in an ON state. When a positive bias is applied to the gate contact 30 of the conventional power MOSFET 10, an inversion layer channel 36 is formed at the surface of the drift layer 14 underneath the gate contact 30, thereby placing the conventional power MOSFET 10 in an ON state. In the ON state of the conventional power MOSFET 10, current (shown by the shaded region in FIG. 2) is allowed to flow from each one of the source contacts 32 through the inversion layer channel 36 and into the JFET region 18 of the drift layer 14. Once in the JFET region 18, current flows downward through the drift layer 14 towards the drain contact 34. An electric field presented by junctions formed between the deep well region 20, the base region 22, and the drift layer 14 constricts current flow in the JFET region 18 into a JFET channel 38 having a JFET channel width 40. At a certain spreading distance 42 from the inversion layer channel 36 when the electric field presented by the junction implants 16 is diminished, the flow of current is distributed laterally, or spread out in the drift layer 14, as shown in FIG. 2. The JFET channel width 40 and the spreading distance 42 determine the internal resistance of the power MOSFET 10, thereby dictating the performance of the device. A conventional power MOSFET 10 generally requires a channel width 26 of 3 microns or wider in order to sustain an adequate JFET channel width and 40 spreading distance 42 for proper operation of the device.
The electric field formed by the junctions between the deep well region 20, the base region 22, and the drift layer 14 radiates through the gate oxide layer 28, thereby physically degrading the gate oxide layer 28 over time. Eventually, the electric field will cause the gate oxide layer 28 to break down, and the conventional power MOSFET 10 will cease to function.
Accordingly, a power MOSFET is needed that is capable of handling high voltages in the OFF state while maintaining a low ON state resistance and having an improved longevity.
SUMMARY
The present disclosure relates to a transistor device including a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. Each one of the junction implants may include a deep well region, a base region, and a source region. The transistor device further includes a gate oxide layer, a gate contact, a pair of source contacts, and a drain contact. The gate oxide layer is on a portion of the spreading layer such that the gate oxide layer partially overlaps and runs between each source region of each junction implant. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer such that each source contact partially overlaps both the source region and the deep well region of each junction implant, respectively. The drain contact is on the surface of the substrate opposite the drift layer.
According to one embodiment, the spreading layer has a graded doping profile, such that the doping concentration of the spreading layer decreases in proportion to the distance of the point in the spreading layer from the JFET region.
According to an additional embodiment, the spreading layer includes multiple layers, each having a different doping concentration that progressively decreases in proportion to the distance of the layer from the JFET region.
By placing a spreading layer over the drift layer, the space between each junction implant, or length of the JFET region, can be reduced while simultaneously maintaining or reducing the ON resistance of the device. By reducing the space between each junction implant, a larger portion of the electric field generated during reverse bias of the transistor device is terminated by each one of the junction implants, thereby reducing the electric field seen by the gate oxide layer and increasing the longevity of the device.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
BRIEF DESCRIPTION OF THE DRAWING FIGURES
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
FIG. 1 shows a schematic representation of a conventional power MOSFET device.
FIG. 2 shows details of the operation of the conventional power MOSFET device shown in FIG. 1.
FIG. 3 shows a power MOSFET device according to one embodiment of the present disclosure.
FIG. 4 shows details of the operation of the power MOSFET device shown in FIG. 3 according to one embodiment of the present disclosure.
FIG. 5 shows an alternative embodiment of the power MOSFET device shown in FIG. 3.
FIGS. 6-15 illustrate a process for manufacturing the power MOSFET device shown in FIG. 3.
FIG. 16 shows a graph indicating performance improvements achieved by the power MOSFET device shown in FIG. 3.
FIG. 17 shows a graph indicating longevity improvements achieved by the power MOSFET device shown in FIG. 3.
 DETAILED DESCRIPTION
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Turning now to FIG. 3, a power MOSFET device 44 is shown according to one embodiment of the present disclosure. The power MOSFET device 44 includes a substrate 46, a drift layer 48 formed over the substrate 46, a spreading layer 50 formed over the drift layer 48, one or more junction implants 52 in the surface of the spreading layer 50 opposite the drift layer 48, and a junction gate field effect transistor (JFET) region 54 between each one of the junction implants 52. Each one of the junction implants 52 may be formed by an ion implantation process, and may include a deep well region 56, a base region 58, and a source region 60. Each deep well region 56 extends from a corner of the spreading layer 50 opposite the drift layer 48 downwards towards the drift layer 48 and inwards towards the center of the spreading layer 50. The deep well region 56 may be formed uniformly or include one or more protruding regions. Each base region 58 is formed vertically from the surface of the spreading layer 50 opposite the drift layer 48 downwards towards the drift layer 48 along a portion of the inner edge of each one of the deep well regions 56. Each source region 60 is formed in a shallow portion on the surface of the spreading layer 50 opposite the drift layer 48, and extends laterally to overlap a portion of the deep well region 56 and the base region 58, without extending over either. The JFET region 54 defines a channel width 62 between each one of the junction implants 52.
A gate oxide layer 64 is positioned on the surface of the spreading layer 50 opposite the drift layer 48, and extends laterally between a portion of the surface of each source region 60, such that the gate oxide layer 64 partially overlaps and runs between the surface of each source region 60 in the junction implants 52. A gate contact 66 is positioned on top of the gate oxide layer 64. Two source contacts 68 are each positioned on the surface of the spreading layer 50 opposite the drift layer 48 such that each one of the source contacts 68 partially overlaps both the source region 60 and the deep well region 56 of the junction implants 52, respectively, and does not contact the gate oxide layer 64 or the gate contact 66. A drain contact 70 is located on the surface of the substrate 46 opposite the drift layer 48.
In operation, when a biasing voltage is not applied to the gate contact 66 and the drain contact 70 is positively biased, a junction between each deep well region 56 and the spreading layer 50 is reverse biased, thereby placing the power MOSFET 44 in an OFF state. In an OFF state of the power MOSFET 44, any voltage between the source and drain contact is supported by the drift layer 48 and the spreading layer 50. Due to the vertical structure of the power MOSFET 44, large voltages may be placed between the source contacts 68 and the drain contact 70 without damaging the device.
FIG. 4 shows the operation of the power MOSFET 44 when the device is in an ON state. When a positive bias is applied to the gate contact 66 of the power MOSFET 44, an inversion layer channel 72 is formed at the surface of the spreading layer 50 underneath the gate contact 66, thereby placing the power MOSFET 44 in an ON state. In the ON state of the power MOSFET 44, current (shown by the shaded region in FIG. 4) is allowed to flow from each one of the source contacts 68 through the inversion layer channel 72 and into the JFET region 54. Once in the JFET region 54, current flows downward through the spreading layer 50 towards the drain contact 70. An electric field presented by the junctions formed between the deep well region 56, the base region 58, and the spreading layer 50 constricts current flow in the JFET region 54 into a JFET channel 74 having a JFET channel width 76.
At a certain spreading distance 78 from the inversion layer channel 72 when the electric field presented by the junction implants 52 is diminished, the flow of current is distributed laterally, or spread out, in the spreading layer 50, as shown in FIG. 4. The spreading layer 50 is doped in such a way to decrease resistance in the spreading layer 50, thereby mitigating the effects of the electric field by increasing the JFET channel width 76 and decreasing the spreading distance 78. By increasing the JFET channel width 76 and decreasing the spreading distance 78, the spreading layer 50 significantly reduces the ON resistance of the power MOSFET 44. For example, the ON resistance of the power MOSFET 44 may be about 2.2 mΩ/cm2 when the device is rated to handle 1200V and about 1.8 mΩ/cm2 when the device is rated to handle 600V.
By reducing the ON resistance of the power MOSFET 44, the spreading layer 50 allows for a reduction of the channel width 62 between each one of the junction implants 52. Reducing the channel width 62 of the power MOSFET 44 not only improves the footprint of the device, but also the longevity. As each one of the junction implants 52 is moved closer to one another, a larger portion of the electric field generated by the junctions between the deep well region 56, the base region 58, and the spreading layer 50 is terminated by the opposite junction implant 52. Accordingly, the electric field seen by the gate oxide layer 64 is significantly reduced, thereby resulting in improved longevity of the power MOSFET 44. According to one embodiment, the channel width 62 of the power MOSFET 44 is less than 3 microns.
The power MOSFET 44 may be, for example, a silicon carbide (SiC), gallium arsenide (GaAs), or gallium nitride (GaN) device. Those of ordinary skill in the art will appreciate that the concepts of the present disclosure may be applied to any materials system. The substrate 46 of the power MOSFET 44 may be about 180-350 microns thick. The drift layer 48 may be about 3.5-12 microns thick, depending upon the voltage rating of the power MOSFET 44. The spreading layer 50 may be about 1.0-2.5 microns thick. Each one of the junction implants 52 may be about 1.0-2.0 microns thick. The JFET region 54 may be about 0.75-1.5 microns thick.
According to one embodiment, the spreading layer 50 is an N-doped layer with a doping concentration from about 2×1017 cm−3 to 5×1016 cm−3. The spreading layer 50 may be graded, such that the portion of the spreading layer 50 closest to the drift layer 48 has a doping concentration about 5×1016 cm−3 that is graduated as the spreading layer 50 extends upwards to a doping concentration of about 2×1017 cm−3. According to an additional embodiment, the spreading layer 50 may comprise multiple layers. The layer of the spreading layer 50 closest to the drift layer 48 may have a doping concentration about 5×1016 cm−3. The doping concentration of each additional layer in the spreading layer may decrease in proportion to the distance of the layer from the JFET region 54. The layer of the spreading layer 50 closest to the drift layer 48 may have a doping concentration about 2×1017 cm−3.
The JFET region 54 may be an N-doped layer with a doping concentration from about 1×1016 cm−3 to 2×1017 cm−3. The drift layer 48 may be an N-doped layer with a doping concentration from about 6×1015 cm−3 to 1.5×1016 cm−3. The deep well region 56 may be a heavily P-doped region with a doping concentration from about 5×1017 cm−3 to 1×1020 cm−3. The base region 58 may be a P-doped region with a doping concentration from about 5×1016 cm−3 to 1×1019cm−3. The source region 60 may be an N-doped region with a doping concentration from about 1×1019 cm−3 to 1×1021 cm−3. The N doping agent may be nitrogen, phosphorous, or any other suitable element, as will be appreciated by those of ordinary skill in the art. The P doping agent may be aluminum, boron, or any other suitable element, as will be appreciated by those of ordinary skill in the art.
The gate contact 66, the source contacts 68, and the drain contact 70 may be comprised of multiple layers. For example, each one of the contacts may include a first layer of nickel or nickel-aluminum, a second layer of titanium over the first layer, a third layer of titanium-nickel over the second layer, and a fourth layer of aluminum over the third layer. Those of ordinary skill in the art will appreciate that the gate contact 66, the source contacts 68, and the drain contact 70 may be formed of any suitable material.
FIG. 5 shows the power MOSFET 44 according to an additional embodiment of the present disclosure. The power MOSFET 44 shown in FIG. 5 is substantially similar to that of FIG. 3, but further includes a channel Re-growth layer 80 between the gate oxide layer 64 and the spreading layer 50. The channel re-growth layer 80 is provided to lower the threshold voltage of the power MOSFET 44. Specifically, the deep well region 56, due to a heavy level of doping, may raise the threshold voltage of the power MOSFET 44 to a level that inhibits optimum performance. Accordingly, the channel re-growth layer 80 may offset the effects of the deep well region 56 in order to lower the threshold voltage of the power MOSFET 44. The channel re-growth layer 80 may be an N-doped region with a doping concentration from about 1×1015 cm−3 to 1×1017 cm−3
FIGS. 6-15 illustrate a process for manufacturing the power MOSFET 44 shown in FIG. 3. First, as illustrated by FIG. 6, the drift layer 48 is grown on top of the substrate 46. Those of ordinary skill in the art will recognize that any suitable growth process may be used to produce the drift layer 48 without departing from the principles of the present disclosure. For example, a chemical vapor deposition process may be used to form the drift layer 48.
Next, as illustrated by FIG. 7, the spreading layer 50 is grown on top of the drift layer 48. As discussed above, any suitable growth process may be used to create the spreading layer 50 without departing from the principles of the present disclosure. According to one embodiment, the spreading layer 50 is grown such that it includes a graded doping profile.
Next, as illustrated by FIG. 8, the deep well region 56 of each one of the junction implants 52 is implanted in the spreading layer 50. As will be appreciated by those of ordinary skill in the art, the deep well regions 56 may be implanted by any suitable implantation process. For example, an ion implantation process may be used to form the deep well regions 56. The base regions 58 are then implanted, as illustrated by FIG. 9, followed by the source regions 60, as illustrated by FIG. 10.
Next, as illustrated by FIG. 11, the JFET region 54 is implanted. As discussed above, any suitable implantation process may be used to create the JFET region 54 without departing from the principles of the present disclosure. Additionally, although not illustrated, the JFET region 54 may alternatively be created by a growth process.
Next, as illustrated by FIG. 12, the gate oxide layer 64 is formed on top of the spreading layer 50, such that the gate oxide layer 64 partially overlaps and runs between the surface of each source region 60 in the junction implants 52. In FIG. 13, the gate contact 66 is formed on top of the gate oxide layer 64. The source contacts 68 are then formed on the surface of the spreading layer 50 such that each one of the source contacts 68 partially overlaps both the source region 60 and the deep well region 56 of the junction implants 52, respectively, and does not contact the gate oxide layer 64 or the gate contact 66, as illustrated by FIG. 14. Finally, in FIG. 15, the drain contact 70 is provided on the surface of the substrate 46 opposite the drift layer 48.
FIG. 16 is a chart depicting the effect of the spreading layer 50 on the ON resistance of the power MOSFET 44. As shown, the spreading layer provides about a 20% decrease in the ON resistance of the device.
FIG. 17 is a chart depicting the effect of the spreading layer 50 on the electric field seen by the gate oxide layer 64. Because the spreading layer 50 allows a reduction in channel width 62 without impeding the performance of the power MOSFET 44, up to 26% of the electric field seen by the gate oxide layer 64 may be terminated by the opposing junction implants 52, thereby significantly increasing the longevity of the device.
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims (32)

What is claimed is:
1. A transistor device comprising a gate, a source, and a drain, wherein the gate and the source are separated from the drain by at least a JFET region, a spreading layer including a graded doping profile, and a drift layer, wherein a doping concentration of the spreading layer varies more than a factor of about 102 cm−3 between the JFET region and the drift layer, a thickness of the JFET region is between 0.75 μm and 1.5 μm, a pair of junction implants is in the spreading layer such that the pair of junction implants is separated by the JFET region, the pair of junction implants is provided to a depth between 1.0 μm and 2.0 μm measured from a surface of the spreading layer opposite the drift layer, the doping concentration of the spreading layer increases as a distance from the drift layer increases, and a thickness of the spreading layer is between 1.0 μm and 2.5 μm.
2. The transistor device of claim 1 wherein the JFET region, the spreading layer, and the drift layer comprise silicon carbide.
3. The transistor device of claim 1 wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).
4. The transistor device of claim 1 wherein the JFET region has a first doping concentration, the spreading layer has a second doping concentration that is different from the first doping concentration, and the drift layer has a third doping concentration that is different from the first doping concentration and the second doping concentration.
5. The transistor device of claim 4 wherein the spreading layer has a doping concentration in the range of approximately 2×1017 cm−3 to approximately 5×1016 cm−3.
6. The transistor device of claim 4 wherein the JFET region has a doping concentration in the range of approximately 1×1016 cm−3 to approximately 2×1017 cm−3.
7. The transistor device of claim 1 wherein a thickness of the JFET region is in the range of approximately 0.75 microns to approximately 1 micron drift layer is in the range of approximately 3.5 μm to approximately 12 μm.
8. The transistor device of claim 1 wherein a thickness of the spreading layer is in the range of approximately 1.0 microns to approximately 2.5 microns.
9. The transistor device of claim 1 wherein a thickness of the drift layer is in the range of approximately 3.5 microns to approximately 12 microns.
10. The transistor device of claim 1 wherein an internal resistance of the transistor device is less than approximately 2.2 mΩ/cm2.
11. The transistor device of claim 1 wherein the transistor device is adapted to support a voltage between the source and the drain of at least 600V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 1.8 mΩ/cm2.
12. The transistor device of claim 1 wherein the transistor device is adapted to support a voltage between the source and the drain of at least 1200V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 2.2 mΩ/cm2.
13. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer having a graded doping profile such that a doping concentration of the spreading layer varies more than a factor of about 102 cm−3 between a JFET region and the drift layer, the doping concentration of the spreading layer increases as a distance from the drift layer increases, a thickness of the spreading layer is between 1.0 μm and 2.5 μm, and a thickness of the JFET region is between 0.75 μm and 1.5 μm; a pair of junction implants in the spreading layer and separated by the JFET region, each one of the pair of junction implants comprising a deep well region, a base region, and a source region such that a depth of the deep well region as measured from a surface of the spreading layer opposite the drift layer is between 1.0 μm and 2.0 μm; a gate contact and a source contact on the spreading layer, such that the gate contact partially overlaps and runs between each source region in the pair of junction implants; and a drain contact on the substrate opposite the drift layer.
14. The transistor device of claim 13 further comprising a gate oxide layer between the gate contact and the spreading layer.
15. The transistor device of claim 13 wherein the source contact is divided into two sections, and each section of the source contact is on a portion of the spreading layer such that each section of the source contact partially overlaps both the source region and the deep well region of each one of the pair of junction implants, respectively.
16. The transistor device of claim 13 wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).
17. The transistor device of claim 13 wherein the drift layer and the spreading layer comprise silicon carbide.
18. The transistor device of claim 13 wherein a width of the JFET region is approximately 3 microns μm or less.
19. The transistor device of claim 18 wherein an internal resistance of the transistor device is less than approximately 2.2 mΩ/cm2.
20. The transistor device of claim 13 wherein the transistor device is adapted to support a voltage between the source contact and the drain contact of at least 600V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 1.8 mΩ/cm2.
21. The transistor device of claim 13 wherein the transistor device is adapted to support a voltage between the source contact and the drain contact of at least 1200V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 2.2 mΩ/cm2.
22. The transistor device of claim 13 wherein a thickness of the drift layer is in the range of approximately 3.5 microns to approximately 12 microns.
23. The transistor device of claim 13 wherein a thickness of the spreading layer is in the range of approximately 1.0 microns to approximately 2.5 microns.
24. The transistor device of claim 13 wherein a thickness of the JFET region is in the range of approximately 0.75 microns to approximately 1.0 microns drift layer is in a range of approximately 3.5 μm to approximately 12 μm.
25. The transistor device of claim 13 wherein a thickness of each one of the pair of junction implants is in the range of approximately 1.0 microns to approximately 2.0 microns.
26. A method for manufacturing a transistor device, the method comprising:
providing a substrate;
providing a drift layer on the substrate;
providing a spreading layer on the drift layer such that the spreading layer has a thickness between 1.0 μm and 2.5 μm and the spreading layer has a graded doping profile wherein a doping concentration of the spreading layer increases as a distance from the drift layer increases such that a ratio of the doping concentration at a surface of the spreading layer adjacent to the drift layer to the doping concentration at a surface of the spreading layer opposite the drift layer is 1:x where x is greater than or equal to 2;
providing a pair of junction implants in the spreading layer such that each of the pair of junction implants is laterally separated from one another and a depth of the pair of junction implants as measured from a surface of the spreading layer opposite the drift layer is between 1.0 μm and 2.0 μm;
providing a junction field effect transistor (JFET) region between the pair of junction implants, the JFET region having a thickness between 0.75 μm and 1.5 μm;
providing a gate oxide layer on the spreading layer opposite the drift layer;
providing a gate contact on the gate oxide layer;
providing a source contact on the spreading layer over at least one of the pair of junction implants; and
providing a drain contact on the substrate opposite the drift layer.
27. The method of claim 26 wherein the substrate, the drift layer, and the spreading layer are silicon carbide.
28. The method of claim 26 wherein x is less than or equal to 4.
29. The method of claim 26 wherein the spreading layer is provided such that the doping concentration at the surface of the spreading layer adjacent to the drift layer is 5×1016cm−3 and the doping concentration at the surface of the spreading layer opposite the drift layer is 2×1017 cm−3.
30. The method of claim 26 wherein providing the spreading layer comprises providing a plurality of layers, each having a different doping concentration to provide the graded doping profile of the spreading layer.
31. The method of claim 26 wherein the substrate, the drift layer, the spreading layer, and the pair of junction implants are provided such that a distance between the pair of junction implants is less than 3 μm, an on-state resistance of the transistor device is between 1.8 mΩ/cm2 and 2.2 mΩ/cm2, and a blocking voltage of the transistor device is between 600 volts and 1200 volts.
32. The transistor device of claim 31 wherein x is less than or equal to 4.
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US10868169B2 (en) 2013-09-20 2020-12-15 Cree, Inc. Monolithically integrated vertical power transistor and bypass diode
CN106898652B (en) * 2017-03-09 2019-06-04 电子科技大学 A kind of silicon carbide VDMOS device
US10608102B2 (en) 2017-09-29 2020-03-31 Electronics And Telecommunications Research Institute Semiconductor device having a drain electrode contacting an epi material inside a through-hole and method of manufacturing the same
US10685886B2 (en) 2017-12-15 2020-06-16 International Business Machines Corporation Fabrication of logic devices and power devices on the same substrate
JP7106881B2 (en) * 2018-02-09 2022-07-27 株式会社デンソー Silicon carbide substrate and silicon carbide semiconductor device
CN110718452A (en) 2018-07-12 2020-01-21 创能动力科技有限公司 Silicon carbide device and method for manufacturing same
US11075295B2 (en) * 2018-07-13 2021-07-27 Cree, Inc. Wide bandgap semiconductor device
US11069804B2 (en) 2018-08-31 2021-07-20 Alpha And Omega Semiconductor (Cayman) Ltd. Integration of HVLDMOS with shared isolation region
JP7413701B2 (en) 2019-10-03 2024-01-16 富士電機株式会社 Nitride semiconductor device and method for manufacturing nitride semiconductor device
CN112670344B (en) * 2020-12-10 2022-07-22 复旦大学 SiC MOSFET with gradually-changed channel and self-alignment process thereof
CN116137283A (en) 2021-11-17 2023-05-19 苏州东微半导体股份有限公司 Semiconductor super junction power device
TWI818652B (en) * 2022-07-29 2023-10-11 鴻海精密工業股份有限公司 Manufacturing method of semiconductor device
US20240145551A1 (en) * 2022-10-27 2024-05-02 Panjit International Inc. Manufacturing Method of Forming Semiconductor Device and Semiconductor Device

Citations (131)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4126900A (en) * 1977-01-28 1978-11-21 U.S. Philips Corporation Random access junction field-effect floating gate transistor memory
JPS5742164A (en) 1980-08-27 1982-03-09 Hitachi Ltd Semiconductor device
JPS6149474A (en) 1984-08-17 1986-03-11 Matsushita Electronics Corp Field-effect transistor and manufacture thereof
US4803533A (en) 1986-09-30 1989-02-07 General Electric Company IGT and MOSFET devices having reduced channel width
US4967243A (en) 1988-07-19 1990-10-30 General Electric Company Power transistor structure with high speed integral antiparallel Schottky diode
US5111253A (en) 1989-05-09 1992-05-05 General Electric Company Multicellular FET having a Schottky diode merged therewith
US5241195A (en) 1992-08-13 1993-08-31 North Carolina State University At Raleigh Merged P-I-N/Schottky power rectifier having extended P-I-N junction
JPH065867A (en) 1992-06-19 1994-01-14 Hitachi Ltd Semiconductor device and its production
US5365102A (en) 1993-07-06 1994-11-15 North Carolina State University Schottky barrier rectifier with MOS trench
US5378911A (en) 1993-02-23 1995-01-03 Nissan Motor Co., Ltd. Structure of semiconductor device
US5536977A (en) 1993-11-30 1996-07-16 Siliconix Incorporated Bidirectional current blocking MOSFET for battery disconnect switching
EP0748520A1 (en) 1994-03-04 1996-12-18 Siemens Aktiengesellschaft Silicon carbide-based mis structure with high latch-up resistance
US5661314A (en) 1990-05-09 1997-08-26 International Rectifier Corporation Power transistor device having ultra deep increased concentration
US5674766A (en) 1994-12-30 1997-10-07 Siliconix Incorporated Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer
US5689144A (en) 1996-05-15 1997-11-18 Siliconix Incorporated Four-terminal power MOSFET switch having reduced threshold voltage and on-resistance
EP0867943A1 (en) 1997-03-28 1998-09-30 STMicroelectronics, Inc. DMOS transistors with schottky diode body structure
US5886383A (en) 1997-01-10 1999-03-23 International Rectifier Corporation Integrated schottky diode and mosgated device
US5973367A (en) 1995-10-13 1999-10-26 Siliconix Incorporated Multiple gated MOSFET for use in DC-DC converter
US6057558A (en) 1997-03-05 2000-05-02 Denson Corporation Silicon carbide semiconductor device and manufacturing method thereof
US6239463B1 (en) 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
US20020038891A1 (en) 2000-10-03 2002-04-04 Sei-Hyung Ryu Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel
FR2814855A1 (en) 2000-10-03 2002-04-05 St Microelectronics Sa Schottky junction with a stable live gate height on a layer of silicon carbide covered by a layer of metallic carbide
US20020047124A1 (en) 2000-10-23 2002-04-25 Matsushita Electric Industrial Co., Ltd. Semiconductor element
US20020125541A1 (en) 1999-12-30 2002-09-12 Jacek Korec Method of fabricating trench junction barrier rectifier
US20030006452A1 (en) 2001-07-03 2003-01-09 Ashok Challa Trench structure for semiconductor devices
US20030040144A1 (en) 2001-08-23 2003-02-27 Blanchard Richard A. Trench DMOS transistor with embedded trench schottky rectifier
US20030080355A1 (en) 2001-10-26 2003-05-01 Hitachi, Ltd. Semiconductor device
US20030178672A1 (en) 2002-03-25 2003-09-25 Tetsuo Hatakeyama High-breakdown-voltage semiconductor device
US20030214011A1 (en) 2002-05-03 2003-11-20 International Rectifier Corporation Short channel trench power MOSFET with low threshold voltage
US6700175B1 (en) 1999-07-02 2004-03-02 Kabushiki Kaisha Toyota Chuo Kenkyusho Vertical semiconductor device having alternating conductivity semiconductor regions
US20040099905A1 (en) * 2001-04-11 2004-05-27 Baliga Bantval Jayant Power semiconductor devices having laterally extending base shielding regions that inhibit base reach-through and schottky rectifying flyback diodes
US20040195618A1 (en) 2003-04-07 2004-10-07 Wataru Saito Insulated gate semiconductor device
US20040212011A1 (en) 2003-04-24 2004-10-28 Sei-Hyung Ryu Silicon carbide mosfets with integrated antiparallel junction barrier schottky free wheeling diodes and methods of fabricating the same
US20040251503A1 (en) 2003-06-16 2004-12-16 Nissan Motor Co., Ltd. Insulated gate drive semiconductor device
US20050035398A1 (en) 1999-05-25 2005-02-17 Williams Richard K. Trench MOSFET with recessed clamping diode
US20050045960A1 (en) 2003-08-27 2005-03-03 Mitsubishi Denki Kabushiki Kaisha Insulated gate transistor incorporating diode
US20050082611A1 (en) 2002-02-02 2005-04-21 Peake Steven T. Cellular mosfet devices and their manufacture
EP1576672A2 (en) 2002-12-20 2005-09-21 Cree, Inc. Silicon carbide power mos field effect transistors and manufacturing methods
US20050253190A1 (en) * 2004-04-09 2005-11-17 Kabushiki Kaisha Toshiba Semiconductor device
CN1729577A (en) 2002-12-20 2006-02-01 克里公司 Silicon carbide power metal-oxide semiconductor field effect transistors and manufacturing methods
US20060192256A1 (en) 2005-01-21 2006-08-31 Cooper James A High-voltage power semiconductor device
US20060202264A1 (en) 2005-02-11 2006-09-14 Alpha & Omega Semiconductor, Ltd Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout
US20060214221A1 (en) 2003-05-20 2006-09-28 Ashok Challa Power semiconductor devices and methods of manufacture
US20070012983A1 (en) 2005-07-15 2007-01-18 Yang Robert K Terminations for semiconductor devices with floating vertical series capacitive structures
US20070034901A1 (en) 2005-02-11 2007-02-15 Alpha & Omega Semiconductor, Ltd Trench junction barrier controlled Schottky
US20070045655A1 (en) 2005-08-25 2007-03-01 Samsung Electro-Mechanics Co., Ltd. Nitride semiconductor light emitting device
US20070096237A1 (en) 2003-01-15 2007-05-03 Microsemi Corp. -Power Products Group Design and fabrication of rugged fred, power mosfet or igbt
US20070120201A1 (en) 2005-11-25 2007-05-31 Denso Corporation Semiconductor device having super junction MOS transistor and method for manufacturing the same
US20070145414A1 (en) 2005-12-27 2007-06-28 Richard Francis Ultrafast recovery diode
JP2007184434A (en) 2006-01-10 2007-07-19 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof
US20070235745A1 (en) 2006-04-11 2007-10-11 Nissan Motor Co., Ltd. Semiconductor device and manufacturing method thereof
US20080012026A1 (en) 2006-07-10 2008-01-17 Fuji Electric Holdings Co., Ltd. Trench mos type silicon carbide semiconductor device and method for manufacturing the same
US20080029812A1 (en) 2005-02-11 2008-02-07 Alpha & Omega Semiconductor, Ltd Planar SRFET using no additional masks and layout method
US20080050876A1 (en) 2006-08-23 2008-02-28 General Electric Company Method for fabricating silicon carbide vertical mosfet devices
US20080128850A1 (en) 2004-11-08 2008-06-05 Alfred Goerlach Semiconductor Device And Method For Manufacturing Same
US20080142811A1 (en) * 2006-12-13 2008-06-19 General Electric Company MOSFET devices and methods of fabrication
US20080149963A1 (en) 2005-06-08 2008-06-26 Adan Alberto O Trench Type Mosfet and Method of Fabricating the Same
US20080197439A1 (en) 2004-11-08 2008-08-21 Alfred Goerlach Semiconductor Device And Method For Manufacturing Same
US20080206941A1 (en) 2007-02-23 2008-08-28 Denso Corporation Method for manufacturing sic semiconductor device
US20080230787A1 (en) 2007-03-20 2008-09-25 Denso Corporation Silicon carbide semiconductor device, and method of manufacturing the same
US20080308838A1 (en) 2007-06-13 2008-12-18 Mcnutt Ty R Power switching transistors
US20090057757A1 (en) 2007-08-31 2009-03-05 Kabushiki Kaisha Toshiba Trench gate semiconductor device and method of manufacturing the same
US20090065814A1 (en) 2005-02-11 2009-03-12 Alpha & Omega Semiconductor Limited MOS device with schottky barrier controlling layer
US20090072242A1 (en) 2007-09-18 2009-03-19 Cree, Inc. Insulated Gate Bipolar Conduction Transistors (IBCTS) and Related Methods of Fabrication
US20090079001A1 (en) 2007-09-21 2009-03-26 Ali Salih Multi-channel esd device and method therefor
US20090078971A1 (en) 2007-09-20 2009-03-26 Infineon Technologies Austria Ag Semiconductor device with structured current spread region and method
US20090090920A1 (en) 2007-10-05 2009-04-09 Denso Corporation Silicon carbide semiconductor device
US20090146154A1 (en) 2007-12-07 2009-06-11 Cree, Inc. Transistor with A-Face Conductive Channel and Trench Protecting Well Region
US20090173949A1 (en) 2006-03-02 2009-07-09 National Institute Of Adv. Industrial Sci. & Tech. Silicon carbide mos field effect transistor with built-in schottky diode and method for manufacturing such transistor
US20090179297A1 (en) 2008-01-16 2009-07-16 Northrop Grumman Systems Corporation Junction barrier schottky diode with highly-doped channel region and methods
US20090189228A1 (en) 2008-01-25 2009-07-30 Qingchun Zhang Semiconductor transistor with p type re-grown channel layer
US20090218621A1 (en) 2005-07-27 2009-09-03 Infineon Technologies Austria Ag Semiconductor component with a drift region and a drift control region
US7592647B2 (en) 2005-03-31 2009-09-22 Eudyna Devices Inc. Semiconductor device and manufacturing method thereof
US20090236612A1 (en) 2008-03-24 2009-09-24 Fuji Electric Device Technology Co., Ltd. Silicon carbide mos semiconductor device
US20090272983A1 (en) 2004-11-08 2009-11-05 Denso Corporation Silicon carbide semiconductor device and method for manufacturing the same
US20090278197A1 (en) 2006-08-24 2009-11-12 Rohm Co., Ltd Mis field effect transistor and method for manufacturing the same
US20090283798A1 (en) 2007-06-20 2009-11-19 Denso Corporation Semiconductor device and manufacturing method thereof
US20090283776A1 (en) 2008-04-17 2009-11-19 Fuji Electric Device Technology Co., Ltd. Wide band gap semiconductor device and method for producing the same
US20100013007A1 (en) 2006-12-07 2010-01-21 Nobuki Miyakoshi Semiconductor device and method for manufacturing the same
US20100025693A1 (en) 2008-07-30 2010-02-04 Denso Corporation Wide band gap semiconductor device including junction field effect transistor
US20100073039A1 (en) 2008-09-24 2010-03-25 Oki Semiconductor Co., Ltd. H-Bridge circuit
US20100078710A1 (en) 2007-10-18 2010-04-01 Infineon Technologies Austria Ag Semiconductor component with a drift zone and a drift control zone
US20100093116A1 (en) 2008-10-14 2010-04-15 General Electric Company Dimension profiling of sic devices
US20100176443A1 (en) 2007-06-15 2010-07-15 Rohm Co., Ltd. Semiconductor Device
US20100219417A1 (en) 2006-02-07 2010-09-02 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing same
US20100270586A1 (en) 2009-04-28 2010-10-28 Fuji Electric Systems Co. Ltd. Wide band gap semiconductor device
US20110049564A1 (en) 2009-08-31 2011-03-03 Alpha & Omega Semiconductor, Inc. Integrated schottky diode in high voltage semiconductor device
US20110156810A1 (en) 2009-12-30 2011-06-30 Intersil Americas Inc. Integrated dmos and schottky
US20110193057A1 (en) * 2007-11-30 2011-08-11 Osram Opto Semiconductors Gmbh LED Having Current Spreading Layer
US20110241068A1 (en) 2010-03-30 2011-10-06 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the semiconductor device
US20110254088A1 (en) 2010-04-20 2011-10-20 Maxpower Semiconductor Inc. Power MOSFET With Embedded Recessed Field Plate and Methods of Fabrication
US20120025874A1 (en) 2010-07-27 2012-02-02 Denso Corporation Semiconductor device having switching element and free wheel diode and method for controlling the same
US20120037955A1 (en) 2010-08-12 2012-02-16 Infineon Technologies Austria Ag Transistor Component with Reduced Short-Circuit Current
US20120088339A1 (en) * 2010-10-12 2012-04-12 Io Semiconductor, Inc. Vertical Semiconductor Device with Thinned Substrate
US8178920B2 (en) * 2006-01-17 2012-05-15 Fuji Electric Co., Ltd. Semiconductor device and method of forming the same
JP2012114104A (en) 2009-02-24 2012-06-14 Hitachi Ltd Storage insulation gate type field effect transistor
US20120187419A1 (en) 2009-07-15 2012-07-26 Infineon Technologies Ag Production Method for a Unipolar Semiconductor Component and Semiconductor Device
US20120236615A1 (en) 2010-10-29 2012-09-20 Makoto Kitabatake Converter
US8283973B2 (en) 2009-08-19 2012-10-09 Panasonic Corporation Semiconductor element, semiconductor device, and electric power converter
US20120256195A1 (en) 2011-04-06 2012-10-11 Rohm Co., Ltd. Semiconductor device
WO2012137914A1 (en) 2011-04-08 2012-10-11 独立行政法人産業技術総合研究所 Silicon carbide vertical field effect transistor
US20120280258A1 (en) * 2010-12-31 2012-11-08 Xiamen Sanan Optoelectronics Technology Co., Ltd. Nitride Light-Emitting Diode with a Current Spreading Layer
US20120292742A1 (en) 2011-05-20 2012-11-22 Sumitomo Electric Industries, Ltd. Semiconductor device
US20120306009A1 (en) 2011-06-03 2012-12-06 Suku Kim Integration of superjunction mosfet and diode
US20120313212A1 (en) 2010-02-23 2012-12-13 Fuji Electric Co., Ltd. Semiconductor device
US20130026493A1 (en) 2011-05-16 2013-01-31 Cree, Inc. Sic devices with high blocking voltage terminated by a negative bevel
WO2013014943A2 (en) 2011-07-27 2013-01-31 Kabushiki Kaisha Toyota Chuo Kenkyusho Diode, semiconductor device, and mosfet
US20130026568A1 (en) 2005-02-11 2013-01-31 Anup Bhalla Planar srfet using no additional masks and layout method
US8415671B2 (en) * 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
US20130105889A1 (en) 2011-10-31 2013-05-02 Denso Corporation Switching device and method for manufacturing the same
US20130153995A1 (en) 2011-12-14 2013-06-20 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2013149837A (en) 2012-01-20 2013-08-01 Mitsubishi Electric Corp Silicon carbide semiconductor device and method of manufacturing the same
US8575692B2 (en) 2011-02-11 2013-11-05 Freescale Semiconductor, Inc. Near zero channel length field drift LDMOS
US20130306983A1 (en) 2011-02-02 2013-11-21 Rohm Co., Ltd. Semiconductor device and method for producing same
US20130313635A1 (en) 2011-02-02 2013-11-28 Rohm Co., Ltd. Semiconductor device
US20130341674A1 (en) 2012-06-21 2013-12-26 Infineon Technologies Ag Reverse Conducting IGBT
US20140021484A1 (en) 2012-07-19 2014-01-23 Infineon Technologies Ag Semiconductor Device
US20140027781A1 (en) 2012-07-26 2014-01-30 Cree, Inc. Monolithic bidirectional silicon carbide switching devices and methods of forming the same
US20140070268A1 (en) * 2011-05-18 2014-03-13 Fuji Electric Co., Ltd. Semiconductor device and semiconductor device manufacturing method
US20140077311A1 (en) * 2012-09-16 2014-03-20 Sensor Electronic Technology, Inc. Lateral/Vertical Semiconductor Device
US8686439B2 (en) 2011-06-27 2014-04-01 Panasonic Corporation Silicon carbide semiconductor element
US20140117376A1 (en) 2012-10-30 2014-05-01 Hitachi Metals, Ltd. Nitride Semiconductor Element and Method of Manufacturing the Same
US20140203299A1 (en) 2011-07-28 2014-07-24 Rohm Co., Ltd. Semiconductor device
US20140252554A1 (en) 2013-03-05 2014-09-11 Silergy Semiconductor Technology (Hangzhou) Ltd Wafer structure and power device using the same
US20150041886A1 (en) 2013-08-08 2015-02-12 Cree, Inc. Vertical power transistor device
US20150053920A1 (en) * 2012-06-19 2015-02-26 Xiamen Sanan Optoelectronics Technology Co., Ltd. LED with Current Spreading Layer and Fabrication Method
US20150084118A1 (en) 2013-09-20 2015-03-26 Cree, Inc. Semiconductor device including a power transistor device and bypass diode
US20150084063A1 (en) 2013-09-20 2015-03-26 Cree, Inc. Semiconductor device with a current spreading layer
US20150084125A1 (en) 2013-09-20 2015-03-26 Cree, Inc. Monolithically integrated vertical power transistor and bypass diode
US20150084119A1 (en) 2013-09-20 2015-03-26 Cree, Inc. Layout configurations for integrating schottky contacts into a power transistor device
US10192960B2 (en) 2013-07-26 2019-01-29 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09146329A (en) 1995-11-20 1997-06-06 Fuji Xerox Co Ltd Image forming device
EP2052414B1 (en) 2006-08-17 2016-03-30 Cree, Inc. High power insulated gate bipolar transistors
JP4863468B2 (en) * 2006-09-15 2012-01-25 三菱レイヨン株式会社 Manufacturing method of optical disk

Patent Citations (144)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4126900A (en) * 1977-01-28 1978-11-21 U.S. Philips Corporation Random access junction field-effect floating gate transistor memory
JPS5742164A (en) 1980-08-27 1982-03-09 Hitachi Ltd Semiconductor device
JPS6149474A (en) 1984-08-17 1986-03-11 Matsushita Electronics Corp Field-effect transistor and manufacture thereof
US4803533A (en) 1986-09-30 1989-02-07 General Electric Company IGT and MOSFET devices having reduced channel width
US4967243A (en) 1988-07-19 1990-10-30 General Electric Company Power transistor structure with high speed integral antiparallel Schottky diode
US5111253A (en) 1989-05-09 1992-05-05 General Electric Company Multicellular FET having a Schottky diode merged therewith
US5661314A (en) 1990-05-09 1997-08-26 International Rectifier Corporation Power transistor device having ultra deep increased concentration
JPH065867A (en) 1992-06-19 1994-01-14 Hitachi Ltd Semiconductor device and its production
US5241195A (en) 1992-08-13 1993-08-31 North Carolina State University At Raleigh Merged P-I-N/Schottky power rectifier having extended P-I-N junction
US5378911A (en) 1993-02-23 1995-01-03 Nissan Motor Co., Ltd. Structure of semiconductor device
US5365102A (en) 1993-07-06 1994-11-15 North Carolina State University Schottky barrier rectifier with MOS trench
US5536977A (en) 1993-11-30 1996-07-16 Siliconix Incorporated Bidirectional current blocking MOSFET for battery disconnect switching
EP0748520A1 (en) 1994-03-04 1996-12-18 Siemens Aktiengesellschaft Silicon carbide-based mis structure with high latch-up resistance
US5674766A (en) 1994-12-30 1997-10-07 Siliconix Incorporated Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer
US5973367A (en) 1995-10-13 1999-10-26 Siliconix Incorporated Multiple gated MOSFET for use in DC-DC converter
US5689144A (en) 1996-05-15 1997-11-18 Siliconix Incorporated Four-terminal power MOSFET switch having reduced threshold voltage and on-resistance
US5886383A (en) 1997-01-10 1999-03-23 International Rectifier Corporation Integrated schottky diode and mosgated device
US6057558A (en) 1997-03-05 2000-05-02 Denson Corporation Silicon carbide semiconductor device and manufacturing method thereof
EP0867943A1 (en) 1997-03-28 1998-09-30 STMicroelectronics, Inc. DMOS transistors with schottky diode body structure
US6239463B1 (en) 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
US20050035398A1 (en) 1999-05-25 2005-02-17 Williams Richard K. Trench MOSFET with recessed clamping diode
US6700175B1 (en) 1999-07-02 2004-03-02 Kabushiki Kaisha Toyota Chuo Kenkyusho Vertical semiconductor device having alternating conductivity semiconductor regions
US20020125541A1 (en) 1999-12-30 2002-09-12 Jacek Korec Method of fabricating trench junction barrier rectifier
US20020038891A1 (en) 2000-10-03 2002-04-04 Sei-Hyung Ryu Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel
FR2814855A1 (en) 2000-10-03 2002-04-05 St Microelectronics Sa Schottky junction with a stable live gate height on a layer of silicon carbide covered by a layer of metallic carbide
US20020047124A1 (en) 2000-10-23 2002-04-25 Matsushita Electric Industrial Co., Ltd. Semiconductor element
US20040099905A1 (en) * 2001-04-11 2004-05-27 Baliga Bantval Jayant Power semiconductor devices having laterally extending base shielding regions that inhibit base reach-through and schottky rectifying flyback diodes
US20030006452A1 (en) 2001-07-03 2003-01-09 Ashok Challa Trench structure for semiconductor devices
US20030040144A1 (en) 2001-08-23 2003-02-27 Blanchard Richard A. Trench DMOS transistor with embedded trench schottky rectifier
US20030080355A1 (en) 2001-10-26 2003-05-01 Hitachi, Ltd. Semiconductor device
US20050082611A1 (en) 2002-02-02 2005-04-21 Peake Steven T. Cellular mosfet devices and their manufacture
US20030178672A1 (en) 2002-03-25 2003-09-25 Tetsuo Hatakeyama High-breakdown-voltage semiconductor device
US20030214011A1 (en) 2002-05-03 2003-11-20 International Rectifier Corporation Short channel trench power MOSFET with low threshold voltage
TWI330894B (en) 2002-12-20 2010-09-21 Cree Inc Vertical jfet limited silicon carbide power metal-oxide semiconductor field effect transistors and methods of fabricating vertical jfet limited silicon carbide metal-oxide semiconductor field effect transistors
CN1729577A (en) 2002-12-20 2006-02-01 克里公司 Silicon carbide power metal-oxide semiconductor field effect transistors and manufacturing methods
US7221010B2 (en) * 2002-12-20 2007-05-22 Cree, Inc. Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors
US7923320B2 (en) * 2002-12-20 2011-04-12 Cree, Inc. Methods of fabricating vertical JFET limited silicon carbide metal-oxide semiconductor field effect transistors
EP1576672A2 (en) 2002-12-20 2005-09-21 Cree, Inc. Silicon carbide power mos field effect transistors and manufacturing methods
KR101020344B1 (en) 2002-12-20 2011-03-08 크리 인코포레이티드 Silicon carbide power MOS field effect transistors and manufacturing methods
US8492827B2 (en) * 2002-12-20 2013-07-23 Cree, Inc. Vertical JFET limited silicon carbide metal-oxide semiconductor field effect transistors
US20070096237A1 (en) 2003-01-15 2007-05-03 Microsemi Corp. -Power Products Group Design and fabrication of rugged fred, power mosfet or igbt
US20040195618A1 (en) 2003-04-07 2004-10-07 Wataru Saito Insulated gate semiconductor device
US6979863B2 (en) 2003-04-24 2005-12-27 Cree, Inc. Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same
US20040212011A1 (en) 2003-04-24 2004-10-28 Sei-Hyung Ryu Silicon carbide mosfets with integrated antiparallel junction barrier schottky free wheeling diodes and methods of fabricating the same
US20060214221A1 (en) 2003-05-20 2006-09-28 Ashok Challa Power semiconductor devices and methods of manufacture
US20040251503A1 (en) 2003-06-16 2004-12-16 Nissan Motor Co., Ltd. Insulated gate drive semiconductor device
US20050045960A1 (en) 2003-08-27 2005-03-03 Mitsubishi Denki Kabushiki Kaisha Insulated gate transistor incorporating diode
US20050253190A1 (en) * 2004-04-09 2005-11-17 Kabushiki Kaisha Toshiba Semiconductor device
US20090272983A1 (en) 2004-11-08 2009-11-05 Denso Corporation Silicon carbide semiconductor device and method for manufacturing the same
US20080128850A1 (en) 2004-11-08 2008-06-05 Alfred Goerlach Semiconductor Device And Method For Manufacturing Same
US20080197439A1 (en) 2004-11-08 2008-08-21 Alfred Goerlach Semiconductor Device And Method For Manufacturing Same
US20060192256A1 (en) 2005-01-21 2006-08-31 Cooper James A High-voltage power semiconductor device
US7498633B2 (en) * 2005-01-21 2009-03-03 Purdue Research Foundation High-voltage power semiconductor device
US20070034901A1 (en) 2005-02-11 2007-02-15 Alpha & Omega Semiconductor, Ltd Trench junction barrier controlled Schottky
US20130026568A1 (en) 2005-02-11 2013-01-31 Anup Bhalla Planar srfet using no additional masks and layout method
US20060202264A1 (en) 2005-02-11 2006-09-14 Alpha & Omega Semiconductor, Ltd Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout
US20080029812A1 (en) 2005-02-11 2008-02-07 Alpha & Omega Semiconductor, Ltd Planar SRFET using no additional masks and layout method
US20090065814A1 (en) 2005-02-11 2009-03-12 Alpha & Omega Semiconductor Limited MOS device with schottky barrier controlling layer
US7592647B2 (en) 2005-03-31 2009-09-22 Eudyna Devices Inc. Semiconductor device and manufacturing method thereof
US20080149963A1 (en) 2005-06-08 2008-06-26 Adan Alberto O Trench Type Mosfet and Method of Fabricating the Same
US20070012983A1 (en) 2005-07-15 2007-01-18 Yang Robert K Terminations for semiconductor devices with floating vertical series capacitive structures
US20090218621A1 (en) 2005-07-27 2009-09-03 Infineon Technologies Austria Ag Semiconductor component with a drift region and a drift control region
US20070045655A1 (en) 2005-08-25 2007-03-01 Samsung Electro-Mechanics Co., Ltd. Nitride semiconductor light emitting device
US20070120201A1 (en) 2005-11-25 2007-05-31 Denso Corporation Semiconductor device having super junction MOS transistor and method for manufacturing the same
US20070145414A1 (en) 2005-12-27 2007-06-28 Richard Francis Ultrafast recovery diode
JP2007184434A (en) 2006-01-10 2007-07-19 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof
US8178920B2 (en) * 2006-01-17 2012-05-15 Fuji Electric Co., Ltd. Semiconductor device and method of forming the same
US20100219417A1 (en) 2006-02-07 2010-09-02 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing same
US20090173949A1 (en) 2006-03-02 2009-07-09 National Institute Of Adv. Industrial Sci. & Tech. Silicon carbide mos field effect transistor with built-in schottky diode and method for manufacturing such transistor
US20070235745A1 (en) 2006-04-11 2007-10-11 Nissan Motor Co., Ltd. Semiconductor device and manufacturing method thereof
US20080012026A1 (en) 2006-07-10 2008-01-17 Fuji Electric Holdings Co., Ltd. Trench mos type silicon carbide semiconductor device and method for manufacturing the same
US20080050876A1 (en) 2006-08-23 2008-02-28 General Electric Company Method for fabricating silicon carbide vertical mosfet devices
US20090278197A1 (en) 2006-08-24 2009-11-12 Rohm Co., Ltd Mis field effect transistor and method for manufacturing the same
US20100013007A1 (en) 2006-12-07 2010-01-21 Nobuki Miyakoshi Semiconductor device and method for manufacturing the same
US20080142811A1 (en) * 2006-12-13 2008-06-19 General Electric Company MOSFET devices and methods of fabrication
US20080206941A1 (en) 2007-02-23 2008-08-28 Denso Corporation Method for manufacturing sic semiconductor device
US20080230787A1 (en) 2007-03-20 2008-09-25 Denso Corporation Silicon carbide semiconductor device, and method of manufacturing the same
US20080308838A1 (en) 2007-06-13 2008-12-18 Mcnutt Ty R Power switching transistors
US20100176443A1 (en) 2007-06-15 2010-07-15 Rohm Co., Ltd. Semiconductor Device
US20090283798A1 (en) 2007-06-20 2009-11-19 Denso Corporation Semiconductor device and manufacturing method thereof
US20090057757A1 (en) 2007-08-31 2009-03-05 Kabushiki Kaisha Toshiba Trench gate semiconductor device and method of manufacturing the same
US20090072242A1 (en) 2007-09-18 2009-03-19 Cree, Inc. Insulated Gate Bipolar Conduction Transistors (IBCTS) and Related Methods of Fabrication
US20090078971A1 (en) 2007-09-20 2009-03-26 Infineon Technologies Austria Ag Semiconductor device with structured current spread region and method
US20090079001A1 (en) 2007-09-21 2009-03-26 Ali Salih Multi-channel esd device and method therefor
US20090090920A1 (en) 2007-10-05 2009-04-09 Denso Corporation Silicon carbide semiconductor device
US20100078710A1 (en) 2007-10-18 2010-04-01 Infineon Technologies Austria Ag Semiconductor component with a drift zone and a drift control zone
US20110193057A1 (en) * 2007-11-30 2011-08-11 Osram Opto Semiconductors Gmbh LED Having Current Spreading Layer
US20090146154A1 (en) 2007-12-07 2009-06-11 Cree, Inc. Transistor with A-Face Conductive Channel and Trench Protecting Well Region
US20090179297A1 (en) 2008-01-16 2009-07-16 Northrop Grumman Systems Corporation Junction barrier schottky diode with highly-doped channel region and methods
US20090189228A1 (en) 2008-01-25 2009-07-30 Qingchun Zhang Semiconductor transistor with p type re-grown channel layer
US20090236612A1 (en) 2008-03-24 2009-09-24 Fuji Electric Device Technology Co., Ltd. Silicon carbide mos semiconductor device
US20090283776A1 (en) 2008-04-17 2009-11-19 Fuji Electric Device Technology Co., Ltd. Wide band gap semiconductor device and method for producing the same
US20100025693A1 (en) 2008-07-30 2010-02-04 Denso Corporation Wide band gap semiconductor device including junction field effect transistor
US20100073039A1 (en) 2008-09-24 2010-03-25 Oki Semiconductor Co., Ltd. H-Bridge circuit
US20100093116A1 (en) 2008-10-14 2010-04-15 General Electric Company Dimension profiling of sic devices
JP2012114104A (en) 2009-02-24 2012-06-14 Hitachi Ltd Storage insulation gate type field effect transistor
US20100270586A1 (en) 2009-04-28 2010-10-28 Fuji Electric Systems Co. Ltd. Wide band gap semiconductor device
US20120187419A1 (en) 2009-07-15 2012-07-26 Infineon Technologies Ag Production Method for a Unipolar Semiconductor Component and Semiconductor Device
US8283973B2 (en) 2009-08-19 2012-10-09 Panasonic Corporation Semiconductor element, semiconductor device, and electric power converter
US20110049564A1 (en) 2009-08-31 2011-03-03 Alpha & Omega Semiconductor, Inc. Integrated schottky diode in high voltage semiconductor device
US20110156810A1 (en) 2009-12-30 2011-06-30 Intersil Americas Inc. Integrated dmos and schottky
US20120313212A1 (en) 2010-02-23 2012-12-13 Fuji Electric Co., Ltd. Semiconductor device
US20110241068A1 (en) 2010-03-30 2011-10-06 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the semiconductor device
US8415671B2 (en) * 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
US20110254088A1 (en) 2010-04-20 2011-10-20 Maxpower Semiconductor Inc. Power MOSFET With Embedded Recessed Field Plate and Methods of Fabrication
US20120025874A1 (en) 2010-07-27 2012-02-02 Denso Corporation Semiconductor device having switching element and free wheel diode and method for controlling the same
US20120037955A1 (en) 2010-08-12 2012-02-16 Infineon Technologies Austria Ag Transistor Component with Reduced Short-Circuit Current
US20120088339A1 (en) * 2010-10-12 2012-04-12 Io Semiconductor, Inc. Vertical Semiconductor Device with Thinned Substrate
US20120236615A1 (en) 2010-10-29 2012-09-20 Makoto Kitabatake Converter
US20120280258A1 (en) * 2010-12-31 2012-11-08 Xiamen Sanan Optoelectronics Technology Co., Ltd. Nitride Light-Emitting Diode with a Current Spreading Layer
US20130313635A1 (en) 2011-02-02 2013-11-28 Rohm Co., Ltd. Semiconductor device
US20130306983A1 (en) 2011-02-02 2013-11-21 Rohm Co., Ltd. Semiconductor device and method for producing same
US8575692B2 (en) 2011-02-11 2013-11-05 Freescale Semiconductor, Inc. Near zero channel length field drift LDMOS
US20120256195A1 (en) 2011-04-06 2012-10-11 Rohm Co., Ltd. Semiconductor device
WO2012137914A1 (en) 2011-04-08 2012-10-11 独立行政法人産業技術総合研究所 Silicon carbide vertical field effect transistor
US20130026493A1 (en) 2011-05-16 2013-01-31 Cree, Inc. Sic devices with high blocking voltage terminated by a negative bevel
US20140070268A1 (en) * 2011-05-18 2014-03-13 Fuji Electric Co., Ltd. Semiconductor device and semiconductor device manufacturing method
US20120292742A1 (en) 2011-05-20 2012-11-22 Sumitomo Electric Industries, Ltd. Semiconductor device
US20120306009A1 (en) 2011-06-03 2012-12-06 Suku Kim Integration of superjunction mosfet and diode
US8686439B2 (en) 2011-06-27 2014-04-01 Panasonic Corporation Silicon carbide semiconductor element
WO2013014943A2 (en) 2011-07-27 2013-01-31 Kabushiki Kaisha Toyota Chuo Kenkyusho Diode, semiconductor device, and mosfet
US20140048847A1 (en) 2011-07-27 2014-02-20 Toyota Jidosha Kabushiki Kaisha Diode, semiconductor device, and mosfet
US20140203299A1 (en) 2011-07-28 2014-07-24 Rohm Co., Ltd. Semiconductor device
US20130105889A1 (en) 2011-10-31 2013-05-02 Denso Corporation Switching device and method for manufacturing the same
US20130153995A1 (en) 2011-12-14 2013-06-20 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2013149837A (en) 2012-01-20 2013-08-01 Mitsubishi Electric Corp Silicon carbide semiconductor device and method of manufacturing the same
US20150053920A1 (en) * 2012-06-19 2015-02-26 Xiamen Sanan Optoelectronics Technology Co., Ltd. LED with Current Spreading Layer and Fabrication Method
US20130341674A1 (en) 2012-06-21 2013-12-26 Infineon Technologies Ag Reverse Conducting IGBT
US20140021484A1 (en) 2012-07-19 2014-01-23 Infineon Technologies Ag Semiconductor Device
US20140027781A1 (en) 2012-07-26 2014-01-30 Cree, Inc. Monolithic bidirectional silicon carbide switching devices and methods of forming the same
US20140077311A1 (en) * 2012-09-16 2014-03-20 Sensor Electronic Technology, Inc. Lateral/Vertical Semiconductor Device
US20140117376A1 (en) 2012-10-30 2014-05-01 Hitachi Metals, Ltd. Nitride Semiconductor Element and Method of Manufacturing the Same
US20140252554A1 (en) 2013-03-05 2014-09-11 Silergy Semiconductor Technology (Hangzhou) Ltd Wafer structure and power device using the same
US10192960B2 (en) 2013-07-26 2019-01-29 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing same
US20150041886A1 (en) 2013-08-08 2015-02-12 Cree, Inc. Vertical power transistor device
US9331197B2 (en) 2013-08-08 2016-05-03 Cree, Inc. Vertical power transistor device
US9741842B2 (en) * 2013-08-08 2017-08-22 Cree, Inc. Vertical power transistor device
US20160211360A1 (en) 2013-08-08 2016-07-21 Cree, Inc. Vertical power transistor device
US20150084118A1 (en) 2013-09-20 2015-03-26 Cree, Inc. Semiconductor device including a power transistor device and bypass diode
US9318597B2 (en) 2013-09-20 2016-04-19 Cree, Inc. Layout configurations for integrating schottky contacts into a power transistor device
US20150084062A1 (en) 2013-09-20 2015-03-26 Cree, Inc. Monolithically integrated vertical power transistor and bypass diode
US20150084119A1 (en) 2013-09-20 2015-03-26 Cree, Inc. Layout configurations for integrating schottky contacts into a power transistor device
US20150084125A1 (en) 2013-09-20 2015-03-26 Cree, Inc. Monolithically integrated vertical power transistor and bypass diode
US20150084063A1 (en) 2013-09-20 2015-03-26 Cree, Inc. Semiconductor device with a current spreading layer

Non-Patent Citations (20)

* Cited by examiner, † Cited by third party
Title
Agarwal, A. et al., "A New Degradation Mechanism in High-Voltage SiC Power MOSFETs," IEEE Electron Device Letters, vol. 28, No. 7, Jul. 2007, pp. 587-589.
Author Unknown, "NextPowerS3 MOSFETs Offer Super-Fast Switching with Soft Recovery," PowerPulse.Net, Copyright: 2013, 3 pages, www.powerpulse.net/story.php?storyID=28455;s=091820131.
Author Unknown, "The Industry's First SiC Power MOSFET with Internal SiC SBD Significantly Reduces Power Loss in Inverters and Requires Fewer Components," ROHM Semiconductor Website-Press Releases, Jul. 11, 2012, 3 pages, http://www.rohm.com/web/global/news-detail?news-title=the-industry-s-first%E2%80%BB-sic-power-mosfet-with-internal-sic-sbd&defaultGroupId=false.
Author Unknown, "The Industry's First SiC Power MOSFET with Internal SiC SBD Significantly Reduces Power Loss in Inverters and Requires Fewer Components," ROHM Semiconductor Website—Press Releases, Jul. 11, 2012, 3 pages, http://www.rohm.com/web/global/news-detail?news-title=the-industry-s-first%E2%80%BB-sic-power-mosfet-with-internal-sic-sbd&defaultGroupId=false.
Baliga, B. Jayant, "Advanced Power MOSFET Concepts," 2010, Springer Science + Business Media, LLC, Chapters 2, 3, and 8, pp. 23-117, 399-476.
Baliga, B. Jayant, "Advanced Power Rectifier Concepts," First Edition, 2009, Springer Science + Business Media, LLC, pp. 29 and 72.
Baliga, B. Jayant, "Chapter 8: Integral Diode," Advanced Power MOSFET Concepts, Copyright: 2010, pp. 399-476, Springer Science+Business Media, LLC, London, England.
Baliga, B. Jayant, "Fundamentals of Power Semiconductor Devices," Second Edition, 2008 Springer US, p. 168.
Bhatnagar, M. et al., "Effect of Surface Inhomogeneities on the Electrical Characteristics of SiC Schottky Contacts," IEEE Trans. Electron Devices, vol. 43, No. 1, Jan. 1996, pp. 150-156.
Decision of Allowance for Taiwanese Patent Application No. 103127134, mailed Feb. 26, 2016, 10 pages.
International Preliminary Report on Patentability for PCT/US2014/049941, mailed Feb. 18, 2016, 8 pages.
International Search Report and Written Opinion for PCT/US2014/049941, mailed Oct. 22, 2014, 12 pages.
Jang, T. et al., "Electrical Characteristics of Tantalum and Tantalum Carbide Schottky Diodes on n- and p-type Silicon Carbide as a Function of Temperature," Presented at the High Temperature Electronics Conference, Jun. 14-18, 1998, Albuquerque, NM, IEEE, pp. 280-286.
Office Action and Search Report for Taiwanese Patent Application No. 103127134, mailed Oct. 22, 2015, 15 pages.
Sheng, K. et al., "A Vertical SiC JFET with Monolithically Integrated JBS Diode," 21st International Symposium on Power Semiconductor Devices & IC's (ISPSD), Jun. 14-18, 2009, IEEE, pp. 255-258.
Sui, Y., et al., "On-State Characteristics of SiC power UMOSFETs on 115-μm drift Layers," Electron Device Letters, vol. 26, Issue 4, Apr. 2005, IEEE, pp. 255-257.
Tsuji et. al. "On-stae Characteristics of SiC Power UMOSFETs on 115-micrometer Drift Layers" Apr. 2005, IEEE Electron Device Letters vol. 26, No. 4. *
Wang, S.R. et al., "Double-Self-Aligned Short-Channel Power DMOSFETs in 4H-SiC," Device Research Conference, Jun. 22-24, 2009, University Park, PA, IEEE, pp. 277-278.
Wang, S.R. et al., "Double-Self-Aligned Short-Channel Power DMOSFETs in 4H—SiC," Device Research Conference, Jun. 22-24, 2009, University Park, PA, IEEE, pp. 277-278.
Zhu Lin et al., "Analytical Modeling of High-Voltage 4H-SiC Junction Barrier Schottky (JBS) Rectifiers," IEEE Transactions on Electron Devices, vol. 55, Issue 8, Aug. 8, 2008, IEEE, pp. 1857-1863.

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