Nothing Special   »   [go: up one dir, main page]

US8492263B2 - Protected solder ball joints in wafer level chip-scale packaging - Google Patents

Protected solder ball joints in wafer level chip-scale packaging Download PDF

Info

Publication number
US8492263B2
US8492263B2 US11/941,429 US94142907A US8492263B2 US 8492263 B2 US8492263 B2 US 8492263B2 US 94142907 A US94142907 A US 94142907A US 8492263 B2 US8492263 B2 US 8492263B2
Authority
US
United States
Prior art keywords
layer
buffer layer
electrodes
solder ball
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US11/941,429
Other versions
US20090130840A1 (en
Inventor
Chung Yu Wang
Chien-Hsiun Lee
Pei-Haw Tsao
Kuo-Chin Chang
Chung-Yi Lin
Bill Kiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US11/941,429 priority Critical patent/US8492263B2/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, KUO-CHIN, KIANG, BILL, LIN, CHUNG-YI, LEE, CHIEN-HSIUN, TSAO, PEI-HAW, WANG, CHUNG YU
Priority to TW97108282A priority patent/TWI453840B/en
Priority to CNA2008100863034A priority patent/CN101436559A/en
Publication of US20090130840A1 publication Critical patent/US20090130840A1/en
Priority to US13/946,187 priority patent/US9136211B2/en
Application granted granted Critical
Publication of US8492263B2 publication Critical patent/US8492263B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H01L2224/02351—Shape of the redistribution layers comprising interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13027—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being offset with respect to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates generally to wafer level chip scale packaging (WLCSP), and more particularly to enhancing the reliability of solder ball joints in WLCSP.
  • WLCSP wafer level chip scale packaging
  • Chip-scale or chip-size packaging (CSP) and BGA are just some of the solutions that enable dense electrode arrangement without greatly increasing the package size.
  • CSP provides for wafer packaging on a chip-size scale.
  • CSP typically results in packages within 1.2 times the die size, which greatly reduces the potential size of devices made with the CSP material.
  • WLCSP wafer-level CSP
  • One disadvantage of current WLCSP technology is the formation of cracks between the solder ball and the electrode post.
  • the solder ball or bump is typically placed onto the bump electrode or post directly, relying on the soldered joint for structural integrity.
  • the different layers making up the WLCSP device typically have different coefficient of thermal expansion (CTE).
  • CTE coefficient of thermal expansion
  • the solder ball is typically located above the layers of the underlying wafer. This exposure makes the solder ball more susceptible to physical impact, and places the more vulnerable joint in an exposed position as well.
  • FIG. 1 is a cross-section of a typical, single solder ball of WLCSP feature 10 .
  • WLCSP feature 10 in formed directly on die 100 .
  • Copper pad 102 is formed on die 100 .
  • Copper pad 102 acts as a contact and bonding pad for solder ball 101 .
  • IMC intermetallic compounds
  • cracks such as crack 104
  • IMC layer 103 is located above the top surface of die 100 , thus, exposing this area to greater direct physical impact.
  • a small crack that starts along one side of solder ball 101 , such as crack 104 may easily propagate across the length of the straight solder joint.
  • This graduated CTE helps alleviate the stresses that would be cause by sharply different CTE.
  • the multiple layers of the sealing film still usually exhibit a weak sheer strength and do not reduce the propagation of any cracks that may form in the IMC layer, thus, reducing the overall reliability of the joint.
  • the second embodiment provides for the solder ball to be placed directly onto the die bonding pad or directly onto a redistribution layer. An insulating layer is then used to encapsulate the solder ball leaving a portion exposed for contact. While this embodiment improves the ball joint strength, placing the solder ball directly onto the die contact pads is a complex design process. The level of customization that would occur between the wafer fabrication process and the subsequent packaging process would greatly increase the costs of CSP features. Moreover, the configurations of interconnect contacts would also be limited to the die contact pad configuration.
  • a method for manufacturing a semiconductor device includes forming one or more electrode posts on a first surface of a semiconductor substrate.
  • Each of the electrode posts is made up of an array of two or more columns electrically connected to a wiring layer of the semiconductor substrate.
  • a buffer layer which encapsulates the array, is deposited over the first surface. Material from the electrode posts is removed so that the top surface of the multi-column electrode posts is exposed at a depth below the top of the buffer layer.
  • a conductive capping layer is then deposited over the top surface of the multi-column electrode posts, where the conductive capping layer also lies below the top of the buffer layer.
  • a solder ball is then placed onto each of the conductive capping layers, wherein a solder joint between the solder ball and the conductive capping layer resides below the top of the buffer layer.
  • a semiconductor device is made up of a substrate, a buffer layer on a surface of the substrate, and one or more electrodes embedded within the buffer layer.
  • the electrodes have a plating layer between themselves and the buffer layer, where a top surface of the electrodes lies below an exterior surface of the buffer layer.
  • a method for manufacturing a semiconductor device includes forming a plurality of electrodes on a first surface of a semiconductor substrate, where the electrodes protrude from the first surface.
  • the electrodes are plated with a plating material and covered with a deposited buffer layer through which the plated electrodes extend. Parts of the buffer layer are selectively etched such that a top surface of the electrodes is exposed at a depth below a top of the buffer layer.
  • a solder ball is placed onto the each of the electrodes, such that a joint between the solder ball and the each of the electrodes lies below the top of the buffer layer, and the solder ball is electrically connected to a wiring layer of the semiconductor substrate through the plating material and the electrodes.
  • a semiconductor device in accordance with another preferred embodiment of the present invention, includes a substrate, one or more electrodes protruding from the surface of the substrate through a buffer layer also on the surface of the substrate.
  • the electrodes are each made up of a plurality of columns, wherein a top surface of the multi-column electrodes lies below a top of the buffer layer.
  • Each of the multi-column electrodes is also covered on an external surface by a plating layer.
  • An advantage of a preferred embodiment of the present invention is an increased strength and reliability of the solder ball joint. Because the joint is located below the buffer layer, it is protected from direct outside contact.
  • a further advantage of a preferred embodiment of the present invention is the protection of copper electrodes.
  • the capping layer protects the copper from oxidizing.
  • An additional advantage of a preferred embodiment of the present invention configured with multi-column electrodes is an increased strength and reliability of the solder joint.
  • the multiple columns provide a barrier for crack propagation and also supply a redundancy in which the device would remain operable even if a first few of the columns cracked.
  • Another advantage of a preferred embodiment of the present invention that uses nickel as either a plating material or for the electrodes is the decreased IMC that forms because of the chemical interaction that occurs between nickel and solder. Moreover, because nickel is softer than copper, the electrodes/posts may deflect a greater amount without cracking than copper.
  • FIG. 1 is a cross-sectional view of a typical, single solder ball of a WLCSP feature
  • FIG. 2 is a cross-sectional view of a WLCSP feature configured according to one embodiment of the present invention
  • FIGS. 3A-3E are cross-sectional views of an early manufacturing stage of a WLCSP feature configured according to one embodiment of the present invention.
  • FIGS. 4A-4E are cross-sectional views of a semiconductor wafer during various stages of a process of forming a WLCSP feature configured according to one embodiment of the present invention
  • FIGS. 5A-5F are cross-sectional views of a semiconductor wafer during various stages of a process of forming a WLCSP feature configured according to one embodiment of the present invention
  • FIG. 6 is a flowchart illustrating example steps executed to implement one embodiment of the present invention.
  • FIG. 7 is a flowchart illustrating example steps executed to implement one embodiment of the present invention.
  • FIG. 8 is a flowchart illustrating example steps executed to implement one embodiment of the present invention.
  • Wafer 200 includes electrode post 201 formed thereon.
  • Insulating layer 202 is formed on top of wafer 200 and surrounds electrode post 201 .
  • electrode post 201 was flush at the top with the top of insulating layer 202 .
  • Electrode post 201 is etched back below the level of insulating layer 202 . In a preferred embodiment, no extra photoresist layer is used during the etching process because the material for insulating layer 202 is selected, such that etching of electrode post 201 may occur without affecting insulating layer 202 .
  • Capping layer 203 is deposited onto electrode post 201 which protects the material of electrode post 201 from oxidizing.
  • electrode post 201 is made of copper.
  • Capping layer 203 thus, prevents copper electrode post 201 from oxidizing.
  • Capping layer 203 may be deposited using any number of different methods, including electroless plating, and the like.
  • Solder ball 204 is then welded, soldered, or printed onto wafer 200 . The result of the welding places the joint on top of capping layer 203 , which is below the top surface of insulating layer 202 . Therefore, solder ball 204 is located partially below and partially above insulating layer 202 .
  • IMC layer 205 forms at the juncture between solder ball 204 and capping layer 203 , such that it is protected from direct physical contact by insulating layer 202 .
  • wafer 200 By configuring wafer 200 to receive a portion of solder ball 204 above and below insulating layer 202 , placing the solder joint below the top surface of insulating layer 202 , and protecting electrode post 201 from oxidation by capping layer 205 , the solder joint becomes more reliable and exhibits greater sheer and general strength.
  • FIG. 3A is a cross-sectional view of an early manufacturing stage of WLCSP feature 30 configured according to one embodiment of the present invention.
  • Die 300 includes passivation layer 302 and polymer insulation layer 303 .
  • Wiring layer 301 at the top of die 300 , is connected to a circuit layer (not shown) within die 300 .
  • Re-distribution layer (RDL) 304 is deposited on the top of polymer insulation layer 303 of die 300 .
  • RDL 304 extends the electrical connectivity to wiring layer 301 .
  • polymer insulation layer 303 may comprise various insulating materials, such as polyimide or other such polymer insulator.
  • the descriptions provided in FIGS. 3A-3E are not intended to limit the present invention to any particular material for providing such an insulation layer.
  • construction of an inventive WLCSP feature may not include an insulation layer, such as polymer insulation layer 303 .
  • FIG. 3B is a cross-sectional view of another manufacturing stage of WLCSP feature 30 configured according to one embodiment of the present invention.
  • Electrode post 305 is deposited onto die 300 . It is physically in contact with RDL 304 , which creates an electrical connection with wiring layer 301 . Therefore, contact with electrode post 305 may provide electrical connection with the circuit layer in die 300 .
  • the material for RDL 304 may be selected from various beneficial conducting materials, such as copper, gold, aluminum, tin, or any beneficial combination or alloy of conducting materials.
  • FIG. 3C is a cross-sectional view of another manufacturing stage of WLCSP feature 30 configured according to one embodiment of the present invention.
  • Buffer layer 306 is deposited on top of die 300 to add protection to both die 300 and electrode post 305 .
  • the material selected for buffer layer 306 may be selected based in part on the material's CTE in order to reduce the stress exhibited on the WLCSP packaging because of the varying CTE in the different layers.
  • Example materials for buffer layer 307 may include epoxy, polyimide, or the like.
  • Another selection criteria, for the material of buffer layer 307 in a preferred embodiment of the present invention may also be the level of resistance that the material exhibits to etchants that may be used to etch the material of electrode post 305 .
  • FIG. 3D is a cross-sectional view of another manufacturing step for WLCSP feature 30 configured according to one embodiment of the present invention.
  • Electrode post 305 is etched back below the top of buffer layer 307 using an etchant that does not affect buffer layer 307 . In this manner, electrode post 305 may be etched back without using another photoresist layer.
  • capping layer 307 is deposited onto electrode post 305 , such that the exposed surface of electrode post 305 is covered, but that the top of capping layer 307 is still below the top of buffer layer 307 . By covering the exposed surface of electrode post 305 , capping layer 307 prevents electrode post 305 from oxidizing.
  • Capping layer 307 is selected from a conductive material so that an electrical connection continues between capping layer 307 and wiring layer 301 .
  • capping layer 307 may be selected from materials, such as nickel, tin, or other similar materials or alloys.
  • FIG. 3E is a cross-sectional view of WLCSP feature 30 .
  • solder ball 308 is printed or soldered onto electrode post 305 /capping layer 307 .
  • the joint that forms between solder ball 308 and capping layer 307 is, therefore, located at a level beneath the top of buffer layer 306 .
  • buffer layer 306 provides a protective barrier to the joint.
  • the IMC layer that forms at the solder joint is also protected by buffer layer 306 .
  • the resulting WLCSP feature 30 exhibits a stronger, more reliable solder joint.
  • FIGS. 4A-4E are cross-sectional views of semiconductor wafer 40 during various stages of a process of forming a WLCSP feature configured according to one embodiment of the present invention.
  • Semiconductor wafer 40 comprises substrate 400 , die contact 401 , passivation layer 402 , insulation layer 403 , and RDL 404 .
  • RDL 404 provides a connection link to die contact 401 .
  • packaging design and development for integrated circuits may be streamlined because the position of the packaging features is not limited to the positioning of the die contact pads, such as die contact 401 .
  • Multi-column electrode post 405 is formed on RDL 404 providing electrical contact with die contact 401 , as shown in FIG. 4B .
  • Multi-column electrode post 405 may be formed by any various means or methods for forming metal layers. For example, a photoresist layer or laminate may be placed on top of semiconductor wafer 40 with a recess for each of multi-column electrode post 405 etched therein. The recesses would then be filled with some kind of conducting material, such as copper, nickel, aluminum, tungsten, or the like.
  • each column of multi-column electrode post 405 may preferably have an out diameter at some size between approximately 10 ⁇ m and 20 ⁇ m with a space between successive columns preferably measuring between approximately 10 ⁇ m and 20 ⁇ m.
  • the encapsulant material i.e., the stress buffer layer, is then deposited over the feature within these preferred dimensions.
  • FIG. 4C shows buffer layer 406 deposited on top of semiconductor wafer 40 .
  • Buffer layer 406 encapsulates each of the columns of multi-column electrode post 405 . This encasement provides strength to multi-column electrode post 405 .
  • Buffer layer 406 is etched back to expose multi-column electrode post 405 onto which low-reactive layer 407 is deposited, as shown in FIG. 4D .
  • a low-reactive layer 407 preferably comprises a material that enhances bonding with solder ball or bumps and also has a lower growth rate of IMC defects. Examples of such low-reactive material are nickel, tin, and the like.
  • low-reactive layer 407 is deposited onto multi-column electrode posts 405 , solder ball 408 is printed or placed onto semiconductor wafer 40 , as shown in FIG. 4E .
  • Low-reactive layer 407 is placed below the surface of buffer layer 406 , such that the ball joint between solder ball 408 and low-reactive layer 407 is below the surface of buffer layer 406 . This provides some protection against sheer forces exerted on solder ball 408 , while the buffer layer 406 is selected to have a specific coefficient of thermal expansion (CTE) that reduces the thermal expansion stresses on the ball joint, as well.
  • CTE coefficient of thermal expansion
  • the multicolumn electrode embodiment illustrated in FIGS. 4A-4E provides an improved performance in package stress resistance over single-column electrode embodiments.
  • the joint with the solder ball is broken up by each of the multiple columns, cracks will not easily propagate across the entire joint. As a crack propagates along a fracture line, it will typically run into one of the columns instead of propagating along the entire length of the joint.
  • the stress buffer layer embedded between the columns enhances the already improved crack resistance due to the metal-buffer composite structure. Materials such as organic stress buffers are beneficial for increasing the crack resistance with the resulting metal-organic composite structure built into the multi-column electrode post structure.
  • FIGS. 5A-5F are cross-sectional views of semiconductor wafer 50 during various stages of a process of forming a WLCSP feature configured according to one embodiment of the present invention.
  • FIG. 5A illustrates semiconductor wafer 50 comprising integrated circuit (IC) layer 500 , contact pad 501 , metal plating seed layer 502 , RDL 503 , and photoresist 504 .
  • Recess 506 has been etched into photoresist 504 and is lined with plating metal layer 505 .
  • Conducting post 507 is then formed in recess 506 , as shown in FIG. 5B .
  • plating metal layer 505 and conducting post 507 are preferably created from different conducting materials.
  • plating metal layer 505 may comprise nickel, tin, copper, or the like, while conducting post 507 may comprise copper, solder, tin, nickel or the like.
  • conducting post 507 may comprise copper, solder, tin, nickel or the like.
  • the solder/copper IMC growth will be reduced.
  • conducting post 507 comprises solder, the combined post structure is much more compliant than if rigid copper were used. Thus, the post structure may deform more when the package is under thermal stress, which reduces the stress level at the ball joint.
  • FIG. 5C photoresist 504 has been removed and metal plating seed layer 502 is etched back to coincide with RDL 503 .
  • Buffer layer 508 is then deposited onto semiconductor wafer 50 , as shown in FIG. 5D , encapsulating the packaging elements, including plating metal layer 505 and conducting post 507 .
  • the top surface of buffer layer 508 is polished down with conducting post 507 further etched below the surface of buffer layer 508 , as shown in FIG. 5E .
  • Solder ball 509 is then printed or placed onto semiconductor wafer 50 , as shown in FIG. 5F , such that the ball joint is positioned below the surface of buffer layer 508 .
  • the ball joint will experience less sheer stress.
  • FIG. 6 is a flowchart illustrating example steps executed to implement one embodiment of the present invention.
  • one or more electrode posts are formed on a first surface of a semiconductor substrate, where each of the electrode posts is made up of an array of two or more columns electrically connected to a wiring layer of the semiconductor substrate.
  • a buffer layer is deposited, in step 601 , over the first surface encapsulating the array of columns of the electrode posts. Material is removed from the buffer layer, in step 602 , resulting in the electrode posts being exposed at a depth below the top of the buffer layer.
  • a conductive capping layer is deposited over the top surface of the exposed multi-column electrode posts, where the conductive capping layer is also below the top of the buffer layer.
  • a solder ball is placed onto each of the conductive capping layers, in step 604 , where a solder joint between the solder ball and the conductive capping layer resides below the top of the buffer layer.
  • FIG. 7 is a flowchart illustrating example steps executed to implement one embodiment of the present invention.
  • a plurality of electrodes is formed on a first surface of a semiconductor substrate, where the electrodes protrude from the first surface.
  • the electrodes are plated with a plating material, in step 701 .
  • a buffer layer is deposited onto the first surface, in step 702 , through which the electrodes extend.
  • the buffer layer is selectively etched, such that a top surface of the electrodes is exposed at a depth below the top of the buffer layer.
  • step 703 a solder ball is placed onto the each of the electrodes, where the joint between the solder ball and each of the plurality of electrodes lies below the top of the buffer layer, and where the solder ball is electrically connected to a wiring layer of the semiconductor substrate through the plating material and the plurality of electrodes.
  • FIG. 8 is a flowchart illustrating example steps executed to implement one embodiment of the present invention.
  • a plurality of electrodes is formed on a first surface of a semiconductor substrate, where each of the electrode posts is made up of an array of two or more columns.
  • the multi-column electrodes are plated with a plating material, in step 801 .
  • a buffer layer is deposited onto the first surface, in step 802 , in which the multi-column electrodes extending through the buffer layer.
  • the buffer layer is selectively etched, in step 803 , such that a top surface of the multi-column electrodes is exposed at a depth below the top of the buffer layer.
  • a solder ball is placed onto the each of the multi-column electrodes, in step 804 , where a joint between the solder ball and the each of the multi-column electrodes lies below the top of the buffer layer, and where the solder ball is electrically connected to a wiring layer of the semiconductor substrate through the plating material and the multi-column electrodes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.

Description

TECHNICAL FIELD
The present invention relates generally to wafer level chip scale packaging (WLCSP), and more particularly to enhancing the reliability of solder ball joints in WLCSP.
BACKGROUND
The past few decades have seen many shifts in electronics and semiconductor packaging that have impacted the entire semiconductor industry. The introduction of surface-mount technology (SMT) and ball grid array (BGA) packages were generally important steps for high-throughput assembly of a wide variety of integrated circuit (IC) devices, while, at the same time, allowing reduction of the pad pitch on the printed circuit board. Conventionally packaged ICs have a structure basically interconnected by fine gold wire between metal pads on the die and electrodes spreading out of molded resin packages. Dual inline package (DIP) and quad flat package (QFP) are fundamental structures of current IC packaging. However, increased pin count peripherally designed and arranged around the package typically results in too short of a pitch of lead wire, yielding limitations in board mounting of the packaged chip.
Chip-scale or chip-size packaging (CSP) and BGA are just some of the solutions that enable dense electrode arrangement without greatly increasing the package size. CSP provides for wafer packaging on a chip-size scale. CSP typically results in packages within 1.2 times the die size, which greatly reduces the potential size of devices made with the CSP material. Although, these advances have allowed for miniaturization in electronic devices, the ever-demanding trend toward even smaller, lighter, and thinner consumer products have prompted even further attempts at package miniaturization.
To fulfill market demands toward increased miniaturization and functionality, wafer-level CSP (WLCSP) has been introduced in recent years for generally increasing density, performance, and cost-effectiveness, while decreasing the weight and size of the devices in the electronic packaging industry. In WLCSP, the packaging is typically generated directly on the die with contacts provided by BGA and bump electrodes. Recent advanced electronic devices, such as mobile phones, mobile computers, camcorders, personal digital assistants (PDAs), and the like, utilize compact, light, thin, and very densely packaged ICs. Using WLCSP for packaging smaller die size devices with lower numbers of pins, corresponding to larger number of chips on one wafer, is, therefore, usually advantageous and cost-effective.
One disadvantage of current WLCSP technology is the formation of cracks between the solder ball and the electrode post. The solder ball or bump is typically placed onto the bump electrode or post directly, relying on the soldered joint for structural integrity. The different layers making up the WLCSP device typically have different coefficient of thermal expansion (CTE). As a result, a relatively large stress derived from this difference is exhibited on the joint between the post and the bump electrode, which often causes cracks to form in the bonding area between the bump electrode/post and the solder ball or bump. Additionally, the solder ball is typically located above the layers of the underlying wafer. This exposure makes the solder ball more susceptible to physical impact, and places the more vulnerable joint in an exposed position as well.
FIG. 1 is a cross-section of a typical, single solder ball of WLCSP feature 10. WLCSP feature 10 in formed directly on die 100. Copper pad 102 is formed on die 100. Copper pad 102 acts as a contact and bonding pad for solder ball 101. During the soldering process, intermetallic compounds (IMC) are naturally formed in a layer, i.e., IMC formation layer 103, at the joint between solder ball 101 and copper pad 102. While existence of IMC formation layer 103 generally signifies a good weld between the solder and the substrate, it is usually the most brittle part of the weld. Because the weld joint is so small in WLCSP, cracks, such as crack 104, may form more easily under the stresses experienced at the joint, and such cracks, because of the size of the overall package, may be more damaging. Furthermore, IMC layer 103 is located above the top surface of die 100, thus, exposing this area to greater direct physical impact. A small crack that starts along one side of solder ball 101, such as crack 104, may easily propagate across the length of the straight solder joint.
One method that has been suggested to diminish this stress cracking is described in U.S. Pat. No. 6,600,234, to Kuwabara, et al., entitled, “MOUNTING STRUCTURE HAVING COLUMNAR ELECTRODES AND A SEALING FILM.” This method describes forming a sealing film using multiple layers where a portion of the bump electrode protruding from the sealing film. The protruding electrode assists in absorbing part of the stress caused by the difference in CTE. The multiple layers of the sealing film are also selected to have graduated CTE, such that the CTE of the film near the substrate is close to the CTE of the substrate, while the CTE of the film near the circuit substrate is close to the CTE of the circuit substrate. This graduated CTE helps alleviate the stresses that would be cause by sharply different CTE. However, the multiple layers of the sealing film still usually exhibit a weak sheer strength and do not reduce the propagation of any cracks that may form in the IMC layer, thus, reducing the overall reliability of the joint.
An additional method suggested to improve CSP is described in U.S. Pat. No. 6,717,245, to Kinsman, et al., entitled, “CHIP SCALE PACKAGES PERFORMED BY WAFER LEVEL PROCESSING.” This method provides for a first bumped layer that is completely encapsulated in an epoxy or other similar material. This encapsulation layer is then polished back to expose the tops of the encased bumps. Regulation solder balls are then printed or placed onto the exposed portions of the first bumped layer. By isolating the solder balls from the circuit board through the first encapsulated layer of bumps, the stress caused by thermal expansion is reduced. However, the ball joints still are subject to cracks that form along the IMC layer, thus again, reducing the overall reliability of the joint.
An additional method suggested to improve CSP is described in U.S. Pat. No. 6,906,418, to Hiatt, et al., entitled, “SEMICONDUCTOR COMPONENT HAVING ENCAPSULATED, BONDED, INTERCONNECT CONTACTS.” This method provides two different embodiments for CSP. The first embodiment extends the tip of an interconnect contact from the die pad through an insulating layer. After a metallization layer is deposited on the tip of the interconnect contact, solder balls are placed onto each of the extended tips. The metallization layer is selected to improve the bonding between the metallization material and the solder ball. However, the ball joint is still subject to considerable sheer forces because the ball joint is at or above the surface of the insulating layer. The second embodiment provides for the solder ball to be placed directly onto the die bonding pad or directly onto a redistribution layer. An insulating layer is then used to encapsulate the solder ball leaving a portion exposed for contact. While this embodiment improves the ball joint strength, placing the solder ball directly onto the die contact pads is a complex design process. The level of customization that would occur between the wafer fabrication process and the subsequent packaging process would greatly increase the costs of CSP features. Moreover, the configurations of interconnect contacts would also be limited to the die contact pad configuration.
SUMMARY OF THE INVENTION
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which locate the solder ball joint with the electrode posts below the surface level of the encapsulating buffer layer. Locating the joint below the surface level of the buffer layer protects the joint from external sheer forces. Additional improvements are made in selected embodiments by forming each of the electrode posts with multiple columns. Still other embodiments apply a plating layer around the electrode posts (either single or multiple column posts). The plating material may be selected from low-reactive material that reduces the amount of IMC defects that may be formed at the ball joint. Further still, the entire set of posts may be made from materials such as nickel, tin, solder, and the like, thus, decreasing defects that may be caused by deflection of the stiffer copper posts.
In accordance with a preferred embodiment of the present invention, a method for manufacturing a semiconductor device includes forming one or more electrode posts on a first surface of a semiconductor substrate. Each of the electrode posts is made up of an array of two or more columns electrically connected to a wiring layer of the semiconductor substrate. A buffer layer, which encapsulates the array, is deposited over the first surface. Material from the electrode posts is removed so that the top surface of the multi-column electrode posts is exposed at a depth below the top of the buffer layer. A conductive capping layer is then deposited over the top surface of the multi-column electrode posts, where the conductive capping layer also lies below the top of the buffer layer. A solder ball is then placed onto each of the conductive capping layers, wherein a solder joint between the solder ball and the conductive capping layer resides below the top of the buffer layer.
In accordance with another preferred embodiment of the present invention, a semiconductor device is made up of a substrate, a buffer layer on a surface of the substrate, and one or more electrodes embedded within the buffer layer. The electrodes have a plating layer between themselves and the buffer layer, where a top surface of the electrodes lies below an exterior surface of the buffer layer. There is also a solder ball on each of the electrodes, where a solder joint between the solder ball and the conductive capping layer lies below the exterior surface of the buffer layer.
In accordance with another preferred embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a plurality of electrodes on a first surface of a semiconductor substrate, where the electrodes protrude from the first surface. The electrodes are plated with a plating material and covered with a deposited buffer layer through which the plated electrodes extend. Parts of the buffer layer are selectively etched such that a top surface of the electrodes is exposed at a depth below a top of the buffer layer. A solder ball is placed onto the each of the electrodes, such that a joint between the solder ball and the each of the electrodes lies below the top of the buffer layer, and the solder ball is electrically connected to a wiring layer of the semiconductor substrate through the plating material and the electrodes.
In accordance with another preferred embodiment of the present invention, a semiconductor device includes a substrate, one or more electrodes protruding from the surface of the substrate through a buffer layer also on the surface of the substrate. The electrodes are each made up of a plurality of columns, wherein a top surface of the multi-column electrodes lies below a top of the buffer layer. Each of the multi-column electrodes is also covered on an external surface by a plating layer. There are also solder balls on each of the multi-column electrodes, where the solder joint between the solder ball and the plating layer lies below the top of the buffer layer.
An advantage of a preferred embodiment of the present invention is an increased strength and reliability of the solder ball joint. Because the joint is located below the buffer layer, it is protected from direct outside contact.
A further advantage of a preferred embodiment of the present invention is the protection of copper electrodes. In embodiments where the electrode posts are formed using copper, the capping layer protects the copper from oxidizing.
An additional advantage of a preferred embodiment of the present invention configured with multi-column electrodes is an increased strength and reliability of the solder joint. The multiple columns provide a barrier for crack propagation and also supply a redundancy in which the device would remain operable even if a first few of the columns cracked.
Another advantage of a preferred embodiment of the present invention that uses nickel as either a plating material or for the electrodes is the decreased IMC that forms because of the chemical interaction that occurs between nickel and solder. Moreover, because nickel is softer than copper, the electrodes/posts may deflect a greater amount without cracking than copper.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a cross-sectional view of a typical, single solder ball of a WLCSP feature;
FIG. 2 is a cross-sectional view of a WLCSP feature configured according to one embodiment of the present invention;
FIGS. 3A-3E are cross-sectional views of an early manufacturing stage of a WLCSP feature configured according to one embodiment of the present invention;
FIGS. 4A-4E are cross-sectional views of a semiconductor wafer during various stages of a process of forming a WLCSP feature configured according to one embodiment of the present invention;
FIGS. 5A-5F are cross-sectional views of a semiconductor wafer during various stages of a process of forming a WLCSP feature configured according to one embodiment of the present invention;
FIG. 6 is a flowchart illustrating example steps executed to implement one embodiment of the present invention;
FIG. 7 is a flowchart illustrating example steps executed to implement one embodiment of the present invention; and
FIG. 8 is a flowchart illustrating example steps executed to implement one embodiment of the present invention.
 DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
With reference now to FIG. 2, there is shown a cross-sectional view of WLCSP feature 20 configured according to one embodiment of the present invention. Wafer 200 includes electrode post 201 formed thereon. Insulating layer 202 is formed on top of wafer 200 and surrounds electrode post 201. During the manufacturing process, electrode post 201 was flush at the top with the top of insulating layer 202. Electrode post 201 is etched back below the level of insulating layer 202. In a preferred embodiment, no extra photoresist layer is used during the etching process because the material for insulating layer 202 is selected, such that etching of electrode post 201 may occur without affecting insulating layer 202.
Capping layer 203 is deposited onto electrode post 201 which protects the material of electrode post 201 from oxidizing. In a preferred embodiment, electrode post 201 is made of copper. Capping layer 203, thus, prevents copper electrode post 201 from oxidizing. Capping layer 203 may be deposited using any number of different methods, including electroless plating, and the like. Solder ball 204 is then welded, soldered, or printed onto wafer 200. The result of the welding places the joint on top of capping layer 203, which is below the top surface of insulating layer 202. Therefore, solder ball 204 is located partially below and partially above insulating layer 202. Moreover, IMC layer 205 forms at the juncture between solder ball 204 and capping layer 203, such that it is protected from direct physical contact by insulating layer 202. By configuring wafer 200 to receive a portion of solder ball 204 above and below insulating layer 202, placing the solder joint below the top surface of insulating layer 202, and protecting electrode post 201 from oxidation by capping layer 205, the solder joint becomes more reliable and exhibits greater sheer and general strength.
FIG. 3A is a cross-sectional view of an early manufacturing stage of WLCSP feature 30 configured according to one embodiment of the present invention. Die 300 includes passivation layer 302 and polymer insulation layer 303. Wiring layer 301, at the top of die 300, is connected to a circuit layer (not shown) within die 300. Re-distribution layer (RDL) 304 is deposited on the top of polymer insulation layer 303 of die 300. RDL 304 extends the electrical connectivity to wiring layer 301.
It should be noted that polymer insulation layer 303 may comprise various insulating materials, such as polyimide or other such polymer insulator. The descriptions provided in FIGS. 3A-3E are not intended to limit the present invention to any particular material for providing such an insulation layer. In fact, in additional and/or alternative embodiments, construction of an inventive WLCSP feature may not include an insulation layer, such as polymer insulation layer 303.
FIG. 3B is a cross-sectional view of another manufacturing stage of WLCSP feature 30 configured according to one embodiment of the present invention. Electrode post 305 is deposited onto die 300. It is physically in contact with RDL 304, which creates an electrical connection with wiring layer 301. Therefore, contact with electrode post 305 may provide electrical connection with the circuit layer in die 300. The material for RDL 304 may be selected from various beneficial conducting materials, such as copper, gold, aluminum, tin, or any beneficial combination or alloy of conducting materials.
FIG. 3C is a cross-sectional view of another manufacturing stage of WLCSP feature 30 configured according to one embodiment of the present invention. Buffer layer 306 is deposited on top of die 300 to add protection to both die 300 and electrode post 305. In some embodiments, the material selected for buffer layer 306 may be selected based in part on the material's CTE in order to reduce the stress exhibited on the WLCSP packaging because of the varying CTE in the different layers. Example materials for buffer layer 307 may include epoxy, polyimide, or the like. Another selection criteria, for the material of buffer layer 307 in a preferred embodiment of the present invention, may also be the level of resistance that the material exhibits to etchants that may be used to etch the material of electrode post 305.
FIG. 3D is a cross-sectional view of another manufacturing step for WLCSP feature 30 configured according to one embodiment of the present invention. Electrode post 305 is etched back below the top of buffer layer 307 using an etchant that does not affect buffer layer 307. In this manner, electrode post 305 may be etched back without using another photoresist layer. After etching back electrode post 305, capping layer 307 is deposited onto electrode post 305, such that the exposed surface of electrode post 305 is covered, but that the top of capping layer 307 is still below the top of buffer layer 307. By covering the exposed surface of electrode post 305, capping layer 307 prevents electrode post 305 from oxidizing. Capping layer 307 is selected from a conductive material so that an electrical connection continues between capping layer 307 and wiring layer 301. For example, capping layer 307 may be selected from materials, such as nickel, tin, or other similar materials or alloys.
FIG. 3E is a cross-sectional view of WLCSP feature 30. After depositing capping layer 307 onto each of the electrode posts, such as electrode post 305, solder ball 308 is printed or soldered onto electrode post 305/capping layer 307. The joint that forms between solder ball 308 and capping layer 307 is, therefore, located at a level beneath the top of buffer layer 306. Thus, buffer layer 306 provides a protective barrier to the joint. Moreover, the IMC layer that forms at the solder joint is also protected by buffer layer 306. The resulting WLCSP feature 30 exhibits a stronger, more reliable solder joint.
FIGS. 4A-4E are cross-sectional views of semiconductor wafer 40 during various stages of a process of forming a WLCSP feature configured according to one embodiment of the present invention. Semiconductor wafer 40 comprises substrate 400, die contact 401, passivation layer 402, insulation layer 403, and RDL 404. RDL 404 provides a connection link to die contact 401. By using RDL 404, packaging design and development for integrated circuits may be streamlined because the position of the packaging features is not limited to the positioning of the die contact pads, such as die contact 401.
Multi-column electrode post 405 is formed on RDL 404 providing electrical contact with die contact 401, as shown in FIG. 4B. Multi-column electrode post 405 may be formed by any various means or methods for forming metal layers. For example, a photoresist layer or laminate may be placed on top of semiconductor wafer 40 with a recess for each of multi-column electrode post 405 etched therein. The recesses would then be filled with some kind of conducting material, such as copper, nickel, aluminum, tungsten, or the like.
In example implementation of the WLCSP feature illustrated in FIGS. 4A-4E, each column of multi-column electrode post 405 may preferably have an out diameter at some size between approximately 10 μm and 20 μm with a space between successive columns preferably measuring between approximately 10 μm and 20 μm. The encapsulant material, i.e., the stress buffer layer, is then deposited over the feature within these preferred dimensions.
FIG. 4C shows buffer layer 406 deposited on top of semiconductor wafer 40. Buffer layer 406 encapsulates each of the columns of multi-column electrode post 405. This encasement provides strength to multi-column electrode post 405. Buffer layer 406 is etched back to expose multi-column electrode post 405 onto which low-reactive layer 407 is deposited, as shown in FIG. 4D. A low-reactive layer 407 preferably comprises a material that enhances bonding with solder ball or bumps and also has a lower growth rate of IMC defects. Examples of such low-reactive material are nickel, tin, and the like.
Once low-reactive layer 407 is deposited onto multi-column electrode posts 405, solder ball 408 is printed or placed onto semiconductor wafer 40, as shown in FIG. 4E. Low-reactive layer 407 is placed below the surface of buffer layer 406, such that the ball joint between solder ball 408 and low-reactive layer 407 is below the surface of buffer layer 406. This provides some protection against sheer forces exerted on solder ball 408, while the buffer layer 406 is selected to have a specific coefficient of thermal expansion (CTE) that reduces the thermal expansion stresses on the ball joint, as well.
The multicolumn electrode embodiment illustrated in FIGS. 4A-4E provides an improved performance in package stress resistance over single-column electrode embodiments. First, because the joint with the solder ball is broken up by each of the multiple columns, cracks will not easily propagate across the entire joint. As a crack propagates along a fracture line, it will typically run into one of the columns instead of propagating along the entire length of the joint. Furthermore, the stress buffer layer embedded between the columns enhances the already improved crack resistance due to the metal-buffer composite structure. Materials such as organic stress buffers are beneficial for increasing the crack resistance with the resulting metal-organic composite structure built into the multi-column electrode post structure.
FIGS. 5A-5F are cross-sectional views of semiconductor wafer 50 during various stages of a process of forming a WLCSP feature configured according to one embodiment of the present invention. FIG. 5A illustrates semiconductor wafer 50 comprising integrated circuit (IC) layer 500, contact pad 501, metal plating seed layer 502, RDL 503, and photoresist 504. Recess 506 has been etched into photoresist 504 and is lined with plating metal layer 505. Conducting post 507 is then formed in recess 506, as shown in FIG. 5B.
It should be noted that plating metal layer 505 and conducting post 507 are preferably created from different conducting materials. For example, plating metal layer 505 may comprise nickel, tin, copper, or the like, while conducting post 507 may comprise copper, solder, tin, nickel or the like. When plating metal layer 505 comprises nickel, the solder/copper IMC growth will be reduced. When plating metal layer 505 comprises nickel and conducting post 507 comprises solder, the combined post structure is much more compliant than if rigid copper were used. Thus, the post structure may deform more when the package is under thermal stress, which reduces the stress level at the ball joint.
In FIG. 5C, photoresist 504 has been removed and metal plating seed layer 502 is etched back to coincide with RDL 503. Buffer layer 508 is then deposited onto semiconductor wafer 50, as shown in FIG. 5D, encapsulating the packaging elements, including plating metal layer 505 and conducting post 507. The top surface of buffer layer 508 is polished down with conducting post 507 further etched below the surface of buffer layer 508, as shown in FIG. 5E. Solder ball 509 is then printed or placed onto semiconductor wafer 50, as shown in FIG. 5F, such that the ball joint is positioned below the surface of buffer layer 508. By placing the ball joint below the surface, it is effectively positioned away from the higher stress location even with the surface of buffer layer 508. Thus, the ball joint will experience less sheer stress.
FIG. 6 is a flowchart illustrating example steps executed to implement one embodiment of the present invention. In step 600, one or more electrode posts are formed on a first surface of a semiconductor substrate, where each of the electrode posts is made up of an array of two or more columns electrically connected to a wiring layer of the semiconductor substrate. A buffer layer is deposited, in step 601, over the first surface encapsulating the array of columns of the electrode posts. Material is removed from the buffer layer, in step 602, resulting in the electrode posts being exposed at a depth below the top of the buffer layer. In step 603, a conductive capping layer is deposited over the top surface of the exposed multi-column electrode posts, where the conductive capping layer is also below the top of the buffer layer. A solder ball is placed onto each of the conductive capping layers, in step 604, where a solder joint between the solder ball and the conductive capping layer resides below the top of the buffer layer.
FIG. 7 is a flowchart illustrating example steps executed to implement one embodiment of the present invention. In step 700, a plurality of electrodes is formed on a first surface of a semiconductor substrate, where the electrodes protrude from the first surface. The electrodes are plated with a plating material, in step 701. A buffer layer is deposited onto the first surface, in step 702, through which the electrodes extend. In step 703, the buffer layer is selectively etched, such that a top surface of the electrodes is exposed at a depth below the top of the buffer layer. In step 703, a solder ball is placed onto the each of the electrodes, where the joint between the solder ball and each of the plurality of electrodes lies below the top of the buffer layer, and where the solder ball is electrically connected to a wiring layer of the semiconductor substrate through the plating material and the plurality of electrodes.
FIG. 8 is a flowchart illustrating example steps executed to implement one embodiment of the present invention. In step 800, a plurality of electrodes is formed on a first surface of a semiconductor substrate, where each of the electrode posts is made up of an array of two or more columns. The multi-column electrodes are plated with a plating material, in step 801. A buffer layer is deposited onto the first surface, in step 802, in which the multi-column electrodes extending through the buffer layer. The buffer layer is selectively etched, in step 803, such that a top surface of the multi-column electrodes is exposed at a depth below the top of the buffer layer. A solder ball is placed onto the each of the multi-column electrodes, in step 804, where a joint between the solder ball and the each of the multi-column electrodes lies below the top of the buffer layer, and where the solder ball is electrically connected to a wiring layer of the semiconductor substrate through the plating material and the multi-column electrodes.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that the materials, dimensions, and layers may be varied while remaining within the scope of the present invention.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (13)

What is claimed is:
1. A method for manufacturing a semiconductor device comprising:
forming one or more re-distribution layers (RDLs) on a first surface of a semiconductor wafer, wherein the one or more RDLs do not extend beyond the first surface of the semiconductor wafer;
forming one or more electrode posts on respective ones of the RDLs, wherein each of said one or more electrode posts comprises an array of two or more columns, said one or more electrode posts electrically connected to a wiring layer of said semiconductor substrate;
depositing a buffer layer over said first surface, said buffer layer encapsulating said array and being in physical contact with a conductive portion of at least one of said RDLs;
removing portions of said buffer layer, the removing portions of said buffer layer resulting in a top surface of said one or more electrode posts being at a depth below a top of remaining portions of said buffer layer;
depositing a conductive capping layer over said top surface and into the opening, wherein said conductive capping layer is below said top of said remaining portions of said buffer layer; and
placing a solder ball onto each of said conductive capping layers, wherein a solder joint between said solder ball and said conductive capping layer resides below said top of said remaining portions of said buffer layer, and wherein the solder ball remains outside of a region between the columns of the one or more electrode posts.
2. The method of claim 1 wherein said semiconductor substrate comprises:
a passivation layer deposited over a semiconductor substrate layer, wherein said top portion of said passivation layer comprises said first surface; and
a circuit layer in an active region of said semiconductor substrate layer, wherein said circuit layer is electrically connected to said wiring layer.
3. The method of claim 2 wherein said semiconductor substrate further comprises:
a polymer insulation layer deposited over said passivation layer, wherein a top side of said polymer insulation layer becomes said first surface of said semiconductor substrate.
4. The method of claim 3 wherein a material for said polymer insulation layer is selected based at least in part on the material's coefficient of thermal expansion (CTE).
5. The method of claim 3 wherein said polymer insulation layer is made from a material selected from the group consisting essentially of
epoxy; and
polyimide.
6. The method of claim 1 wherein said removing comprises:
etching said buffer layer.
7. The method of claim 1 wherein said depositing said conductive capping layer comprises:
depositing said conductive capping layer through electroless plating.
8. The method of claim 1 wherein said conductive capping layer is made from a material selected from a group consisting essentially of:
nickel; and
tin.
9. A method for manufacturing a semiconductor device comprising:
forming a conductive line on a first surface of a semiconductor substrate, wherein the conductive line extends no further than the semiconductor substrate;
forming a plurality of electrodes on the conductive line, wherein said plurality of electrodes protrude from the conductive line;
plating said plurality of electrodes with a plating material, the plating material forming a planar layer;
depositing a buffer layer onto and in physical contact with the conductive line, said plurality of electrodes extending through said buffer layer;
selectively etching said buffer layer such that a top surface of said plurality of electrodes is exposed at a depth below a top of said buffer layer, the selectively etching exposing an entire top surface of at least one of said plurality of electrodes;
placing a solder ball onto said each of said plurality of electrodes, wherein a joint between said solder ball and said each of said plurality of electrodes lies below said top of said buffer layer, and wherein said solder ball is electrically connected to a wiring layer of said semiconductor substrate through said plating material and said plurality of electrodes.
10. The method of claim 9 further comprising:
a passivation layer deposited over a semiconductor substrate layer, wherein said top portion of said passivation layer comprises said first surface; and
a polymer insulation layer deposited over said passivation layer, wherein a top side of said polymer insulation layer becomes said first surface of said semiconductor substrate, wherein a material for said polymer insulation layer is selected based at least in part on the material's coefficient of thermal expansion (CTE).
11. The method of claim 9 wherein said forming said plurality of electrodes comprises:
forming two or more columns connected at a first end to said wiring layer, wherein said two or more columns are formed for each of said plurality of electrodes.
12. The method of claim 9 wherein said plating material comprises one of:
copper;
nickel; and
tin.
13. The method of claim 9 wherein said plurality of electrodes is made from a material comprising one of:
copper;
solder;
nickel; and
tin.
US11/941,429 2007-11-16 2007-11-16 Protected solder ball joints in wafer level chip-scale packaging Active US8492263B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US11/941,429 US8492263B2 (en) 2007-11-16 2007-11-16 Protected solder ball joints in wafer level chip-scale packaging
TW97108282A TWI453840B (en) 2007-11-16 2008-03-10 Protected solder ball joints in wafer level chip-scale packaging
CNA2008100863034A CN101436559A (en) 2007-11-16 2008-03-25 Method for manufacturing semiconductor device
US13/946,187 US9136211B2 (en) 2007-11-16 2013-07-19 Protected solder ball joints in wafer level chip-scale packaging

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/941,429 US8492263B2 (en) 2007-11-16 2007-11-16 Protected solder ball joints in wafer level chip-scale packaging

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/946,187 Continuation US9136211B2 (en) 2007-11-16 2013-07-19 Protected solder ball joints in wafer level chip-scale packaging

Publications (2)

Publication Number Publication Date
US20090130840A1 US20090130840A1 (en) 2009-05-21
US8492263B2 true US8492263B2 (en) 2013-07-23

Family

ID=40642416

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/941,429 Active US8492263B2 (en) 2007-11-16 2007-11-16 Protected solder ball joints in wafer level chip-scale packaging
US13/946,187 Expired - Fee Related US9136211B2 (en) 2007-11-16 2013-07-19 Protected solder ball joints in wafer level chip-scale packaging

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/946,187 Expired - Fee Related US9136211B2 (en) 2007-11-16 2013-07-19 Protected solder ball joints in wafer level chip-scale packaging

Country Status (3)

Country Link
US (2) US8492263B2 (en)
CN (1) CN101436559A (en)
TW (1) TWI453840B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120146226A1 (en) * 2010-12-12 2012-06-14 Stmicroelectronics (Crolles 2) Sas Integrated circuit chip and fabrication method
US8980738B2 (en) 2010-12-30 2015-03-17 Stmicroelectronics (Crolles 2) Sas Integrated circuit chip and fabrication method
US9293432B2 (en) 2012-11-08 2016-03-22 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for chip packaging structure
US9379077B2 (en) 2012-11-08 2016-06-28 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device
US9412686B2 (en) * 2014-08-26 2016-08-09 United Microelectronics Corp. Interposer structure and manufacturing method thereof
US9548282B2 (en) 2012-11-08 2017-01-17 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device
US20200328114A1 (en) * 2017-11-13 2020-10-15 Analog Devices Global Unlimited Company Plated metallization structures

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7820543B2 (en) * 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US8183095B2 (en) 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
JP2009164442A (en) * 2008-01-09 2009-07-23 Nec Electronics Corp Semiconductor device
US9524945B2 (en) * 2010-05-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with L-shaped non-metal sidewall protection structure
US8377816B2 (en) 2009-07-30 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming electrical connections
US8841766B2 (en) 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US8847387B2 (en) * 2009-10-29 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Robust joint structure for flip-chip bonding
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8299616B2 (en) * 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
US8610270B2 (en) 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8318596B2 (en) * 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8264089B2 (en) * 2010-03-17 2012-09-11 Maxim Integrated Products, Inc. Enhanced WLP for superior temp cycling, drop test and high current applications
US8441124B2 (en) 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
FR2959868A1 (en) * 2010-05-06 2011-11-11 St Microelectronics Crolles 2 SEMICONDUCTOR DEVICE HAVING CONNECTING PLATES WITH INSERTS
KR101119839B1 (en) * 2010-05-23 2012-02-28 주식회사 네패스 Bump structure and fabrication method thereof
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8241963B2 (en) 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
US9048135B2 (en) 2010-07-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Copper pillar bump with cobalt-containing sidewall protection
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
CN102455373B (en) * 2010-10-19 2014-04-23 群成科技股份有限公司 Probe card structure
JP5559023B2 (en) * 2010-12-15 2014-07-23 日本特殊陶業株式会社 Wiring board and manufacturing method thereof
US9324659B2 (en) * 2011-08-01 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the lower die
US9437564B2 (en) 2013-07-09 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9401308B2 (en) 2013-03-12 2016-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices, methods of manufacture thereof, and packaging methods
US9589862B2 (en) 2013-03-11 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9368398B2 (en) 2012-01-12 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9607921B2 (en) * 2012-01-12 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package interconnect structure
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9263839B2 (en) 2012-12-28 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
US10015888B2 (en) 2013-02-15 2018-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect joint protective layer apparatus and method
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US8766441B2 (en) * 2012-03-14 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder on slot connections in package on package structures
US9289841B2 (en) * 2012-04-16 2016-03-22 Tanigurogumi Corporation Soldering device, soldering method, and substrate and electronic component produced by the soldering device or the soldering method
US9515036B2 (en) 2012-04-20 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder connections
US9082776B2 (en) 2012-08-24 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having protective layer with curved surface and method of manufacturing same
US9589815B2 (en) * 2012-11-08 2017-03-07 Nantong Fujitsu Microelectronics Co., Ltd. Semiconductor IC packaging methods and structures
WO2014071814A1 (en) * 2012-11-08 2014-05-15 南通富士通微电子股份有限公司 Chip packaging structure and packaging method
CN102931097B (en) * 2012-11-08 2016-11-23 南通富士通微电子股份有限公司 The forming method of semiconductor package
CN102931158B (en) * 2012-11-08 2015-12-09 南通富士通微电子股份有限公司 Chip-packaging structure
US9620468B2 (en) * 2012-11-08 2017-04-11 Tongfu Microelectronics Co., Ltd. Semiconductor packaging structure and method for forming the same
US9806047B2 (en) * 2014-03-31 2017-10-31 Maxim Integrated Products, Inc. Wafer level device and method with cantilever pillar structure
US9520370B2 (en) 2014-05-20 2016-12-13 Micron Technology, Inc. Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor device assemblies and interconnect structures
CN104979318A (en) * 2015-05-19 2015-10-14 南通富士通微电子股份有限公司 Wafer level chip packaging structure and packaging method therefor
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US9640497B1 (en) * 2016-06-30 2017-05-02 Semiconductor Components Industries, Llc Semiconductor backmetal (BM) and over pad metallization (OPM) structures and related methods
US10068865B1 (en) * 2017-05-10 2018-09-04 Nanya Technology Corporation Combing bump structure and manufacturing method thereof
DE102017210654B4 (en) * 2017-06-23 2022-06-09 Infineon Technologies Ag An electronic device comprising a redistribution layer pad comprising a cavity
US10297561B1 (en) * 2017-12-22 2019-05-21 Micron Technology, Inc. Interconnect structures for preventing solder bridging, and associated systems and methods
KR20210016119A (en) * 2019-07-31 2021-02-15 삼성전자주식회사 Semiconductor package
KR20210084736A (en) * 2019-12-27 2021-07-08 삼성전자주식회사 Semiconductor package
US20220231067A1 (en) * 2021-01-18 2022-07-21 Taiwan Semiconductor Manufacturing Co., Ltd. Stilted pad structure
KR20220141065A (en) 2021-04-12 2022-10-19 삼성전자주식회사 Semiconductor package including under bump metallization

Citations (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5466635A (en) 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US5736456A (en) 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US5759910A (en) 1996-12-23 1998-06-02 Motorola, Inc. Process for fabricating a solder bump for a flip chip integrated circuit
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6107164A (en) 1998-08-18 2000-08-22 Oki Electric Industry Co., Ltd. Using grooves as alignment marks when dicing an encapsulated semiconductor wafer
US6107180A (en) 1998-01-30 2000-08-22 Motorola, Inc. Method for forming interconnect bumps on a semiconductor die
US6175161B1 (en) 1998-05-22 2001-01-16 Alpine Microsystems, Inc. System and method for packaging integrated circuits
US6229220B1 (en) 1995-06-27 2001-05-08 International Business Machines Corporation Bump structure, bump forming method and package connecting body
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6232243B1 (en) 1997-03-31 2001-05-15 Micron Technology, Inc. Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6279815B1 (en) 1998-06-17 2001-08-28 International Business Machines Corporation Stacked chip process carrier
US6323546B2 (en) * 1999-01-14 2001-11-27 United Microelectronics Corp. Direct contact through hole type wafer structure
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US6434016B2 (en) 1999-06-18 2002-08-13 Intel Corporation Apparatus for interconnecting multiple devices on a circuit board
US6448661B1 (en) 2001-02-09 2002-09-10 Samsung Electornics Co., Ltd. Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof
US20020132461A1 (en) 2001-03-19 2002-09-19 Casio Computer Co., Ltd. Semiconductor device having bump electrodes with a stress dissipating structure and method of manufacturing the same
US6454159B1 (en) 1999-08-18 2002-09-24 International Business Machines Corporation Method for forming electrical connecting structure
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6562665B1 (en) 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US6570248B1 (en) 1998-08-31 2003-05-27 Micron Technology, Inc. Structure and method for a high-performance electronic packaging assembly
US20030107137A1 (en) * 2001-09-24 2003-06-12 Stierman Roger J. Micromechanical device contact terminals free of particle generation
US6600234B2 (en) 1999-02-03 2003-07-29 Casio Computer Co., Ltd. Mounting structure having columnar electrodes and a sealing film
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6607938B2 (en) 2001-07-19 2003-08-19 Samsung Electronics Co., Ltd. Wafer level stack chip package and method for manufacturing same
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6717245B1 (en) 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6756294B1 (en) 2002-01-30 2004-06-29 Taiwan Semiconductor Manufacturing Company Method for improving bump reliability for flip chip devices
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US20050026416A1 (en) 2003-07-31 2005-02-03 International Business Machines Corporation Encapsulated pin structure for improved reliability of wafer
US20050084989A1 (en) * 2003-10-15 2005-04-21 Casio Computer Co., Ltd. Semiconductor device manufacturing method
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6906418B2 (en) 2002-07-11 2005-06-14 Micron Technology, Inc. Semiconductor component having encapsulated, bonded, interconnect contacts
US6908785B2 (en) 2001-12-06 2005-06-21 Samsung Electronics Co., Ltd. Multi-chip package (MCP) with a conductive bar and method for manufacturing the same
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6943067B2 (en) 2002-01-08 2005-09-13 Advanced Micro Devices, Inc. Three-dimensional integrated semiconductor devices
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US6960829B2 (en) * 2002-03-28 2005-11-01 Infineon Technologies Ag Method for producing a semiconductor wafer, semiconductor chip, and intermediate semiconductor product
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US20060055032A1 (en) 2004-09-14 2006-03-16 Kuo-Chin Chang Packaging with metal studs formed on solder pads
US20060108685A1 (en) 2004-11-22 2006-05-25 Au Optronics Corp. Integrated circuit package and assembly thereof
US20060113681A1 (en) * 2003-01-10 2006-06-01 Jeong Se-Young Reinforced solder bump structure and method for forming a reinforced solder bump
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US20060180887A1 (en) * 2005-02-15 2006-08-17 Sharp Kabushiki Kaisha Semiconductor device and production method thereof
US20060207088A1 (en) * 2005-03-15 2006-09-21 Shinko Electric Industries Co., Ltd Wiring board manufacturing method
US20060211233A1 (en) * 2005-03-21 2006-09-21 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
JP2006287048A (en) 2005-04-01 2006-10-19 Rohm Co Ltd Semiconductor device
US7129575B1 (en) 2000-10-13 2006-10-31 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped metal pillar
US7151009B2 (en) 2004-06-18 2006-12-19 Samsung Electronics Co., Ltd. Method for manufacturing wafer level chip stack package
US20070029654A1 (en) * 2005-08-01 2007-02-08 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure and method of manufacturing the same
US7215033B2 (en) 2003-11-19 2007-05-08 Samsung Electronics Co., Ltd. Wafer level stack structure for system-in-package and method thereof
US20070145101A1 (en) 2005-12-21 2007-06-28 Tdk Corporation Method for mounting chip component and circuit board
US7276799B2 (en) 2003-08-26 2007-10-02 Samsung Electronics Co., Ltd. Chip stack package and manufacturing method thereof
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US7285867B2 (en) 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
US7327040B2 (en) * 2004-11-16 2008-02-05 Kabushiki Kaisha Toshiba Module substrate and disk apparatus
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
US20080093738A1 (en) 2006-10-19 2008-04-24 Novatek Microelectronics Corp. Chip structure and wafer structure
US7382049B2 (en) 2005-08-30 2008-06-03 Via Technologies, Inc. Chip package and bump connecting structure thereof
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US20080296764A1 (en) 2007-05-29 2008-12-04 Kuo-Chin Chang Enhanced copper posts for wafer level chip scale packaging
US20090020869A1 (en) 2007-07-17 2009-01-22 Qing Xue Interconnect joint
US7482703B2 (en) 2005-11-22 2009-01-27 Samsung Electronics Co., Ltd. Semiconductor device having align mark layer and method of fabricating the same
US7494845B2 (en) 2004-06-22 2009-02-24 Samsung Electronics Co., Ltd. Method of forming a thin wafer stack for a wafer level package
US20090096092A1 (en) 2007-10-11 2009-04-16 Patel Pradip D Bump I/O Contact for Semiconductor Device
US20090108453A1 (en) 2004-08-12 2009-04-30 Megica Corporation Chip structure and method for fabricating the same
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US7834450B2 (en) 2007-08-20 2010-11-16 Samsung Electronics Co., Ltd. Semiconductor package having memory devices stacked on logic device
US20110186986A1 (en) 2010-01-29 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. T-Shaped Post for Semiconductor Devices
US20110193220A1 (en) 2010-02-11 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar Structure having a Non-Planar Surface for Semiconductor Devices
US20120012997A1 (en) 2010-07-13 2012-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed Pillar Structure

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0005088D0 (en) 2000-03-01 2000-04-26 Unilever Plc Composition and method for bleaching laundry fabrics
US6987031B2 (en) * 2002-08-27 2006-01-17 Micron Technology, Inc. Multiple chip semiconductor package and method of fabricating same
JP3929966B2 (en) 2003-11-25 2007-06-13 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
TWI252546B (en) * 2004-11-03 2006-04-01 Advanced Semiconductor Eng Bumping process and structure thereof
JP4458029B2 (en) * 2005-11-30 2010-04-28 カシオ計算機株式会社 Manufacturing method of semiconductor device
JP4922891B2 (en) 2006-11-08 2012-04-25 株式会社テラミクロス Semiconductor device and manufacturing method thereof
US20090197114A1 (en) 2007-01-30 2009-08-06 Da-Yuan Shih Modification of pb-free solder alloy compositions to improve interlayer dielectric delamination in silicon devices and electromigration resistance in solder joints
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US20110227216A1 (en) 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices

Patent Citations (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5481133A (en) 1994-03-21 1996-01-02 United Microelectronics Corporation Three-dimensional multichip package
US5466635A (en) 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US6229220B1 (en) 1995-06-27 2001-05-08 International Business Machines Corporation Bump structure, bump forming method and package connecting body
US6187678B1 (en) 1995-12-27 2001-02-13 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6236115B1 (en) 1995-12-27 2001-05-22 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US5736456A (en) 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US5759910A (en) 1996-12-23 1998-06-02 Motorola, Inc. Process for fabricating a solder bump for a flip chip integrated circuit
US6232243B1 (en) 1997-03-31 2001-05-15 Micron Technology, Inc. Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps
US6107180A (en) 1998-01-30 2000-08-22 Motorola, Inc. Method for forming interconnect bumps on a semiconductor die
US6175161B1 (en) 1998-05-22 2001-01-16 Alpine Microsystems, Inc. System and method for packaging integrated circuits
US6279815B1 (en) 1998-06-17 2001-08-28 International Business Machines Corporation Stacked chip process carrier
US6107164A (en) 1998-08-18 2000-08-22 Oki Electric Industry Co., Ltd. Using grooves as alignment marks when dicing an encapsulated semiconductor wafer
US6570248B1 (en) 1998-08-31 2003-05-27 Micron Technology, Inc. Structure and method for a high-performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6562653B1 (en) 1999-01-11 2003-05-13 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6323546B2 (en) * 1999-01-14 2001-11-27 United Microelectronics Corp. Direct contact through hole type wafer structure
US6600234B2 (en) 1999-02-03 2003-07-29 Casio Computer Co., Ltd. Mounting structure having columnar electrodes and a sealing film
US6434016B2 (en) 1999-06-18 2002-08-13 Intel Corporation Apparatus for interconnecting multiple devices on a circuit board
US6454159B1 (en) 1999-08-18 2002-09-24 International Business Machines Corporation Method for forming electrical connecting structure
US6717245B1 (en) 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US7129575B1 (en) 2000-10-13 2006-10-31 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped metal pillar
US6562665B1 (en) 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US6448661B1 (en) 2001-02-09 2002-09-10 Samsung Electornics Co., Ltd. Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof
US20020132461A1 (en) 2001-03-19 2002-09-19 Casio Computer Co., Ltd. Semiconductor device having bump electrodes with a stress dissipating structure and method of manufacturing the same
CN1375869A (en) 2001-03-19 2002-10-23 卡西欧计算机株式会社 Semiconductor device and its making method
US6607938B2 (en) 2001-07-19 2003-08-19 Samsung Electronics Co., Ltd. Wafer level stack chip package and method for manufacturing same
US20030107137A1 (en) * 2001-09-24 2003-06-12 Stierman Roger J. Micromechanical device contact terminals free of particle generation
US7531890B2 (en) 2001-12-06 2009-05-12 Samsung Electronics Co., Ltd. Multi-chip package (MCP) with a conductive bar and method for manufacturing the same
US6908785B2 (en) 2001-12-06 2005-06-21 Samsung Electronics Co., Ltd. Multi-chip package (MCP) with a conductive bar and method for manufacturing the same
US6943067B2 (en) 2002-01-08 2005-09-13 Advanced Micro Devices, Inc. Three-dimensional integrated semiconductor devices
US6756294B1 (en) 2002-01-30 2004-06-29 Taiwan Semiconductor Manufacturing Company Method for improving bump reliability for flip chip devices
US7056807B2 (en) 2002-02-06 2006-06-06 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US7037804B2 (en) 2002-02-06 2006-05-02 Intel Corporation Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US7157787B2 (en) 2002-02-20 2007-01-02 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6960829B2 (en) * 2002-03-28 2005-11-01 Infineon Technologies Ag Method for producing a semiconductor wafer, semiconductor chip, and intermediate semiconductor product
US6906418B2 (en) 2002-07-11 2005-06-14 Micron Technology, Inc. Semiconductor component having encapsulated, bonded, interconnect contacts
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US7285867B2 (en) 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US20060113681A1 (en) * 2003-01-10 2006-06-01 Jeong Se-Young Reinforced solder bump structure and method for forming a reinforced solder bump
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
US20050026416A1 (en) 2003-07-31 2005-02-03 International Business Machines Corporation Encapsulated pin structure for improved reliability of wafer
US7276799B2 (en) 2003-08-26 2007-10-02 Samsung Electronics Co., Ltd. Chip stack package and manufacturing method thereof
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
US20050084989A1 (en) * 2003-10-15 2005-04-21 Casio Computer Co., Ltd. Semiconductor device manufacturing method
US7215033B2 (en) 2003-11-19 2007-05-08 Samsung Electronics Co., Ltd. Wafer level stack structure for system-in-package and method thereof
US7151009B2 (en) 2004-06-18 2006-12-19 Samsung Electronics Co., Ltd. Method for manufacturing wafer level chip stack package
US7494845B2 (en) 2004-06-22 2009-02-24 Samsung Electronics Co., Ltd. Method of forming a thin wafer stack for a wafer level package
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US20090108453A1 (en) 2004-08-12 2009-04-30 Megica Corporation Chip structure and method for fabricating the same
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
CN1750257A (en) 2004-09-14 2006-03-22 台湾积体电路制造股份有限公司 Packaging module with metal studs formed on solder pads, packaging, base board structure and packaging method
US20060055032A1 (en) 2004-09-14 2006-03-16 Kuo-Chin Chang Packaging with metal studs formed on solder pads
US7327040B2 (en) * 2004-11-16 2008-02-05 Kabushiki Kaisha Toshiba Module substrate and disk apparatus
US20060108685A1 (en) 2004-11-22 2006-05-25 Au Optronics Corp. Integrated circuit package and assembly thereof
US20060180887A1 (en) * 2005-02-15 2006-08-17 Sharp Kabushiki Kaisha Semiconductor device and production method thereof
US20060207088A1 (en) * 2005-03-15 2006-09-21 Shinko Electric Industries Co., Ltd Wiring board manufacturing method
US7370411B2 (en) 2005-03-15 2008-05-13 Shinko Electric Industries Co., Ltd. Wiring board manufacturing method
US20060211233A1 (en) * 2005-03-21 2006-09-21 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
JP2006287048A (en) 2005-04-01 2006-10-19 Rohm Co Ltd Semiconductor device
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US20070029654A1 (en) * 2005-08-01 2007-02-08 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure and method of manufacturing the same
US7382049B2 (en) 2005-08-30 2008-06-03 Via Technologies, Inc. Chip package and bump connecting structure thereof
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7482703B2 (en) 2005-11-22 2009-01-27 Samsung Electronics Co., Ltd. Semiconductor device having align mark layer and method of fabricating the same
US20070145101A1 (en) 2005-12-21 2007-06-28 Tdk Corporation Method for mounting chip component and circuit board
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US20080093738A1 (en) 2006-10-19 2008-04-24 Novatek Microelectronics Corp. Chip structure and wafer structure
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US20080296764A1 (en) 2007-05-29 2008-12-04 Kuo-Chin Chang Enhanced copper posts for wafer level chip scale packaging
US20110057313A1 (en) 2007-05-29 2011-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced Copper Posts for Wafer Level Chip Scale Packaging
US20090020869A1 (en) 2007-07-17 2009-01-22 Qing Xue Interconnect joint
US7834450B2 (en) 2007-08-20 2010-11-16 Samsung Electronics Co., Ltd. Semiconductor package having memory devices stacked on logic device
US20090096092A1 (en) 2007-10-11 2009-04-16 Patel Pradip D Bump I/O Contact for Semiconductor Device
US20110186986A1 (en) 2010-01-29 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. T-Shaped Post for Semiconductor Devices
US20110193220A1 (en) 2010-02-11 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar Structure having a Non-Planar Surface for Semiconductor Devices
US20120012997A1 (en) 2010-07-13 2012-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed Pillar Structure

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120146226A1 (en) * 2010-12-12 2012-06-14 Stmicroelectronics (Crolles 2) Sas Integrated circuit chip and fabrication method
US8980738B2 (en) 2010-12-30 2015-03-17 Stmicroelectronics (Crolles 2) Sas Integrated circuit chip and fabrication method
US9093505B2 (en) * 2010-12-30 2015-07-28 Stmicroelectronics (Crolles 2) Sas Integrated circuit chip and fabrication method
US9455239B2 (en) 2010-12-30 2016-09-27 Stmicroelectronics (Crolles 2) Sas Integrated circuit chip and fabrication method
US9293432B2 (en) 2012-11-08 2016-03-22 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for chip packaging structure
US9379077B2 (en) 2012-11-08 2016-06-28 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device
US9548282B2 (en) 2012-11-08 2017-01-17 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device
US9412686B2 (en) * 2014-08-26 2016-08-09 United Microelectronics Corp. Interposer structure and manufacturing method thereof
US20200328114A1 (en) * 2017-11-13 2020-10-15 Analog Devices Global Unlimited Company Plated metallization structures
US11862518B2 (en) * 2017-11-13 2024-01-02 Analog Devices International Unlimited Company Plated metallization structures

Also Published As

Publication number Publication date
US9136211B2 (en) 2015-09-15
CN101436559A (en) 2009-05-20
TWI453840B (en) 2014-09-21
US20130299984A1 (en) 2013-11-14
TW200924090A (en) 2009-06-01
US20090130840A1 (en) 2009-05-21

Similar Documents

Publication Publication Date Title
US9136211B2 (en) Protected solder ball joints in wafer level chip-scale packaging
US7932601B2 (en) Enhanced copper posts for wafer level chip scale packaging
US6906429B2 (en) Semiconductor device and method of fabricating the same
US7078822B2 (en) Microelectronic device interconnects
US9059159B2 (en) Routing layer for mitigating stress in a semiconductor die
US8035226B1 (en) Wafer level package integrated circuit incorporating solder balls containing an organic plastic-core
US20090096098A1 (en) Inter-connecting structure for semiconductor package and method of the same
KR100659527B1 (en) Semiconductor chip having three dimension type ubm for flip chip bonding and mounting structure thereof
EP3018707B1 (en) Method of manufacturing a semiconductor device
JP2000228420A (en) Semiconductor device and manufacture thereof
US20090096093A1 (en) Inter-connecting structure for semiconductor package and method of the same
US8431478B2 (en) Solder cap bump in semiconductor package and method of manufacturing the same
US20060249844A1 (en) Contact structure on chip and package thereof
US20090174069A1 (en) I/o pad structure for enhancing solder joint reliability in integrated circuit devices
US6841884B2 (en) Semiconductor device
JP2007242782A (en) Semiconductor device and electronic apparatus
US20090008764A1 (en) Ultra-Thin Wafer-Level Contact Grid Array
US7355286B2 (en) Flip chip bonded package applicable to fine pitch technology
US9589815B2 (en) Semiconductor IC packaging methods and structures
KR20090011713A (en) Semiconductor and fabricating method thereof
CN105789066A (en) Manufacturing method for semiconductor packaging structure
JP2005094040A (en) Semiconductor device and packaging structure of semiconductor device
CN117393532A (en) Semiconductor structure, packaging device and manufacturing method of semiconductor structure
CN105826289A (en) Semiconductor packaging structure
JP2010147319A (en) Semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, CHUNG YU;LEE, CHIEN-HSIUN;TSAO, PEI-HAW;AND OTHERS;REEL/FRAME:020342/0671;SIGNING DATES FROM 20071030 TO 20071101

Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, CHUNG YU;LEE, CHIEN-HSIUN;TSAO, PEI-HAW;AND OTHERS;SIGNING DATES FROM 20071030 TO 20071101;REEL/FRAME:020342/0671

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8