US7843229B2 - Signal output circuit - Google Patents
Signal output circuit Download PDFInfo
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- US7843229B2 US7843229B2 US12/382,833 US38283309A US7843229B2 US 7843229 B2 US7843229 B2 US 7843229B2 US 38283309 A US38283309 A US 38283309A US 7843229 B2 US7843229 B2 US 7843229B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
- H03F3/087—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light with IC amplifier blocks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/50—Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/297—Indexing scheme relating to amplifiers the loading circuit of an amplifying stage comprising a capacitor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45342—Indexing scheme relating to differential amplifiers the AAC comprising control means on a back gate of the AAC
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/50—Indexing scheme relating to amplifiers in which input being applied to, or output being derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
- H03F2203/5027—Indexing scheme relating to amplifiers in which input being applied to, or output being derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower the source follower has a current mirror output circuit in its source circuit
Definitions
- the present invention relates to a signal output circuit of an optical receiver circuit, and in particular, to a signal output circuit and an optical receiver circuit that can handle lower voltages in power supply voltage.
- FIG. 5 is a diagram showing a configuration of a signal output circuit disclosed in Patent Document 1.
- the signal output circuit is provided with a first and a second emitter follower circuit and a comparator 20 .
- the first emitter follower circuit has an NPN bipolar transistor T 1 and a constant current source 12 .
- a base of the transistor T 1 is connected to an input signal terminal 52 , and a collector is connected to a power supply terminal (Vcc) 56 .
- the constant current source 12 includes an NPN bipolar transistor T 2 and a resistor element R 1 .
- a collector of the transistor T 2 is connected to an emitter of the transistor T 1 , a base is connected to a bias signal terminal (bias 1 ) 54 , and an emitter is connected to a ground terminal 58 via the resistor element R 1 .
- the second emitter follower circuit has an NPN bipolar transistor T 3 and a constant current source 14 .
- a base of the transistor T 3 is connected to the input signal terminal 52 , and a collector is connected to the power supply terminal 56 .
- the comparator 20 receives output signals from the first and second emitter follower circuits, makes a comparison as to magnitude relationship between the received signals, and outputs a result.
- the comparator 20 includes transistors T 5 and T 6 forming a differential pair, a resistor element R 3 , and a current mirror circuit 30 including transistors T 7 and T 8 .
- the resistor element R 3 is connected between emitters of the transistors T 5 and T 6 .
- the current mirror circuit 30 is connected to collectors of the transistors T 5 and T 6 .
- the comparator 20 further includes PNP bipolar transistors T 9 and T 10 , and constant current sources 42 , 44 , 46 , and 48 .
- the transistor T 9 has an emitter connected to a base of the transistor T 5 , has a base connected to an output of the first emitter follower circuit (the emitter of the transistor Ti), and has a collector connected to the ground terminal 58 .
- the transistor T 10 has an emitter connected to a base of the transistor T 6 , has a base connected to an output of the second emitter follower circuit (the emitter of the transistor T 3 ), and has a collector connected to the ground terminal 58 .
- the constant current source 42 is connected between an emitter of the transistor T 9 and the power supply terminal 56 .
- the constant current source 44 is connected between an emitter of the transistor T 5 and the power supply terminal 56 .
- the constant current source 46 is connected between an emitter of the transistor T 6 and the power supply terminal 56 .
- the constant current source 48 is connected between an emitter of the transistor T 10 and the power supply terminal 56 .
- An output of the second emitter follower circuit (the emitter of the transistor T 3 ) is connected to an external load 90 .
- the comparator 20 performs voltage comparison between an output voltage Vo of the second emitter follower circuit and an output (the emitter of the transistor T 1 ) voltage V 2 of the first emitter follower circuit.
- the comparator 20 controls so that a current is supplied to the second emitter follower circuit (T 3 ) connected to the load 90 , by a bias supply circuit 60 , and the voltage shift is remedied.
- FIG. 6 is a diagram showing a configuration of a voltage generator disclosed in Patent Document 2.
- the voltage generator includes: an NPN bipolar transistor 8 having a base supplied with a voltage VOP output by an error detector (OP amplifier) 5 that receives a reference voltage VREF from a reference voltage generator 4 and a feedback voltage VFBK, to detect an error; a current mirror circuit including PNP bipolar transistors 10 and 11 , which outputs a current obtained by multiplying a current flowing in the NPN bipolar transistor 8 ; and resistors 6 and 7 which cause generation of the feedback voltage VFBK to the error detector 5 from an output voltage VREG generated by current flowing in the current mirror circuit.
- OP amplifier error detector
- Vcc-Vsat saturation voltage between collector and emitter
- An output voltage can be set by the feed back voltage VFBK which is an output of dividing resistors (R 1 and R 2 ) connected between an output 3 and GND and the reference voltage VREF from a reference voltage generator 4 . At this time, the output voltage is constant.
- an output voltage VOP of the error detector (OP amplifier) 5 increases in order that a current flows to a PNP bipolar transistor 10 , a collector current of the PNP bipolar transistor 10 increases, and a collector current of the PNP bipolar transistor 11 forming a current mirror with the PNP bipolar transistor 10 , increases.
- Patent Documents 1 and 2 The entire disclosure of Patent Documents 1 and 2 is incorporated herein by reference thereto.
- an emitter follower is used by an NPN transistor as signal output, and maximum output voltage on the power supply voltage Vcc side is less than or equal to Vcc-Vbe (Vbe is emitter-base voltage).
- Vcc-Vbe Vbe is emitter-base voltage
- an output voltage can be set to Vcc-Vsat on the power supply voltage Vcc side.
- an output signal waveform becomes dull (that is, slew rate decreases).
- resistors 6 and 7 R 1 and R 2 ) for determining set voltage are necessary.
- the circuit shown in FIG. 6 can cope with the increasing fluctuations of a current flowing through a load. When the current flowing through the load decreases, since there are resistors (R 1 and R 2 ) for setting the output voltage, the output signal waveform becomes dull.
- a signal output circuit including:
- a first transistor of an emitter follower configuration the first transistor receiving an input signal
- a second transistor of an emitter follower configuration the second transistor receiving the input signal and having an emitter connected to an external load
- a comparator circuit having an input pair for receiving emitter outputs of the first and the second transistors and comparing the received emitter outputs of the first and the second transistors;
- a first current mirror circuit having an input connected to an output of a first current source, and having an output connected to the emitter of the first transistor;
- a second current mirror circuit having an input connected to a connection node of an output of a second current source and an output of the comparator circuit, and having an output connected to the emitter of the second transistor.
- the emitters of the first and second transistors are respectively connected to the input pair of the comparator circuit via first and second resistors.
- an optical receiver circuit including:
- an optical detector which detects light and outputs a current
- the signal output circuit includes the abovementioned signal output circuit according to the present invention.
- the current-to-voltage conversion circuit includes a differential amplifier having an inverting input terminal connected to a cathode of a photodiode included by the optical detector, and having a non-inverting input terminal supplied with a prescribed reference voltage.
- the signal output circuit receives an output signal of the differential amplifier as an input signal.
- the emitter output of the first transistor of the signal output circuit is connected to the inverting input terminal of the differential amplifier via a feedback resistor.
- a signal amplitude is able to be ensured even in case of lowering of a power supply voltage and slew rate of an output waveform is also able to be ensured, thereby making it possible to cope with lower power dissipation.
- FIG. 1 is a diagram showing a circuit configuration of a first exemplary embodiment of the present invention.
- FIGS. 2A to 2C are diagrams comparing and describing an input output characteristic of a comparative example and an exemplary embodiment of the present invention.
- FIG. 3 is a diagram showing a circuit configuration of a second exemplary embodiment of the present invention.
- FIG. 4 is a diagram showing a circuit configuration of a third exemplary embodiment of the present invention.
- FIG. 5 is a diagram showing a configuration of related technology (Patent Document 1).
- FIG. 6 is a diagram showing a configuration of related technology (Patent Document 2).
- a signal output circuit which includes:
- a first transistor (Q 11 ) of an emitter follower configuration which receives an input signal
- a second transistor (Q 8 ) of an emitter follower configuration which receives the input signal (input), and which has an output ( ) emitter) connected to an external load ( 106 );
- a comparator circuit which has an input pair for receiving emitter outputs (V 1 and Vo) of the first and the second transistors (Q 11 and Q 8 ) and performs a comparison of emitter outputs (V 1 and Vo);
- a first current mirror circuit (Q 9 , Q 10 ) which has an input connected to output of a first current source transistor (Q 13 ), and has an output connected to an emitter of the first transistor (Q 11 );
- a second current mirror circuit (Q 6 , Q 7 ) which has an input connected to a connection node of an output of a second current source transistor (Q 14 ) and an output of the comparator circuit ( 104 ), and has an output connected to an emitter of the second transistor (Q 8 ).
- the outputs (emitters) of the first and second transistors (Q 11 and Q 8 ) are respectively connected to the input pair (bases of Q 1 and Q 2 ) of the comparator circuit ( 104 ) via resistors (R 1 and R 2 ).
- the first and second current source transistors (Q 13 and Q 14 ) are biased by a common bias voltage.
- a dynamic range on a power supply voltage (Vcc) side is secured.
- the comparator circuit ( 104 ) by performing control so that a transitioning characteristic of Vo follows V 1 and by performing control to vary current of an output part emitter follower (Q 8 ), in accordance with fluctuations of the load, a decrease in a slew rate of an output signal waveform is able to be avoided.
- FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.
- the signal output circuit includes:
- a PNP bipolar transistor Q 5 having an emitter connected to the power supply terminal (Vcc) 101 , having a base connected to a base of the bipolar transistor Q 4 , and having the emitter and the base connected in common to a collector of the bipolar transistor Q 1 .
- the bipolar transistors Q 1 and Q 2 form a differential pair.
- the bipolar transistors Q 4 and Q 5 form a current mirror and serves as an active load of the differential pair (Q 1 , Q 2 ).
- the signal output circuit further includes:
- a PNP bipolar transistor Q 11 having an emitter connected to GND, having a base supplied with an input signal, and having a collector connected to a collector of the bipolar transistor Q 10 .
- a connection node of the collector of the bipolar transistor Q 10 and an emitter of the bipolar transistor Q 11 is connected to the base of the bipolar transistor Q 2 via the resistor R 2 .
- the signal output circuit further includes:
- a bipolar transistor Q 14 having an emitter connected to GND via a resistor R 4 , having a base supplied with a bias voltage from a bias supply circuit 102 , and having a collector to a connection node of a collector of the bipolar transistor Q 4 and the collector and base of the bipolar transistor Q 6 ;
- a connection node of the collector of the bipolar transistor Q 7 and an emitter of the bipolar transistor Q 8 is connected to the base of the bipolar transistor Q 1 via the resistor R 1 .
- the transistor Q 11 constitutes a first emitter follower circuit
- the transistor Q 8 constitutes a second emitter follower circuit
- the transistor Q 13 and the resistor R 5 constitute the first current source.
- the transistor Q 14 and the resistor R 4 constitute the second current source.
- the transistor Q 3 and the resistor R 3 constitute a third current source.
- the differential transistor pair (Q 1 , Q 2 ), the constant current source (Q 3 , R 3 ), the current mirror (Q 4 , Q 5 ), and the resistor elements R 1 and R 2 constitute a comparator circuit 104 .
- Vcc-Vsat PNP transistor collector-emitter saturation voltage
- V is an output voltage range
- I is a load supply current
- t is a voltage supply time
- CL is a capacitance load
- the slew rate has a dependency on load capacitance and load current. Therefore, the slew rate deteriorates by a load change under a constant current.
- FIG. 2A is a diagram showing, for the comparative example (the circuit in the related technology) and the present exemplary embodiment, output voltage waveforms (transient characteristic in a time region) when the square wave input voltage (refer to FIG. 2C ) is applied.
- FIG. 3 is a diagram showing a configuration of a second exemplary embodiment of the present invention.
- transistor polarity conductivity type
- Transistors Q 1 , Q 2 , Q 3 , Q 11 , Q 13 , Q 8 , and Q 14 are PNP bipolar transistors
- transistors Q 4 , Q 5 , Q 6 , Q 7 , Q 9 , and Q 10 are NPN bipolar transistors.
- the present exemplary embodiment by being able to secure a dynamic range on a power supply voltage Vcc side, and to secure a slew rate, it is made possible in lowering of a power supply voltage to ensure a signal amplitude and slew rate, thereby achieving lower power dissipation.
- FIG. 4 is a diagram showing a configuration of a third exemplary embodiment of the present invention.
- the optical receiver circuit includes: a differential amplifier circuit (OP amplifier) 202 , having an inverting input terminal ( ⁇ ) connected to a cathode terminal of a photodiode 200 forming an optical detector, and having a non-inverting input terminal (+) supplied with a reference voltage Vc and a signal output circuit ( 204 ) according to the present invention, connected to output of the differential amplifier circuit (OP amplifier) 202 .
- a differential amplifier circuit OP amplifier
- an internal node V 1 (for example, V 1 in FIG. 1 ) is connected to the inverting input terminal ( ⁇ ) of the differential amplifier circuit (OP amplifier) 202 , via a feedback resistor Rf.
- the differential amplifier circuit (OP amplifier) 202 functions as a current-to-voltage converter.
- a low power supply voltage condition for example, a power supply voltage Vcc of 3.3V
- Vcc a power supply voltage
- the constant current sources 44 and 46 are considered to be configured by commonly used transistors, a range of the input voltage (Vo and V 2 ), at which the comparator 20 can be stably operated, becomes extremely limited, and a desired characteristic cannot be obtained.
- input of the comparator 20 is configured by 2 transistors T 5 and T 9 , or T 6 and T 10 , and hence with an input voltage of 1 ⁇ 2 Vcc or the like, transistors making up a constant current are saturated.
- the base potential of the transistor Q 1 of the differential pair is of a value obtained by subtracting a voltage drop of [base current] ⁇ [base resistance R 1 ] from an output Vo of a second emitter follower circuit (Q 8 ) connected to a load ( 106 ) and the base potential of the transistor Q 2 of the differential pair is of a value obtained by subtracting a voltage drop of [base current] ⁇ [base resistance R 2 ] from an output V 1 of a first emitter follower circuit (Q 11 ).
- the resistors R 1 and R 2 that determine a bias current are provided.
- an amplitude of an output signal is limited.
- the bias current of an output section is supplied by a current mirror circuit. With this configuration, the output amplitude is able to be expanded up to Vcc-Vsat.
- Patent Documents 1 and 2 are incorporated by reference into the present document. Modifications and adjustments of exemplary embodiments and examples are possible within bounds of the entire disclosure (including the scope of the claims) of the present invention, and also based on fundamental technological concepts thereof. Furthermore, a wide variety of combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention clearly includes every type of transformation and modification that a person skilled in the art can realize according to technological concepts and the entire disclosure including the scope of the claims.
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Abstract
Description
t=V/(I×CL) (1)
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2008-078468 | 2008-03-25 | ||
JP2008078468A JP2009232409A (en) | 2008-03-25 | 2008-03-25 | Signal output circuit |
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US20090243691A1 US20090243691A1 (en) | 2009-10-01 |
US7843229B2 true US7843229B2 (en) | 2010-11-30 |
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US12/382,833 Active 2029-05-23 US7843229B2 (en) | 2008-03-25 | 2009-03-25 | Signal output circuit |
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JP (1) | JP2009232409A (en) |
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JP5096507B2 (en) * | 2010-02-15 | 2012-12-12 | 日本電信電話株式会社 | Amplitude limiting amplifier circuit and optical receiver |
Citations (12)
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US4533844A (en) * | 1982-02-26 | 1985-08-06 | Motorola, Inc. | Peak storage amplifier |
US4739281A (en) * | 1986-08-28 | 1988-04-19 | Solid State Micro Technology For Music, Inc | Analog buffer amplifier |
US5038055A (en) * | 1988-12-02 | 1991-08-06 | Kabushiki Kaisha Toshiba | Peak level detecting device and method |
US5291149A (en) * | 1992-03-30 | 1994-03-01 | Murata Manufacturing Co., Ltd. | Operational amplifier |
US5818295A (en) * | 1995-06-30 | 1998-10-06 | Texas Instruments Incorporated | Operational amplifier with stabilized DC operations |
US6020768A (en) * | 1998-05-13 | 2000-02-01 | Oak Technology, Inc. | CMOS low-voltage comparator |
JP2001325034A (en) | 2000-03-07 | 2001-11-22 | Mitsubishi Electric Corp | Voltage generator, output circuit for error detector, and current generator |
US6323695B1 (en) * | 1998-09-11 | 2001-11-27 | Stmicroelectronics Gmbh | Comparator with controllable bias current source |
US6566852B2 (en) | 2000-08-09 | 2003-05-20 | Mitsubishi Denki Kabushiki Kaisha | Voltage generator, output circuit for error detector, and current generator |
US6642791B1 (en) * | 2002-08-09 | 2003-11-04 | Lsi Logic Corporation | Self-biased amplifier circuit and method for self-basing amplifier circuit |
JP2006311419A (en) | 2005-05-02 | 2006-11-09 | Nec Electronics Corp | Signal output circuit |
US7495478B2 (en) * | 2005-04-14 | 2009-02-24 | Sharp Kabushiki Kaisha | Comparator and infrared remote control receiver |
Family Cites Families (6)
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FR2493069A1 (en) * | 1980-10-23 | 1982-04-30 | Efcis | INTEGRATED AMPLIFIER IN CLASS AB IN CMOS TECHNOLOGY |
JPS63302621A (en) * | 1987-06-02 | 1988-12-09 | Fujitsu Ltd | Semiconductor integrated circuit |
JPH1127065A (en) * | 1997-07-02 | 1999-01-29 | Tadahiro Omi | Semiconductor integrated circuit |
JP3166678B2 (en) * | 1997-09-22 | 2001-05-14 | 日本電気株式会社 | Semiconductor integrated circuit |
JP3524795B2 (en) * | 1999-01-29 | 2004-05-10 | シャープ株式会社 | Light receiving amplifier |
JP3916431B2 (en) * | 2001-10-04 | 2007-05-16 | シャープ株式会社 | Receiver amplifier circuit |
-
2008
- 2008-03-25 JP JP2008078468A patent/JP2009232409A/en active Pending
-
2009
- 2009-03-25 US US12/382,833 patent/US7843229B2/en active Active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4533844A (en) * | 1982-02-26 | 1985-08-06 | Motorola, Inc. | Peak storage amplifier |
US4739281A (en) * | 1986-08-28 | 1988-04-19 | Solid State Micro Technology For Music, Inc | Analog buffer amplifier |
US5038055A (en) * | 1988-12-02 | 1991-08-06 | Kabushiki Kaisha Toshiba | Peak level detecting device and method |
US5291149A (en) * | 1992-03-30 | 1994-03-01 | Murata Manufacturing Co., Ltd. | Operational amplifier |
US5818295A (en) * | 1995-06-30 | 1998-10-06 | Texas Instruments Incorporated | Operational amplifier with stabilized DC operations |
US6020768A (en) * | 1998-05-13 | 2000-02-01 | Oak Technology, Inc. | CMOS low-voltage comparator |
US6323695B1 (en) * | 1998-09-11 | 2001-11-27 | Stmicroelectronics Gmbh | Comparator with controllable bias current source |
JP2001325034A (en) | 2000-03-07 | 2001-11-22 | Mitsubishi Electric Corp | Voltage generator, output circuit for error detector, and current generator |
US6566852B2 (en) | 2000-08-09 | 2003-05-20 | Mitsubishi Denki Kabushiki Kaisha | Voltage generator, output circuit for error detector, and current generator |
US6642791B1 (en) * | 2002-08-09 | 2003-11-04 | Lsi Logic Corporation | Self-biased amplifier circuit and method for self-basing amplifier circuit |
US7495478B2 (en) * | 2005-04-14 | 2009-02-24 | Sharp Kabushiki Kaisha | Comparator and infrared remote control receiver |
JP2006311419A (en) | 2005-05-02 | 2006-11-09 | Nec Electronics Corp | Signal output circuit |
US7148724B2 (en) | 2005-05-02 | 2006-12-12 | Nec Electronics Corporation | Signal output circuit |
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US20090243691A1 (en) | 2009-10-01 |
JP2009232409A (en) | 2009-10-08 |
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