Nothing Special   »   [go: up one dir, main page]

US6816426B2 - Semiconductor device with self refresh test mode - Google Patents

Semiconductor device with self refresh test mode Download PDF

Info

Publication number
US6816426B2
US6816426B2 US10/408,527 US40852703A US6816426B2 US 6816426 B2 US6816426 B2 US 6816426B2 US 40852703 A US40852703 A US 40852703A US 6816426 B2 US6816426 B2 US 6816426B2
Authority
US
United States
Prior art keywords
refresh
signals
self refresh
self
test mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US10/408,527
Other versions
US20030202410A1 (en
Inventor
Terry R. Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Round Rock Research LLC
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US10/408,527 priority Critical patent/US6816426B2/en
Publication of US20030202410A1 publication Critical patent/US20030202410A1/en
Priority to US10/852,031 priority patent/US6928019B2/en
Application granted granted Critical
Publication of US6816426B2 publication Critical patent/US6816426B2/en
Priority to US11/181,298 priority patent/US7428181B2/en
Priority to US11/196,971 priority patent/US20050265105A1/en
Priority to US12/176,710 priority patent/US8687446B2/en
Assigned to ROUND ROCK RESEARCH, LLC reassignment ROUND ROCK RESEARCH, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Adjusted expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002—Characteristic

Definitions

  • the invention relates to a semiconductor device having dynamic memory, such as a DRAM device. More particularly, the invention relates to such a semiconductor device that includes a self refresh test mode in which self refresh is monitored and/or modified by an external testing device. The invention also includes a method for constructing such a semiconductor device.
  • DRAMS dynamic random access memory
  • Such cells may include capacitive elements to which a charge is applied to signify a high or low voltage.
  • the voltage of the charge decreases over time, making the contents of the cells unreliable.
  • Refresh involves reading a datum from a cell before the datum becomes corrupted and rewriting the datum into the cell. The read and rewriting process may be essentially simultaneous.
  • DRAMs are often referred to as either “standard refresh” or “extended refresh.” Whether a DRAM is a standard refresh or an extended refresh device may be determined by dividing the specified refresh time by the number of cycles. Table 1 lists some of the standard DRAMs that have been marketed by Micron Technology, Inc., assignee of the present invention, and their refresh specifications:
  • DRAMs having refresh rates of 15.6 ⁇ s are standard refresh devices, while DRAMs having refresh rates of substantially greater than 15.6 ⁇ s/row are extended refresh devices.
  • DRAM refresh cycles Two basic means of performing refresh are distributed and burst refresh. Distributing the refresh cycles so that they are evenly spaced is known as distributed refresh. When not being refreshed, the DRAM may be read from or written to. In distributed refresh, the DRAM controller is set up to perform a refresh cycle, for example, every 15.6 ⁇ s. Usually, this means the controller allows the current cycle to be completed, and then holds off all instructions while a refresh is performed on the DRAM. The requested cycle is then allowed to resume. Refresh may be achieved in a burst method by performing a series of refresh cycles, one right after the other until all rows have been accessed. During refresh, other commands are not allowed.
  • Standard refresh types include (1) ⁇ overscore (RAS) ⁇ -ONLY refresh, (2) ⁇ overscore (CAS) ⁇ -BEFORE- ⁇ overscore (RAS) ⁇ (CBR) refresh, and (3) Hidden refresh.
  • RAS ⁇ overscore
  • CBR ⁇ overscore
  • Hidden refresh To perform a ⁇ overscore (RAS) ⁇ -ONLY refresh, a row address is put on the address lines and then ⁇ overscore (RAS) ⁇ is dropped. When ⁇ overscore (RAS) ⁇ falls, that row will be refreshed and, as long as ⁇ overscore (CAS) ⁇ is held high, the Dqs will remain open.
  • the DRAM controller provides addresses of cells to be refreshed.
  • the row order of refreshing does not matter as long as each row is refreshed in the specified amount of time.
  • a CBR refresh cycle is performed by dropping ⁇ overscore (CAS) ⁇ and then dropping ⁇ overscore (RAS) ⁇ .
  • One refresh cycle will be performed each time ⁇ overscore (RAS) ⁇ falls.
  • WE write enable
  • the Dqs will remain open during the cycle.
  • CBR refresh an internal counter is initialized to a random count when the DRAM device is powered up. Each time a CBR refresh is performed, the device refreshes a row based on the counter, and then the counter is incremented. When CBR refresh is performed again, the next row is refreshed and the counter is incremented. The counter will automatically wrap and continue when it reaches the end of its count. There is no way to reset the counter.
  • Row addresses are not externally supplied or monitored.
  • ⁇ overscore (CAS) ⁇ is held low before and after ⁇ overscore (RAS) ⁇ falls to meet t CSR and t CHR.
  • ⁇ overscore (CAS) ⁇ may stay low and only ⁇ overscore (RAS) ⁇ toggles. Every time ⁇ overscore (RAS) ⁇ falls, a refresh cycle is performed.
  • ⁇ overscore (CAS) ⁇ may be toggled each time, but it is not necessary.
  • the address buffers are powered-down because CBR refresh uses the internal counter and not an external address. For power sensitive applications, this may be a benefit, because there is no additional current used in switching address lines on a bus, nor will the DRAMs pull extra power if the address voltage is at an intermediate state. Because CBR refresh uses its own internal counter, there is not a concern about the controller having to supply the refresh addresses.
  • a self refresh mode helps maximize power savings in DRAMS and provide a very low-current data-retention mode.
  • Low-power, extended-refresh DRAMs LPDRAMs
  • Self refresh DRAMs require additional circuitry to be added to the standard DRAM to perform the self refresh function.
  • Self refresh mode provides the DRAM with the ability to refresh itself while in an extended standby mode (sleep or suspend). It is similar to the extended refresh mode of an LPDRAM except the self refresh DRAM utilizes an internally generated refresh clock while in the self refresh mode. During a system's suspend mode, the internally generated refresh clock on the DRAM replaces the DRAM controller refresh signals. Therefore, it is no longer necessary to power-up the DRAM controller while the system is in the suspend mode. Consulting the devices' data sheets will determine the power savings achieved.
  • Self refresh may employ parameters t RASS, t CHD and t RPS.
  • the DRAM's self refresh mode is initiated by executing a ⁇ overscore (CAS) ⁇ -BEFORE- ⁇ overscore (RAS) ⁇ (CBR) refresh cycle and holding both ⁇ overscore (RAS) ⁇ and ⁇ overscore (CAS) ⁇ LOW for a specified period.
  • the industry standard for this value is 100 ⁇ s minimum ( t RASS).
  • the DRAM will remain in the self refresh mode while ⁇ overscore (RAS) ⁇ is LOW. Once ⁇ overscore (CAS) ⁇ has been held LOW for t CHD, ⁇ overscore (CAS) ⁇ is no longer required to remain LOW and becomes a “don't care.”
  • the self refresh mode is terminated by taking ⁇ overscore (RAS) ⁇ HIGH for t RPS (the minimum time of an operation cycle). Once the self refresh mode has been terminated, the DRAM may be accessed normally.
  • RAS ⁇ overscore
  • Self refresh may be implemented in both a distributed method and a wait and burst method.
  • accesses to the DRAM may begin as soon as self refresh is exited.
  • the first CBR pulse should occur immediately prior to active use of the DRAM to ensure data integrity. Since CBR refresh is commonly implemented as the standard refresh, this ability to access the DRAM immediately after exiting self refresh is a big benefit over the burst scheme described later.
  • a burst of all rows should be executed when exiting self refresh. This is because the CBR counter and the DRAM controller counter will not likely be at the same count. If the CBR counter and the DRAM controller counter are not at the same count and both are being used in the distributed method, then refresh will be violated and data will eventually be lost.
  • Self refresh may be implemented with an internal burst refresh scheme. Instead of turning on a row at regular intervals, a circuit would sense when the array needs to be refreshed and then sequence through the rows until all had been refreshed. When exiting a burst-type self refresh, the entire array must be refreshed before any accesses are allowed, regardless of the type of refresh used. This full burst is necessary because self refresh may have been exited just before the entire array was going to be refreshed. If the burst is not performed when exiting this type of self refresh, the refresh requirements may be violated, leading to lost data.
  • Some DRAMs allow access to the DRAM as soon as self refresh is exited, while other DRAMs may require a full burst when exiting, regardless of the refresh used. To prevent possible compatibility problems, the controllers are designed to perform the burst when existing self refresh.
  • FIG. 1 shows a functional block diagram for an exemplary prior art DRAM 10 . It will be apparent to those skilled in the art that there are different types of DRAMs and that there is some flexibility in the choice of block diagrams to characterize the DRAM. It will also be apparent that, for clarity and simplicity, various components and conductors are not shown, but that an understanding of such components and conductors are within the knowledge of those skilled in the art. Accordingly, FIG. 1 is only exemplary. Referring to FIG. 1, data is written to or read from memory locations (or cells) of a memory array 14 through sense amplifier and input/output gating 18 , data-in buffer 22 and data-out buffer 24 .
  • DRAM 10 may include a complement select and row select circuit between row decoder 28 and memory array 14 .
  • a ⁇ overscore (RAS) ⁇ signal is received by a clock generator 44 , which, in response thereto, supplies the ⁇ overscore (RAS) ⁇ signal to a refresh controller and self refresh oscillator and timer 64 .
  • Clock generator 44 also supplies clock signals to sense amp and input/output gating 18 , row decoder 28 , a clock generator 48 .
  • a ⁇ overscore (CAS) ⁇ signal is supplied to control logic 56 , a clock generator 48 , column address buffers 40 , and refresh controller and self refresh oscillator and timer 64 .
  • a write enable ⁇ overscore (WE) ⁇ signal and an output enable ⁇ overscore (OE) ⁇ signal are also received by control logic 56 .
  • Control logic 56 controls data-in buffer 22 and data-out buffer 24 based on the state of ⁇ overscore (CAS) ⁇ , ⁇ overscore (WE) ⁇ , and ⁇ overscore (OE) ⁇ , and a clock signal from clock generator 48 , according to well-known protocols.
  • CAS ⁇ overscore
  • WE ⁇ overscore
  • OE ⁇ overscore
  • refresh controller and self refresh oscillator and timer 64 and a refresh counter 66 control the row address of the cell to be refreshed, while the column cells are refreshed simultaneously.
  • a memory device such as a DRAM that contains circuitry that allows an external testing device to have general access to internal signals of the memory device, as well as provide external control or modification of the self refresh cycle while in a test mode.
  • the present invention relates to a semiconductor device having dynamic memory and a system and method for testing self refresh functions of the semiconductor device.
  • the semiconductor device may include an interface for connection with an external device such as a testing device that may supervise the testing of the self refresh functions and analyze information transmitted from the semiconductor device regarding the refresh.
  • Information regarding the testing may be transmitted to the external testing device in real time or after the conclusion of the testing. Alternatively, the testing may be done internally without the aid of the external tester. However, information regarding the testing would be transmitted to an external device, in real time or otherwise.
  • the semiconductor device may include self refresh circuitry, selection circuitry, and a self refresh test mode controller.
  • the self refresh circuitry may produce refresh signals including preliminary refresh signals and location refresh signals. At least some of the preliminary refresh signals are used in producing the location refresh signals. Still other refresh signals may control various aspects of self refresh, such as communicating with the circuits in the semiconductor device or with the external device.
  • the self refresh circuitry may include a refresh controller and a refresh counter.
  • the selection circuitry may receive the location refresh signals and select memory locations within the memory array to be refreshed according to the values of the location refresh signals.
  • the memory of the semiconductor device may be a memory array having rows and columns.
  • the memory locations selected by the selection circuitry may be rows.
  • the memory location selecting circuitry may be directly or indirectly responsive to the location refresh signals.
  • the self refresh test mode controller may interact with the self refresh circuitry and transmits indicating signals to the interface that are indicative of at least one of the refresh signals.
  • the indicating signals may be indicative of some or all of the preliminary refresh signals, some or all of the location refresh signals, or other refresh signals.
  • the preliminary refresh signals may include row address strobe signals and/or column address strobe signals.
  • the external testing device may analyze the indicating signals to evaluate the refreshing of the memory array, including a failure in refreshing.
  • the self refresh test mode controller provides at least one or more of the following four functions: the ability to control internal signals while in self refresh mode; the ability to monitor internal signals while in self refresh mode; the ability to add a programmable delay, change the delay, or change internal timing while in self refresh mode; and the ability to have the device do a device read in a self refresh test mode.
  • a semiconductor device may include more than one memory array and more than one die.
  • the interface may include address lines, DQ lines, and/or other lines including those not ordinarily activated.
  • the interaction between the self refresh test mode controller and the self refresh circuitry may include merely monitoring at least some of the refresh signals or, in addition, include controlling some aspect of the self refresh circuitry, such as controlling the production of some or all refresh signals.
  • a sense amplifier and input/output gating and a self refresh oscillator and timer may assist in the performance of the self refresh.
  • the self refresh circuitry and the self refresh test mode controller each may be dedicated hardware, or may be included within a microprocessor.
  • the invention includes a method for making and operating such a semiconductor device and a system including an external testing device connectable to the semiconductor device.
  • the external testing device may test more than one semiconductor device according to the invention (which may but do not have to be identical) simultaneously or essentially simultaneously.
  • a semiconductor device may be a DRAM, or a variety of other devices having dynamic memory, including a microprocessor and an ASIC (application specific integrated circuit).
  • a microprocessor and an ASIC (application specific integrated circuit).
  • ASIC application specific integrated circuit
  • FIG. 1 shows a functional block diagram of an exemplary prior art DRAM.
  • FIG. 2 shows a functional block diagram of a semiconductor device according to the present invention.
  • FIG. 3 shows a functional block diagram of a more specific embodiment of a semiconductor device according to the present invention.
  • FIG. 4 shows a block diagram of a system including a testing device and semiconductor devices according to the present invention.
  • FIG. 5 shows a computer system in block diagram form that includes a semiconductor device according to the present invention.
  • FIG. 6 shows an electronic device in block diagram form that includes a semiconductor device according to the present invention.
  • a semiconductor device 110 (such as a DRAM) includes a memory array 114 that has dynamic memory cells. Data is written to or read from memory locations or cells of memory array 114 through sense amplifier and input/output gating 118 , date-in buffer 122 and data-out buffer 124 . Although only four DQ lines are illustrated in connection with data-in buffer 122 and data-out buffer 124 , there could be a greater or lesser number of DQ lines. Further, although it is not ordinarily preferred, separate input and output lines could be used rather than DQ lines.
  • the address of a particular memory location or cell to be written to or read from is selected by a row decoder 128 and a column decoder 134 under the direction of addresses A 0 -A 9 , which are processed by row address buffers 138 and column address buffers 140 .
  • Semiconductor device 110 may include a complement select and row select between row decoder 128 and memory array 114 . There may be more or less than ten address lines.
  • a ⁇ overscore (RAS) ⁇ signal is received by a clock generator 144 which in response thereto supplies the ⁇ overscore (RAS) ⁇ signal to a refresh controller and self refresh oscillator and timer 164 .
  • Clock generator 144 also supplies clock signals to sense amp and input/output gating 118 , row decoder 128 , and clock generator 148 .
  • a ⁇ overscore (CAS) ⁇ signal is supplied to control logic 156 , a clock generator 148 , column address buffers 140 , and refresh controller and self refresh oscillator and timer 164 .
  • a write enable ⁇ overscore (WE) ⁇ signal and an output enable ⁇ overscore (OE) ⁇ signal are also received by control logic 156 .
  • Control logic 156 controls data-in buffer 122 and data-out buffer 124 based on the state of ⁇ overscore (CAS) ⁇ , ⁇ overscore (WE) ⁇ , and ⁇ overscore (OE) ⁇ , and a clock signal from clock generator 148 , under well-known operations.
  • CAS ⁇ overscore
  • WE ⁇ overscore
  • OE ⁇ overscore
  • the refresh controller and self refresh oscillator and timer 164 , and a refresh counter 166 control the row address of the memory locations to be refreshed, while the column cells may be refreshed simultaneously.
  • FIG. 2 may be identical to or differ somewhat from the blocks of FIG. 1 .
  • a self refresh test mode controller 170 monitors and/or controls various blocks and internal signals on conductors between blocks in semiconductor device 110 .
  • the self refresh test mode may be entered or initiated by a particular sequence of inputs such as, for example, WCBR ( ⁇ overscore (WE) ⁇ and ⁇ overscore (CAS) ⁇ before ⁇ overscore (RAS) ⁇ ) operations.
  • WCBR ⁇ overscore
  • CAS ⁇ overscore
  • RAS ⁇ overscore
  • the self refresh test mode may be initiated by activation of a single line or more than one line.
  • Self refresh test mode controller 170 may communicate with a testing device (shown in FIG. 4) through various conductors including one or more DQ lines and/or one or more address lines.
  • a testing device shown in FIG. 4
  • N conductors are shown as being connected to DQ lines, where N is equal to or greater than one. In some cases, output buffers will need to be added to address pins.
  • FIG. 2 conductors are shown between self refresh test mode controller 170 and a wide variety of blocks and conductors. In practice, it is expected that self refresh test mode controller 170 would not be connected to so many blocks and conductors. However, FIG. 2 illustrates a variety of possibilities. Different embodiments of the invention may include different combinations of these conductors. Some embodiments may include only one of the conductors. Further, self refresh test mode controller 170 may be connected to and monitor and/or control additional blocks and conductors for which FIG. 2 does not show a connection.
  • a semiconductor device 190 is identical to semiconductor device 110 in FIG. 2 except that a self refresh test mode controller 170 is connected to fewer blocks and conductors between blocks.
  • Refresh controller and self refresh oscillator and timer 164 and refresh counter 166 are examples of self refresh circuitry. However, self refresh circuitry may be implemented through a variety of means. In this respect, refresh controller and self refresh oscillator and timer 164 and refresh counter 166 may be implemented in dedicated hardware or through a microprocessor. Refresh controller and self refresh oscillator and timer 164 and refresh counter 166 produce a variety of signals which may be considered self refresh signals in that they are directly or indirectly involved with the self refresh process. There are a variety of self refresh signals. The signals from row decoder 128 may be considered location refresh signals because they control the memory location in memory array 114 that is refreshed.
  • refresh controller and self refresh oscillator and timer 164 are considered to be preliminary refresh signals in that they are preliminary to some other functions.
  • the signals passing between refresh counter 166 and row address buffers 138 are preliminary to the location refresh signals and are considered to be preliminary refresh signals.
  • the signals at the outputs of row address buffers 138 and row decoder 128 may be considered to be preliminary refresh signals or location refresh signals.
  • Self refresh test mode controller 170 provides at least one or more of the following four functions:
  • the DQ pins may be used to read particular data on the row, while the column address is frozen.
  • the following signals may be analyzed and acted upon by self refresh test mode controller 170 , or transmitted through self refresh test mode controller 170 to conductors connected to a remote testing device.
  • the following are signals that may be received or produced by self refresh test mode controller 170 , and then analyzed and acted upon or transmitted through self refresh test mode controller 170 to one or more of the various blocks of semiconductor device 110 :
  • a signal overriding internal ⁇ overscore (RAS) ⁇ signals generated by self refresh circuitry including initiating a row change or the rate at which row change occurs;
  • Self refresh test mode controller 170 The structure of self refresh test mode controller 170 will depend on the particular functions it is to perform. Self refresh test mode controller 170 may be hardwired or programmable, allowing ease in determining which signals to observe in semiconductor device 110 . Self refresh test mode controller 170 may be accessible to the various blocks and signals of semiconductor device 110 through one or more common buses. If the blocks are implemented in a microprocessor, the microprocessor may have access to essentially all aspects of all blocks.
  • a system 202 includes a testing device 204 that is external to semiconductor device 110 and that communicates with semiconductor device 110 through conductors that carry ⁇ overscore (WE) ⁇ , ⁇ overscore (CAS) ⁇ , address (e.g. A 0 -A 9 ), ⁇ overscore (RAS) ⁇ , ⁇ overscore (OE) ⁇ , and input/output signals (e.g. on DQ lines), and perhaps other signals. Depending on the implementation, not all of these signals are necessary. Further, some signals may originate from a source other than testing device 204 . Testing device 204 and semiconductor device 110 may be configured so that testing device 204 may communicate with and program or otherwise control self refresh test mode controller 170 .
  • WE ⁇ overscore
  • CAS ⁇ overscore
  • address e.g. A 0 -A 9
  • RAS ⁇ overscore
  • OE ⁇ overscore
  • input/output signals e.g. on DQ lines
  • Testing device 204 may analyze and possibly repair semiconductor device 110 based on signals testing device 204 receives from semiconductor device 110 regarding self refresh operation. Testing device 204 preferably tests more than one semiconductor device simultaneously or essentially simultaneously. For example, a semiconductor device 206 according to the present invention (which may be, but is not required to be, identical to semiconductor device 110 or 190 ) is tested by testing device 204 . A conductor 208 may, but is not required to, carry the same signals as are carried between testing device 204 and semiconductor device 110 .
  • FIG. 5 illustrates a computer system 220 that includes a computer chassis 224 , a keyboard 226 , and a display monitor 230 .
  • Computer chassis 224 includes various electronic components including semiconductor device 234 , which is a semiconductor device according to the present invention, such as is illustrated in FIGS. 2 and 3.
  • FIG. 6 illustrates an electronic device 240 that includes various electronic components including a semiconductor device 244 according to the present invention, such as is illustrated in FIGS. 2 and 3.
  • Electronic device 240 could be, without limitation, memory devices, printers, displays, keyboards, computers (such as computer system 220 ), oscilloscopes, medical diagnostic equipment, and automobile control systems, to name only a few.
  • Semiconductor devices 110 and 190 may be a DRAM or essentially any other semiconductor device with dynamic memory, including microprocessors and ASICs.
  • the DRAM may also be a synchronous DRAM.
  • Semiconductor devices 110 and 190 may have more than one die. Each die may include one or more than one memory array. Further, at the time of any testing, semiconductor devices 110 and 190 may be a chip on a wafer, a bare chip off a wafer, a packaged chip including a package and leads.
  • Semiconductor devices 110 and 190 may be in a first-level package (e.g., DIP, SIP, ZIP, etc.) and in higher-level package assemblies (e.g., MCMs, including SIMMs and DIMMs, etc.).
  • Semiconductor devices 110 and 190 may be packetized protocol DRAMs in which at least two signals are supplied serially on a single conductor.
  • Semiconductor devices 110 and 190 may be multi-bank DRAMs (e.g., having 16 independent memory arrays).
  • a memory array does not have to store data in sequential rows or columns.
  • many semiconductor devices include redundant memory elements (such as a row) so that if a particular row is defective, it can be replaced by another row that is not defective.
  • connection As used in the claims, the terms “connect,” “connectable,” or “connected” are not necessarily limited to a direct connection. For example, there may be buffers or other components between two elements, making them indirectly connected. In this respect, the figures are only in block diagram form. Various well-known components have been omitted from the disclosure because their description would tend to obscure the actual invention. Although certain conductors in FIG. 2 are shown as only a single line, semiconductor device 110 may be implemented with parallel conductors in place of a single conductor. Also, signals, such as the row and column address strobes, output enable, and write enable, may be active low or active high.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

A semiconductor device (such as a DRAM) includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines. The self refresh test mode controller provides at least one or more of the following four functions: (1) the ability to control internal signals while in self refresh test mode; (2) the ability to monitor internal signals while in self refresh test mode; (3) the ability to put in a programmable delay, change the delay, or change internal timing while in self refresh test mode (add delay or make delay programmable, adjustable); (4) the ability to have the device do a device read in a self refresh test mode (the DQ pins may be used to read particular data on the row, while the column address is frozen).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of application Ser. No. 10/062,756, filed Jan. 30, 2002, now U.S. Pat. No. 6,545,925, issued Apr. 8, 2003, which is a continuation of application Ser. No. 08/705,149, filed Aug. 29, 1996, now U.S. Pat. No. 6,392,948 B1, issued May 21, 2002.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device having dynamic memory, such as a DRAM device. More particularly, the invention relates to such a semiconductor device that includes a self refresh test mode in which self refresh is monitored and/or modified by an external testing device. The invention also includes a method for constructing such a semiconductor device.
2. State of the Art
DRAMS (dynamic random access memory) include numerous cells in which data are stored. Such cells may include capacitive elements to which a charge is applied to signify a high or low voltage. However, because of leakage, the voltage of the charge decreases over time, making the contents of the cells unreliable. Refresh involves reading a datum from a cell before the datum becomes corrupted and rewriting the datum into the cell. The read and rewriting process may be essentially simultaneous.
There are various types of DRAM devices and various types of refresh. DRAMs are often referred to as either “standard refresh” or “extended refresh.” Whether a DRAM is a standard refresh or an extended refresh device may be determined by dividing the specified refresh time by the number of cycles. Table 1 lists some of the standard DRAMs that have been marketed by Micron Technology, Inc., assignee of the present invention, and their refresh specifications:
REFRESH
DRAM TIME NO. OF CYCLES REFRESH RATE
4 Meg × 1 16 ms 1,024 15.6 μs
256K × 16  8 ms   512 15.6 μs
256K × 16 64 ms   512  125 μs
(L Version)
4 Meg × 4 32 ms 2,048 15.6 μs
(2K)
4 Meg × 4 64 ms 4,096 15.6 μs
(4K)
DRAMs having refresh rates of 15.6 μs are standard refresh devices, while DRAMs having refresh rates of substantially greater than 15.6 μs/row are extended refresh devices.
Two basic means of performing refresh are distributed and burst refresh. Distributing the refresh cycles so that they are evenly spaced is known as distributed refresh. When not being refreshed, the DRAM may be read from or written to. In distributed refresh, the DRAM controller is set up to perform a refresh cycle, for example, every 15.6 μs. Usually, this means the controller allows the current cycle to be completed, and then holds off all instructions while a refresh is performed on the DRAM. The requested cycle is then allowed to resume. Refresh may be achieved in a burst method by performing a series of refresh cycles, one right after the other until all rows have been accessed. During refresh, other commands are not allowed.
Different cycles may be used to refresh DRAMs, all of which may be used in a distributed or burst method. Standard refresh types include (1) {overscore (RAS)}-ONLY refresh, (2) {overscore (CAS)}-BEFORE-{overscore (RAS)} (CBR) refresh, and (3) Hidden refresh. To perform a {overscore (RAS)}-ONLY refresh, a row address is put on the address lines and then {overscore (RAS)} is dropped. When {overscore (RAS)} falls, that row will be refreshed and, as long as {overscore (CAS)} is held high, the Dqs will remain open.
The DRAM controller provides addresses of cells to be refreshed. The row order of refreshing does not matter as long as each row is refreshed in the specified amount of time.
A CBR refresh cycle is performed by dropping {overscore (CAS)} and then dropping {overscore (RAS)}. One refresh cycle will be performed each time {overscore (RAS)} falls. WE (write enable) is held high while {overscore (RAS)} falls. The Dqs will remain open during the cycle. In the case of CBR refresh, an internal counter is initialized to a random count when the DRAM device is powered up. Each time a CBR refresh is performed, the device refreshes a row based on the counter, and then the counter is incremented. When CBR refresh is performed again, the next row is refreshed and the counter is incremented. The counter will automatically wrap and continue when it reaches the end of its count. There is no way to reset the counter. Row addresses are not externally supplied or monitored. {overscore (CAS)} is held low before and after {overscore (RAS)} falls to meet tCSR and tCHR. {overscore (CAS)} may stay low and only {overscore (RAS)} toggles. Every time {overscore (RAS)} falls, a refresh cycle is performed. {overscore (CAS)} may be toggled each time, but it is not necessary. The address buffers are powered-down because CBR refresh uses the internal counter and not an external address. For power sensitive applications, this may be a benefit, because there is no additional current used in switching address lines on a bus, nor will the DRAMs pull extra power if the address voltage is at an intermediate state. Because CBR refresh uses its own internal counter, there is not a concern about the controller having to supply the refresh addresses.
In Hidden refresh, the user does a READ or WRITE cycle and then, leaving {overscore (CAS)} low, brings {overscore (RAS)} high (for minimum of tRP) and then low. Since {overscore (CAS)} was low before {overscore (RAS)} went low, the part will execute a CBR refresh. In a READ cycle, the output data will remain valid during the CBR refresh. The refresh is “hidden” in the sense that data-out will stay on the lines while performing the function. READ and Hidden refresh cycles will take the same amount of time: tRC. The two cycles together take 2×tRC. A READ followed with a standard CBR refresh (instead of a Hidden refresh) would take the same amount of time: 2×tRC.
A self refresh mode helps maximize power savings in DRAMS and provide a very low-current data-retention mode. Low-power, extended-refresh DRAMs (LPDRAMs) have the same functionality as a standard DRAM, except they have been tested to meet the lower CMOS standby current and the extended refresh specifications. Self refresh DRAMs, on the other hand, require additional circuitry to be added to the standard DRAM to perform the self refresh function.
Self refresh mode provides the DRAM with the ability to refresh itself while in an extended standby mode (sleep or suspend). It is similar to the extended refresh mode of an LPDRAM except the self refresh DRAM utilizes an internally generated refresh clock while in the self refresh mode. During a system's suspend mode, the internally generated refresh clock on the DRAM replaces the DRAM controller refresh signals. Therefore, it is no longer necessary to power-up the DRAM controller while the system is in the suspend mode. Consulting the devices' data sheets will determine the power savings achieved.
Self refresh may employ parameters tRASS, tCHD and tRPS. The DRAM's self refresh mode is initiated by executing a {overscore (CAS)}-BEFORE-{overscore (RAS)} (CBR) refresh cycle and holding both {overscore (RAS)} and {overscore (CAS)} LOW for a specified period. The industry standard for this value is 100 μs minimum (tRASS). The DRAM will remain in the self refresh mode while {overscore (RAS)} is LOW. Once {overscore (CAS)} has been held LOW for tCHD, {overscore (CAS)} is no longer required to remain LOW and becomes a “don't care.”
The self refresh mode is terminated by taking {overscore (RAS)} HIGH for tRPS (the minimum time of an operation cycle). Once the self refresh mode has been terminated, the DRAM may be accessed normally.
Self refresh may be implemented in both a distributed method and a wait and burst method. In a system that utilizes distributed CBR refresh as the standard refresh, accesses to the DRAM may begin as soon as self refresh is exited. The first CBR pulse should occur immediately prior to active use of the DRAM to ensure data integrity. Since CBR refresh is commonly implemented as the standard refresh, this ability to access the DRAM immediately after exiting self refresh is a big benefit over the burst scheme described later. If anything other than CBR refresh is used as the standard refresh, a burst of all rows should be executed when exiting self refresh. This is because the CBR counter and the DRAM controller counter will not likely be at the same count. If the CBR counter and the DRAM controller counter are not at the same count and both are being used in the distributed method, then refresh will be violated and data will eventually be lost.
Self refresh may be implemented with an internal burst refresh scheme. Instead of turning on a row at regular intervals, a circuit would sense when the array needs to be refreshed and then sequence through the rows until all had been refreshed. When exiting a burst-type self refresh, the entire array must be refreshed before any accesses are allowed, regardless of the type of refresh used. This full burst is necessary because self refresh may have been exited just before the entire array was going to be refreshed. If the burst is not performed when exiting this type of self refresh, the refresh requirements may be violated, leading to lost data.
Some DRAMs allow access to the DRAM as soon as self refresh is exited, while other DRAMs may require a full burst when exiting, regardless of the refresh used. To prevent possible compatibility problems, the controllers are designed to perform the burst when existing self refresh.
FIG. 1 shows a functional block diagram for an exemplary prior art DRAM 10. It will be apparent to those skilled in the art that there are different types of DRAMs and that there is some flexibility in the choice of block diagrams to characterize the DRAM. It will also be apparent that, for clarity and simplicity, various components and conductors are not shown, but that an understanding of such components and conductors are within the knowledge of those skilled in the art. Accordingly, FIG. 1 is only exemplary. Referring to FIG. 1, data is written to or read from memory locations (or cells) of a memory array 14 through sense amplifier and input/output gating 18, data-in buffer 22 and data-out buffer 24. In ordinary operation, the address of a particular cell to be written to or read from is selected by a row decoder 28 and a column decoder 34 under the direction of addresses A0-A9, which are processed by row address butters 38 and column address buffers 40. DRAM 10 may include a complement select and row select circuit between row decoder 28 and memory array 14.
A {overscore (RAS)} signal is received by a clock generator 44, which, in response thereto, supplies the {overscore (RAS)} signal to a refresh controller and self refresh oscillator and timer 64. Clock generator 44 also supplies clock signals to sense amp and input/output gating 18, row decoder 28, a clock generator 48. A {overscore (CAS)} signal is supplied to control logic 56, a clock generator 48, column address buffers 40, and refresh controller and self refresh oscillator and timer 64. A write enable {overscore (WE)} signal and an output enable {overscore (OE)} signal are also received by control logic 56. Control logic 56 controls data-in buffer 22 and data-out buffer 24 based on the state of {overscore (CAS)}, {overscore (WE)}, and {overscore (OE)}, and a clock signal from clock generator 48, according to well-known protocols.
In self refresh mode, refresh controller and self refresh oscillator and timer 64 and a refresh counter 66 control the row address of the cell to be refreshed, while the column cells are refreshed simultaneously.
There may be difficulties in testing DRAM devices that incorporate a self refresh mode if the failures are present during self refresh operation. This complication may result because the external testing device no longer has control of internal DRAM clock signals such as {overscore (RAS)} and {overscore (CAS)}. Once the self refresh mode is entered, the DRAM internally times the necessary clock signals, and the external signals are ignored, except for external {overscore (RAS)} which is used to terminate self refresh. A difficult test problem is encountered when a device failure occurs related to self refresh. In other failure modes, it is possible to vary timing to-determine sensitivities of the failure to aid in troubleshooting the problem. In some cases, the failure is related to the period of the cycle the DRAM is in when self refresh is exited.
Prior systems have been proposed to provide signals indicative of the operations of a DRAM during self refresh. For example, U.S. Pat. No. 5,450,364 to Stephens, Jr. et al. describes a system the purpose of which is to create significant time savings in testing self refresh operation. The system is purported to generate a signal upon completion of the self refresh cycle, thus allowing a fast determination of whether the self refresh cycle has been completed within the pause time of the memory part. U.S. Pat. No. 5,418,754 to Sakakibara describes a system in which a self refresh cycle time is purported to be directly measured at a data output pin. U.S. Pat. No. 5,299,168 to Kang proposes a semiconductor memory circuit having a refresh address test circuit for detecting whether all of the refresh addresses have been generated.
However, these prior systems do not allow an external testing device to have general access to internal signals such as {overscore (RAS)}, {overscore (CAS)}, or other timing signals during self refresh.
Accordingly, there remains a need for a memory device such as a DRAM that contains circuitry that allows an external testing device to have general access to internal signals of the memory device, as well as provide external control or modification of the self refresh cycle while in a test mode.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to a semiconductor device having dynamic memory and a system and method for testing self refresh functions of the semiconductor device. The semiconductor device may include an interface for connection with an external device such as a testing device that may supervise the testing of the self refresh functions and analyze information transmitted from the semiconductor device regarding the refresh. Information regarding the testing may be transmitted to the external testing device in real time or after the conclusion of the testing. Alternatively, the testing may be done internally without the aid of the external tester. However, information regarding the testing would be transmitted to an external device, in real time or otherwise.
The semiconductor device may include self refresh circuitry, selection circuitry, and a self refresh test mode controller.
The self refresh circuitry may produce refresh signals including preliminary refresh signals and location refresh signals. At least some of the preliminary refresh signals are used in producing the location refresh signals. Still other refresh signals may control various aspects of self refresh, such as communicating with the circuits in the semiconductor device or with the external device. The self refresh circuitry may include a refresh controller and a refresh counter.
The selection circuitry may receive the location refresh signals and select memory locations within the memory array to be refreshed according to the values of the location refresh signals. The memory of the semiconductor device may be a memory array having rows and columns. The memory locations selected by the selection circuitry may be rows. The memory location selecting circuitry may be directly or indirectly responsive to the location refresh signals.
The self refresh test mode controller may interact with the self refresh circuitry and transmits indicating signals to the interface that are indicative of at least one of the refresh signals. The indicating signals may be indicative of some or all of the preliminary refresh signals, some or all of the location refresh signals, or other refresh signals. The preliminary refresh signals may include row address strobe signals and/or column address strobe signals. The external testing device may analyze the indicating signals to evaluate the refreshing of the memory array, including a failure in refreshing.
The self refresh test mode controller provides at least one or more of the following four functions: the ability to control internal signals while in self refresh mode; the ability to monitor internal signals while in self refresh mode; the ability to add a programmable delay, change the delay, or change internal timing while in self refresh mode; and the ability to have the device do a device read in a self refresh test mode.
The external control of self refresh would generally only be allowed when in a self refresh test mode, rather than in normal operation of self refresh.
A semiconductor device may include more than one memory array and more than one die.
The interface may include address lines, DQ lines, and/or other lines including those not ordinarily activated.
The interaction between the self refresh test mode controller and the self refresh circuitry may include merely monitoring at least some of the refresh signals or, in addition, include controlling some aspect of the self refresh circuitry, such as controlling the production of some or all refresh signals.
A sense amplifier and input/output gating and a self refresh oscillator and timer may assist in the performance of the self refresh.
The self refresh circuitry and the self refresh test mode controller each may be dedicated hardware, or may be included within a microprocessor.
The invention includes a method for making and operating such a semiconductor device and a system including an external testing device connectable to the semiconductor device. The external testing device may test more than one semiconductor device according to the invention (which may but do not have to be identical) simultaneously or essentially simultaneously.
A semiconductor device according to the present invention may be a DRAM, or a variety of other devices having dynamic memory, including a microprocessor and an ASIC (application specific integrated circuit).
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
FIG. 1 shows a functional block diagram of an exemplary prior art DRAM.
FIG. 2 shows a functional block diagram of a semiconductor device according to the present invention.
FIG. 3 shows a functional block diagram of a more specific embodiment of a semiconductor device according to the present invention.
FIG. 4 shows a block diagram of a system including a testing device and semiconductor devices according to the present invention.
FIG. 5 shows a computer system in block diagram form that includes a semiconductor device according to the present invention.
FIG. 6 shows an electronic device in block diagram form that includes a semiconductor device according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 2, a semiconductor device 110 (such as a DRAM) includes a memory array 114 that has dynamic memory cells. Data is written to or read from memory locations or cells of memory array 114 through sense amplifier and input/output gating 118, date-in buffer 122 and data-out buffer 124. Although only four DQ lines are illustrated in connection with data-in buffer 122 and data-out buffer 124, there could be a greater or lesser number of DQ lines. Further, although it is not ordinarily preferred, separate input and output lines could be used rather than DQ lines.
In ordinary operation, the address of a particular memory location or cell to be written to or read from is selected by a row decoder 128 and a column decoder 134 under the direction of addresses A0-A9, which are processed by row address buffers 138 and column address buffers 140. Semiconductor device 110 may include a complement select and row select between row decoder 128 and memory array 114. There may be more or less than ten address lines.
A {overscore (RAS)} signal is received by a clock generator 144 which in response thereto supplies the {overscore (RAS)} signal to a refresh controller and self refresh oscillator and timer 164. Clock generator 144 also supplies clock signals to sense amp and input/output gating 118, row decoder 128, and clock generator 148. A {overscore (CAS)} signal is supplied to control logic 156, a clock generator 148, column address buffers 140, and refresh controller and self refresh oscillator and timer 164. A write enable {overscore (WE)} signal and an output enable {overscore (OE)} signal are also received by control logic 156. Control logic 156 controls data-in buffer 122 and data-out buffer 124 based on the state of {overscore (CAS)}, {overscore (WE)}, and {overscore (OE)}, and a clock signal from clock generator 148, under well-known operations.
In self refresh test mode, the refresh controller and self refresh oscillator and timer 164, and a refresh counter 166 control the row address of the memory locations to be refreshed, while the column cells may be refreshed simultaneously.
Except as described below, the blocks of FIG. 2 described heretofore may be identical to or differ somewhat from the blocks of FIG. 1.
In a self refresh test mode, a self refresh test mode controller 170 monitors and/or controls various blocks and internal signals on conductors between blocks in semiconductor device 110. The self refresh test mode may be entered or initiated by a particular sequence of inputs such as, for example, WCBR ({overscore (WE)} and {overscore (CAS)} before {overscore (RAS)}) operations. Alternatively, the self refresh test mode may be initiated by activation of a single line or more than one line.
The external control of self refresh would generally only be allowed when in a self refresh test mode, rather than in normal operation of self refresh. However, monitoring and control of self refresh signals and self refresh could occur during ordinary operation of the semiconductor device.
Self refresh test mode controller 170 may communicate with a testing device (shown in FIG. 4) through various conductors including one or more DQ lines and/or one or more address lines. In FIG. 2, N conductors are shown as being connected to DQ lines, where N is equal to or greater than one. In some cases, output buffers will need to be added to address pins.
In FIG. 2, conductors are shown between self refresh test mode controller 170 and a wide variety of blocks and conductors. In practice, it is expected that self refresh test mode controller 170 would not be connected to so many blocks and conductors. However, FIG. 2 illustrates a variety of possibilities. Different embodiments of the invention may include different combinations of these conductors. Some embodiments may include only one of the conductors. Further, self refresh test mode controller 170 may be connected to and monitor and/or control additional blocks and conductors for which FIG. 2 does not show a connection.
As a more specific example, in FIG. 3 a semiconductor device 190 is identical to semiconductor device 110 in FIG. 2 except that a self refresh test mode controller 170 is connected to fewer blocks and conductors between blocks.
Refresh controller and self refresh oscillator and timer 164 and refresh counter 166 are examples of self refresh circuitry. However, self refresh circuitry may be implemented through a variety of means. In this respect, refresh controller and self refresh oscillator and timer 164 and refresh counter 166 may be implemented in dedicated hardware or through a microprocessor. Refresh controller and self refresh oscillator and timer 164 and refresh counter 166 produce a variety of signals which may be considered self refresh signals in that they are directly or indirectly involved with the self refresh process. There are a variety of self refresh signals. The signals from row decoder 128 may be considered location refresh signals because they control the memory location in memory array 114 that is refreshed.
Other signals produced by refresh controller and self refresh oscillator and timer 164, refresh counter 166, and other components are considered to be preliminary refresh signals in that they are preliminary to some other functions. For example, the signals passing between refresh counter 166 and row address buffers 138 are preliminary to the location refresh signals and are considered to be preliminary refresh signals. Depending on how it is viewed, the signals at the outputs of row address buffers 138 and row decoder 128 may be considered to be preliminary refresh signals or location refresh signals.
Self refresh test mode controller 170 provides at least one or more of the following four functions:
(1) the ability to control internal signals while in self refresh mode;
(2) the ability to monitor internal signals while in self refresh mode;
(3) the ability to add a programmable delay, change the delay, or change internal timing while in self refresh mode; and
(4) the ability to have the device do a device read in a self refresh test mode (the DQ pins may be used to read particular data on the row, while the column address is frozen).
Merely as examples, the following signals may be analyzed and acted upon by self refresh test mode controller 170, or transmitted through self refresh test mode controller 170 to conductors connected to a remote testing device.
(1) internal {overscore (RAS)} signals;
(2) bits from refresh counter 166 (note that self refresh test mode controller 170 may initiate a row change or the rate at which row changes occur);
(3) {overscore (RAS)} chain; and
(4) equilibrate signals.
Merely as examples, the following are signals that may be received or produced by self refresh test mode controller 170, and then analyzed and acted upon or transmitted through self refresh test mode controller 170 to one or more of the various blocks of semiconductor device 110:
(1) a signal overriding internal {overscore (RAS)} signals generated by self refresh circuitry (including initiating a row change or the rate at which row change occurs);
(2) a signal that controls incrementing-of refresh counter 166 (which may be useful in, for example, analyzing a failure that consistently occurs at the same row); and
(3) signals that alter an internal time or programmable delay element;
The structure of self refresh test mode controller 170 will depend on the particular functions it is to perform. Self refresh test mode controller 170 may be hardwired or programmable, allowing ease in determining which signals to observe in semiconductor device 110. Self refresh test mode controller 170 may be accessible to the various blocks and signals of semiconductor device 110 through one or more common buses. If the blocks are implemented in a microprocessor, the microprocessor may have access to essentially all aspects of all blocks.
Referring to FIG. 4, a system 202 includes a testing device 204 that is external to semiconductor device 110 and that communicates with semiconductor device 110 through conductors that carry {overscore (WE)}, {overscore (CAS)}, address (e.g. A0-A9), {overscore (RAS)}, {overscore (OE)}, and input/output signals (e.g. on DQ lines), and perhaps other signals. Depending on the implementation, not all of these signals are necessary. Further, some signals may originate from a source other than testing device 204. Testing device 204 and semiconductor device 110 may be configured so that testing device 204 may communicate with and program or otherwise control self refresh test mode controller 170. Testing device 204 may analyze and possibly repair semiconductor device 110 based on signals testing device 204 receives from semiconductor device 110 regarding self refresh operation. Testing device 204 preferably tests more than one semiconductor device simultaneously or essentially simultaneously. For example, a semiconductor device 206 according to the present invention (which may be, but is not required to be, identical to semiconductor device 110 or 190) is tested by testing device 204. A conductor 208 may, but is not required to, carry the same signals as are carried between testing device 204 and semiconductor device 110.
In a preferred embodiment, self refresh test mode controller 170 continues to be part of semiconductor device 110 (although preferably it is not operational) after testing of semiconductor device 110 is completed and semiconductor device 110 is in ordinary operation. For example, FIG. 5 illustrates a computer system 220 that includes a computer chassis 224, a keyboard 226, and a display monitor 230. Computer chassis 224 includes various electronic components including semiconductor device 234, which is a semiconductor device according to the present invention, such as is illustrated in FIGS. 2 and 3. As another example, FIG. 6 illustrates an electronic device 240 that includes various electronic components including a semiconductor device 244 according to the present invention, such as is illustrated in FIGS. 2 and 3. Electronic device 240 could be, without limitation, memory devices, printers, displays, keyboards, computers (such as computer system 220), oscilloscopes, medical diagnostic equipment, and automobile control systems, to name only a few.
Semiconductor devices 110 and 190 may be a DRAM or essentially any other semiconductor device with dynamic memory, including microprocessors and ASICs. The DRAM may also be a synchronous DRAM. Semiconductor devices 110 and 190 may have more than one die. Each die may include one or more than one memory array. Further, at the time of any testing, semiconductor devices 110 and 190 may be a chip on a wafer, a bare chip off a wafer, a packaged chip including a package and leads. Semiconductor devices 110 and 190 (or other semiconductor devices within the invention) may be in a first-level package (e.g., DIP, SIP, ZIP, etc.) and in higher-level package assemblies (e.g., MCMs, including SIMMs and DIMMs, etc.). Semiconductor devices 110 and 190 (or other semiconductor devices within the invention) may be packetized protocol DRAMs in which at least two signals are supplied serially on a single conductor. Semiconductor devices 110 and 190 (or other semiconductor devices within the invention) may be multi-bank DRAMs (e.g., having 16 independent memory arrays).
A memory array does not have to store data in sequential rows or columns. Merely as an example, many semiconductor devices include redundant memory elements (such as a row) so that if a particular row is defective, it can be replaced by another row that is not defective.
Those skilled in the art appreciate that there are various structures for implementing dynamic memory. Accordingly, the invention is not limited to the particular examples in the figures.
As used in the claims, the terms “connect,” “connectable,” or “connected” are not necessarily limited to a direct connection. For example, there may be buffers or other components between two elements, making them indirectly connected. In this respect, the figures are only in block diagram form. Various well-known components have been omitted from the disclosure because their description would tend to obscure the actual invention. Although certain conductors in FIG. 2 are shown as only a single line, semiconductor device 110 may be implemented with parallel conductors in place of a single conductor. Also, signals, such as the row and column address strobes, output enable, and write enable, may be active low or active high.
Having thus described in detail preferred embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description as many apparent variations thereof are possible without departing from the spirit or scope thereof.

Claims (20)

What is claimed is:
1. A semiconductor device having an interface for receiving self refresh test control signals from an external device and a memory array, the semiconductor device comprising:
a self refresh test mode controller coupled to the interface for outputting internal test control signals in response to the self refresh test control signals during a self refresh test mode of the semiconductor device, the self refresh test mode controller including circuitry for outputting indicating signals;
self refresh circuitry coupled to the self refresh test mode controller for producing refresh signals including preliminary refresh signals and location refresh signals in response to the internal test control signals during the self refresh test mode, with at least some of the preliminary refresh signals being used in producing the location refresh signals, the self refresh test mode controller including the circuitry for outputting the indicating signals that are indicative of at least one of the refresh signals through the interface to the external device; and
selection circuitry coupled to the self refresh circuitry and the memory array for selecting memory locations within the memory array to be refreshed in response to the location refresh signals.
2. The semiconductor device of claim 1, wherein the indicating signals are indicative of one of the location refresh signals, at least some of the preliminary refresh signals, and of at least some of the preliminary refresh signals and of the location refresh signals.
3. The semiconductor device of claim 1, wherein the memory array includes rows and columns, and the memory locations selected by the selection circuitry are rows.
4. The semiconductor device of claim 1, wherein the refresh signals include one of row address strobe signals and column address strobe signals.
5. The semiconductor device of claim 1, wherein the memory array is a first memory array, and further comprising a second memory array that is refreshed in response to the self refresh circuitry, which refresh is monitored by the self refresh test mode controller.
6. The semiconductor device of claim 1, wherein the memory array is a first memory array, the self refresh circuitry is a first self refresh circuitry, and the self refresh test mode controller is a first self refresh test mode controller, and further comprising a second memory array, a second self refresh circuitry, and a second self refresh test mode controller, wherein the second memory array is refreshed in response to the second self refresh circuitry monitored by the second self refresh test mode controller.
7. The semiconductor device of claim 1, wherein the interface includes at least one of address lines, DQ lines, and lines activated when the self refresh test mode controller is activated.
8. The semiconductor device of claim 1, wherein the selection circuitry is one of directly responsive to the location refresh signals and indirectly responsive to the location refresh signals.
9. The semiconductor device of claim 1, further comprising a sense amplifier and input/output gating assisting in a performance of the self refresh test mode.
10. The semiconductor device of claim 1, wherein the self refresh circuitry includes at least one of a self refresh oscillator and timer and a refresh controller and a refresh counter.
11. The semiconductor device of claim 1, further including a column decoder.
12. The semiconductor device of claim 1, wherein the selection circuitry includes a column decoder.
13. The semiconductor device of claim 1, wherein the refresh signals include signals in addition to the preliminary refresh signals and the location refresh signals, the additional signals controlling various functions of self refresh.
14. The semiconductor device of claim 1, wherein the self refresh circuitry and the self refresh test mode controller are each included in a microprocessor.
15. A semiconductor device having an interface allowing connection with an external device and a memory array, the semiconductor device comprising:
self refresh circuitry for producing refresh signals including preliminary refresh signals and for producing location refresh signals, at least some of the preliminary refresh signals for use in producing the location refresh signals during a self refresh test mode of the semiconductor device;
selection circuitry connected to the self refresh circuitry and connected to the memory array for selecting memory locations within the memory array to be refreshed in response to the location refresh signals; and
a self refresh test mode controller connected to the self refresh circuitry and connected to the interface for receiving control signals from the interface and for responding to the control signals by modifying self refreshing operations of the semiconductor device during the self refresh test mode of the semiconductor device.
16. The device of claim 15, wherein the selection circuitry includes a row decoder and the memory locations are a row of memory locations.
17. The device of claim 15, wherein interaction between the self refresh test mode controller and the self refresh circuitry includes at least one of controlling the self refresh circuitry in producing the self refresh signals and controlling at least some aspect of the self refresh circuitry.
18. A method for testing signals used in self refresh of a memory array of a semiconductor device, the method comprising:
providing self refresh test control signals from an external testing device for controlling a self refresh test mode within the semiconductor device, the self refresh test control signals including at least some preliminary refresh signals and some location refresh signals;
producing refresh signals including the preliminary refresh signals and the location refresh signals in response to the self refresh test control signals, with at least some of the preliminary refresh signals being used in producing the location refresh signals;
selecting memory locations within the memory array to be refreshed in response to the location refresh signals;
interacting with self refresh circuitry and providing indicating signals indicative of at least one of the refresh signals and controlling production of the refresh signals; and
analyzing the indicating signals, thereby evaluating self refreshing of the memory array.
19. A method of testing self refreshing operations of a semiconductor memory, the method comprising:
causing the semiconductor memory to enter a self refresh test mode by using a Row Address Strobe (RAS) signal and a Column Address Strobe (CAS) signal;
self refreshing the semiconductor memory while the semiconductor memory is in the self refresh test mode, outputting self refresh timing signals from a self refresh timer within the semiconductor memory by outputting row addresses from a self refresh counter of the semiconductor memory in response to the self refresh timing signals; and refreshing rows in a memory array of the semiconductor memory selected in accordance with row addresses using a row decoder of the semiconductor memory; and
controlling the self refreshing of the semiconductor memory by providing self refresh test mode control signals to the semiconductor memory from a testing device external to the semiconductor memory during the self refresh test mode of the semiconductor memory.
20. The method of claim 19, wherein controlling the self refreshing of the semiconductor memory comprises controlling at least one of the self refresh timer, the self refresh counter, and the row decoder of the semiconductor memory using the self refresh test mode control signals.
US10/408,527 1996-08-29 2003-04-07 Semiconductor device with self refresh test mode Expired - Fee Related US6816426B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US10/408,527 US6816426B2 (en) 1996-08-29 2003-04-07 Semiconductor device with self refresh test mode
US10/852,031 US6928019B2 (en) 1996-08-29 2004-05-24 Semiconductor device with self refresh test mode
US11/181,298 US7428181B2 (en) 1996-08-29 2005-07-14 Semiconductor device with self refresh test mode
US11/196,971 US20050265105A1 (en) 1996-08-29 2005-08-04 Semiconductor device with self refresh test mode
US12/176,710 US8687446B2 (en) 1996-08-29 2008-07-21 Semiconductor device with self refresh test mode

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/705,149 US6392948B1 (en) 1996-08-29 1996-08-29 Semiconductor device with self refresh test mode
US10/062,756 US6545925B2 (en) 1996-08-29 2002-01-30 Semiconductor device with self refresh test mode
US10/408,527 US6816426B2 (en) 1996-08-29 2003-04-07 Semiconductor device with self refresh test mode

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/062,756 Continuation US6545925B2 (en) 1996-08-29 2002-01-30 Semiconductor device with self refresh test mode

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/852,031 Continuation US6928019B2 (en) 1996-08-29 2004-05-24 Semiconductor device with self refresh test mode

Publications (2)

Publication Number Publication Date
US20030202410A1 US20030202410A1 (en) 2003-10-30
US6816426B2 true US6816426B2 (en) 2004-11-09

Family

ID=24832242

Family Applications (8)

Application Number Title Priority Date Filing Date
US08/705,149 Expired - Lifetime US6392948B1 (en) 1996-08-29 1996-08-29 Semiconductor device with self refresh test mode
US10/062,756 Expired - Fee Related US6545925B2 (en) 1996-08-29 2002-01-30 Semiconductor device with self refresh test mode
US10/408,527 Expired - Fee Related US6816426B2 (en) 1996-08-29 2003-04-07 Semiconductor device with self refresh test mode
US10/408,540 Expired - Fee Related US6856567B2 (en) 1996-08-29 2003-04-07 Semiconductor device with self refresh test mode
US10/852,031 Expired - Fee Related US6928019B2 (en) 1996-08-29 2004-05-24 Semiconductor device with self refresh test mode
US11/181,298 Expired - Fee Related US7428181B2 (en) 1996-08-29 2005-07-14 Semiconductor device with self refresh test mode
US11/196,971 Abandoned US20050265105A1 (en) 1996-08-29 2005-08-04 Semiconductor device with self refresh test mode
US12/176,710 Expired - Fee Related US8687446B2 (en) 1996-08-29 2008-07-21 Semiconductor device with self refresh test mode

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US08/705,149 Expired - Lifetime US6392948B1 (en) 1996-08-29 1996-08-29 Semiconductor device with self refresh test mode
US10/062,756 Expired - Fee Related US6545925B2 (en) 1996-08-29 2002-01-30 Semiconductor device with self refresh test mode

Family Applications After (5)

Application Number Title Priority Date Filing Date
US10/408,540 Expired - Fee Related US6856567B2 (en) 1996-08-29 2003-04-07 Semiconductor device with self refresh test mode
US10/852,031 Expired - Fee Related US6928019B2 (en) 1996-08-29 2004-05-24 Semiconductor device with self refresh test mode
US11/181,298 Expired - Fee Related US7428181B2 (en) 1996-08-29 2005-07-14 Semiconductor device with self refresh test mode
US11/196,971 Abandoned US20050265105A1 (en) 1996-08-29 2005-08-04 Semiconductor device with self refresh test mode
US12/176,710 Expired - Fee Related US8687446B2 (en) 1996-08-29 2008-07-21 Semiconductor device with self refresh test mode

Country Status (1)

Country Link
US (8) US6392948B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040125680A1 (en) * 2002-10-31 2004-07-01 Kim Yong-Ki Semiconductor memory device with self-refresh device for reducing power consumption
US20050249012A1 (en) * 1996-08-29 2005-11-10 Lee Terry R Semiconductor device with self refresh test mode

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6812726B1 (en) * 2002-11-27 2004-11-02 Inapac Technology, Inc. Entering test mode and accessing of a packaged semiconductor device
US7444575B2 (en) * 2000-09-21 2008-10-28 Inapac Technology, Inc. Architecture and method for testing of an integrated circuit device
US6754866B1 (en) 2001-09-28 2004-06-22 Inapac Technology, Inc. Testing of integrated circuit devices
US6732304B1 (en) 2000-09-21 2004-05-04 Inapac Technology, Inc. Chip testing within a multi-chip semiconductor package
US7240254B2 (en) * 2000-09-21 2007-07-03 Inapac Technology, Inc Multiple power levels for a chip within a multi-chip semiconductor package
US7085186B2 (en) * 2001-04-05 2006-08-01 Purple Mountain Server Llc Method for hiding a refresh in a pseudo-static memory
DE10125022A1 (en) * 2001-05-22 2002-12-12 Infineon Technologies Ag Dynamic memory and method for testing dynamic memory
JP2003045200A (en) * 2001-08-02 2003-02-14 Mitsubishi Electric Corp Semiconductor module and semiconductor memory used for the same
ITRM20010556A1 (en) * 2001-09-12 2003-03-12 Micron Technology Inc DECODER TO DECODE SWITCHING COMMANDS IN INTEGRATED CIRCUIT TEST MODE.
US8166361B2 (en) * 2001-09-28 2012-04-24 Rambus Inc. Integrated circuit testing module configured for set-up and hold time testing
US8286046B2 (en) 2001-09-28 2012-10-09 Rambus Inc. Integrated circuit testing module including signal shaping interface
US7313740B2 (en) * 2002-07-25 2007-12-25 Inapac Technology, Inc. Internally generating patterns for testing in an integrated circuit device
US20040019841A1 (en) * 2002-07-25 2004-01-29 Ong Adrian E. Internally generating patterns for testing in an integrated circuit device
US8001439B2 (en) * 2001-09-28 2011-08-16 Rambus Inc. Integrated circuit testing module including signal shaping interface
US6560155B1 (en) * 2001-10-24 2003-05-06 Micron Technology, Inc. System and method for power saving memory refresh for dynamic random access memory devices after an extended interval
US7061263B1 (en) 2001-11-15 2006-06-13 Inapac Technology, Inc. Layout and use of bond pads and probe pads for testing of integrated circuits devices
KR100465597B1 (en) * 2001-12-07 2005-01-13 주식회사 하이닉스반도체 Refresh circuit for semiconductor memory device and refresh method thereof
US6693837B2 (en) * 2002-04-23 2004-02-17 Micron Technology, Inc. System and method for quick self-refresh exit with transitional refresh
JP2004013987A (en) * 2002-06-06 2004-01-15 Toshiba Corp Semiconductor storage device
DE10228527B3 (en) * 2002-06-26 2004-03-04 Infineon Technologies Ag Method for checking the refresh function of an information store
US6711093B1 (en) * 2002-08-29 2004-03-23 Micron Technology, Inc. Reducing digit equilibrate current during self-refresh mode
US6711082B1 (en) 2002-11-18 2004-03-23 Infineon Technologies, Ag Method and implementation of an on-chip self refresh feature
US8063650B2 (en) 2002-11-27 2011-11-22 Rambus Inc. Testing fuse configurations in semiconductor devices
US6853591B2 (en) 2003-03-31 2005-02-08 Micron Technology, Inc. Circuit and method for decreasing the required refresh rate of DRAM devices
US7234099B2 (en) * 2003-04-14 2007-06-19 International Business Machines Corporation High reliability memory module with a fault tolerant address and command bus
US7164615B2 (en) * 2004-07-21 2007-01-16 Samsung Electronics Co., Ltd. Semiconductor memory device performing auto refresh in the self refresh mode
US7177208B2 (en) * 2005-03-11 2007-02-13 Micron Technology, Inc. Circuit and method for operating a delay-lock loop in a power saving manner
US20060218455A1 (en) * 2005-03-23 2006-09-28 Silicon Design Solution, Inc. Integrated circuit margin stress test system
JP4609813B2 (en) * 2005-05-18 2011-01-12 エルピーダメモリ株式会社 Semiconductor device
US7532532B2 (en) 2005-05-31 2009-05-12 Micron Technology, Inc. System and method for hidden-refresh rate modification
KR100670657B1 (en) * 2005-06-30 2007-01-17 주식회사 하이닉스반도체 Semiconductor memory device
US7333382B2 (en) * 2006-02-16 2008-02-19 Infineon Technologies Ag Method and apparatus for an oscillator within a memory device
JP2007273028A (en) * 2006-03-31 2007-10-18 Matsushita Electric Ind Co Ltd Semiconductor storage device
DE102006018921A1 (en) * 2006-04-24 2007-11-08 Infineon Technologies Ag Integrated semiconductor memory with refreshment of memory cells
KR100854497B1 (en) * 2006-07-10 2008-08-26 삼성전자주식회사 semiconductor memory device and method thereof
US7408813B2 (en) * 2006-08-03 2008-08-05 Micron Technology, Inc. Block erase for volatile memory
WO2008042403A2 (en) 2006-10-03 2008-04-10 Inapac Technologies, Inc. Memory accessing circuit system
KR100899392B1 (en) * 2007-08-20 2009-05-27 주식회사 하이닉스반도체 Refresh Characteristic Test Circuit and Refresh Characteristic Test Method using the same
JP5599559B2 (en) * 2008-11-27 2014-10-01 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device and refresh method thereof
JP2010135032A (en) * 2008-12-08 2010-06-17 Renesas Electronics Corp Semiconductor memory device and self-refresh test method
KR101798920B1 (en) * 2010-11-30 2017-11-17 삼성전자주식회사 Semiconductor memory device performing multi-cycle self refresh and method of verifying the same
US9268941B1 (en) * 2012-05-01 2016-02-23 Marvell International Ltd. Method for secure software resume from low power mode
CN104103246B (en) * 2013-04-12 2017-04-12 乐金显示有限公司 Driving circuit for display device and method of driving the same
US9911485B2 (en) * 2013-11-11 2018-03-06 Qualcomm Incorporated Method and apparatus for refreshing a memory cell
US9761296B2 (en) 2015-04-17 2017-09-12 Samsung Electronics Co., Ltd. Smart in-module refresh for DRAM
US9524769B2 (en) * 2015-04-17 2016-12-20 Samsung Electronics Co., Ltd. Smart in-module refresh for DRAM
US11462284B2 (en) * 2015-08-31 2022-10-04 Keysight Technologies, Inc. Method and system for analyzing a refresh rate of a volatile memory device
KR20170045795A (en) 2015-10-20 2017-04-28 삼성전자주식회사 Memory device and memory system including the same
TWI643199B (en) * 2016-09-06 2018-12-01 鈺創科技股份有限公司 Circuit for outputting information of a memory circuit during self-refresh mode and related method thereof
KR20180028783A (en) 2016-09-09 2018-03-19 삼성전자주식회사 Memory device including command controller

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317169A (en) 1979-02-14 1982-02-23 Honeywell Information Systems Inc. Data processing system having centralized memory refresh
US4453237A (en) 1980-10-01 1984-06-05 Intel Corporation Multiple bit output dynamic random-access memory
US4547867A (en) 1980-10-01 1985-10-15 Intel Corporation Multiple bit dynamic random-access memory
US4672583A (en) 1983-06-15 1987-06-09 Nec Corporation Dynamic random access memory device provided with test circuit for internal refresh circuit
US5270982A (en) 1991-04-30 1993-12-14 Nec Corporation Dynamic random access memory device improved in testability without sacrifice of current consumption
US5295109A (en) 1991-06-21 1994-03-15 Sharp Kabushiki Kaisha Semiconductor memory
US5299168A (en) 1992-04-22 1994-03-29 Samsung Electronics Co., Ltd. Circuit for detecting refresh address signals of a semiconductor memory device
US5299970A (en) 1993-01-06 1994-04-05 Serge Fontaine Guided rolling circle game
US5299969A (en) 1993-01-28 1994-04-05 Breslow, Morrison, Terzian & Associates, Inc. Loop feature for propelled toy vehicles
US5349562A (en) 1992-06-04 1994-09-20 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory device suitable for shortening time required for testing self-refresh function
US5386385A (en) 1994-01-31 1995-01-31 Texas Instruments Inc. Method and apparatus for preventing invalid operating modes and an application to synchronous memory devices
US5418754A (en) 1993-02-10 1995-05-23 Nec Corporation Dynamic random access memory device with self-refresh cycle time directly measurable at data pin
US5446695A (en) 1994-03-22 1995-08-29 International Business Machines Corporation Memory device with programmable self-refreshing and testing methods therefore
US5450364A (en) 1994-01-31 1995-09-12 Texas Instruments Incorporated Method and apparatus for production testing of self-refresh operations and a particular application to synchronous memory devices
US5627791A (en) 1996-02-16 1997-05-06 Micron Technology, Inc. Multiple bank memory with auto refresh to specified bank
US5636173A (en) 1995-06-07 1997-06-03 Micron Technology, Inc. Auto-precharge during bank selection
US5644544A (en) 1994-10-28 1997-07-01 Nec Corporation Semiconductor dynamic random access memory device variable in refresh cycle
US6392948B1 (en) 1996-08-29 2002-05-21 Micron Technology, Inc. Semiconductor device with self refresh test mode

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62250593A (en) * 1986-04-23 1987-10-31 Hitachi Ltd Dynamic ram
US5321661A (en) * 1991-11-20 1994-06-14 Oki Electric Industry Co., Ltd. Self-refreshing memory with on-chip timer test circuit
JP2606669B2 (en) * 1994-09-22 1997-05-07 日本電気株式会社 Semiconductor storage device
US5623202A (en) * 1994-09-26 1997-04-22 United Microelectronics Corporation Testing multiple IC in parallel by a single IC tester

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317169A (en) 1979-02-14 1982-02-23 Honeywell Information Systems Inc. Data processing system having centralized memory refresh
US4453237A (en) 1980-10-01 1984-06-05 Intel Corporation Multiple bit output dynamic random-access memory
US4547867A (en) 1980-10-01 1985-10-15 Intel Corporation Multiple bit dynamic random-access memory
US4672583A (en) 1983-06-15 1987-06-09 Nec Corporation Dynamic random access memory device provided with test circuit for internal refresh circuit
US5270982A (en) 1991-04-30 1993-12-14 Nec Corporation Dynamic random access memory device improved in testability without sacrifice of current consumption
US5295109A (en) 1991-06-21 1994-03-15 Sharp Kabushiki Kaisha Semiconductor memory
US5299168A (en) 1992-04-22 1994-03-29 Samsung Electronics Co., Ltd. Circuit for detecting refresh address signals of a semiconductor memory device
US5349562A (en) 1992-06-04 1994-09-20 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory device suitable for shortening time required for testing self-refresh function
US5299970A (en) 1993-01-06 1994-04-05 Serge Fontaine Guided rolling circle game
US5299969A (en) 1993-01-28 1994-04-05 Breslow, Morrison, Terzian & Associates, Inc. Loop feature for propelled toy vehicles
US5418754A (en) 1993-02-10 1995-05-23 Nec Corporation Dynamic random access memory device with self-refresh cycle time directly measurable at data pin
US5386385A (en) 1994-01-31 1995-01-31 Texas Instruments Inc. Method and apparatus for preventing invalid operating modes and an application to synchronous memory devices
US5450364A (en) 1994-01-31 1995-09-12 Texas Instruments Incorporated Method and apparatus for production testing of self-refresh operations and a particular application to synchronous memory devices
US5446695A (en) 1994-03-22 1995-08-29 International Business Machines Corporation Memory device with programmable self-refreshing and testing methods therefore
US5644544A (en) 1994-10-28 1997-07-01 Nec Corporation Semiconductor dynamic random access memory device variable in refresh cycle
US5636173A (en) 1995-06-07 1997-06-03 Micron Technology, Inc. Auto-precharge during bank selection
US5627791A (en) 1996-02-16 1997-05-06 Micron Technology, Inc. Multiple bank memory with auto refresh to specified bank
US6392948B1 (en) 1996-08-29 2002-05-21 Micron Technology, Inc. Semiconductor device with self refresh test mode
US6545925B2 (en) 1996-08-29 2003-04-08 Micron Technology, Inc. Semiconductor device with self refresh test mode

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050249012A1 (en) * 1996-08-29 2005-11-10 Lee Terry R Semiconductor device with self refresh test mode
US7428181B2 (en) * 1996-08-29 2008-09-23 Micron Technology, Inc. Semiconductor device with self refresh test mode
US20080279022A1 (en) * 1996-08-29 2008-11-13 Micron Technology, Inc. Semiconductor device with self refresh test mode
US8687446B2 (en) 1996-08-29 2014-04-01 Round Rock Research, Llc Semiconductor device with self refresh test mode
US20040125680A1 (en) * 2002-10-31 2004-07-01 Kim Yong-Ki Semiconductor memory device with self-refresh device for reducing power consumption
US6922369B2 (en) * 2002-10-31 2005-07-26 Hynix Semiconductor Inc. Semiconductor memory device with self-refresh device for reducing power consumption

Also Published As

Publication number Publication date
US6392948B1 (en) 2002-05-21
US20030202410A1 (en) 2003-10-30
US8687446B2 (en) 2014-04-01
US20050265105A1 (en) 2005-12-01
US20040213061A1 (en) 2004-10-28
US20080279022A1 (en) 2008-11-13
US7428181B2 (en) 2008-09-23
US20050249012A1 (en) 2005-11-10
US6545925B2 (en) 2003-04-08
US6856567B2 (en) 2005-02-15
US6928019B2 (en) 2005-08-09
US20030210595A1 (en) 2003-11-13
US20020105843A1 (en) 2002-08-08

Similar Documents

Publication Publication Date Title
US6816426B2 (en) Semiconductor device with self refresh test mode
US5457659A (en) Programmable dynamic random access memory (DRAM)
US7610524B2 (en) Memory with test mode output
US6272588B1 (en) Method and apparatus for verifying and characterizing data retention time in a DRAM using built-in test circuitry
US5673270A (en) Semiconductor memory device having register for holding test resultant signal
JP2843481B2 (en) Semiconductor memory device having refresh address test circuit
US20040199717A1 (en) Semiconductor memory
US7035154B2 (en) Semiconductor memory device and its test method as well as test circuit
JP3797810B2 (en) Semiconductor device
US4347589A (en) Refresh counter test
GB2313937A (en) Refresh counter for SRAM and method of testing the same
CN111462810A (en) Circuit board and method for aging test of memory
EP0019150B1 (en) Method of testing the operation of an internal refresh counter in a random access memory and circuit for the testing thereof
US6108248A (en) Column address strobe signal generator for synchronous dynamic random access memory
JP3319394B2 (en) Semiconductor storage device
US20230408554A1 (en) Test devices and systems that utilize efficient test algorithms to evaluate devices under test
US6981187B1 (en) Test mode for a self-refreshed SRAM with DRAM memory cells
KR19980083772A (en) Semiconductor memory
US20050289410A1 (en) Internal signal test device and method thereof
KR19990080938A (en) DRAM having a self refresh cycle measuring unit and a self refresh cycle measuring method thereof
WO2002047091A1 (en) Memory circuit test system, semiconductor device, and method of tesing memory
JPH0474379A (en) Memory integrated circuit
KR100393973B1 (en) burn-in test mode circuit
KR20080030361A (en) Autorefresh control circuit for semiconductor memory device
JPH0927197A (en) Semiconductor memory and operation method

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20161109