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US6734472B2 - Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device - Google Patents

Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device Download PDF

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Publication number
US6734472B2
US6734472B2 US10/132,996 US13299602A US6734472B2 US 6734472 B2 US6734472 B2 US 6734472B2 US 13299602 A US13299602 A US 13299602A US 6734472 B2 US6734472 B2 US 6734472B2
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Prior art keywords
lines
substrate
power
mesh
shield mesh
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US20030201472A1 (en
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Iu-Meng Tom Ho
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Synopsys Inc
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Synplicity LLC
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Priority to US10/132,996 priority Critical patent/US6734472B2/en
Application filed by Synplicity LLC filed Critical Synplicity LLC
Priority to JP2004500331A priority patent/JP2005524231A/en
Priority to EP02761202A priority patent/EP1497864B1/en
Priority to AU2002326482A priority patent/AU2002326482A1/en
Priority to PCT/US2002/024267 priority patent/WO2003092070A2/en
Priority to DE60227290T priority patent/DE60227290D1/en
Assigned to IOTA TECHNOLOGY, INC. reassignment IOTA TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HO, IU-MENG TOM
Priority to TW091118025A priority patent/TWI285953B/en
Assigned to SYNPLICITY, INC. reassignment SYNPLICITY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IOTA TECHNOLOGY, INC.
Assigned to SYNPLICITY, INC. reassignment SYNPLICITY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HO, IU-MENG TOM, IOTA TECHNOLOGY, INC.
Publication of US20030201472A1 publication Critical patent/US20030201472A1/en
Priority to US10/810,748 priority patent/US7217887B2/en
Application granted granted Critical
Publication of US6734472B2 publication Critical patent/US6734472B2/en
Priority to US11/698,330 priority patent/US7436008B2/en
Assigned to SYNOPSYS, INC., A DELAWARE CORPORATION reassignment SYNOPSYS, INC., A DELAWARE CORPORATION MERGER (SEE DOCUMENT FOR DETAILS). Assignors: SYNPLICITY, INC.
Priority to US12/244,608 priority patent/US7774186B2/en
Priority to US12/848,979 priority patent/US8692297B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the field of the present invention pertains to circuitry to solve the problems caused by capacitive and inductive coupling in signals in an integrated circuit device. This particular issue of capacitive and inductive coupling in signals is becoming increasingly difficult as the industry advances and moves towards reduction in circuit device size (for example, from 0.25 uM technology to 0.18 uM, 0.15 uM, 0.13 uM and beyond).
  • ICs Integrated Circuits
  • VLSI Very Large Scale Integration
  • ULSI Ultra Large Scale Integration
  • Another prior art approach is to reduce the effective (R-L-C) impedance of the signal lines and thereby increasing the spacing between signal lines. In general, increasing the spacing between signal lines by three-fold, the coupling effect will only be reduced by fifty percent. This prior art approach is usually combined with the first prior art approach to minimize coupling and reduce signal to noise ratio. This approach is inconsistent with modern trends for circuit compactness.
  • Yet another prior art approach is to shield the signal lines by using either a supply voltage like VDD or ground. Utilizing this prior art approach, the shielding line (ground) would need to be wide enough (with low impedance) so that the shield itself will not begin to transfer the noise to other signal lines.
  • FIG. 1 These prior art approaches that tend to compensate by increasing signal strength combined with the prior art approach of providing a shielding line adjacent to signal line are shown in FIG. 1 .
  • the signal line 110 is routed along with the shielding line 120 , which is then utilized to shield the noise from a neighboring signal line.
  • the lengths of these signal and shield lines can become relatively long with respect to line thickness and thus can lead to high signal to noise ratio or cross-talk within a said circuit on a given substrate.
  • the present invention minimizes and reduces the signal coupling effects caused by capacitive and/or inductive signal coupling effects of routing in an integrated circuit device.
  • the present invention discloses a circuit composed of a power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing an integrated circuit device.
  • the shield mesh is included in addition to the power and ground grid typically provided in an IC.
  • the units of the shield mesh are placed such that they surround routing resources of the integrated circuit.
  • one embodiment of the present invention describes a method of routing a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Alternating mesh lines of VDD and VSS (or ground) are laid down and signal routing resources are placed in-between.
  • the shield mesh can be single or multi-layered.
  • the shield mesh is included in addition to a power grid and may be connected to the power grid.
  • VDSM Very Deep Sub-Micron
  • the signal lines become even more susceptible to capacitive and inductive coupling and noise from other neighboring signal lines.
  • Relatively long signal lines are routed in between fully connected power and ground shielding mesh which is typically generated by a router during the signal routing phase or during power mesh routing phase.
  • power mesh VDD
  • ground mesh VSS
  • Another embodiment of the invention describes a technique where the signals are shielded using the power and ground mesh for a gridless routing.
  • Another embodiment of the invention presents a multi-layer grid routing technique where signals are routed on an even grid and the power and ground lines are routed on an odd grid.
  • a similar embodiment of the invention represents grid routing technique where the signals are routed between layers N and N+1.
  • Another embodiment of the invention enables signals to be shielded by opposite power and ground grids on left, right, top and bottom.
  • Additional embodiments of the invention also include utilization of similar mesh utilized in standard cell and/or in the gate array routing area or any other area where any other signal line is to be shielded, thereby reducing the effective resistive or RC component of the power or grounding lines.
  • an embodiment of the present invention is drawn to an integrated circuit device comprising: a) a plurality of signal lines disposed within a substrate; b) a power grid disposed on the substrate and comprising: a plurality of power lines having a first thickness; and a plurality of ground lines having the first thickness, the power grid for supplying power and ground to circuitry of the substrate; and c) a shield mesh disposed on the substrate and comprising: a plurality of power lines having a second thickness; and a plurality of ground lines having the second thickness, wherein respective signal lines of the plurality of signal lines are disposed between a respective power line of the shield mesh and a respective ground line of the shield mesh, the shield mesh for reducing the effects of electronic cross-talk between nearby signal lines of the plurality of signal lines.
  • Embodiments include the above and wherein the power and ground lines of the shield mesh are alternatively disposed and parallel to each other within a single metal layer of the substrate.
  • inventions include an integrated circuit as described above generally and wherein the power and ground lines of the shield mesh are alternatively disposed in a first direction parallel to each other within a first metal layer of the substrate and wherein the power and ground lines of the shield mesh are also alternatively disposed in a second direction parallel to each other within a second metal layer of the substrate, the second metal layer being underneath the first metal layer and wherein the first and second directions are 90 degrees apart.
  • FIG. 1 shows a top view of a shielding line and a signal line.
  • FIG. 2 shows a top view of two layers indicating a grid layout according to a shield mesh of one embodiment of the present invention.
  • FIG. 3 shows a planar 2-D view of a shield mesh where the signal lines 1 and 2 of same thickness between VDD and VSS lines are on the same layer according to another embodiment of the present invention.
  • FIG. 4 shows a top view of a shield mesh comprising of two adjacent layers depicting signal lines and VDD and VSS lines on each layer and the appropriate vias between the two layers.
  • FIG. 5 shows a vertical cross-sectional view of a shield mesh having several layers with signal lines, VDD and VSS lines with their appropriate vias on odd/even grid tracks.
  • FIG. 6 shows a top view of two adjacent layers of a shield mesh indicating signals, the VDD and VSS lines in a gridless routing technique with their appropriate vias.
  • FIG. 7 shows a vertical cross-sectional view of a gridless routing embodiment of the shield mesh showing the signal lines with VDD and VSS lines and their appropriate vias.
  • FIG. 8 shows a shielding mesh within a power grid on said substrate according to one embodiment of the present invention.
  • FIG. 9 depicts the shielding mesh within a channel on said substrate and within a block on said substrate according to another embodiment of the present invention.
  • FIG. 10 shows a block diagram depicting a process from logic synthesis to placer to router to tape.
  • the present invention describes a circuit device that comprises a plurality of signal lines of given thickness disposed within a substrate that will in addition to providing power to the circuitry of said substrate circuit, will also perform as a shielding mesh that is utilized to reduce the effects of cross-talk between nearby signal lines of said plurality of signal lines within said circuit
  • the signal line 110 is routed along with the shielding line 120 , which is then utilized to shield the noise from a neighboring signal line.
  • the lengths of these signal and shield lines can become relatively long (up to 100 uM) with respect to line thickness (for example: as short as 0.13 uM) and thus can lead to high signal to noise ratio or cross-talk within a said circuit on a given substrate.
  • FIG. 2 depicts a single signal line, 210 , which is shielded on both sides by utilizing a three dimensional shield mesh of alternating VDD and VSS lines.
  • these alternating VDD and VSS lines are running perpendicular (at 90 degrees) from the previous layer, for example: metal 3 , and are further connected at junctions formed by VIA3, 230 , to form a three dimensional shield mesh of VDD and VSS shield lines for signal line 220 .
  • the shield mesh is included on an IC in addition to a power grid used to supply power and ground to the circuitry.
  • the relative segment distance of the VDD and VSS lines may be reduced by as much as 0.94 uM. Reducing the segment length of VDD and VSS reduces their effective RC component and thereby reducing the coupling effects of noise.
  • FIG. 3 depicts a planar, perspective view of the shield mesh where signal lines 310 and 320 of same thickness are interwoven between alternating VDD and VSS lines on the same layer and of same thickness. Therefore, FIG. 3 illustrates a single layer embodiment of the shield mesh of the present invention. According to an embodiment of shield mesh of the present invention, FIG. 3 illustrates the fact that the due to close proximity of the shielding lines coupled with the fact that these shielding lines will consist of relatively short segments, it can be derived that the effective RC impedance is reduced and thereby the signal coupling between signal lines 310 and 320 is further reduced. According to another embodiment, FIG. 3 also illustrates that the signal lines 310 and 320 are isolated with alternating VDD and VSS shield mesh of the same thickness; depending on technology used, thickness can vary from 0.25 uM to 0.13 uM and even smaller as the industry trends toward further reduction.
  • FIG. 4 is a top view of shield mesh embodiment 400 showing two adjacent substrate layers, 405 A and 405 B, depicting the signal lines ( 410 , 420 and 430 ), alternating VDD and VSS lines on each layer and the appropriate vias between the two layers utilizing a grid layout.
  • Each via provides layer connections and also reduces the segment size of the shielding mesh and thereby reduces the effective R-C resistance according to one embodiment of the present invention.
  • layer N 405 A
  • the signal lines 410 , 420 and 430 are on odd grid tracks
  • the VDD and VSS lines will be on even grid tracks, and vice-versa.
  • the VDD and VSS lines will alternately be on odd grid tracks and vice-versa.
  • Multi-layer routing assignment to signals and shields for the vertical space, the track assignment should be done so that there would not be signal tracks directly on top of one another to avoid top bottom coupling. For example, if signals on layer N are on odd tracks, signals on layer N+2, which has the same routing direction as layer N, would be routed on even tracks. This strategy would enable the signals to be shielded by opposite power/ground both on the left/right, and on top/bottom. Thereby, further reducing the segment lengths and increasing the effective isolation between signal lines to reduce noise coupling.
  • FIG. 5 shows a vertical cross-sectional view of another embodiment 500 of the present invention, that depicts the three dimensional aspect of the shield grid mesh.
  • Several layers, N through N+7, are shown with signals and alternating VDD and VSS lines and their appropriate vias on odd/even grid tracks.
  • the cross-sectional cuts are taken across signal lines ( 510 and 520 ) and VDDNSS lines ( 530 and 540 , respectively).
  • the VDD, signal and VSS lines are also alternatively arranged on odd, even tracks as described in FIG. 4 . Therefore, the shield mesh of FIG. 5 is grid line aligned.
  • Another embodiment of the present invention connects adjacent layers by means of vias as shown in elements 560 A through 560 N. According to another embodiment of the present invention, this multi-layer shielding mesh reduces each component length and thereby according to one embodiment of the present invention, further reduces the coupling effects.
  • FIG. 6 shows another embodiment, 600 , of the present invention which depicts a top view of two adjacent layers indicating the signal and alternating VDD and VSS lines in a gridless routing shield mesh with their appropriate vias.
  • signal 640 is routed on two separate layers and is shielded by a gridless mesh, which includes adjacent VDD ( 620 ABB) and VSS ( 630 ABB) lines on one layer.
  • the same 640 signal line is shielded by VDD ( 620 B) and VSS ( 630 A) lines on another adjacent layer that are 90 degrees alignment to the first layer.
  • Signal line, 640 in this example is routed again on the previous layer, again 90 degrees apart, and is shielded by VDD ( 620 ABA) and VSS ( 630 ABA) lines.
  • signal lines 610 A, 610 B and 610 C can also be traced to have shielding on both adjacent (side-by-side) layers as well as vertical (top-to-bottom) layers.
  • This multi-layer shielding mesh reduces each component length and thereby according to one embodiment of the present invention, further reduces the coupling effects in a gridless routing technique.
  • FIG. 7 shows a vertical cross-sectional view of a gridless shielding mesh showing signals and alternating VDD and VSS lines with their appropriate vias for connecting between adjacent layers.
  • vias 710 and 720 the distance between segment size is not bound by grid width.
  • This gridless example can again be seen in vias 730 and 740 .
  • vias of varying sizes can be utilized in as close proximity as possible without dependency of grid size. Utilizing the close proximity of the vias, relative segment lengths of each signal, VDD or VSS shielding mesh is reduced.
  • the shielding mesh is utilized to provide a path for connecting an integrated circuit device to the main power grid. As shown in FIG. 7, line 740 is connected using two short segments, 710 and 720 to tap to the shielding mesh of either VDD or VSS which are in turn connected to the main power grid.
  • FIG. 8 shows an integrated circuit with a shielding mesh ( 820 ) and a power grid ( 810 ) on a substrate.
  • the shielding mesh is utilized to reduce the capacitive and inductive effects of cross-talk while the power grid is provided to deliver power and ground to IC circuits.
  • the lines of the power grid are much larger than the VSS and VDD lines of the shielding mesh, which are sized to be the size of the signal lines.
  • the size difference between the shielding mesh lines and the true power grid lines may vary by factor of 2 to factor of 10.
  • the shielding mesh in function, reduces the effective RC component of the lines being connected to. This in turn reduces the noise and coupling effect and therefore, the shielding mesh can be deployed on any Substrate area where routing resources are used.
  • FIG. 9 depicts embodiment 900 , which depicts a shielding mesh in the routing channel ( 910 ) between blocks on a substrate and also within a block ( 920 ) of a substrate.
  • the shielding mesh due to relative small segment lengths of the shielding mesh, the shielding mesh further reduces the effective RC component of the routing line thereby reducing the noise and coupling effects caused by cross-talk between signal lines.
  • FIG. 10 illustrates the flow chart of steps for the process, 1000 , of an EDA tool in which the shielding mesh of the present invention may be introduced.
  • initial code is generally written using HDL, step 1010 , (for example) after which logic synthesis, step 1020 , is performed.
  • Placement of a power grid is next performed as shown in block 1030 .
  • shielding mesh as outlined in one embodiment of the present invention can be introduced as shown at point 1040 .
  • the router, 1050 will route the designed circuit and handle the shielding mesh within its parameters.
  • the design is put on tape ( 1060 ).
  • shielding mesh it is important to note that it is not necessary to introduce the shielding mesh on a substrate grid.
  • another embodiment of the present invention allows for said shielding mesh to be introduced in a gridless design on a given substrate.
  • router 1050
  • This fully connected power and ground shielding mesh can be used when it is important to remove capacitive and inductive coupling.
  • the main sources for this mesh would be from the main power grid trunks or independent power and ground trunks dedicated for shielding where they are relatively noiseless.
  • the shielding mesh can also be used in standard cell or gate array routing area, routing channels or routing channels on top of hard macros, data bus routing, control bus routing, address bus routing, analog signal routing, clocks and clock bus routing, or any other signal lines.

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Abstract

A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid. A similar embodiment represents grid routing technique where the signals are routed between layers N and N+1. Another embodiment enables signals to be shielded by opposite power and ground grids on left, right, top and bottom. Additional embodiments also include utilization of similar mesh utilized in standard cell and/or in the gate array routing area or any other area where any other signal line is to be shielded.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of the present invention pertains to circuitry to solve the problems caused by capacitive and inductive coupling in signals in an integrated circuit device. This particular issue of capacitive and inductive coupling in signals is becoming increasingly difficult as the industry advances and moves towards reduction in circuit device size (for example, from 0.25 uM technology to 0.18 uM, 0.15 uM, 0.13 uM and beyond).
2. Related Art
With their growth in commercial markets and consumer demands for smaller Integrated Circuits (ICs—which are used in numerous applications such as cellular phones, wristwatch cameras, and hand-held organizers just to name a few) increase, IC size requirement trends continue towards a small form factor and lowered power consumption. As these IC size requirements shrink, semiconductor manufacturers are forced to design circuits at a much smaller level than in the past. Previously, as the industry moved from Very Large Scale Integration (VLSI) to Ultra Large Scale Integration (ULSI), the relative capacitive and inductive coupling of the circuit itself was not realized to be as critical of an issue.
However, as the semiconductor industry designs and implements circuitry on sub-micron level technology (where spacing between circuitry lines is less than 10−6 m) and beyond, the capacitive and inductive coupling of the signal lines within the circuitry itself is realized to be a critical problem for designers. As circuit size becomes smaller and the relative distances for signal lines becomes longer, the problem of coupling and or cross talk between signal lines and ground or power lines becomes more evident. Furthermore, as the signal line to ground coupling and/or other signal lines becomes stronger, the signal to noise ratio for given signals increases proportionally. This particular issue of capacitive and inductive coupling in signals is becoming increasingly difficult as the industry advances and moves towards reduction in circuit device size (for example, from 0.25 uM technology to 0.18 uM, 0.15 uM, 0.13 uM and beyond).
One prior art approach to minimize the signal to noise ratio (or capacitive and inductive coupling), is to strengthen the signal drive level. By increasing the signal strength, the total signal to noise ratio is reduced. Unfortunately, to increase the signal strength, the device must also be supplied higher power. This solution is inconsistent with the modern trend of reducing power consumption in ICs for heat issues, portability issues and environmental issues.
In addition to higher power requirement, this prior art approach does not eliminate the coupling issue.
Another prior art approach is to reduce the effective (R-L-C) impedance of the signal lines and thereby increasing the spacing between signal lines. In general, increasing the spacing between signal lines by three-fold, the coupling effect will only be reduced by fifty percent. This prior art approach is usually combined with the first prior art approach to minimize coupling and reduce signal to noise ratio. This approach is inconsistent with modern trends for circuit compactness.
Yet another prior art approach is to shield the signal lines by using either a supply voltage like VDD or ground. Utilizing this prior art approach, the shielding line (ground) would need to be wide enough (with low impedance) so that the shield itself will not begin to transfer the noise to other signal lines.
These prior art approaches that tend to compensate by increasing signal strength combined with the prior art approach of providing a shielding line adjacent to signal line are shown in FIG. 1. As shown in this depiction, 100, the signal line 110 is routed along with the shielding line 120, which is then utilized to shield the noise from a neighboring signal line. For sub-micron technologies, the lengths of these signal and shield lines can become relatively long with respect to line thickness and thus can lead to high signal to noise ratio or cross-talk within a said circuit on a given substrate.
Therefore, a need exists for reducing the capacitive and inductive signal coupling effects of routing resources of an IC device.
SUMMARY OF THE INVENTION
Accordingly, the present invention minimizes and reduces the signal coupling effects caused by capacitive and/or inductive signal coupling effects of routing in an integrated circuit device. These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
The present invention discloses a circuit composed of a power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing an integrated circuit device. The shield mesh is included in addition to the power and ground grid typically provided in an IC. The units of the shield mesh are placed such that they surround routing resources of the integrated circuit. Specifically, one embodiment of the present invention describes a method of routing a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Alternating mesh lines of VDD and VSS (or ground) are laid down and signal routing resources are placed in-between. The shield mesh can be single or multi-layered. The shield mesh is included in addition to a power grid and may be connected to the power grid.
As Very Deep Sub-Micron (VDSM) technologies continue to reduce in size (for example from 0.18 uM, 0.15 uM, 0.13 uM, 0.11 uM and beyond), the signal lines become even more susceptible to capacitive and inductive coupling and noise from other neighboring signal lines. Relatively long signal lines are routed in between fully connected power and ground shielding mesh which is typically generated by a router during the signal routing phase or during power mesh routing phase. In one embodiment, leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device.
Another embodiment of the invention describes a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment of the invention presents a multi-layer grid routing technique where signals are routed on an even grid and the power and ground lines are routed on an odd grid. A similar embodiment of the invention represents grid routing technique where the signals are routed between layers N and N+1. While another embodiment of the invention enables signals to be shielded by opposite power and ground grids on left, right, top and bottom. Additional embodiments of the invention also include utilization of similar mesh utilized in standard cell and/or in the gate array routing area or any other area where any other signal line is to be shielded, thereby reducing the effective resistive or RC component of the power or grounding lines.
More specifically, an embodiment of the present invention is drawn to an integrated circuit device comprising: a) a plurality of signal lines disposed within a substrate; b) a power grid disposed on the substrate and comprising: a plurality of power lines having a first thickness; and a plurality of ground lines having the first thickness, the power grid for supplying power and ground to circuitry of the substrate; and c) a shield mesh disposed on the substrate and comprising: a plurality of power lines having a second thickness; and a plurality of ground lines having the second thickness, wherein respective signal lines of the plurality of signal lines are disposed between a respective power line of the shield mesh and a respective ground line of the shield mesh, the shield mesh for reducing the effects of electronic cross-talk between nearby signal lines of the plurality of signal lines. Embodiments include the above and wherein the power and ground lines of the shield mesh are alternatively disposed and parallel to each other within a single metal layer of the substrate.
Other embodiments include an integrated circuit as described above generally and wherein the power and ground lines of the shield mesh are alternatively disposed in a first direction parallel to each other within a first metal layer of the substrate and wherein the power and ground lines of the shield mesh are also alternatively disposed in a second direction parallel to each other within a second metal layer of the substrate, the second metal layer being underneath the first metal layer and wherein the first and second directions are 90 degrees apart.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example and not by way of limitations in the figures accompanying drawings in which like reference numerals refers to similar elements and in which:
FIG. 1 shows a top view of a shielding line and a signal line.
FIG. 2 shows a top view of two layers indicating a grid layout according to a shield mesh of one embodiment of the present invention.
FIG. 3 shows a planar 2-D view of a shield mesh where the signal lines 1 and 2 of same thickness between VDD and VSS lines are on the same layer according to another embodiment of the present invention.
FIG. 4 shows a top view of a shield mesh comprising of two adjacent layers depicting signal lines and VDD and VSS lines on each layer and the appropriate vias between the two layers.
FIG. 5 shows a vertical cross-sectional view of a shield mesh having several layers with signal lines, VDD and VSS lines with their appropriate vias on odd/even grid tracks.
FIG. 6 shows a top view of two adjacent layers of a shield mesh indicating signals, the VDD and VSS lines in a gridless routing technique with their appropriate vias.
FIG. 7 shows a vertical cross-sectional view of a gridless routing embodiment of the shield mesh showing the signal lines with VDD and VSS lines and their appropriate vias.
FIG. 8 shows a shielding mesh within a power grid on said substrate according to one embodiment of the present invention.
FIG. 9 depicts the shielding mesh within a channel on said substrate and within a block on said substrate according to another embodiment of the present invention.
FIG. 10 shows a block diagram depicting a process from logic synthesis to placer to router to tape.
DETAILED DESCRIPTION OF THE INVENTION
Reference will now be made in detail to the embodiments of the invention, a shield power and ground mesh to remove both capacitive and inductive signal coupling effects of routing in ASIC chips, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to obscure aspects of the present invention unnecessarily.
The present invention describes a circuit device that comprises a plurality of signal lines of given thickness disposed within a substrate that will in addition to providing power to the circuitry of said substrate circuit, will also perform as a shielding mesh that is utilized to reduce the effects of cross-talk between nearby signal lines of said plurality of signal lines within said circuit
As shown in depiction 100 of FIG. 1, the signal line 110 is routed along with the shielding line 120, which is then utilized to shield the noise from a neighboring signal line. As discussed earlier, for sub-micron technologies, the lengths of these signal and shield lines can become relatively long (up to 100 uM) with respect to line thickness (for example: as short as 0.13 uM) and thus can lead to high signal to noise ratio or cross-talk within a said circuit on a given substrate.
According to one embodiment of the present invention, 200, FIG. 2 depicts a single signal line, 210, which is shielded on both sides by utilizing a three dimensional shield mesh of alternating VDD and VSS lines. On another layer, e.g. metal 4, these alternating VDD and VSS lines are running perpendicular (at 90 degrees) from the previous layer, for example: metal 3, and are further connected at junctions formed by VIA3, 230, to form a three dimensional shield mesh of VDD and VSS shield lines for signal line 220. In accordance with one embodiment of the present invention it is appreciated that the shield mesh is included on an IC in addition to a power grid used to supply power and ground to the circuitry. According to another embodiment, for example in a 0.25 uM technology, the relative segment distance of the VDD and VSS lines may be reduced by as much as 0.94 uM. Reducing the segment length of VDD and VSS reduces their effective RC component and thereby reducing the coupling effects of noise.
According to another embodiment, 300, of the present invention, FIG. 3 depicts a planar, perspective view of the shield mesh where signal lines 310 and 320 of same thickness are interwoven between alternating VDD and VSS lines on the same layer and of same thickness. Therefore, FIG. 3 illustrates a single layer embodiment of the shield mesh of the present invention. According to an embodiment of shield mesh of the present invention, FIG. 3 illustrates the fact that the due to close proximity of the shielding lines coupled with the fact that these shielding lines will consist of relatively short segments, it can be derived that the effective RC impedance is reduced and thereby the signal coupling between signal lines 310 and 320 is further reduced. According to another embodiment, FIG. 3 also illustrates that the signal lines 310 and 320 are isolated with alternating VDD and VSS shield mesh of the same thickness; depending on technology used, thickness can vary from 0.25 uM to 0.13 uM and even smaller as the industry trends toward further reduction.
FIG. 4 is a top view of shield mesh embodiment 400 showing two adjacent substrate layers, 405A and 405B, depicting the signal lines (410, 420 and 430), alternating VDD and VSS lines on each layer and the appropriate vias between the two layers utilizing a grid layout. Each via provides layer connections and also reduces the segment size of the shielding mesh and thereby reduces the effective R-C resistance according to one embodiment of the present invention. It is important to note that on layer N, 405A, if the signal lines 410, 420 and 430 are on odd grid tracks, then the VDD and VSS lines will be on even grid tracks, and vice-versa. Like wise, on layer N+1, 405B, if the signal lines 440, 450 and 460 are on even tracks, then the VDD and VSS lines will alternately be on odd grid tracks and vice-versa.
Multi-layer routing assignment to signals and shields: for the vertical space, the track assignment should be done so that there would not be signal tracks directly on top of one another to avoid top bottom coupling. For example, if signals on layer N are on odd tracks, signals on layer N+2, which has the same routing direction as layer N, would be routed on even tracks. This strategy would enable the signals to be shielded by opposite power/ground both on the left/right, and on top/bottom. Thereby, further reducing the segment lengths and increasing the effective isolation between signal lines to reduce noise coupling.
FIG. 5 shows a vertical cross-sectional view of another embodiment 500 of the present invention, that depicts the three dimensional aspect of the shield grid mesh. Several layers, N through N+7, are shown with signals and alternating VDD and VSS lines and their appropriate vias on odd/even grid tracks. As seen FIG. 5, the cross-sectional cuts are taken across signal lines (510 and 520) and VDDNSS lines (530 and 540, respectively). As shown on layer N, layer N+2, layer N+4 and N+6, the VDD, signal and VSS lines are also alternatively arranged on odd, even tracks as described in FIG. 4. Therefore, the shield mesh of FIG. 5 is grid line aligned. Another embodiment of the present invention connects adjacent layers by means of vias as shown in elements 560A through 560N. According to another embodiment of the present invention, this multi-layer shielding mesh reduces each component length and thereby according to one embodiment of the present invention, further reduces the coupling effects.
FIG. 6 shows another embodiment, 600, of the present invention which depicts a top view of two adjacent layers indicating the signal and alternating VDD and VSS lines in a gridless routing shield mesh with their appropriate vias. As shown, signal 640 is routed on two separate layers and is shielded by a gridless mesh, which includes adjacent VDD (620ABB) and VSS (630ABB) lines on one layer. The same 640 signal line is shielded by VDD (620B) and VSS (630A) lines on another adjacent layer that are 90 degrees alignment to the first layer. Signal line, 640, in this example is routed again on the previous layer, again 90 degrees apart, and is shielded by VDD (620ABA) and VSS (630ABA) lines. Likewise, according to another embodiment of the present invention, signal lines 610A, 610B and 610C can also be traced to have shielding on both adjacent (side-by-side) layers as well as vertical (top-to-bottom) layers. This multi-layer shielding mesh reduces each component length and thereby according to one embodiment of the present invention, further reduces the coupling effects in a gridless routing technique.
According to another embodiment, 700, of the present invention, FIG. 7 shows a vertical cross-sectional view of a gridless shielding mesh showing signals and alternating VDD and VSS lines with their appropriate vias for connecting between adjacent layers. As shown in vias 710 and 720, the distance between segment size is not bound by grid width. This gridless example can again be seen in vias 730 and 740. According to another embodiment of the present invention, vias of varying sizes can be utilized in as close proximity as possible without dependency of grid size. Utilizing the close proximity of the vias, relative segment lengths of each signal, VDD or VSS shielding mesh is reduced. According to another embodiment of the present invention, the shielding mesh is utilized to provide a path for connecting an integrated circuit device to the main power grid. As shown in FIG. 7, line 740 is connected using two short segments, 710 and 720 to tap to the shielding mesh of either VDD or VSS which are in turn connected to the main power grid.
According to embodiment, 800, FIG. 8 shows an integrated circuit with a shielding mesh (820) and a power grid (810) on a substrate. The shielding mesh is utilized to reduce the capacitive and inductive effects of cross-talk while the power grid is provided to deliver power and ground to IC circuits. The lines of the power grid are much larger than the VSS and VDD lines of the shielding mesh, which are sized to be the size of the signal lines. According to this embodiment, the size difference between the shielding mesh lines and the true power grid lines may vary by factor of 2 to factor of 10. However, due to their relative small segment lengths, the shielding mesh in function, reduces the effective RC component of the lines being connected to. This in turn reduces the noise and coupling effect and therefore, the shielding mesh can be deployed on any Substrate area where routing resources are used.
FIG. 9 depicts embodiment 900, which depicts a shielding mesh in the routing channel (910) between blocks on a substrate and also within a block (920) of a substrate. As described in FIG. 8, due to relative small segment lengths of the shielding mesh, the shielding mesh further reduces the effective RC component of the routing line thereby reducing the noise and coupling effects caused by cross-talk between signal lines.
FIG. 10 illustrates the flow chart of steps for the process, 1000, of an EDA tool in which the shielding mesh of the present invention may be introduced. As shown in this embodiment of the present invention, initial code is generally written using HDL, step 1010, (for example) after which logic synthesis, step 1020, is performed. Placement of a power grid is next performed as shown in block 1030. For example where substrate grid is utilized, shielding mesh as outlined in one embodiment of the present invention can be introduced as shown at point 1040. After this point, the router, 1050, will route the designed circuit and handle the shielding mesh within its parameters. At this point, the design is put on tape (1060).
However, it is important to note that it is not necessary to introduce the shielding mesh on a substrate grid. As described earlier, another embodiment of the present invention allows for said shielding mesh to be introduced in a gridless design on a given substrate. For gridless routing, router (1050) can introduce the shielding mesh into the said substrate.
This fully connected power and ground shielding mesh can be used when it is important to remove capacitive and inductive coupling. The main sources for this mesh would be from the main power grid trunks or independent power and ground trunks dedicated for shielding where they are relatively noiseless.
The shielding mesh can also be used in standard cell or gate array routing area, routing channels or routing channels on top of hard macros, data bus routing, control bus routing, address bus routing, analog signal routing, clocks and clock bus routing, or any other signal lines.
With the addition of this fully connected power and ground shielding mesh, the automated VDSM chip routing can be much more worry-free, and almost unpredictable coupling errors can be virtually eradicated by the present invention.

Claims (20)

What is claimed is:
1. An integrated circuit device comprising:
a) a plurality of signal lines disposed on a substrate;
b) a power grid disposed on said substrate and comprising:
a plurality of power lines having a first thickness; and
a plurality of ground lines having said first thickness, said power grid for
supplying power and ground to circuitry of said substrate; and
c) a shield mesh disposed on said substrate and comprising:
a plurality of power lines having a second thickness; and
a plurality of ground lines having said second thickness,
wherein each of said plurality of signal lines is disposed between an adjacent power line of said shield mesh and an adjacent ground line of said shield mesh on a layer of said substrate, said shield mesh for reducing the effects of electronic cross-talk between nearby signal lines of said plurality of signal lines;
wherein an average line spacing of said power grid is substantially larger than an average line spacing of said shield mesh.
2. An integrated circuit as described in claim 1 wherein said power and ground lines of said shield mesh are alternatively disposed and parallel to each other within a single metal layer on said substrate.
3. An integrated circuit as described in claim 1 wherein said power and ground lines of said shield mesh are alternatively disposed in a first direction parallel to each other within a first metal layer of said substrate and wherein said power and ground lines of said shield mesh are also alternatively disposed in a second direction parallel to each other within a second metal layer of said substrate, said second metal layer being underneath said first metal layer and wherein said first and second directions are 90 degrees apart.
4. An integrated circuit as described in claim 1 wherein said electronic cross-talk comprises capacitive and inductive coupling.
5. An integrated circuit as described in claim 1 wherein said second thickness is less than said first thickness.
6. An integrated circuit as described in claim 5 wherein said signal lines of said plurality of signal lines are as thick as said second thickness.
7. An integrated circuit as described in claim 6 wherein said power and ground lines of said shield mesh are aligned with substrate grid lines.
8. An integrated circuit device comprising:
a) a plurality of signal lines disposed on a substrate;
b) a power grid disposed on said substrate and comprising:
a plurality of first lines having a first thickness and for supplying a first voltage level; and
a plurality of second lines having said first thickness and for supplying a second voltage level, said power grid for supplying power to circuitry of said substrate;
c) a shield mesh disposed on said substrate and comprising:
a plurality of third lines having a second thickness and for supplying said first voltage level; and
a plurality of fourth lines for supplying said second voltage level,
wherein each of said plurality of signal lines is disposed between and adjacent to a respective one of said third lines of said shield mesh and a respective one of said fourth lines of said shield mesh on a layer of said substrate, said shield mesh for reducing the effects of electronic cross-talk between nearby signal lines of said plurality of signal lines;
wherein an average line spacing of said power grid is substantially larger than an average line spacing of said shield mesh.
9. An integrated circuit as described in claim 8 wherein said third and fourth lines of said shield mesh are alternatively disposed and parallel to each other within a single metal layer on said substrate.
10. An integrated circuit as described in claim 8 wherein said electronic cross-talk comprises capacitive and inductive coupling.
11. An integrated circuit as described in claim 8 wherein said shield mesh consumes substantially 50 percent of the available area of said substrate.
12. An integrated circuit as described in claim 8 wherein said second thickness is less than said first thickness.
13. An integrated circuit as described in claim 12 wherein said signal lines of said plurality of signal lines are as thick as said second thickness.
14. An integrated circuit as described in claim 13 wherein said third and fourth lines of said shield mesh are aligned with substrate grid lines.
15. An integrated circuit as described in claim 8 wherein said third and fourth lines of said shield mesh are alternatively disposed in a first direction parallel to each other within a first metal layer on said substrate and wherein said third and fourth lines of said shield mesh are also alternatively disposed in a second direction parallel to each other within a second metal layer on said substrate, said second metal layer being underneath said first metal layer and wherein said first and second directions are 90 degrees apart.
16. An integrated circuit as described in claim 15 wherein third lines of said first metal layer and third lines of said second metal layer are coupled together using first connections.
17. An integrated circuit as described in claim 16 wherein fourth lines of said first metal layer and fourth lines of said second metal layer are coupled together using second connections.
18. An integrated circuit device comprising:
a) a plurality of signal lines disposed on a substrate;
b) a power grid disposed on said substrate and comprising:
a plurality of power lines having a first thickness; and
a plurality of ground lines having said first thickness, said power grid for supplying power and ground to circuitry of said substrate; and
c) a shield mesh disposed on said substrate and comprising:
a plurality of first lines having a second thickness; and
a plurality of second lines having said second thickness,
wherein each of said plurality of signal lines is disposed between and adjacent to a respective one of said first linen of said shield mesh and a respective one of said second lines of said shield mesh on a layer of said substrate, said shield mesh for reducing the effects of electronic cross-talk between nearby signal lines of said plurality of signal lines;
wherein an average line spacing of said power grid is substantially larger than an average line spacing of said shield mesh.
19. An integrated circuit as described in claim 18 wherein said first and second lines of said shield mesh are alternatively disposed and parallel to each other within a single metal layer on said substrate.
20. An integrated circuit as described in claim 18 wherein said first and second lines of said shield mesh are alternatively disposed in a first direction parallel to each other within a first metal layer on said substrate and wherein said first and second lines of said shield mesh are also alternatively disposed in a second direction parallel to each other within a second metal layer on said substrate, said second metal layer being underneath said first metal layer and wherein said first and second directions are 90 degrees apart.
US10/132,996 2002-04-25 2002-04-25 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device Expired - Lifetime US6734472B2 (en)

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US10/132,996 US6734472B2 (en) 2002-04-25 2002-04-25 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
EP02761202A EP1497864B1 (en) 2002-04-25 2002-07-29 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
AU2002326482A AU2002326482A1 (en) 2002-04-25 2002-07-29 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
PCT/US2002/024267 WO2003092070A2 (en) 2002-04-25 2002-07-29 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
JP2004500331A JP2005524231A (en) 2002-04-25 2002-07-29 Feed and ground shield mesh to eliminate both capacitive and inductive signal coupling effects of routing in integrated circuit devices
DE60227290T DE60227290D1 (en) 2002-04-25 2002-07-29 POWER SUPPLY AND MASK SHIELDING NETWORK FOR ELIMINATING CAPACITIVE AND INDUCTIVE SIGNAL COUPLING EFFECTS ON SIGNALING LINES IN INTEGRATED CIRCUITS
TW091118025A TWI285953B (en) 2002-04-25 2002-08-09 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
US10/810,748 US7217887B2 (en) 2002-04-25 2004-03-26 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
US11/698,330 US7436008B2 (en) 2002-04-25 2007-01-25 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
US12/244,608 US7774186B2 (en) 2002-04-25 2008-10-02 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
US12/848,979 US8692297B2 (en) 2002-04-25 2010-08-02 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device

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US10/810,748 Expired - Lifetime US7217887B2 (en) 2002-04-25 2004-03-26 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
US11/698,330 Expired - Lifetime US7436008B2 (en) 2002-04-25 2007-01-25 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
US12/244,608 Expired - Lifetime US7774186B2 (en) 2002-04-25 2008-10-02 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
US12/848,979 Expired - Lifetime US8692297B2 (en) 2002-04-25 2010-08-02 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device

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US11/698,330 Expired - Lifetime US7436008B2 (en) 2002-04-25 2007-01-25 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
US12/244,608 Expired - Lifetime US7774186B2 (en) 2002-04-25 2008-10-02 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
US12/848,979 Expired - Lifetime US8692297B2 (en) 2002-04-25 2010-08-02 Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device

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Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040145033A1 (en) * 2002-07-29 2004-07-29 Mcelvain Kenneth S. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US20050076319A1 (en) * 2003-10-03 2005-04-07 Chow Shau-Lim Stan Pin assignment in block-based integrated circuit design methodologies
US20060015835A1 (en) * 2004-06-04 2006-01-19 Faraday Technology Corp. Placement method for decoupling capacitors
US20060095872A1 (en) * 2002-07-29 2006-05-04 Mcelvain Kenneth S Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US7131096B1 (en) 2004-06-01 2006-10-31 Pulsic Limited Method of automatically routing nets according to current density rules
US20060288323A1 (en) * 2005-06-21 2006-12-21 Pulsic Limited High-Speed Shape-Based Router
US20060294488A1 (en) * 2005-06-24 2006-12-28 Pulsic Limited Integrated Circuit Routing and Compaction
US20070106969A1 (en) * 2005-11-08 2007-05-10 Pulsic Limited Method of Automatically Routing Nets According to Parasitic Constraint Rules
US20070136713A1 (en) * 2002-08-09 2007-06-14 Asmus Hetzel Method and Apparatus for Routing
US7257797B1 (en) 2004-06-07 2007-08-14 Pulsic Limited Method of automatic shape-based routing of interconnects in spines for integrated circuit design
US20080028352A1 (en) * 2004-06-01 2008-01-31 Pulsic Limited Automatically Routing Nets with Variable Spacing
US20080042284A1 (en) * 2006-03-17 2008-02-21 Tatsuya Naruse Semiconductor integrated circuit and the method of designing the layout
US7373628B1 (en) 2004-06-01 2008-05-13 Pulsic Limited Method of automatically routing nets using a Steiner tree
US7519927B1 (en) 2008-07-02 2009-04-14 International Business Machines Corporation Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations
US7571408B1 (en) * 2005-03-09 2009-08-04 Cadence Design Systems, Inc. Methods and apparatus for diagonal route shielding
US7694258B1 (en) 2005-08-01 2010-04-06 Cadence Design Systems, Inc. Method and apparatus for inserting metal fill in an integrated circuit (“IC”) layout
US7784010B1 (en) 2004-06-01 2010-08-24 Pulsic Limited Automatic routing system with variable width interconnect
US20110241216A1 (en) * 2010-03-31 2011-10-06 Renesas Electronics Corporation Semiconductor device
US8458636B1 (en) 2009-03-18 2013-06-04 Pulsic Limited Filling vacant areas of an integrated circuit design
US8607180B2 (en) 2012-05-09 2013-12-10 Lsi Corporation Multi-pass routing to reduce crosstalk
US9219039B2 (en) 2011-11-30 2015-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Interposer and semiconductor package with noise suppression features
US20160064369A1 (en) * 2014-09-02 2016-03-03 Socionext Inc. Semiconductor device
US10652998B2 (en) 2018-09-21 2020-05-12 International Business Machines Corporation Multilayer ceramic electronic package with modulated mesh topology
US11071197B2 (en) 2018-09-21 2021-07-20 International Business Machines Corporation Multilayer ceramic electronic package with modulated mesh topology and alternating rods

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734472B2 (en) 2002-04-25 2004-05-11 Synplicity, Inc. Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device
JP4195821B2 (en) * 2003-02-26 2008-12-17 富士通マイクロエレクトロニクス株式会社 Semiconductor integrated circuit design method
TW594965B (en) * 2003-09-10 2004-06-21 Goyatek Technology Inc Power supply layout structure of integrated circuit
WO2006059547A1 (en) * 2004-12-03 2006-06-08 Rohm Co., Ltd Semiconductor device
EP2148237B1 (en) * 2007-05-18 2013-05-15 Sharp Kabushiki Kaisha Display device
EP2149914B1 (en) 2007-05-18 2013-07-10 Sharp Kabushiki Kaisha Display device
WO2008143213A1 (en) * 2007-05-18 2008-11-27 Sharp Kabushiki Kaisha Display device
JP2009054760A (en) * 2007-08-27 2009-03-12 Nec Electronics Corp Semiconductor device, wiring designing method, wiring designing apparatus, and program
US7861204B2 (en) * 2007-12-20 2010-12-28 International Business Machines Corporation Structures including integrated circuits for reducing electromigration effect
US7870251B2 (en) * 2008-01-10 2011-01-11 At&T Intellectual Property I, L.P. Devices, methods, and computer program products for real-time resource capacity management
KR20090079428A (en) * 2008-01-17 2009-07-22 삼성전자주식회사 Substrate having structures for suppressing power and ground plane noise, and electronic system including the substrate
US8074195B2 (en) * 2008-06-27 2011-12-06 Freescale Semiconductor, Inc. System and method for evaluating a dynamic power consumption of a block
KR101211683B1 (en) * 2008-12-31 2012-12-12 에스케이하이닉스 주식회사 Semiconductor integrated circuit
US8011950B2 (en) 2009-02-18 2011-09-06 Cinch Connectors, Inc. Electrical connector
US8288657B2 (en) * 2009-10-12 2012-10-16 International Business Machines Corporation Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules
US8803320B2 (en) * 2010-10-28 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and fabrication methods thereof
JP5603768B2 (en) * 2010-12-28 2014-10-08 株式会社東芝 Semiconductor integrated circuit wiring method, semiconductor circuit wiring apparatus, and semiconductor integrated circuit
US8847393B2 (en) * 2011-02-28 2014-09-30 Freescale Semiconductor, Inc. Vias between conductive layers to improve reliability
JP2012222151A (en) * 2011-04-08 2012-11-12 Panasonic Corp Semiconductor integrated circuit device
US8356262B1 (en) * 2011-06-22 2013-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Cell architecture and method
TWI467742B (en) * 2011-08-03 2015-01-01 矽品精密工業股份有限公司 Layer structure with emi-shielding effect
DE112015007234T5 (en) * 2015-12-26 2018-10-04 Intel Corporation VERTICAL MASTER LEVEL INSULATION, MASS ELEMENT COAXIAL INSULATION, AND IMPEDANCE TUNING OF HORIZONTAL DATA SIGNAL TRANSMISSION CABLES GUIDED BY HOUSING DEVICES
US9754872B1 (en) 2016-05-16 2017-09-05 Micron Technology, Inc. Assemblies having shield lines of an upper wiring level electrically coupled with shield lines of a lower wiring level
US10304771B2 (en) 2017-03-10 2019-05-28 Micron Technology, Inc. Assemblies having shield lines of an upper wiring layer electrically coupled with shield lines of a lower wiring layer
KR102105785B1 (en) * 2016-05-16 2020-06-29 마이크론 테크놀로지, 인크 Assembly with shield line at upper wiring level electrically coupled to shield line at lower wiring level
US9812396B1 (en) * 2016-06-07 2017-11-07 Globalfoundries Inc. Interconnect structure for semiconductor devices with multiple power rails and redundancy
US10672709B2 (en) * 2016-12-12 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd Power grid, IC and method for placing power grid
CN116613134A (en) 2017-10-06 2023-08-18 谷歌有限责任公司 Signal routing in integrated circuit packages
US10943045B2 (en) 2018-01-31 2021-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same
CN109087922B (en) * 2018-09-19 2020-09-29 合肥鑫晟光电科技有限公司 Array substrate, manufacturing method thereof and display panel
JP2022017605A (en) * 2018-10-25 2022-01-26 ソニーセミコンダクタソリューションズ株式会社 Circuit board, semiconductor apparatus, and electronic equipment
CN113056184A (en) * 2021-03-15 2021-06-29 上海应用技术大学 Shielding net simulation design method based on optimized interference signal and whole framework
CN116090401A (en) * 2023-01-09 2023-05-09 上海为旌科技有限公司 Standard cell, design method of integrated circuit, standard cell, and integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6348722B1 (en) * 1999-08-24 2002-02-19 Nec Corporation Semiconductor memory with shield layer

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2940593A1 (en) * 1979-10-06 1981-04-16 Ibm Deutschland Gmbh, 7000 Stuttgart MULTI-LAYER MODULE WITH CONSTANT WAVE RESISTANCE
JPH01152642A (en) 1987-12-09 1989-06-15 Nec Corp Semiconductor integrated circuit
JP2580301B2 (en) 1988-12-27 1997-02-12 株式会社日立製作所 Semiconductor integrated circuit device
US5288949A (en) * 1992-02-03 1994-02-22 Ncr Corporation Connection system for integrated circuits which reduces cross-talk
US5410107A (en) * 1993-03-01 1995-04-25 The Board Of Trustees Of The University Of Arkansas Multichip module
US5723908A (en) * 1993-03-11 1998-03-03 Kabushiki Kaisha Toshiba Multilayer wiring structure
JP3687041B2 (en) 1997-04-16 2005-08-24 大日本印刷株式会社 WIRING BOARD, WIRING BOARD MANUFACTURING METHOD, AND SEMICONDUCTOR PACKAGE
JP4109340B2 (en) 1997-12-26 2008-07-02 株式会社ルネサステクノロジ Semiconductor integrated circuit device
TW462214B (en) 1999-07-14 2001-11-01 Mitac Int Corp A method and structure of four layer circuit board improving circuit performance and avoiding electromagnetic interference
JP2001127162A (en) 1999-10-25 2001-05-11 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
JP4083977B2 (en) 2000-12-20 2008-04-30 富士通株式会社 Semiconductor integrated circuit and wiring determination method
US6426890B1 (en) 2001-01-26 2002-07-30 International Business Machines Corporation Shared ground SRAM cell
US6428945B1 (en) * 2001-02-13 2002-08-06 Au Optronics Corp. Method of forming barrier ribs used in a plasma display panel
US6650010B2 (en) * 2002-02-15 2003-11-18 International Business Machines Corporation Unique feature design enabling structural integrity for advanced low K semiconductor chips
US6734472B2 (en) 2002-04-25 2004-05-11 Synplicity, Inc. Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6348722B1 (en) * 1999-08-24 2002-02-19 Nec Corporation Semiconductor memory with shield layer

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
Andrey V. Mezhiba, Eby G. Friedman, "Scaling Trands of On-Chip Power Distribution Noise", SLIP'02, Apr. 6-7, 2002, San Diego, California, USA, pp. 47-53.
Khatri, Sunil P.; Brayton, Robert K.; and Sangiovanni-Vincentelli, Alberto L. "Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics," Kluwer Academic Publishers: Boston, 2001 (copy of front cover and pages i-xix, 1-51, 95-112 and copy of back cover).
Magma Design Automation, Inc., "Deep-Submicron Signal Integrity", white paper, 2002.
S. Khatri, A. Mehrotra, R. Brayton, A. Sangiovanni-Vincentelli, and R. Otten, "A novel VLSI layout fabric for deep sub-micron applications," in Proceedings of the Design Automation Conference, (New Orleans), Jun. 1999.
Sani R. Nassif, Onsi Fakhouri, "Technology Trends in Power-Grid-Induced Noise", SLIP'02, Apr. 6-7, 2002, San Diego, California, USA, pp. 55-59.
Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim, "Analytical Signal Integrity Verification Models for Inductance-Dominant Multi-Coupled VLSI Interconnects", SLIP'02, Apr. 6-7, 2002, San Diego, California, USA, pp. 61-68.
Sunil P. Khatri, Robert K. Brayton, Alberto Sangiovanni-Vincentelli, "Cross-talk Immune VLSI Design using a Network of PLAs Embedded in a Regular Layout Fabric", IEEE/ACM International Conference on Computer Aided Design, ICCAD-2000, Nov. 5-9, 2000, San Jose, CA, USA.

Cited By (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8161442B2 (en) 2002-07-29 2012-04-17 Synopsys, Inc. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US8881086B2 (en) 2002-07-29 2014-11-04 Synopsys, Inc. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US8122412B2 (en) 2002-07-29 2012-02-21 Synopsys, Inc. Shelding mesh design for an integrated circuit device
US20060095872A1 (en) * 2002-07-29 2006-05-04 Mcelvain Kenneth S Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US8701068B2 (en) 2002-07-29 2014-04-15 Synopsys, Inc. Interconnection device in a multi-layer shielding mesh
US8386979B2 (en) 2002-07-29 2013-02-26 Synopsys, Inc. Method and apparatus to design an interconnection device in a multi-layer shielding mesh
US8286118B2 (en) 2002-07-29 2012-10-09 Synopsys, Inc. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US8171441B2 (en) 2002-07-29 2012-05-01 Synopsys, Inc. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US20040145033A1 (en) * 2002-07-29 2004-07-29 Mcelvain Kenneth S. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US8166434B2 (en) 2002-07-29 2012-04-24 Synopsys, Inc. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US20090189244A1 (en) * 2002-07-29 2009-07-30 Mcelvain Kenneth S Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US20090193379A1 (en) * 2002-07-29 2009-07-30 Mcelvain Kenneth S Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US20090193380A1 (en) * 2002-07-29 2009-07-30 Mcelvain Kenneth S Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US8074197B2 (en) * 2002-07-29 2011-12-06 Synopsys, Inc. Shielding mesh design for an integrated circuit device
US20110214100A1 (en) * 2002-07-29 2011-09-01 Mcelvain Kenneth S Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US7943436B2 (en) * 2002-07-29 2011-05-17 Synopsys, Inc. Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US7739624B2 (en) 2002-07-29 2010-06-15 Synopsys, Inc. Methods and apparatuses to generate a shielding mesh for integrated circuit devices
US20090132990A1 (en) * 2002-07-29 2009-05-21 Mcelvain Kenneth S Integrated Circuit Devices and Methods and Apparatuses for Designing Integrated Circuit Devices
US20090187872A1 (en) * 2002-07-29 2009-07-23 Mcelvain Kenneth S Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US20070136713A1 (en) * 2002-08-09 2007-06-14 Asmus Hetzel Method and Apparatus for Routing
US7721243B2 (en) 2002-08-09 2010-05-18 Cadence Design Systems, Inc. Method and apparatus for routing
US20050076319A1 (en) * 2003-10-03 2005-04-07 Chow Shau-Lim Stan Pin assignment in block-based integrated circuit design methodologies
US8095903B2 (en) 2004-06-01 2012-01-10 Pulsic Limited Automatically routing nets with variable spacing
US7131096B1 (en) 2004-06-01 2006-10-31 Pulsic Limited Method of automatically routing nets according to current density rules
US8949760B2 (en) 2004-06-01 2015-02-03 Pulsic Limited Automatically routing nets with variable spacing
US20080028352A1 (en) * 2004-06-01 2008-01-31 Pulsic Limited Automatically Routing Nets with Variable Spacing
US7373628B1 (en) 2004-06-01 2008-05-13 Pulsic Limited Method of automatically routing nets using a Steiner tree
US7530040B1 (en) 2004-06-01 2009-05-05 Pulsic Limited Automatically routing nets according to current density rules
US7784010B1 (en) 2004-06-01 2010-08-24 Pulsic Limited Automatic routing system with variable width interconnect
US8171447B1 (en) 2004-06-01 2012-05-01 Pulsic Limited Automatically routing nets according to current density rules
US8479139B1 (en) 2004-06-01 2013-07-02 Pulsic Limited Automatic routing system with variable width interconnect
US20060015835A1 (en) * 2004-06-04 2006-01-19 Faraday Technology Corp. Placement method for decoupling capacitors
US8099700B1 (en) 2004-06-07 2012-01-17 Pulsic Limited Automatic integrated circuit routing using spines
US7823113B1 (en) 2004-06-07 2010-10-26 Pulsic Limited Automatic integrated circuit routing using spines
US8479141B1 (en) 2004-06-07 2013-07-02 Pulsic Limited Automation using spine routing
US7802208B1 (en) 2004-06-07 2010-09-21 Pulsic Limited Design automation using spine routing
US7257797B1 (en) 2004-06-07 2007-08-14 Pulsic Limited Method of automatic shape-based routing of interconnects in spines for integrated circuit design
US8015529B1 (en) * 2005-03-09 2011-09-06 Cadence Design Systems, Inc. Methods and apparatus for diagonal route shielding
US7571408B1 (en) * 2005-03-09 2009-08-04 Cadence Design Systems, Inc. Methods and apparatus for diagonal route shielding
US9245082B2 (en) 2005-06-21 2016-01-26 Pulsic Limited High-speed shape-based router
US11126779B2 (en) 2005-06-21 2021-09-21 Pulsic Limited High-speed shape-based router
US10769343B2 (en) 2005-06-21 2020-09-08 Pulsic Limited High-speed shape-based router
US10346577B2 (en) 2005-06-21 2019-07-09 Pulsic Limited High-speed shape-based router
US20060288323A1 (en) * 2005-06-21 2006-12-21 Pulsic Limited High-Speed Shape-Based Router
US7984411B2 (en) 2005-06-24 2011-07-19 Pulsic Limited Integrated circuit routing and compaction
US7603644B2 (en) 2005-06-24 2009-10-13 Pulsic Limited Integrated circuit routing and compaction
US20090327990A1 (en) * 2005-06-24 2009-12-31 Pulsic Limited Integrated Circuit Routing and Compaction
US20060294488A1 (en) * 2005-06-24 2006-12-28 Pulsic Limited Integrated Circuit Routing and Compaction
US8332799B2 (en) 2005-06-24 2012-12-11 Pulsic Limited Integrated circuit routing with compaction
US8707239B2 (en) 2005-06-24 2014-04-22 Pulsic Limited Integrated circuit routing with compaction
US8074187B2 (en) 2005-08-01 2011-12-06 Candence Design Systems, Inc. Method and apparatus for inserting metal fill in an integrated circuit (“IC”) layout
US7694258B1 (en) 2005-08-01 2010-04-06 Cadence Design Systems, Inc. Method and apparatus for inserting metal fill in an integrated circuit (“IC”) layout
US8751996B1 (en) 2005-11-08 2014-06-10 Pulsic Limited Automatically routing nets according to parasitic constraint rules
US20070106969A1 (en) * 2005-11-08 2007-05-10 Pulsic Limited Method of Automatically Routing Nets According to Parasitic Constraint Rules
US8010928B1 (en) 2005-11-08 2011-08-30 Pulsic Limited Automatically routing nets according to parasitic constraint rules
US8332805B1 (en) 2005-11-08 2012-12-11 Pulsic Limited Automatically routing nets according to parasitic constraint rules
US7363607B2 (en) 2005-11-08 2008-04-22 Pulsic Limited Method of automatically routing nets according to parasitic constraint rules
US20080042284A1 (en) * 2006-03-17 2008-02-21 Tatsuya Naruse Semiconductor integrated circuit and the method of designing the layout
US7514794B2 (en) * 2006-03-17 2009-04-07 Panasonic Corporation Semiconductor integrated circuit and the method of designing the layout
US7519927B1 (en) 2008-07-02 2009-04-14 International Business Machines Corporation Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations
US9767242B1 (en) 2009-03-18 2017-09-19 Pulsic Limited Filling vacant areas of an integrated circuit design
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US8237287B2 (en) * 2010-03-31 2012-08-07 Renesas Electronics Corporation Semiconductor device
US20110241216A1 (en) * 2010-03-31 2011-10-06 Renesas Electronics Corporation Semiconductor device
US8436469B2 (en) 2010-03-31 2013-05-07 Renesas Electronics Corporation Semiconductor device
US8796860B2 (en) 2010-03-31 2014-08-05 Renesas Electronics Corporation Semiconductor device
US10192833B2 (en) 2011-11-30 2019-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. Interposer and semiconductor package with noise suppression features
US9219039B2 (en) 2011-11-30 2015-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Interposer and semiconductor package with noise suppression features
US8607180B2 (en) 2012-05-09 2013-12-10 Lsi Corporation Multi-pass routing to reduce crosstalk
US9871027B2 (en) * 2014-09-02 2018-01-16 Socionext Inc. Semiconductor device having mesh-patterned wirings
US20160064369A1 (en) * 2014-09-02 2016-03-03 Socionext Inc. Semiconductor device
US10652998B2 (en) 2018-09-21 2020-05-12 International Business Machines Corporation Multilayer ceramic electronic package with modulated mesh topology
US11071197B2 (en) 2018-09-21 2021-07-20 International Business Machines Corporation Multilayer ceramic electronic package with modulated mesh topology and alternating rods

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