US3781648A

US3781648A - Temperature compensated voltage regulator having beta compensating means

Info

Publication number: US3781648A
Application number: US00322329A
Authority: US
Inventors: W Owens
Original assignee: Fairchild Camera and Instrument Corp
Current assignee: Fairchild Semiconductor Corp
Priority date: 1973-01-10
Filing date: 1973-01-10
Publication date: 1973-12-25
Anticipated expiration: 1990-12-25
Also published as: JPS5724571B2; HK1379A; DE2400516A1; CA1027176A; JPS49101852A; DE2400516C2; GB1434067A

Abstract

A temperature compensated voltage regulator circuit having a resistive impedance of a particular value disposed in the base circuit of the first of two cascaded transistor elements to provide compensation for possible beta ( Beta ) variations incurred as a result of process variables.

Description

United States Patent [191 Qwens TEMPERATURE COMPENSATED VOLTAGE REGULATOR HAVING BETA COMPENSATING MEANS [75] Inventor: William K. Owens, Sunnyvale, Calif.

[73] Assignee: Fail-child Camera and Instrument Corporation, Mountain View, Calif.

22 Filed: Jan. 10, 1973 21 Appl. No.: 322,329

[52] US. Cl. 323/4, 307/297, 307/299 B, 307/303, 323/9, 323/38, 323/68 [51] Int. Cl. G05f 1/58 [58] Field of Search 323/4, 8, 9, 38, 323/68, 69, 72; 307/270, 296, 297, 299 B,

[56] References Cited UNITED STATES PATENTS Allard 323/4 Dec. 25, 1973 3,538,421 11/1970 Young 323/22 T X 3,617,859 11/1971 Dobkin et a1. 323/69 X 3,721,893 3/1973 Davis 323/4 Primary ExaminerGerald Goldberg Att0rneyRoger S. Borovoy et a1.

[57 ABSTRACT A temperature compensated voltage regulator circuit having a resistive impedance of a particular value disposed in the base circuit of the first of two cascaded transistor elements to provide compensation for possi' ble beta (B) variations incurred as a result of process variables.

6 Claims, 2 Drawing Figures TEMPERATURE COMPENSATED VOLTAGE REGULATOR HAVING BETA COMPENSATING MEANS BACKGROUND OF THE INVENTION The present invention relates generally to reference voltage supply circuitry for integrated circuit applications and more particularly to voltage regulator circuitry for temperature and voltage compensated emitter coupled logic (TVECL) and the like, such circuitry including means for compensating for beta (B) variations incurred as a result of semiconductor process variables.

In electronic circuitry comprised of several discrete integrated circuits, it is important that the bias network be capable of providing a reference voltage that is pre dictable and constant under all adverse conditions, i.e., the output voltage should be invariant as a function of supply voltage, ambient temperature or semiconductor parameters. Although prior art temperature compensated voltage regulators have long been provided with means to compensate for temperature and voltage variations, no means has heretofore been provided to compensate for V variations and base current (I,,) variations resulting from processing variables.

The temperature compensating principle utilized in TVECL drivers is based upon the fact that two transistors operating at different current densities have different base-to-emitter voltage (V temperature coefficients, i.e., the rate of change of base-to-emitter forward voltage versus temperature is different for the two devices, and by coupling the two devices together in a certain manner their differences can be utilized to cancel the temperature coefficient of a third device. Unfortunately however, the previous assumption that runto-run variations in V could be compensated for by the same circuit mechanisms that compensate for temperature variations is not true. For example, in a typical TVECL circuit the range of reference voltage variation AV caused by process variations in V can be expressed as REF/ BE 1 AVREF er:

and may run as high as :tZOmV to i40mV. This is a very significant variation when the reference voltage is used to drive an ECL gate, or the like, since the noise margin of typical ECL integrated circuits is in the range of only 100-150mV.

SUMMARY OF THE PRESENT INVENTION It is therefore a principle object of the present invention to provide a TVECL voltage regulator circuit for developing a reference voltage that is independent of process variables.

Briefly, the circuit of the present invention includes a first terminal for receiving a first bias potential; a second terminal for receiving a second bias potential; an output terminal at which a reference potential is to be developed; a first resistor coupling the first terminal to the output terminal; a second resistor and a forward biased diode forming a first series circuit coupling the output terminal to the second terminal; a third resistor, a first transistor having a base, an emitter and a collector, and a fourth resistor forming a second series circuit coupling the output terminal to the second terminal; a fifth resistor coupling the base of the first transistor to the junction of the second resistor and the diode; and a second transistor having a base coupled to the collector of the first transistor, a collector coupled to the output terminal, and an emitter coupled to the second terminal.

A primary advantage of the present invention is that the circuit may be utilized to provide a reference voltage which is predictable even though manufacturing process variables cause the various component elements to have slightly varying electrical characteristics.

Other objects and advantages of the present invention will no doubt become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the several figures of the drawing.

IN THE DRAWING FIG. 1 of the drawing schematically represents a simplified embodiment of a reference voltage supply circuit having beta (B) compensating means in accordance with the present invention.

FIG. 2 is a diagram schematically illustrating an alternative embodiment of a reference voltage supply circuit for developing a pair of reference voltages.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawing, there is shown In FIG. 1 a simplified schematic diagram representing an integrated circuit (IC) voltage regulator circuit in accordance with the present invention. Although the various elements are shown in the form of discrete classical electrical components, it will be appreciated that these elements are only representative of the electrical characteristics exhibited by various integrated circuit components.

The regulator circuit, sometimes referrzd to as a bias driver, is designated generally by the numeral 10, and is provided with three external contact points including a first terminal 12 to which a positive supply voltage V is applied, a second terminal 14 to which a negative supply voltage V is applied, and an output terminal 16 from which the reference voltage V may be taken. It will be appreciated that the circuit is basically a voltage dividing circuit including a passive resistance R connected between terminals 12 and I6, and in series with an active resistance means R connected between

terminals

16 and 14.

The active resistance portion of the circuit includes means forming what may generally be viewed as three

series circuits

18, 20 and 22 connected in parallel across the

circuit nodes

24 and 26. The first circuit 18 includes a second resistive impedance element represented by the resistor R and a uni-directional current conducting device such as the diode Q The second circuit 20 includes a third resistive impedance element R an NPN transistor Q and a fourth resistive impedance element R The collector 28 of transistor Q is connected to circuit node 4 by resistor R while its emitter 30 is connected to circuit node 26 by resistor R The base 32 of transistor O is coupled to the junction of resistor R and the anode of diode Q represented by the node 34 by a resistive impedance element R having a particular value which will be discussed in detail below. The third circuit 22 is formed pressed as by an NPN transistor Q whose collector 34 is coupled to circuit node 24 and whose emitter 36 is coupled to REF z z a an's b3 3 Where 2 1151 ina/ 4 B is the ratio of the collector current I to the emitter current I of transistor Q I 03 is the base current of transistor Q and V V M2 and V are the baseto-emitter voltages of I the transistors having like numbered subscripts. Substituting equation (2) into equation (1) gives VREI" 2 3 rm VBE2)/R4] ssa oa s Differentiating equation (3) with respect to the first variable base-to-emitter voltage V it can be shown that Y REF/ BE l msr sas This variation, of perhaps flOmV to i40mV in a typical circuit, is of course very significant when the reference voltage is used to drive an ECL gate since the noise margin of typical ECL integrated circuits is in the range of l00-l50mV.

The second variable that causes the reference voltage to vary is the base current. This relationship can be ex- In a typical circuit wherein I =4mA R 6000 BNOM a: 7 Bruin tFeKV LQ- WHI be found to be about 8mV. Therefore,

by'adding the two components of variation it can be seen that the total variation in V lies within the range of 28mV to 48mV.

Since ECL gates require two reference voltages, the above error must be multiplied by a factor of two. Thus, a typical ECL gate could experience a noise margin reduction of approximately 56mV to 96mV. Where the initial noise margin is l25mV, it is obvious that such a reduction in noise margin would be catastrophic.

Since it is known that a major portion of the AV resulting from process variation is a function of beta (B), i.e.,

Av KAB where K is a constant and since the fractiOn of AV E that is a function of AB is very large at the low current levels typically assigned to the transistor Q most of the AV /AV can be eliminated by inserting a resistor R, in the base of transistor Q As a result of so doing, equation (1) can be rewritten as The change in V as a function of V and I, is then REF .z: a/ 4 d bz a o: dv R dl If V is invariant as a function of 1,, and V then dV may be set equal tozero and equation (1 1) may be solved for R to result in the expression z AVBES R3AID3 3 b2/( 3/ 4) ba Thus, by chosing a value of R, capable of satisfying the above equation, the reference voltage variations caused by AV and Al can be eliminated. In examples such as the above, typical values for R, lie within the range of 2500 to 1,0009.

To illustrate application of the present invention in a typical circuit for developing a pair of reference voltages, reference is made to FIG. 2 of the drawing. In this embodiment, which is designed to provide the two bias voltages, V138 a d V three additional transistors Q Q and Q and an additional resistor R is added to the circuit of FIG. 1. In this circuit, the collector 140 of transistor Q, is coupled to terminal 112 while its base 142 is coupled to the lowergend of resistor R, at 144 and its emitter 146 is coupled to the collector 150 of transistor Q I The base 152 of transistor Q is coupled to the junction 154 of the lower end-of resistor R and the collector 134 of transistor Q The emitter 156 of transistor O is coupled to the upper end of resistor R The collector 16 0 of transistor O is also coupled to circuit point l44, while its base 162 is coupled to circuit point 154, and its emitter 166 is coupled to the upper end Of resistor R The reference voltage V,,,, is taken at terminal 170 and the reference voltage V is taken at terminal 180.

The remainder of the circuit elements are as illustrated in the previous embodiment. For purposes of illustration a diode connected transistor Q, is shown in place of the simple diodeshown in FIG. 1.

As in the previous embodiment, if the process variation is not compensated for, the AV will be reflected approximately equal to AV AV At the usual current levels m am 20-30mv.

1- Bm/ b a/ 4) The change in voltage across R caused by AB changes current through R i.e.,

124 am 3122 a 4 and The change in voltage across R caused by the change in voltage across R is AV AI, (1R

or I

AVns 1(R3/R4)AVE T the effects of the process variation AV are cancelled. Therefore, the following equation may be written:

AVn OKRq/RU vass By choosing a value of R, from equation l4), equation (20) can be realized.

With the ill effects of AV eliminated, the R can be further tailored to cancel the base current loading effects on R or R,. if the emitter currents of Q and Q are equal and much greater than I and if R equals R,, then AI R will be totally eliminated, and AI R, will be reduced by 50 percent.

Letting and substituting then a( b2 at R1 R Al 3/ b2 Thus, the total value of R, necessary to compensate for the process variables AV' AV Al R Al R,a is, from equations (14) and (24) The first term in the above equation is general, however the second term depends upon the emitter currents in transistors Q and Q and the relative compensation desired at V and V If I is not equal to I then AI R is not equal to AI R, and AI R is not reduced by 50 percent. Thus, either Al R or AI R can be compensated for totally, but not both terms. In most applications, it should be more desirable to partially undercompensate one term or partially overcompensate for the other.

In summary it may be emphasized that the principle features and advantages of the present invention is the elimination of the effects of V process variations (AV,,,;;, and AV and the significant reduction -of A1,,R effects.

What is claimed is:

l. A temperature compensated voltage regulator circuit including beta compensating means, comprising: a first terminal for receiving a first bias potential;

a second terminal for receiving a second bias potential;

an output terminal at which a reference developed;

first resistive impedance means coupling said first terminal to said output terminal;

a second resistive impedance means and a forward biased diode means forming a first series circuit coupling said output terminal to said second terminal;

a third resistive impedance means, a first transistor device having a base, an emitter and a collector, and a fourth resistive impedance means forming a second series circuit coupling said output terminal to said second terminal;

a fifth resistive impedance means coupling the base of said first transistor device to the junction of said second resistive impedance means and said diode means; and

a second transistor device'having a base coupled to the collector of said first transistor device, a collector coupled to said output terminal and an emitter coupled to said second terminal.

2. A temperature compensated voltage regulator circuit as recited in claim 1 wherein said fifth resistive impedance means has a resistive impedance R selected to satisfy the equation potential is AVBES a ba s oz a a) 02 where R is the resistive impedance of said third impedance means;

R is the resistive impedance of said fourth impedance means;

AV is the base-emitter forward voltage variation of said second transistor device;

Al is the base current variation of said first transistor device; and

Al is the base current variation of said second transistor device.

3. A temperature compensated voltage regulator circuit including beta compensating means comprising:

a first terminal for receiving a first bias potential;

a second terminal for receiving a second bias potential;

an output terminal at which a reference potential is to be developed;

a first resistive impedance means coupling said first terminal to said output terminal;

a second resistive impedance means and a forward biased diode means forming a series circuit coupling said output terminal to said second terminal;

. a third resistive impedance means;

a fourth and a fifth resistive impedance means;

a first transistor device having a first base coupled to the junction of said second resistive impedance means and said diode means by said third resistive impedance means, a first collector coupled to said output terminal by said fourth resistive impedance means, and a first emitter coupled to said second terminal by said fifth resistive impedance means;

and

a second transistor device having a second base coupled to said first collector, a second collector coupled to said output terminal, and a second emitter coupled to said second terminal.

4. A temperature compensated voltage regulator cir-- cuit as recited in claim 3 wherein said fifth resistive impedance means has a resistive impedance R selected to satisfy the equation R1 BEa sA ba Rs o2 (R3/ 4) 02 where 1 R is the resistive impedance of said fourth impedance means; R is the resistive impedance of said fifth impedance means; AV is the base emitter forward voltage variation of said second transistor device; A1,, is the base current variation of said first transistor device; and Al is the base current variation of said second transistor device. 5. A temperature compensated voltage regulator circuit including beta compensating means, comprising:

a first terminal for receiving a first bias potential;

a second terminal for receiving a second bias terminal;

a third terminal at which a first reference potential is to be developed;

a fourth terminal at which a second reference potential is to be developed;

a first resistive impedance means;

a first transistor device having a first base coupled to said first terminal by said first resistive impedance means, a first collector coupled to said first terminal and a first emitter coupled to said third terminal;

a second resistive impedance means;

a second transistor device having a second base coupled to said first terminal by said second resistive impedance means, a second collector coupled to said third terminal and a second emitter coupled to said fourth terminal;

a third resistive impedance means and a forward biased diode means forming a series circuit coupling said fourth terminal to said second terminal;

a third transistor device having a third base coupled to said second base, a third collector coupled to said first base and a third emitter;

a fourth resistive impedance means;

a fifth resistive impedance means;

a sixth resistive impedance means;

a fourth transistor device having a fourth base coupled to the junction of said third impedance means and said diode means by said fifth impedance means, a fourth collector coupled to said third emitter by said fourth impedance means and a fourth emitter coupled to said second terminal by said sixth impedance means; and

a fifth transitor device having a fifth base coupled to said fourth collector, a fifth collector coupled to said first terminal through said second resistive impedance means and a fifth emitter coupled to said second terminal.

6. A temperature compensated voltage regulator circuit as recited in claim 5 wherein said fifth resistive impedance means has a resistive impedance R selected to satisfy the equation 1 ssa a ba a o2/( s 4) az where R is the resistive impedance of said fourth impedance means;

R is the resistive impedance of said sixth impedance means;

AV is the base-emitter forward voltage variation of said fifth transistor device;

A1 is the base current variation of said fourth transistor device; and

Al is the base current variation of said fifth transistor device.

Claims

1. A temperature compensated voltage regulator circuit including beta compensating means, comprising: a first terminal for receiving a first bias potential; a second terminal for receiving a second bias potential; an output terminal at which a reference potential is developed; first resistive impedance means coupling said first terminal to said output terminal; a second resistive impedance means and a forward biased diode means forming a first series circuit coupling said output terminal to said second terminal; a third resistive impedance means, a first transistor device having a base, an emitter and a collector, and a fourth resistive impedance means forming a second series circuit coupling said output terminal to said second terminal; a fifth resistive impedance means coupling the base of said first transistor device to the junction of said second resistive impedance means and said diode means; and a second transistor device having a base coupled to the collector of said first transistor device, a collector coupled to said output terminal and an emitter coupled to said second terminal.

2. A temperature compensated voltage regulator circuit as recited in claim 1 wherein said fifth resistive impedance means has a resistive impedance Rx selected to satisfy the equation Rx Delta VBE3 + R3 Delta Ib3-R3 Delta Ib2/(R3/R4) Delta Ib2 where R3 is the resistive impedance of said third impedance means; R4 is the resistive impedance of said fourth impedance means; Delta VBE3 is the base-emitter forward voltage variation of said seconD transistor device; Delta Ib2 is the base current variation of said first transistor device; and Delta Ib3 is the base current variation of said second transistor device.

3. A temperature compensated voltage regulator circuit including beta compensating means comprising: a first terminal for receiving a first bias potential; a second terminal for receiving a second bias potential; an output terminal at which a reference potential is to be developed; a first resistive impedance means coupling said first terminal to said output terminal; a second resistive impedance means and a forward biased diode means forming a series circuit coupling said output terminal to said second terminal; a third resistive impedance means; a fourth and a fifth resistive impedance means; a first transistor device having a first base coupled to the junction of said second resistive impedance means and said diode means by said third resistive impedance means, a first collector coupled to said output terminal by said fourth resistive impedance means, and a first emitter coupled to said second terminal by said fifth resistive impedance means; and a second transistor device having a second base coupled to said first collector, a second collector coupled to said output terminal, and a second emitter coupled to said second terminal.

4. A temperature compensated voltage regulator circuit as recited in claim 3 wherein said fifth resistive impedance means has a resistive impedance Rx selected to satisfy the equation Rx Delta VBE3 + R3 Delta Ib3 - R3 Delta Ib2/(R3/R4) Delta Ib2 where R3 is the resistive impedance of said fourth impedance means; R4 is the resistive impedance of said fifth impedance means; Delta VBE3 is the base emitter forward voltage variation of said second transistor device; Delta Ib2 is the base current variation of said first transistor device; and Delta Ib3 is the base current variation of said second transistor device.

5. A temperature compensated voltage regulator circuit including beta compensating means, comprising: a first terminal for receiving a first bias potential; a second terminal for receiving a second bias terminal; a third terminal at which a first reference potential is to be developed; a fourth terminal at which a second reference potential is to be developed; a first resistive impedance means; a first transistor device having a first base coupled to said first terminal by said first resistive impedance means, a first collector coupled to said first terminal and a first emitter coupled to said third terminal; a second resistive impedance means; a second transistor device having a second base coupled to said first terminal by said second resistive impedance means, a second collector coupled to said third terminal and a second emitter coupled to said fourth terminal; a third resistive impedance means and a forward biased diode means forming a series circuit coupling said fourth terminal to said second terminal; a third transistor device having a third base coupled to said second base, a third collector coupled to said first base and a third emitter; a fourth resistive impedance means; a fifth resistive impedance means; a sixth resistive impedance means; a fourth transistor device having a fourth base coupled to the junction of said third impedance means and said diode means by said fifth impedance means, a fourth collector coupled to said third emitter by said fourth impedance means and a fourth emitter coupled to said second terminal by said sixth impedance means; and a fifth transitor device having a fifth base coupled to said fourth collector, a fifth collector coupled to said first terminal through said second resistive impedance means and a fifth emitter couPled to said second terminal.

6. A temperature compensated voltage regulator circuit as recited in claim 5 wherein said fifth resistive impedance means has a resistive impedance Rx selected to satisfy the equation Rx Delta VBE3 + R3 Delta Ib3 - R3 Delta Ib2/(R3/R4) Delta Ib2 where R3 is the resistive impedance of said fourth impedance means; R4 is the resistive impedance of said sixth impedance means; Delta VBE3 is the base-emitter forward voltage variation of said fifth transistor device; Delta Ib2 is the base current variation of said fourth transistor device; and Delta Ib3 is the base current variation of said fifth transistor device.