US3638048A

US3638048A - Store read units

Info

Publication number: US3638048A
Application number: US2825A
Authority: US
Inventors: Ferdinand Camerik
Original assignee: US Philips Corp
Current assignee: US Philips Corp
Priority date: 1969-01-16
Filing date: 1970-01-14
Publication date: 1972-01-25
Anticipated expiration: 1989-01-25
Also published as: FR2033242A1; GB1257153A; JPS4911768B1; NL162771B; NL162771C; DE1964791C3; DE1964791A1; NL6900697A; FR2033242B1

Abstract

Read unit suitable for reading a storage element whose stored information is available in the form of a voltage at an information terminal, said unit comprising a second transistor controlled by a first transistor, the latter being rendered conducting when the former is cut off for conducting away the charge accumulated in the base of the second transistor.

Description

United States Patent Camerik STORE READ UNITS [72] Inventor: Ferdinand Camerik, Emmasingel, Eindhoven, Netherlands [73] Assignee: U.S. Philips Corporation, New York, NY. [22] Filed: Jan. 14, 1970 [21] Appl. No.: 2,825

[451 Jan. 25, 1972 3,510,685 5/1970 Watanabe ..307/2 1 8 F ORElGN PATENTS OR APPLICATIONS 1,192,250 2/1964 Primary ExaminerDonald D. Forrer Assistant Examiner-David M. Carter Anorney-Frank R. Trifari [5 7] ABSTRACT Read unit suitable for reading a storage element whose stored information is available in the form of a voltage at an information terminal, said unit comprising a second transistor controlled by a first transistor, the latter being rendered conducting when the former is cut off for conducting away the charge accumulated in the base of the second transistor.

4 Claims, 5 Drawing Figures Germany ..307/299 PATENTED JANZS i972 U INVENTOR.

FERDINAND CAMERIK AGENT sroru: REA!) UNITS The invention relates to a read unit for scanning the information appearing in the form of a bivalent voltage signal at an information terminal, said unit for being selected by bivalent signals comprising an input terminal which is coupled through a first resistor with the base of a first transistor, one emitter of which is connected to the information terminal and the collector of which isconnected to the base of a second transistor, whose emitter is coupled with a source of constant potential and whose collector is connected on the one hand to an output terminal and on the other hand through a second resistor to a terminal of a supply source.

TI-Ie problem of scanning bivalent voltage signals is involved inter alia in semiconductor stores in which the storage elements are formed by bistable semiconductor devices. For this purpose a read unit of the kind set forth has become known from Electronics,"Apr. 4, 1966, page 122.

In this known circuit arrangement the possibility of deriving the information appearing in the form of a bivalent voltage signal at the information terminal from the output terminal is provided by cutting off the second transistor at the appearance of one of the signal values and by driving it in the saturation state at the appearance of the other signal value. In the latter state, however, a great charge will be accumulated in the base of the transistor. Under given conditions it is possible to conduct away this charge only by leakage currents. This involves the disadvantage that under said conditions the time required for switching over from a low output voltage to a high output voltage is long. This long switching time implies that voltages induced from the outside exert a great influence on the output voltage so that there is a narrow range of anti-interferences. Whereby the anti-interference margin is defined as Vs/Vt.

Vs is the maximum value of the input voltage for which the output voltage does not charge, Vt is the maximum voltage variation of the output voltage.

The invention has for its object to provide under any condition a short switching time of the read unit mentioned above and hence to improve the enlargement of the anti-interence range.

The read unit according to the invention is characterized in that the input terminal is connected to a second emitter of the first transistor for temporarily rendering the first transistor conducting when the second transistor is cut off.

The invention will be described more fully with reference to the embodiments shown in the Figures, in which the same references are used for corresponding elements.

FIG. 1 shows a known read unit.

FIG. 2 shows an embodiment of a read unit in accordance with the invention.

FIGS. 3, 4 and 5 show embodiments of the invention, which are extended as compared with the embodiment shown in FIG. 2. t

The read unit shown in FIG. 1 comprises a storage element G, which contains information in the form of a bivalent voltage signal. The values of these voltages are unambiguously determined and they are either low, then corresponding to ground potential, or high, then corresponding to the positive voltage of the supply source.

These signal voltages may be derived from an information terminal of the storage element G. For this purpose the information terminal is connected to an emitter of the multiemitter transistor T,, whose base is connected through a first resistor R, to a first input terminal y and a second emitter of which is connected to a second input terminal x, while the collector thereof is connected to the base of a second transistor T The emitter of the transistor T is connected to ground and the collector is connected on the one hand to the output terminal U and on the other hand through the resistor R to the positive terminal V,, of a supply source (not shown). For selection by coincidence the input terminals x and y receive bivalent signals, a high value of the signal denoting herein a high volt- -age,,i.e., the positive voltage of the supply source (not shown),

and a low value of the signal denoting a low voltage, i.e., ground potential. If the voltage at the input terminal y is low, the transistor T, will be cut off independently of the value of the voltage at the input terminal x, so that no base current is available for the transistor T which is thus also cut oil. The output voltage at the terminal U is then equal to the positive voltage of the supply source (not shown). If the voltage at the input terminal y is high and that at the input terminal x low, the base-emitter junction of the multiemitter transistor T, is conducting. The collector voltage of transistor T, is under these conditions approximately equal to the voltage at the input terminal x so that the base voltage of the transistor T is also low and the transistor T remains cut off. The output voltage of the terminal U remains high. If a high voltage is applied to the two input terminals x and y, and if the voltage at the information is low, the base-emitter junction of the multiemitter transistor T, will be conducting, the collector voltage of transistor T, will be low and the output voltage at terminal U will again be high. However, if the voltages at the input terminals x and y and at the information terminal are high, the base-collector junction of transistor T, and the series-connected base-emitter junction of transistor T are conducting, so that the latter is driven in the conductive state. This results in a voltage drop across the resistor R so that the output voltage at terminal U is reduced. Consequently, only when the two input voltages are high, the inverted value of the voltage of the information stored in the element G will appear at the output terminal U. Since the output voltages may be employed for driving other circuits, it is required for them to have the same levels as the voltages of the element G. Moreover, this read unit is integrated in a circuit so that low dissipation is required. In order to satisfy these requirement, the transistor T is cut off for obtaining a high output voltage and the transistor T is driven in the saturation state for obtaining a low output voltage. This bottoming results in a high charge accumulation in the base of transistor T When the input voltage of the terminal y is changed from a high value to a low value, whereas .the input voltage at terminal x is high, the multiemitter transistor T, is cut off and the charge of the base of transistor T, can be conductedaway only by leakage current. The output voltage of the terminal U then changes slowly from a low value to a high value so that the switching time is long. Thus voltages induced from without have a great influence during this time on the value of the output voltage of terminal U so that the anti-interference range is narrow.

FIG. 2 shown a read unit in accordance with the invention. The read unit shown in FIG. 1 provides herein the connection of a third emitter of the multiemitter transistor T, to the first terminal y so that voltage variations at this input terminal are directly transferred to the emitter. The base of the multiemitter transistor T, has a parasitic capacitance C, to ground. This capacitance, together with the resistor R,, forms a delay element having a time constant C,,R,. A change of the voltage at the terminal y is passed with a time lag of C R, to the base of the multiemitter transistor T,. When the voltage at terminal y is changed from a high to a low value, whereas the voltage at terminal x and at the information terminal is high, the base of the multiemitter transistor T, will be at a high voltage during the time lag C,,R,, whereas the emitter voltage is low so that the multiemitter transistor will operate as a transistor for said time. The base charge of transistor T will then be conducted away with an accelerated rate through the collector-emitter junction of the multiemitter transistor T, and the input terminal y. As a result the switching time is reduced so that the range of interference is smaller. If the time lag C,,R, is too short for a complete drain of the base charge of transistor T the parasitic capacitance C, may be enhanced.

However, this involves the disadvantage that a switching-on time is introduced, when the multiemitter transistor T, has to be changed over from the cut off state to the conducting state.

The read unit shown in FIG. 3 obviates this disadvantage of I the read unit of FIG. 2. In the read unit of FIG. 3 a third transistor T whose base-emitter junction is connected between the resistor R, and the base of the multiemitter transistor T,, is arranged so that the base of the transistor T is connected to the resistor R, and the emitter thereof is connected to the base of the multiemitter transistor T,. The collector of the transistor T is connected through the resistor R to the positive terminal V, of the supply source (not shown). If the two input voltages are high and the voltage at the information terminal is high, the transistor T will be conducting because the base current for the transistor T passes from the positive tenninal of the supply source (not shown), via resistor R the emitter-collector junction of transistor T the basecollector junction of transistor T, and the base-emitter junction of transistor T The transistor T is then driven in the saturation state and a great charge is then accumulated in the base of this transistor. If only the voltage at the input terminal y is changed from a high to a low value, the base of the transistor T will follow this voltage drop with the time lag C,,R,; thus transistor T is cut off, which requires a certain amount of time, after which the base of the multiemitter transistor T, assumes a low voltage. The emitter voltage of the multiemitter transistor T,, however, has followed the voltage drop at the input terminal y. The multiemitter transistor T, operates as a transistor for the time C R, plus the time required for the transistor T,, to be cut off and the stored charge will be conducted away completely via the base of transistor T and the collector-emitter junction of the multiemitter transistor T, to the input terminal y. The transistor T is definitely cut off as soon as the base charge is conducted away so that a longer time lag than that strictly required is not objectionable.

Because the switching-on time of a conventional transistor is much shorter than the switching-off time, the result of including transistor T in the base circuit of the multiemitter transistor T, is that the base charge of transistor T is completely conducted away without the introduction of an additional time lag when the input voltage at terminal y is changed from a low to a high value.

ln practice the switching time was reduced by these measures from 300 to 60 nsec.

if the input voltage at terminal y is high and if the input voltage at terminal x is low, the base-emitter junction of the multiemitter transistor T, of these embodiments will be conducting. The collector voltage of the multiemitter transistor T, is then substantially equal to the low emitter voltage so that the base of the transistor T,, which is connected to the collector of the transistor T,, has a low voltage and the transistor T will be cut off. Owing to the conducting state of the base-emitter junction of transistor T,, energy will be dissipated in the read unit, which is advantageous when the unit is integrated. This is obviated by the read unit shown in FIG. 4. This includes a fourth transistor in the base circuit of the multiemitter transistor T, so that the collector of the transistor T is connected to the emitter of transistor T the emitter of transistor T, is connected to the base of the multiemitter transistor T, and the base of transistor T is connected through a resistor R to the input terminal 1:. Also in this case transistor T is only conducting, when the two input voltages and the voltage at the information terminal are high. Then a base current will flow for the transistor T, from the positive terminal V, through the resistor R the collector-emitter junction of transistor T,,, the collector-emitter junction of transistor T the base-emitter junction of the multiemitter transistor T, and the base-emitter junction of transistor T to earth. If the input voltage at the terminals x or y is changed from a high to a low value, the read unit operates in a similar manner as that shown in H6. 3. If only the input voltage of terminal .1: is low, transistor T is cut off and the circuit for the base current of transistor T, is interrupted so that also in this case the multiemitter transistor T, and all other transistors included in the read unit are cut off so that the read unit is better suitable for being integrated.

In the embodiment shown in FIG. 5 the read unit of HO. 3 has removed from it the resistor R and the collector of transistor T, directly connected to the positive terminal of the supply source and a resistor R connected between the emitter of transistor T,, and the base of the multiemitter transistor T,. The operation of this read unit is equal to that of H6. 3 with the exception that a lower input control current is sufi'rcient since the transistor T; is connected as an emitter follower. This has the advantage that a plurality of these inputs may be connected to one output. It is not essential for the embodiments described, above, with the exception of read unit shown in FIG. 4, for the input terminal at to be provided so that for certain uses this terminal need not be accessible.

I claim:

1. A read unit for scanning information appearing in the form of a bivalent information signal on an information input terminal in response to bivalent switching signals on a switching signal input terminal, comprising a first multiemitter transistor having a base, a collector, and at least two emitters, a first resistor, means for connecting the base of the first transistor to the switching signal input terminal through the first resistor, means for connecting a first emitter of the first transistor to the information input terminal, a second transistor having a base, a collector, and an emitter, conductor means for connecting the collector of the first transistor directly to the base of the second transistor, conductor means for connecting the emitter of the second transistor to a source of constant potential, conductor means for connecting the collector of the second transistor directly to an output terminal, a second resistor, means for connecting the collector of the second transistor to a supply voltage input terminal through the second resistor, and conductor means for connecting the switching signal input terminal directly to a second emitter of the first transistor through a low impedance path whereby the first transistor is driven temporarily into a conductive state in response to a change of condition of the second transistor from conductive to a cutoff state.

2. A read unit as claimed in claim 1, further comprising a third transistor having a base, a collector, and an emitter, a third resistor, the means for connecting the base of the first transistor to the switching signal input terminal through the first resistor comprising the emitter and base terminals of the third transistor, the emitter of the third transistor being connected to the base of the first transistor, and further comprising means for connecting the collector of the third transistor to the supply voltage input terminal through the third resistor.

3. A read unit as claimed in claim 2, further comprising a second switching signal input terminal, a fourth transistor, conductor means for connecting the second switching signal input terminal directly to a third emitter of the first transistor, a fourth resistor, means comprising the collector and emitter of the fourth transistor for connecting the emitter of the third transistor to the base of the first transistor, and means for connecting the base of the fourth transistor to the second switching signal input terminal through the fourth resistor.

4. A read unit as claimed in claim 1, further comprising a third transistor, a third resistor, means for connecting the side of the first resistor remote from the switching signal input terminal to the base of the third transistor, means for connecting the collector of the third transistor to the supply voltage terminal, and means for connecting the emitter of the third transistor to the base of the first transistor through the third resistor.