US3562494A

US3562494A - Code detecting and control circuit for sorting articles

Info

Publication number: US3562494A
Application number: US685565A
Authority: US
Inventors: Warren J Schmidt
Original assignee: FMC Corp
Current assignee: FMC Corp
Priority date: 1967-11-24
Filing date: 1967-11-24
Publication date: 1971-02-09
Anticipated expiration: 1988-02-09
Also published as: DE1810810A1; GB1227818A; FR1593331A

Abstract

A code detecting and control circuit in which a reader senses label identification indicia to first determine whether the label viewed is the intended label and then samples destination code indicia during clock pulse time initiated by clock pulse marks on the label. Prearranged sets of light sensing devices in the reader not only read the indicia on the label but check the width of clock pulse marks and the space between successive clock pulse marks to verify the authenticity of the marks controlling time sampling of the destination code indicia.

Description

United States Patent Inventor Warren J. Schmidt Sunnyvale. Calif.

Appl. No 685.565

Filed Nov. 24. I967 Patented Feb. 9. I971 Assignee FMC Corporation San Jose, Calif. a corporation of Delaware CODE DETECTING AND CONTROL CIRCUIT FOR SORTING ARTICLES 9 Claims, 12 Drawing Figs.

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[56] References Cited UNITED STATES PATENTS 3,086.12] 4/1963 (ockrell 209/111.7X 3.211.470 Ill/11165 Wilson 4. 235/6112 3.222.501 12/1965 Wood .4 250/219(ID)X 3,225,175 12/1965 Hyypolainen 235/61] Primary limmim'r- Maynard R. Wilbur Axsislnnl lz'xumim'r- Thomas J. Sloyan Alrorrwyx-F. W Anderson and C. E. 'l'ripp 2:1 GATE LABEL 5;; IDENTIFICATION 27: DETECTOR 111 c c c c c GATE 3,2 1,! e |o F rnew 20A A 1 J 11 1 J1 3 4 l6 ,1

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' J WARREN J SCHMIDT ATTORNEY CODE DETECTING AND CONTROL CIRCUIT FOR SORTING ARTICLES The present invention relates in general to code detecting and control circuits, and more particularly to a code detecting and control circuit employed in a package or article sorting system.

An object of the present invention is to provide a code detecting and control circuit for 'sorting packages in which indicia carried by the package causes identification of the label as the intended label and initiates the generation of synchronizing clock pulses.

Another object of the present invention is to provide a code detecting and control circuit for sorting packages in which clock pulse indicia carried by the package determine the sampling time and duration for sensing respective destination code indicia and wherein light sensing devices are prearranged to sense whether the clock pulse indicia are the intended marks.

Another object of the present invention is to provide a code detecting and control circuit for sorting packages in which indicia carried by the package cause identification of the label as the intended label and initiate the generation of synchronizing clock pulses to enable the sorting operation to be independent of the speed of a conveyor advancing the article thereon.

Another object of the present invention is to provide a code detecting and control circuit for sorting articles that reduces false operations and readings from occurring because of dirt or extraneous black marks.

Another object of the present invention is to provide a code detecting and control circuit for sorting articles that reduces false operations and readings from occurring because of skew conditions of a label or foreign marks on the label.

Another object of the present invention is to provide a code detecting and control circuit for sorting articles in which a label identification is made for reducing false operations.

Another object of the present invention is to provide a code detecting and control circuit for sorting articles in which a label identification is made prior to sensing destination code indicia for improved accuracy in sorting.

Other and further objects and advantages of the present invention will be apparent to one skilled in the art from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a diagrammatic front elevational view of a coded label read by the code detecting and control circuit of the present invention.

FIGS. 2A and 28 when placed side-by-side with the FIG. 23 to the right of the FIG. 2A are a block diagram of a code detecting and control circuit of the present invention illustrated diagrammatically with a label of the type shown in FIG. 1.

FIGS. 3A and 38 when placed side-by-side with the FIG. 3B to the right of the FIG. 3A are a schematic diagram of a label identification circuit employed in the code detecting and control circuit of the present invention.

FIG. 4 is a schematic diagram of a code reading and clock counting circuit employed in the code detecting and control circuit of the present invention.

FIG. 5 is a schematic diagram of a mark-space detector employed in the code detecting and control circuit of the present invention.

FIGS. 6A-6C with FIG. 68 to the right of FIG. 6A and with FIG. 6C to the right of FIG. 6B illustrate an error detecting and correction circuit employed in the code detecting and control circuit of the present invention.

FIG. 7 is located below FIG. 6B and illustrates the manner in which FIGS. 6A-6C are arranged to the error and correction circuit.

FIG. 8 is a block diagram of the memory circuit employed in the code detecting and control circuit of the present invention.

GENERAL DESCRIPTION Illustrated in FIG. 1 is a label L, which is prepared by a conventional labelling machine or a well-known computer printer and is affixed to a package at a predetermined location. While reference herein is made to a package, it is apparent that an article may be equally applicable. The label L comprises a label identification zone, which includes three leading vertically disposed marks or indicia A,A The marks A, and A are positioned in a vertically disposed parallel relation spaced in the direction of travel of the label L with the mark A below the marks A, and A The mark A is vertically disposed and occupies an area in vertical alignment with the space between the marks A, and A As viewed in FIG. 2A, the label is carried by a package that advances in the direction of an arrow 10 and, hence, the zone A is the leading area of the label L.

At the trailing area of the label L and in the upper portion thereof are located a series of synchronizing clock pulse marks or indicia C,C,,,, which in the preferred embodiment equal 10. The marks C,-C, are positioned in a vertically disposed. parallel relation spaced in the direction of travel of the label L. Below the synchronizing clock pulse marks C,C, in the trailing area of the label L is the destination code I for identifying the destination or diversion zone for the package on which the label L appears. The destination code I on the label L includes the vertically disposed, parallel identification marks or indicia I,I It is to be observed that the code identification marks I,-I are in vertical alignment with selected synchronizing clock pulse marks and are spaced in the direction of travel of the label L. While the marks I,l indicate the presence of a mark, a space below the clock pulse mark indicates the absence of a mark. Both the presence of a mark and the absence of a mark could serve to designate the destination code I.

From the foregoing, it is to be observed that the indicia A,- A, identifies the label L as a label to be read. The series of marks C,---C, initiate the generation of synchronizing clock pulses and the indicia I,l identify the destination or diversion zone for the package on which the label appears.

The code detecting and control circuit 15 (FIGS. 2A and 2B) of the present invention is employed in a package sorting system to read the labels, such as the label L, and to direct the operation of sorting the packages on which the labels appear by causing the diversion of the packages at preselected sorting stations.

Generally, packages bearing labels L emanate from a source area in a warehouse and are advanced through various feeder conveyors to an endless sorting conveyor. Along the sorting conveyor are respective sorting stations with individual pushoff mechanisms or diverters. The packages on the endless sorting conveyor are selectively diverted at the selected sorting station into chutes, onto conveyors, for delivery to selected trucks. A sorting system of this general type is described in detail in US. Pat. No. 3,379,321.

In FIG. 2A is shown a package P on which is affixed the label L. The package P advances in the direction of the arrow 10. The code detecting and control circuit 15 (FIGS. 2A and 2B) of the present invention comprises a suitable reader I6, which includes three sets of conventional light sensing devices, such as

phototransistors

16A, 16B and 16C. The phototransistors 16B are vertically disposed at spaced elevations below the top of the intended marks A,, A and C,-C,L, and extend throughout the height of the intended marks so as to face the marks A,, A and C,C,,, as the label L advances in the direction of the arrow 10.

Similarly, the phototransistors 16A are vertically disposed and of the same elevations as the phototransistors 16B. The phototransistors 16A are aligned with phototransistors 16B taken with respect to the direction of travel of the label L. In addition, the

phototransistors

16B and 16A are spaced apart with respect to the direction of travel of the label L a predetermined distance S, which predetermined distance S is less than the width of the respective marks A,A but greater than the width of the individual marks C -C Also, the distance S is less than the space between marks A and C or each space between individual marks C,-C Marks A,A are of a different width than marks C,C as a further safeguard against reading markings other than an intended label.

The phototransistors 16C are vertically disposed at elevations below the top of marks A and I,-I In addition thereto, the phototransistors 36C are aligned vertically with the phototransistors 16A and are disposed at intervals throughout the height of the intended marks A and I,---I so as to confront the marks A and I,-l as the label L advances in the direction of the arrow W.

The construction and operation of the reader 16, except for the location and layout of the phototransistors lloAlloC, is similar to the viewer described in the aforementioned US. Pat. No. 3,379,321. Suitable lamps, not shown, illuminate the label L as it advances past the reader 16.

Connected to the output of the phototransistors res-rec are conventional gate circuits ZllA-ZiiC, respectively. Should two or more of the phototransistors 1613 change their conduction state, then the logic output of gate circuit 2M3 will change. In a like manner, should two or more of the phototransistors 16A change their conduction state, then the logic output of the gate circuit 20A will change its logic output. The same applies for the gate circuit 20C with the understanding that the phototransistors 116C are involved.

A labelidentification detector to be described in detail hereinafter is connected to the gate circuits 20A20C over conductors 26A'-26C', respectively. In the output of the label identification detector 25 is a reject output conductor 27, which is connected to a conventional or gate circuit 30 and an enable output conductor 31, which is connected to a code reader and clock counter circuit that is coupled to a mark-space space detector 40. The label identification detector 25, in a manner to be described hereinafter, determines whether the label L is an intended label for the code detecting and control circuit 15.

If the printing on the label L is placed so that the synchronizing clock pulse marks C,C are adjacent to the label identification indicia A,--A in such a manner as to prevent the clock pulse sensors 163 and 16A from detecting any space between the label identification indicia A,A and the synchronizing clock pulse marks C,C then a reject signal is transmitted over the conductor 27. This reduces the possibility of reading a false code. Should the label L be excessively skewed, then a reject signal will be transmitted over the conductor 27. On the other hand, should the label L be the intended label, then an enabling signal is transmitted over the conductor 31, which is fed to the code reader and clock counter circuit 35 is connected to the reader 116 through the gate circuits ZllA-ZOC.

The code reader and clock counter circuit 35, which will be described in detail hereinafter, allows the reading of the destination code l,-l of label L to occur only while the

phototransistors

16B and 16A sense a synchronizing clock pulse mark and after the label L has been properly identified through the marks A,-A;,. To ensure that the sampling of the destination code occurs during the clock pulse duration and that valid synchronizing clock pulse marks are detected, the code reader and clock counter circuit 35 allows the clock pulse counting to occur only when the phototransistors 16A detect an absence of a clock pulse mark, while the phototransistors 116B detect the presence of a clock pulse mark. The destination code I,I in the form of binary bits are transmitted from the code reader and clock counter 35 serially over a conductor ill to an error detection and correction circuit 4S.

Connected to the output of the reader 16 over the

conductors

26A, 26B and 26C is the mark-space detector 40, which will be described in detail hereinafter. It is the mark-space detector 40 that determines whether the clock pulse marks are the intended marks. Toward this end, the spacing between phototransistors 16B and MA is predetermined to check the width of synchronizing clock pulse marks and the space between successive marks. If the sets of phototransistors [6B and MA sense simultaneously synchronizing clock pulse marks, then the mark-space detector 40 will transmit a reject signal over a conductor 46 to the or" gate circuit 30. The test to be performed is whether the intended synchronizing clock pulse mark is of a width greater than the space S, which is the distance between the

phototransistors

16B and 16A, and also whether the space between successive intended synchronizing clock pulse marks is less than the space S. Hence, a mark width greater than the acceptable minimum width and/or a space between successive marks less than the acceptable minimum distance will cause a reject signal to be transmitted over the conductor 46.

Another test performed by the mark-space detector 40 is whether the space between successive synchronizing clock pulse marks is greater than an acceptable maximum. Should the

phototransistors

16B and 16A at any time during the label read time sense simultaneously a lack of marks, a time delay is initiated which will provide a reject if at the end of the time period, the phototransistors 16A still sense the absence of a mark. When this condition occurs, the mark-space detector 40 transmits a reject signal over the conductor 46 to the or" gate circuit 30. The mark-space detector 40 will also transmit a reject signal over the conductor 46 when the

phototransistors

16A and 16C do not detect an absence of a code mark just prior to the phototransistors 16A detecting a clock pulse mark. This action guards against the possibility of a smudge or black mark in the area of the code marks from generating a code error,

The error detection and correction circuit 45, which will be described in detail hereinafter, detects and corrects individual errors in the destination code. A comparison check is made for errors and corrections. Over a conductor 389, the error correct and detect circuit 45 transmits a reject signal to the or" gate circuit 30. Also connected to the input of the or" gate circuit 3 is the conductor 27 over which is transmitted the label identification reject signal and the conductor 46 over which is transmitted the mark-space detector reject signal.

A reject logic signal over either the

conductor

27, 46 or 389 will produce a no-read signal from the output of the or" gate for transmission to a memory circuit 50. A read signal is transmitted from the error detection and correction circuit over a conductor 47 to the memory circuit 50 and if there are no reject signals over

conductors

389, 27, and 46, the or" gate circuit 30 will enable transmission of a code message to the memory circuit 50. When the memory circuit 50 receives the read signal over conductor 47, the destination code in the form of binary code bits is transmitted to the memory circuit 50 from the error detection and correction circuit over'conductors 60-65.

The memory circuit 50, which will be described in detail hereinafter, will control the operation of gates or diverters at sorting or diverting stations to sort the packages. The packages are selectively diverted into chutes, onto conveyors, for delivery to respective trucks.

LABEL IDENTIFICATION CIRCUIT As previously described, the logic output signals from the gate circuits 20A20C are transmitted over the conductors 26A26C, respectively, to'the label identification circuit 25 The label indicia identification circuit 76 includes a conventional and gate circuit 78 with its output connected to a pair of conventional flip-flop circuits 82 and 83. An inverter circuit 84 connects the output of the and" gate circuit 78 with the input side of the flip-flop circuit 82. in a like manner, the label indicia identification circuit 75 includes a conventional and gate circuit 85 with the output thereof connected to a pair of conventional flip-

flop circuits

86 and 87. An inverter circuit 88 connects the input of the flip-flop circuit 86 with the output of the and gate circuit 85. Similarly, the label indicia identification circuit 77 has a conventional and" gate circuit 89 with the output thereof connected to conventional flip-

flop circuits

90 and 91. The flip-flop circuit 90 is connected to the and" gate circuit 89 through an inverter circuit 92.

When the

phototransistors

16A, 16B and 16C detect a transition from a space or an absence of a mark to a label identification mark, the logic output of the gates circuits A, 20B, 20C, respectively, are changed to cause a change in the logic outputs of the and

gate circuits

85, 78 and 89, respectively. This action causes the flip-

flop circuits

87, 83 and 91, respectively, to change their conduction mode. When the

phototransistors

16A, 16B and 16C detect a transition from a mark to a space or an absence of a mark, then logic outputs of the gate circuits 20A, 20B and 20C cause the and

gate circuits

85, 78 and 89, respectively, to change the conduction state of the flip-

flop circuits

86, 82 and 90, respectively.

However, before the and

gate circuits

78, 85 and 89 can change their logic outputs, it is necessary that they be enabled to do so. This is accomplished by an enabling signal transmitted over a conductor 81 from a light sensing device 80, such as a photocell 80 (FIG. 2A). The photocell 80 is disposed along the path of travel of the package P. A source of light,.not shown, continuously casts a beam of light across the path of travel of the package P for impingement on the photocell 80. When the leading edge of the package P interrupts the beam of light, the photocell 80 changes its conducting state and remains in such a state until the trailing edge of the package P advances beyond a point in which the beam of light is no longer interrupted.

Prior to label identification, all flip-flop circuits are reset by the leading edge of the package P interrupting the beam of light cast toward the photocell 80. When the beam of light cast toward the photocell 80 is interrupted by the leading edge of the package P, the photocell 80 changes its state of conduction to transmit an enabling signal over the conductor 81. As a consequence thereof, a conventional or gate circuit 95 changes its logic output to cause a monostable single shot multivibrator 96 to change its state. The multivibrator 96 produces a reset pulse to reset all flip-flops of the label identification detector circuit 25, excepting an output conventional flip-flop 97.

The output flip-flop 97 is reset through the reset multivibrator 96 through conventional reset and"

gate circuits

98 and 99. A change in logic output of either the "and gate circuit 98 or the and" gate circuit 99 causes a conventional or circuit 100 to change its logic output. The change in logic output of the or gate circuit 100 produces a reset pulse to reset the output flip-flop circuit 97.

All the flip-flops of the label identification circuit will be reset if the phototransistors 16A detect a second transition from a label identification mark to a space or an absence of a mark without the phototransistors 16B detecting a transition from a label identification mark to a space or an absence of a mark. This is to reduce the possibility of sensing a series of narrow bars as the label identification code.

Toward this end, a reset conventional and" gate circuit .101 has a four input circuit. To change the logic output of the and" gate circuit 101, it is necessary to first change the mode of a conventional flip-flop circuit 110 by changing the logic output of a conventional and" gate circuit 103. This operation is efi'ected in the manner described in detail hereinafter. When the phototransistors 168 have not detected a label identification mark or have sensed a label identification mark for the first time, then one of the input circuits of the and gate circuit 101 is enabled from the logic output of the flipflop circuit 82 over a conductor 102. Also, the and gate circuit 103 had one of its input circuits enabled by the flip-flop circuit 82 changing its conduction mode. Another input circuit to the and gate circuit 103 was initially enabled over the conductor 111 by the flip-flop circuit 91 as described below.

At the time the phototransistors 16A make the second transition from a label identification mark to a space or absence of a mark, the flip-flop circuit 87 has a logic output to enable the and" gate circuit 101 over

conductors

104 and 105. At the same time, the flip-flop circuit 86 produces a logic output to enable the and gate circuit 101 over

conductors

121 and 107. In addition, the flip-flop circuit 87 through its logic output had enabled the and gate circuit 103 over a conductor 108. The last output of the and" gate circuit 101 is enabled through a conventional flip-flop circuit 1 10.

The mode of the flip-flop circuit is controlled by the logic output of the and" gate circuit 103. At this time two of the three inputs of the and gate circuit 103 is enabled. When the phototransistors 16C initially detected a space or absence of a label identification mark, an enabling signal is transmitted from the flip-flop circuit 91 to the and" gate circuit 103 over conductors 111 and 112.

Now, the and gate circuit 103 has changed its logic output to cause the flip-flop circuit 110 to change its mode. The and gate circuit 101 was triggered as the flip-flop circuit 86 changed its state. Thereupon, the "or" gate circuit 95 causes the multivibrator circuit 96 to produce a reset pulse in the manner previously described.

All flip-flop circuits of the label identification detection circuit are reset if the phototransistors 16A detect a second transition from a space or absence of a label identification mark to a label identification mark without the phototransistors 16C detecting a transition from a space or absence of a label identification mark to a label identification mark. This operation is accomplished through a reset conventional and" gate circuit 115 with three input circuits.

When the phototransistors 16A made a second transition from a space or absence of label identification mark to a label identification mark, the flip-flop circuit 86 enabled one input of the and gate circuit 115 over

conductors

116 and 117 and the flip-flop circuit 87 enabled another input circuit of the and gate circuit 115 over the

conductors

104 and 105. At the time the phototransistors 16C detect a space or absence of a label identification mark and before it undergoes a transition from a space or absence of a label identification mark to a label identification mark, the flip-flop circuit 91 enables the last input circuit of the and gate circuit 115 over the conductors 111 and 112 and a conductor 118. Thereupon, the "and" gate circuit 115 changes its logic output to change the logic output of the or gate circuit 95. This action causes the multivibrator 96 to produce a reset pulse and the flip-flop of the label identification detection circuit 25 are reset in the manner previously described.

All the flip-flops of the label identification detector circuit 25 are reset if the phototransistors 16A detect a second transi' tion from a label identification mark to a space or absence of a label identification mark while the phototransistors 16C sense a label identification mark. For this purpose, a reset conventional and gate circuit 120 with four input circuits is employed. This arrangement is intended to reset the flip-flops of the label identification detector circuit 25 should the intended label identification code not be detected.

When the phototransistors 16A detect the second transition from the black to white, one input of the and" gate circuit is enabled by the logic output of the flip-flop circuit 87 over the

conductors

104 and 105. Another input circuit of the and gate circuit 120 is enabled from the logic output of the flipflop circuit 86 over a conductor 121. Until the phototransistors 16C make a transition from a mark to a space or absence of a label identification mark, the flip-flop circuit 90 through its logic output enables another input circuit of the and" gate circuit 120 over a conductor 122. The last input circuit of the and gate circuit 120 is enabled by the logic output of the flip-flop circuit 91 over

conductors

123 and 124 when the phototransistors 16C detect a label identification mark for the first time.

From the foregoing, the and gate circuit 120 changes its logic output to cause the or" gate circuit 95 to operate the multivibrator 96. Thereupon, the multivibrator 96 produces a reset pulse to reset the flip-flop circuits of the label identification detector circuit 25 in a manner previously described.

in the exemplary embodiment of the present invention, in order for an enabling signal to be transmitted by the enabling output flip-flop circuit 97 over the conductor 31 to the code reading and clock counting circuit 35, the following conditions are to exist in the proper sequence:

1. Phototransistors 16A detect a label identification mark and neither the phototransistors 168 nor the phototransistors 16C have detected a label identification mark.

2.

Phototransistors

16B and 16C respectively detect a label identification mark for the first time and the photodetectors 16A are making their first transition from a label identification mark to a space or an absence of a label identification mark.

3. Phototransistors 16A sense the second label identification mark while the phototransistors 16B detect a space or an absence of a label identification mark after sensing a label identification mark, and the phototransistors 16C make their first transition from a label identification mark to a space or an absence of a label identification mark.

4. Phototransistors 16B sense their second label identification mark while the phototransistors 16C detect a space or an absence of a mark after detecting one label identification mark and the phototransistors 16A make their second transition from a label identification mark to a space or an absence of a label identification mark.

When the phototransistors 16A detect a label identification mark, the logic output of the flip-flop circuit 87 as transmitted over the conductor 108 enables one input circuit of the and gate circuit 103. While the phototransistors 16B detect a space or an absence of a label identification mark, the flip-flop circuit 82 through its logic output signal enables another input circuit of the and gate circuit 103. The last input circuit of the and gate circuit 103 is enabled over the conductors 112 and 111 by the logic output of the flip-flop circuit 91. This occurs when the phototransistors 16C detect a space or an absence of a label identification mark.

After the above conditions have been fulfilled, the logic output of the and gate circuit 103 is changed to cause the flipflop circuit 110 to change its state. By changing the state of the flip-flop circuit 110 a conventional and gate circuit 125 has one of its input circuits enabled.

At this time should the phototransistors 16B sense a label identification mark, then the logic output of the flip-flop circuit 83 transmitted over a conductor 126 enables another input circuit of the and gate circuit 125. With the phototransistors 16C sensing a label identification mark, a third input circuit of the and gate circuit 125 is enabled by the logic output of the flip-flop circuit 91 over the

conductors

123 and 124. When the phototransistors 16A make their first transition from a label identification mark to a space or an absence of a label identification mark, then the last input circuit of the and gate circuit 126 is enabled. This is accomplished by the logic output of the flip-flop circuit 86 transmitting an enabling signal over the conductor 116.

Now, the and gate circuit 125 has changed its logic output to cause a conventional flip-flop circuit 130 to change its conduction state. When the flip-flop circuit 130 changed its mode, an enabling signal was transmitted to one input circuit ofa conventional and gate circuit 131.

Now, the phototransistors 16A detect the second label identification mark. Thereupon, the flip-flop circuit 87 transmits a logic signal over the conductor 104 and over a conductor 132 to enable another input circuit of the and gate circuit 131. While the phototransistors 16A detect the second space or an absence of a label identification mark after detecting a label identification mark. As a consequence thereof, the flip-flop circuit 82 transmits an enabling signal over

conduc tors

133 and 134 to enable another input circuit of the and" gate circuit 131. When the phototransistors 16C make their first transition from a label identification code to a space or an absence of a label identification mark, the flip-flop transmits an enabling signal to another input circuit of the and" gate circuit 131 over

conductors

136 and 137.

As a result thereof, the and gate circuit 131 changes its logic output to cause a conventional flip-flop circuit 140 to change its state of conduction. This action enables one input circuit of an output enabling conventional and" gate circuit 141 through the logic output signal transmitted by the flip-flop circuit 140 over a conductor 142.

The other input circuit of the output enabling and gate circuit 141 is connected to the output of an output enabling conventional and gate circuit 143.

When the phototransistors 16B detect their second label identification mark, the flip-flop circuit 82 transmits an enabling signal over theconductor 133 and a conductor 144 to an input circuit of the and gate circuit 143. The flip-flop circuit 83, in turn, transmits an enabling signal over conductors 145 and 146 to another input circuit of the and" gate circuit 143. During this time, the phototransistors 16C detect a space or an absence of an identification mark. This results in the flip-flop circuit 90 transmitting an enabling signal over the conductor 136 to another input circuit of the and gate circuit 143. The phototransistors 16A detect the second transition from a label identification mark to a space or an absence of a label identification mark. This results in the flip-flop circuit 86 transmitting an enabling signal over a conductor 148 to another input circuit of the and gate circuit 143.

As a consequence thereof, the logic output of the enabling and gate circuit 143 is changed to change the logic output of the enabling and gate circuit 141. This action causes the enabling output flip-flop circuit 97 to change its mode for transmitting an enabling output signal over the conductors 31 to the code reader and clock counting circuit 35.

If the printing on the label L is placed so that the synchronizing clock pulses C C are adjacent to the label identification code A,A in such a manner as to prevent package P should the phototransistors 16C sense a label identification code when neither the phototransistors 16A nor the phototransistors 16B detect a space or an absence of a label identification mark.

When the foregoing occurs, an enabling signal ,is transmitted from the output enabling flip-flop circuit 97 to a reject conventional and gate circuit 150 over

conductors

151 and 152. Had the flip-flop circuit 97 changed its mode, then an inhibiting signal would be transmitted over the conductors 1S1 and 152 to the reject and gate circuit 150. The flip-flop circuit 82 transmits an enabling signal to another input circuit of the reject and gate 150 over the

conductors

133 and 144. Also, the flip-flop circuit 86 transmits an enabling signal over the

conductors

116 and 117 to another input circuit of the reject and gate circuit 150. Lastly, the flip-flop circuit 87 transmits an enabling signal over the

conductors

104 and 153 to another input circuit of the reject and gate circuit 150.

The reject and gate circuit 150 changes its logic output to transmit an enabling signal to a reject conventional and" gate circuit 155. Should the flip-flop circuit 140 have changed its mode in the manner above described, then another input circuit of the reject and gate circuit 155 is enabled over the conductor 142 to ensure that the condition remains unique. If the phototransistors 16C detect a label identification mark space or an absence of a label identification mark, then the flip-flop circuit 91 transmits an enabling signal over the conductor 111 and the conductor 112 to the last input circuit of the and gate circuit 155 to cause the and gate circuit 155 to change its logic output.

The change of logic output of the and gate circuit 155 causes a change of logic output in a reject conventional or gate circuit 156. The change in logic output of the or" gate circuit 156 produces a reject pulse for transmission over the conductor 27 to the reject or gate circuit 30.

If the phototransistors 16C detect a second transition from a mark to a space or an absence of a mark before the phototransistors 16B sense a second space or absence of a label identification mark, then the package P is to be rejected. This is intended to cover the condition in which the label L is excessively skewed or has a series of black marks simulating the label identification code marks.

For this purpose, a skewed reject conventional and gate circuit 160 has its output connected to an input circuit of the or gate circuit 156. While the phototransistors 16B detect a second label identification mark, the flip-flop circuit 83 transmits an enabling signal over the conductor 145 to one input of the and gate circuit 160 and the flip-flop circuit 82 transmits an enabling signal over the conductor 133 and a conductor 161 to another input circuit of the and gate circuit 160.

When the phototransistors 16C sense a second mark to space transition, the flip-flop circuit 90 transmits an enabling signal over the conductor 122 and a conductor 162 to enable another input circuit of the and gate circuit 120 and the flip-flop circuit 91 transmits an enabling signal over the conductors 111 and 112 to enable another input circuit of the and gate circuit 160.

Thereupon, the skewed reject and" gate circuit 160 changes its logic output to change the logic output of the or gate circuit 156 for the transmission of a reject signal over the conductor 27 to the or gate circuit 30 (FIG. 2B).

CODE READING AND CLOCK COUNTING CIRCUIT The code reading and clock counting circuit 35 (FIG. 4) comprises a code storage circuit 165 in the form of serially connected conventional shift register circuits 166-175. A bit code is stored in the 10 stages of shift register circuits 166 175 and each bit is advanced sequentially step-by-step from the first shift register stage 166 through the last shift register circuit 175.

To insure that the shift register circuits 166-175 of the code storage circuit 165 are reset before each label L is read by the

phototransistors

16A, 16B and 16C, (FIG. 2A) the photocell 80 in a manner previously described has the light cast toward it interrupted by the leading edge of the package P, which causes a signal to be transmitted over a conductor 176 to the input side of a conventional single shot multivibrator circuit 180, which in turn operates a conventional current driver circuit 181. The current driver circuit 181 produces a reset pulse just prior to the reader 16 detecting the label L. Thus, the shift register circuits 166-175 are reset just prior to reading and there is no residual count in the code storage circuit 165.

For shifting bit signals sequentially through the shift register circuits 166-175, the code reading and clock counting circuit 35 includes a clock pulse generator 190 that comprises a conventional current driver circuit 191. Each time the current driver circuit 191 operates, a shift clock pulse is transmitted simultaneously to the

shift register circuits

166 and 175 over a conductor 192. The shift clock pulse serves to advance each code bit in the shift register circuits 166-175 to the succeeding shift register circuit. The code bit stored in the shift register circuit 175 is advanced for transmission over the conductor 41 to the ergp detectionand correction circuit 45.

Connected to the input of the current driver circuit 191 is a conventional or gate circuit 193. The or" gate circuit 193 and the current driver circuit 191 insure a fast rise time pulse for the shifting of the code bits stored in the shift register circuits 166-175.

The or gate circuit 193 includes two input circuits. One

input circuit of the or" gate circuit 193 is connected to a read-out output conductor 195. The other input circuit of the or" gate circuit is connected to the output ofa conventional single shot multivibrator circuit 195. A conventional and" gate circuit 196 controls the operation of a flip-flop circuit 197, which in turn controls the operation of the single shot multivibrator 195'. Thus, the clock pulse generator for shifting serially and sequentially the code bits stored in the shift registers 166175 includes the and gate circuit 196, the flipflop circuit 197, the single shot multivibrator circuit 195', the or" gate circuit 193 and the current driver circuit 191. Each time the and gate circuit 196 changes its state to a positive pulse, the current drive circuit 19] produces a shift clock pulse for simultaneous transmission to the shift register circuits 166175.

The and gate circuit 196 has five input circuits. One input circuit is connected to the label identification circuit 25 over the conductor 31. Thus, a shift clock pulse can be generated only after the label identification circuit 25 has established that the label L is an intended label. Another input circuit is connected to the gate circuit 20A over the conductor 26A through an inverter circuit 198. A third input circuit is connected to the gate circuit 20B over the conductor 26B. The fourth input circuit of the and gate circuit 196 is connected to a counting circuit 200 so as to disable the change of state of conduction ofthe and gate circuit 196 when a count of I0 is reached to stop the generation of the shift clockpulses for a given label, such as the label L. It is the last input circuit that is connected to the output of the flip-flop circuit 197 to inhibit the and gate circuit 196 once the flip-flop circuit 197 has changed its state for the generation of a shift clock pulse. The flip-flop circuit 197 in turn is reset after the phototransistors 16A detect a mark and the phototransistors 16B detect a space or the absence of a mark.

The counting circuit 200 comprises four conventional flipflop circuits 201-204. A conventional inverter circuit 205 connects the multivibrator circuit 195 with the first flip-flop circuit 201 of the counting circuit 200. A conventional and gate circuit 206 has one input circuit thereof connected to the last flip-flop circuit 204. The other input circuit of the and gate circuit 206 is connected to the output circuit of the flipflop circuit 202 over a conductor 208. The output of the and gate circuit 206 is connected to the input side of the and gate circuit 196 over a conductor 209 and through an inverter circuit 210. The four flip-flop circuits 201-204 are connected to form a binary counter with the and" gate circuit 206. When a count of 10 clock pulses are generated for each label, the and gate circuit 206 changes its state to disable the and gate circuit 196 over the conductor 209.

When the reset pulse produced by the current driver circuit 181 resets the shift register circuits 166-175, the same reset pulse simultaneously resets the flip-flop circuits 201-204 by transmitting the reset pulse over a conductor 211. Thus, initially the flip-flop circuits 201-204 are in a zero state. This action ensures that no residual count exists due to noise or any other extraneous inputs.

For purposes of convenience the following table illustrates the state of the flip-flop circuits 201-204 during each decimal pulse count and thereby the operation of the counting circuit 200.

I The first pulse transmitted the multivibrator I 195 through the inverter circuit 205 changes the state of the flipflop circuit 201 from a logic state to a logic 1 state. It is the succeeding pulse that returns the flip-flop circuit 201 to its zero state and changes the flip-flop circuit 202 from a 0 logic state to a logic 1 state. The third and continuing pulses produce the logic states for the flip-flop circuits 201-204 in the manner shown above with the number of pulses represented by the decimal count.

After l0 pulses are fed to the counter circuit 200, the flipflop circuit 202 is in a logic 1 state to produce an enabling signal for one input circuit of the and gate circuit 206 and the flip-flop circuit 204 is at a logic 1 state to produce an enabling signal for transmission to the other input circuit of the and gate circuit 206 to change the state thereof. As a consequence thereof, an inhibiting signal is transmitted over the conductor 209 to the input side of the and gate circuit 196. During the decimal count 0-9, the flip-

flop circuits

202 and 204 are not simultaneously in a logic 1 state. Thus, only after the count of pulses does the and gate circuit 206 change its state.

Initially, all the shift register circuits 166-175 and the counting flip-flop circuits 201-204 are in a reset state. Thus, enabling signals are transmitted over the conductor 209 to the input side of the and gate circuit 196. If the intended label has been identified by the label identification circuit 25, an enabling signal is transmitted over the conductor 31 to the input side of the and gate circuit 196. When the phototransistors 16A have detected a mark and the phototransistors 16B have detected a space or an absence of a mark, enabling signals are transmitted over the conductors 26A and 268 to change the state of a conventional and gate circuit 215. A conventional inverter circuit 216 interconnects one input circuit of the and gate circuit 215 with the conductor 268. When the and gate circuit 215 changes its state, the flip-flop circuit 197 is reset for producing an enabling signal for transmission to the input side of the and" gate circuit 196. The operation of the flip-flop circuit 197 serves to ensure that the shift registers on the code reader to be described hereinafter advance in step with the clock counting pulses. In this manner both operations occur substantially simultaneously.

To insure that a valid synchronizing clock pulse is detected

by'the phototransistors

16A and 168, a counting pulse is generated only when the phototransistors 16B detect an intended synchronizing clock pulse, such as C C of label L, and the phototransistors 16A detect a space or an absence of a clock mark. This is the input function that basically provides the clock pulses. Both inputs are necessary in order to prevent clock pulses from being produced by dirt or extraneous black marks between clock pulses. From the foregoing, it is to be observed that each time the and gate circuit 196 changes its state to a positive pulse, it causes the flip-flop circuit 197 to operate the single shot multivibrator 195'. The multivibrator 195 produces a clock pulse having a leading edge that initiates the shift clock pulse transmitted to the shift register circuits 166-175 by the current driver circuit 191 while a trailing edge thereof through the inverter circuit 205 triggers the counter flip-flop circuits 201-204 and a shift register storage reset to be described hereinafter.

The code reading and clock counting circuit comprises a reader circuit 220. Included in the reader circuit 220 is the previously mentioned and gate circuit 215. Also, included in the reader circuit 220 is a conventional and gate circuit 221 with three input circuits. One input circuit is connected to the label identification enabling conductor 31 over a conductor 222. Another input circuit is connected to the conductor 26A over a conductor 223 and the third input circuit is connected to the conductor 26C. Over the conductor 26C is transmitted the destination code signals produced by the phototransistors 16C detecting the destination code indicia.

Thus, the and gate circuit allows the reading of the destination code, which destination code appears over the conductor 26C. This occurs only while the phototransistors 16A detect a clock pulse mark, such as marks C,C on label identification circuit 25 as an intended label.

When the and" gate circuit 221 changes its state of conduction in response to the destination code signals transmitted over the conductor 26A, which signals are initiated by the destination code marks I l a flip-flop circuit 225 changes its mode. The flip-flop circuit 225 in changing its conduction mode transmits an enabling signal to a conventional and gate circuit 226 of the reader 220. Also connected to the input side of the and gate circuit 226 over a conductor 227 is the output of the previously mentioned and gate circuit-215.

The and gate circuit 226 is enabled to advance the destination code transmitted from the flip-flop circuit 225 only when the phototransistors 16B detect a space or an absence of a clock pulse mark, while the phototransistors 16A detect the presence of a clock pulse mark. This is accomplished through the and gate circuit 215. In this regard, the and gate circuit 215 changes its state when the phototransistors 16A sense the presence of a clock pulse mark and the phototransistors 16B detect the absence of a clock pulse mark.

Connected to the output of the storage flip-flop circuit 230 are conventional and

gate circuits

231 and 232. Each time the flip-flop circuit 230 changes its state during the clock pulse count of 10 for a given label, the and gate circuits feed a destination code bit to the shift register circuit 166 over the

conductors

233 and 234.

The flip-flop circuit 230 in conjunction with the and" gate circuit 226 insures that only one code pulse could occur should the phototransistors 16A encounter several space areas during the destination code sampling time or should the phototransistors 16C encounter several space areas.

Should the counting circuit 200 register a count of 10 clock pulses by the and gate circuit 206 changing its state, an inhibiting signal is transmitted through the inverter circuit 210 over the conductor 209 and over a conductor 235 to inhibit the and

gate circuits

231 and 232 from changing their state and thereby preventing the further transmissions of code bits to the shift register circuit after the count of 10 clock pulses has been reached.

During the time the destination code from the circuit 165 is read from the transmission of destination code signals over the conductor 41, read out pulses are transmitted over the conductor in a manner to be described hereinafter. Such read-out pulses are applied to the input side of the or" gate circuit 193 to produce from the current driver circuit 191 shift clock pulses.

In addition thereto, the read out pulses transmitted over the conductor 195 advance through an inverter circuit 236 for application to the input sides of the and

gate circuits

231 and 232, respectively. This action inhibits code bits being transmitted to the shift register circuit 166 over the

conductors

233 and 234 during the time the destination code circuit 165 is being read.

MARK-SPACE DETECTOR CIRCUIT The mark-space detector circuit 40 is connected to the or" gate circuit 30 over the conductor 46 for transmitting thereto a reject signal should a clock pulse mark width be more than a predetermined width, should the space between clock pulse marks be less than a predetermined width, or should the space between clock pulse marks exceed a predetermined distance.

Toward this end, a conventional or gate circuit 250 (FIG. 5) has its output circuit connected to the conductor 46. When the or gate circuit 250 changes its state, a reject signal is produced in the output thereof for transmission over the conductor 46.

The or gate circuit 250 includes three input circuits. One input circuit is connected to a conventional and" gate circuit 251 over a conductor 252. Included in the and gate circuit 251 are two input circuits. One input circuit of the and" gate circuit 251 is connected to the conductor 268 through an and gate circuit 253 over a conductor 254. Another input ductor 26A through an and gate circuit 255 over a conductor 256. Also connected to the input sides of the and"

gate circuits

253 and 255 is the label identification enabling conductor 31.

As previously described, the spacing between the

phototransistors

16B and 16A is of the predetermined distance S (FIG. 2A) in order to check the width of synchronizing clock pulse marks and the space between successive synchronizing clock pulse marks to determine whether the synchronizing clock pulse marks are the intended ones.

If both sets of

phototransistors

16B and 16A detect simultaneously a synchronizing clock pulse mark then a rejection signal will be transmitted over the conductor 46. This action is predicated on the fact that the clock pulse mark width is greater than a predetermined distance or the space between successive clock pulse marks is less than a predetermined distance.

When the clock pulse mark is greater than a predetermined width or the space between successive clock pulse marks is less than a predetermined distance, the

phototransistors

16B and 16A will detect the clock pulse mark and the gate circuits 20B and 20A will change their state of conduction. As a consequence thereof, the and

gate circuits

253 and 255 will change their state when the label identification circuit 25 has transmitted an enabling signal over the conductor 31. This results in the and gate circuit 251 changing its state to cause the or" gate circuit 250 to change its mode for the transmission of a rejection pulse over the conductor 46.

To test for a maximum allowable space between successive synchronizing clock pulses, a time delay circuit 260 is provided which includes a conventional and" gate circuit 261 with three input circuits. One input circuit of the and gate circuit 261 is connected to the output of the and gate circuit 253 through an inverter circuit 262. Another input circuit is connected to the output circuit of the and gate circuit 255 through an inverter circuit 263. The third input circuit of the and" gate circuit 261 is connected to the label identification enabling conductor 31 via a conductor 264.

When the

phototransistors

16B and 16A simultaneously sense a space or absence of clock pulse marks, while an enabling signal is transmitted from the label identification circuit 25, the output signals from the and

gate circuits

253 and 255 through the

inverter circuits

262 and 263, respectively, cause the and" gate circuit 261 to change its state. This action causes a single-shot multivibrator circuit 265 to operate. Normally, the output of the multivibrator circuit 265 is a logic 1 signal. When the and circuit 261 changes its state, the multivibrator circuit 265 within a fixed time period goes from a logic 1 output to a logic output and then back to the logic 1 output to produce a predetermined time delay.

' Connected to the output of the multivibrator 265 is a conventional flip-flop circuit 266, which serves to provide an output pulse at the conclusion of the timing period which is when the multivibrator circuit 265 returns to the logic 1 output. The flip-flop circuit 266 in conjunction with a multivibrator 272 serves to inhibit the production of a reject pulse before the commencement of the time delay period.

A conventional and" gate circuit 270 has one input thereof connected to the output of the flip-flop circuit 266 and another output thereof connected over the following path: conductor 271, the inverter circuit 263 and the and gate circuit 255.

Should the phototransistors 16A still sense a space or absence of a clock pulse mark after the time delay period, a reject pulse would be transmitted over the conductor 46. With the phototransistors 16A still sensing a space or an absence of a clock pulse mark after the time delay period, the and gate circuit 270 changes its state to cause the or gate circuit 250 to emit a reject pulse over the conductor 46.

On the other hand, should the phototransistors 16A sense a clock pulse mark during the time delay period, then the and" gate circuit 270 is inhibited over the conductor 271 and does not change its state. Hence, no reject pulse is produced by the or" gate circuit 250.

When the phototransistors 16A detect a clock pulse mark, the multivibrator 272 connected to the output of the and" gate circuit 255 over a conductor 273 resets the multivibrator 265 and the flip-flop circuit 266. In this manner, the multivibrator circuit 265 commences another timing cycle the moment the

phototransistors

16A and 16B simultaneously detect an absence of a clock pulse mark or a space.

To reduce the possibility of a smudge mark or an accidental black mark in the area of the destination code I,l from generating a code error, a conventional or" gate circuit 274 has its input circuits connected to the and"

gate circuits

253 and 255, respectively, over conducts 275 and 276, respectively. Connected to the output of the or" gate circuit 274 is a conventional flip-flop circuit 280 and connected to the output circuit of the flip-flop circuit 280 is a conventional flip-flop circuit 281. A conventional and" gate circuit 282 has one input circuit thereof connected to the output of the fiipflop circuit 280 and the other input circuit thereof connected to the output side of the flip-flop circuit 281.

Each time either the phototransistors 16A or the phototransistors 16B detect the transition from a space to a clock pulse mark, the or" gate circuit 274 changes its state to sequentially operate the counting flip-

flop circuits

280 and 281.

A reset circuit 285 is connected to the counting flip-

flop circuits

280 and 281, which includes a conventional and gate circuit 286 and a conventional reset multivibrator circuit 287. One input circuit of the and" gate circuit 286 is connected to the conductor 26A through the and" gate circuit 255 and the inverter circuit 263. The other input circuit of the and" gate circuit 286 is connected to the conductor 26C through a conventional and gate circuit 288 and an inverter circuit 289.

Should the

phototransistors

16A and 16C detect simultaneously a space or an absence ofa mark, then the "and gate circuit 286 changes its state to operate the reset multivibrator 287 for resetting the counter flip-

flop circuits

280 and 281. On the other band, should the

phototransistors

16A and 16B detect in the aggregate three transitions from a space to a black mark so as to produce a count of 3 in the flip-

flop counting circuits

280 and 281 before the

phototransistors

16A and 16C simultaneously detect a space, then the and" gate circuit 282 changes its state to transmit a reject pulse over the conductor 250.

ERROR DETECTION AND CORRECTION CIRCUIT The error detection and correction circuit 45 (FIGS. 6A- 6C) detects and corrects single errors in the destination 10- bit code message. As previously described, the code storage circuit of the code reading and clock counting circuit 35 transmits serially over the conductor 41 the destination lO-bit code message.

Included in the error detection and correction circuit 45 is a four-bit shift register, parity check circuit 290 and a l0-bit shift register destination code storage circuit 295. The l0-bit destination code message transmitted over the conductor 41 is fed simultaneously to the parity check circuit 290 and the destination code storage circuit 295. The parity check circuit 290 performs a parity check with two adjacent destination code bits to check destination code bits that are three bits removed. The destination code storage circuit 295 stores I0- bit destination code message and transmits in parallel over the conductors 60-65 the destination code message to the memory circuit 50, when a message read signal is transmitted to the memory circuit 50 over the conductor 47. In practice only the first six bits are transmitted and the remaining bits are used for parity checking.

Also included in the error detection and correction circuit 45 is a clock pulse generator 300 (FIG. 6A), which provides read-out pulses for transmission over the conductor to the code reader and clock counter circuit 35 via conductor 301, conductor 302, a conventional nand" gate circuit 303 and an inverter circuit 304. In addition thereto, the clock generator 300 transmits the clock shifting pulses for the parity check shift register circuit 290 and the storage shift register circuit 295.

Connected to the output of the clock generator 300 is a binary counter circuit 305, which limits the clock pulse count for a given label to 20 clock pulses. After the count of 10 clock pulses, the binary counter 305 serves to turn off the transmission of clock pulses from the clock pulse generator 300 to the reading and clock counting circuit 35 to discontinue the read-back pulses transmitted over the conductor 195 by inhibiting the nand gate circuit 303 over a conductor 306. The binary counter 305 through its conventional flip-flop circuit 307 produces a read signal for the memory circuit 50 by way of the conductor 47 and a conductor 308 and also produces an enabling signal for the or" gate circuit 30.

The error detection and correction circuit 45 also includes exclusive or" function mod-2 summation circuits 310-312. During the destination code reading time for each label, the storage shift register circuit 295 undergoes a total of 20 clock pulse shifts. The first 10 clock pulse shifts serve to feed into the shift register circuit 295 the 10-bit destination code message. The last 10 clock pulse shifts is the correction period, in which the output of the shift register circuit 295 is fed back into the input end thereof through the exclusive or" function summation circuit 312. The exclusive or function summation circuit 312 receives the stored IO-bit destination code from the storage shift register circuit 295 and compares it with the stored information in the parity check shift register circuit 290. It is the exclusive or function summation circuit 311 that performs a parity check in the last two stages of the four-bit shift register parity check circuit 290. The exclusive or function summation circuit 311 receives the output of the summation circuit 310 and compares it with the incoming l-bit destination code message transmitted over the conductor 41.

The incoming -bit destination code message transmitted serially over the conductor 41 changes the logic output of a conventional nand gate circuit 315 as each bit is fed thereto. The nand" gate circuit 315 is enabled during the previously mentioned 10 clock pulse count for each label. Connected to the output of the nand gate circuit 315, over a conductor 316 is a conventional or gate circuit 317. As the or gate circuit 317 changes its logic output for each change of logic output of the nand gate circuit 315 a destination code bit is fed directly to the lO-bit shift register storage cir' cuit 295 and also optionally through an inverter circuit 318.

Included in the storage circuit 295 are 10 conventional flipflop circuits 320-329. The 10-bit destination code is fed serially and initially to the flip-flop circuit 320 and then advanced by shift clock pulses sequentially through the storage circuit 295.

During the time the destination code' bits are being fed to the shift register storage circuit 295, the destination code bits are fed to the four-bit parity check, shift register circuit 290 over a path including the conductor 41, the hand gate circuit 315, an inverter circuit 319 and the exclusive or function circuit 311. The 4 shift register, parity check circuit 290 includes conventional flip-flop circuits 320'323'. Destination code bits are fed serially and initially to the flip-flop circuit 320' and then advanced by shift clock pulses sequentially through the parity check circuit 290.

The shift clock pulses for shifting the destination code bits through the parity check circuit 290 and the storage shift re gister circuit 295 are generated by the clock pulse generator 300. As shown in FIG. 6A, the clock pulse generator 300 comprises a conventional nand gate circuit 325, an inverter circuit 326', a conventional monostable multivibrator 327, a conventional monostable multivibrator 320, a conventional nand gate circuit 329 and a suitable amplifier 330. The nand" gate circuit 325, the inverter circuit 326, and the multivibra'tors 327' and 328' are connected up as an oscillator with conductor 331 constituting a feedback loop and the nand gate circuit 325' disposed in the feedback loop.

Initially, one input circuit of the nand" gate circuit 325' is fed an enabling signal over a conductor 332. After 20 pulses have been counted, by the binary counter circuit 305 for a given label, such as the label L, an inhibiting or turn off signal is transmitted over the conductor 332. The third input circuit of the nand gate circuit 325 is connected to a conductor 335 over a conductor 336. Connected to the conductor 335 is the output of a photocell 340 (FIG. 2A).

A source of light, not shown, casts a beam of light across the path of travel of the package P and toward the photocell 340 When the leading edge of the package P interrupts the beam of light cast toward the photocell 340, an enabling signal is transmitted over the conductor 335 to change the logic output of the hand gate circuit 325 thereby turning on the clock pulse generator 300. The clock pulse generator 300 is turned off when the binary counter 305 makes a 20 count. The photocell 340 is located so that the light impinging thereon is interrupted by the leading edge of the package P after the destination code has been read by the reader 1.

The clock pulse generator 300 (FIG. 6A) transmits shift clock pulses to the storage shift register circuit 295 over the conductor 301 and a conductor 335 and also transmits shift clock pulses to the parity check shift register circuit 290 over the conductor 301 and a conductor 336'. In addition thereto, the clock pulse generator 300 transmits pulses over the conductor to the code reader and clock counter circuit 35 through the' hand gate circuit 303 and the inverter circuit 304.

During the first 10 clock pulse count for the binary counter 305 for a given label, the binary counter 305 transmits over the conductor an enabling signal to the nand" gate circuit 303, thereby permitting the transmission of pulses to the code reader and clock counter circuit 35. During the last 10 clock pulse count for the binary counter 305 for a given label, the binary counter 305 transmits an inhibiting signal over the con ductor 306 to prevent the transmission of read-out pulses over the conductor 195.

In addition to the foregoing, the clock pulse generator 300 transmits clock pulses to the binary counter circuit 305, which limits the clock pulse count to 20 for a given label, such as the label L. The binary counter 305 comprises four conventional flip-flop circuits 340-343 connected for a conventional binary counting operation. The clock pulses produced by the clock pulse generator 300 are fed to the flip-flop circuit 340.

Connected to the output side of the flip-flop circuit 343 is a conventional nand gate circuit 344 and an inverter circuit 346. Substantially in a manner previously described in detail in connection with the operation of the counting circuit 200 in the code reading and clock counting circuit 35, the binary counter 305 counts to 10. At the end of a IO-pulse count, the nand gate circuit 344 changes its logic output. As a consequence thereof, a lO-count flip-flop circuit 345 changes its state after each 10 count.

After the first 10 count for a given label, the flip-flop circuit 345 transmits over the conductor 306 a disabling signal to prevent the nand gate circuit 303 from transmitting shift pulses to the code reader and clock counter circuit 35 over the conductor 195. Also, the flip-flop circuit 345 at the end of the first 10 count for a given label transmits a disabling signal over the conductor 306 and over a conductor 356 to the nand" gate circuit 315 to prevent any destination code bits after 10 for a given label being transmitted to either the parity check shift register circuit 290 or the storage shift register circuit 295. In addition, an enabling signal is transmitted over a conductor 347 to a conventional nand gate circuit 348 in the storage shift register circuit 295.

When the flip-flop circuit 345 changed its mode, a conven tional nand gate circuit 350 has an enabling signal transmitted to its input side. After the ZO-pulse count for a given label, the flip-flop circuits 342 and 343 of the binary counter circuit 305 cause the nand gate circuit 350 to change its logic output. This action causes the 20-count flip-flop circuit 307 to change its mode via an inverter circuit 351.

By changing the mode of the 20-count flip-flop circuit 307, an inhibiting signal is transmitted over the conductor 332 to inhibit the nand" gate circuit 325', thereby turning off the clock pulse generator 300 after the count of 20. Over the

conductors

308 and 47, the flip-flop circuit 307 transmits a readout signal to the memory circuit 50. Lastly, the flip-flop circuit 307 transmits an enabling signal to a conventional nand gate circuit 353 through an inverter circuit 354 is the multiple error reject or" gate circuit 30.

As previously described, the storage 10-bit shift register 295 stores 10 code bits of infonnation during the first 10-clock pulse count for a label. The shift register 295 is reset when the package following the package P has its leading edge interrupt the light cast toward the photocell 80. When the light casts toward the photocell 80 is interrupted by the succeeding package, a signal is transmitted over a conductor 355, through

reset amplifiers

356 and 357 and over

conductors

358 and 359 to reset the flip-flops 320-329. The binary flip-flop 340-343 are reset at the same time over a path including the conductor 355, the amplifier 356 and a conductor 360. Simultaneously, the flip-flops 320'-323' are reset by the reset pulse transmitted over the conductor 355, the amplifier 356 and conductors 361-363.

Reverting back to the condition in which the shift register storage circuit 295 stores and holds 10 destination code bits during the first 10 count of a given label stores. The second 10 count of a -pulse count for a given label is used to correct any errors in the destination code. In practice, the last six stages of the storage shift register circuit, namely: flip-flops 324-329 are brought out as inputs to the code memory. The remaining code 10 are employed for visual purposes. During the last lO-count of the 20-pulse count for the correction process, the output of the storage shift register circuit 295 is fed from the flip-flop 329 to the exclusive or summation circuit 312 over a conductor 365.

exclusive or summation circuit 312 comprises nand" gate circuits 366-369. Each nand" gate has 2 input circuits and one output circuit. The output of the storage shift register circuit 295 is fed to the input side of the nand gate circuits 366 and 269 of the exclusive or circuit 312 over the conductor 365. It is the function of the exclusive or circuit 312 to receive the code bits shifted from the output of the storage shift register circuit 295 and compare it with the stored code bits in the parity check shift register circuit 290.

As previously described, code bits are fed over the conductor 41, through the and" gate circuit 315, the inverter circuit 319, the exclusive or summation circuit 311 into the fourcode bit parity check shift register circuit 290. The output sides of the flip flop 320-323 of the parity check shift register circuit 290 are fed to the input side of a conventional nand gate circuit 370, which in turn has its output side connected to the input sides of the

nandcounting gate circuits

366 and 367 of the exclusive or circuit 312.

Now, the exclusive or circuit will receive the code bits shifted around the lO-bit shift register storage circuit 295 and compare it with the stored bits in the parity check shift register circuit 290 and correct for single errors registering in the storage shift register circuit 295. This is accomplished through the output of the exclusive or circuit 312 taken from the nand" gate circuit 368, through an inverter circuit 371, the and gate circuit 348 and the or circuit 317 to the shift register circuit 295.

The exclusive or" summation circuit 310 includes four conventional nand" gate circuits 372-375. Each nand" gate circuit has two input circuits with one output circuit. The output of the third flip-flop circuit 322 of the parity check shift register circuit 290 is connected to the input sides of the nand"

gate circuits

374 and 375 of the exclusive or circuit 310. The output of the fourth flip-flop circuit 323' of the parity check shift register circuit 290 is connected to the input sides of the

hand gate circuits

374 and 373 of the exclusive or circuit 310. The output of the exclusive or circuit 310 is connected to the input side of the exclusive or summation circuit 311. It is the exclusive or circuit 310 that makes a parity check on the code bits using the flip-flop circuits 322' and 323 of the parity check shift register circuit 290.

As shown in FIG. 6A, the exclusive or circuit 311 includes four conventional nand" gate circuits 376-379. Each nand" gate circuit has two input circuits and one output circuit. It is the output of the exclusive or summation circuit 310 that is connected to the input sides of the nand"

gate circuits

376 and 378 of the exclusive or summation circuit 311. Also, the lO-bit destination code is transmitted over the conductor 41 from the code reading and counting circuit 35 for feeding to the nand"

gates

376 and 377. The output side of the exclusive or circuit 3]] taken from the nand" gate circuit 379 is fed directly to the flip-flop circuit 320' of the parity check flip-flop circuit 290 and also optionally through an inverter circuit 382. It is the exclusive or" circuit 311 that compares the output if the exclusive or" circuit 310 with the incoming destination code bits. Thus, any incoming destination code bit is compared with the last two bits in the parity check, shift register circuit 290. In this manner, two adjacent bits are used to check bits that are three bits removed.

Connected to the output sides of the flip-flop circuits 320': -323 of the parity check, shift register circuit 290 is a conventional or gate circuit 385, which has its output connected to the input side of the nand gate circuit 353. Should the parity check shift register circuit 290 detect an excessive number of errors, then the logic output of the "or" gate circuit 385 will be changed. This action enables the nand" gate circuit 353. At the end of the 20 count, the nand" gate circuit 353 is also enabled by the flip-flop circuit 307. Another enabling circuit for the nand" gate circuit 353 is through a flip-flop circuit 386 and an inverter circuit 387. When the logic output of the nand" gate circuit 370 is changed, the flip-flop circuit 386 changes its mode. The flip-flop circuit 386 is reset from a signal transmitted over the path including the conductor 361 and a conductor 388. When the nand gate circuit 353 changes its logic output, a reject signal is transmitted to the or" gate circuit over a conductor 389.

The reject circuit 30 transmits a reject signal over the ap propriate conductors 51 when either a reject signal is transmitted over the label identification reject conductor 27, the mark space reject conductor 46 or when the parity check shift register circuit 290 detects multiple errors.

If the code reader and clock counter circuit has not counted to 10 before the photocell 340 has changed its state, a nand gate circuit 390 changes its logic output to transmit a reject signal to the or" logic circuit 30 over a conductor 391. The photocell 340 changes its state when the leading edge of the package P has interrupted the beam of light cast toward the photocell 340.

The photocell 340 is connected to the input side of the nand" gate circuit 390 over the conductor 335. The code reader and clock counter circuit 35 is connected to the input side of the error detection and correction circuit from the and gate circuit 206 thereof (FIG. 4) over a conductor 392 and through an inverter circuit 393.

When no reject signal is transmitted from the or" gate circuit 30 to the memory circuit 50 and a signal for the memory circuit 50 to read is transmitted by the error detection and correction circuit 45 over the conductor 47, the destination code bits stored in the storage shift register circuit 295 are transmitted simultaneously or in parallel to the memory circuit 50 over the conductors -65. Also, the destination code bits are transmitted over conductors 60'-69 to visual indicators for checking the information in the storage shift register 295.

MEMORY CIRCUIT The memory'circuit 50 (FIG. 8) upon command from the error detection and correction circuit 45 over the conductor 47 receives from the error detection and correction circuit 45 destination code bits over the conductors 60-65. In turn, the

Claims

1. A code detecting and control circuit for scanning a moving object having thereon a series of spaced clock pulse indicia and a related series of spaced code indicia which normally conform to a uniform standard width and a uniform standard spacing between standard width marks that exceeds the mark width, said code detecting and control circuit comprising first, second and third indicia detectors for producing output signals in response to indicia sense, said first and second indicia detectors being spaced apart in the direction of travel of the moving object by a distance greater than the width of a conforming clock pulse indicium and different than the space between any two clock pulse indicia and positioned to detect the clock pulse indicia in sequence as the object moves past each detector, said third indicia detector being positioned to detect in sequence the code indicia related to the clock pulse indicia at the time the clock pulse indicia is sensed by said first indicia detector, circuit means connected to said first, second and third indicia detector for registering code signals in binary number form representing the simultaneous occurrences and nonoccurrences of clock and code indiciums sensed by the first and third indicia detectors, and a clock pulse testing circuit connected to said first and second indicia detectors for simultaneously sensing the outputs thereof to produce a control signal if both outputs are of a predetermined sense at the time of sensing.

2. A code detecting and control circuit as described in claim 1 wherein said first and second indicia detectors are spaced apart by a distance greater than the width of a conforming clock pulse indicium and less than a space between successive clock pulse indicia, and said clock pulse testing circuit produces a reject signal in response to both said first and second indicia detectors simultaneously sensing clock pulse indicia.

3. A code detecting and control circuit as described in claim 2 wherein said clock pulse testing circuit includes a time delay circuit that initiates a predetermined time delay period in response to both said first and second indicia detectors simultaneously sensing a space between clock pulse indicia, and said clock pulse testing circuit produces a reject signal after expiration of the time delay period if said first indicia detector fails to sense a clock pulse indicia during the time delay period.

4. A code detecting and control circuit as described in claim 1 wherein said first, second and third indicia detectors sense transition between indicia and spaces and said circuit means produces a reject signal responsive to said first and second indicia detectors sensing transitions from indicia to space and back to indicia without said third indicia detector sensing a space.

5. A code detecting and control circuit as described in claim 1 wherein said moving object includes identification indicia; said first, second and third indicia detectors sense transitions between indicia and spaces; and an identification circuit connected to said first, second and third indicia detectors for sensing sequentially transitions detected by each indicia detector and producing an enabling signal to said circuit means responsive to sensing a predetermined sequence of transitions representing an identification code.

6. A code detecting and control circuit as described in claim 5 wherein said first and second indicia detectors are spaced apart in the direction of travel of the moving object by a distance less than the width of an identification indicium, and said identIfication circuit resets without producing an enabling signal when the first indicia detector senses two transitions before the second indicia detector senses one transition.

7. A code detecting and control circuit as described in claim 5 wherein said first and third indicia detectors are spaced vertically in relationship to each other, and said identification circuit resets without producing an enabling signal when the first indicia detector senses two transitions before the third indicia detector senses one transition.

8. A code detecting and control circuit as described in claim 5 wherein said clock pulse testing circuit produces a reject signal in response to the first indicia detector sensing a clock pulse indicium at the same time that the second indicia detector senses an identification indicium.

9. A code detecting and control circuit as described in claim 1 including an error detection and correction circuit connected to said circuit means for checking the code signals registered in binary number form and correcting single signal errors therein.