US3098161A

US3098161A - Bilaterally operable transistorized shifting register

Info

Publication number: US3098161A
Application number: US749865A
Authority: US
Inventors: Bizet Pierre Michel
Original assignee: Compagnie Industrielle des Telephones SA
Current assignee: Compagnie Industrielle des Telephones SA
Priority date: 1958-07-21
Filing date: 1958-07-21
Publication date: 1963-07-16
Anticipated expiration: 1980-07-16

Description

July 16, 1963 P. M. BIZET 3,

BILATERALLY OPERABLE TRANSISTORIZED SHIFTING REGISTER Filed July 21, 1958 3 Sheets-Sheet 1 Fig.1

Lu u W 26 2 U2 Ul 2d I I l2 I l l /NV/V7'0/? Fig.2

P/fF/Yf 3/2157- Afro/FIVE),

July 16, 1963 P. M. BIZET 3,

BILATERALLY OPERABLE TRANSISTORIZED SHIFTING REGISTER Filed July 21, 1958 5 Sheets-Sheet 3 United States Patent 3,098,161 BILATERALLY OPERABLE TRANSISTORIZED SHEFTING REGISTER Pierre Michel Bizet, Saint-Quest, France, assignor to Compagnie Indnstrielle des Telephones, Paris, France, a corporation of France Filed July 21, 1958, Ser. No. 749,865 10 Qiaims. (Cl. 307-885) This invention relates to electrical signal conversion circuits, more particularly to such circuits comprising information storage devices of the type useful, for example, in encoding and decoding signals in telegraphic comrnunication.

It is known that each sign or character of the: arhythmic telegraphic code is constituted by five elementary signals of positive or negative polarity, said signals are preceded by a start signal of negative polarity and followed by a stop signal of positive polarity. The purpose of the transmitting apparatus of telegraphic signals is to provide a means for having one of the 2 :32 characters of the telegraphic alphabet correspond to one of the combinations of the five elementary signals of the code, for transmitting said combination in a correct order with a start signal at the beginning and a stop signal at the end.

The receiving apparatus of arrhythmic telegraphic signals have the purpose of converting the 2 combinations of five elementary signals into the corresponding 2 signs or characters of the telegraphic alphabet.

For each combination, such conversion can only be made after the five elementary signzds of the coded character combination have been received, that is to say, after the transmission of the character is completed. As a consequence it is necessary to have these five characteristic signals recorded until the time the receiver has them converted into the sign or character they stand for.

In mechanical devices such functions are provided by displacement of mechanical components.

In certain electronic receiving devices, it is necessary to record successively the five elementary signals of the code when they appear on the receiving line, then to reveal their polarity, simultaneously and instantaneously,

at live different terminals in order to make the decoding conversion possible.

In certain other electronic transmitting or recording devices, it is necessary to impose simultaneously and instantaneously at five different terminals, signals con-responding to the signal elements of a coded character and to reveal the polarity of such signal elements sequentially for transmission or recording thereof.

In what follows the recording function will be referred to as series recording. The function consisting of simultaneously revealing the recorded data will be known as parallel output.

The designation of the sign or character to be trans mitted can be done:

(a) Either by immediate designation of said sign or character, for instance, by pushing down the appropriate key of a keyboard,

(12) Or by simultaneous and instantaneous indication of the five elements of the code corresponding to the sign or character.

In any event the transmitting apparatus will transform the above designation (a) into the indication (b) before proceeding with the transmission.

Generally speaking, the function consisting of indicating simultaneously and instantaneously the information to be eventually transmitted sequentially will be referred to as the parallel input; and the function which consists of transmitting successively the recorded data will be known as the series output. The complementary 3,098,161 Patented July 16, 1963 ice functions for the insertion of the start and stop signals will be considered as auxiliary since they are not indispensable when the sign or telegraphic character emitted is only characterized by its five code signals, as it is for instance in the rhythmic telegraphic transmitting systems.

Accordingly, it is an object of this invention to provide improved circuitry for accomplishing the above-mentioned and other information storage functions.

Another object of this invention is to provide improved circuitry for accomplishing the foregoing series output and parallel output functions.

Still another object of the present invention is to provide improved bi-stable circuits which are useful in combination in, for example, information storage circuits having either series output or a parallel output function.

Still another object of the present invention is to provide simplified .transistorized circuits of the aforementioned types.

A further object of this invention is to provide simplified and improved means for cryptographically coding a conventional telegraphic coded message.

Another object is to provide improved means for decoding the aforementioned cryptographic code.

Another object of this invention is to provide an improved plural element chain-like circuit arrangement having either a single input or a single output and wherein stored information is transferred progressively along said chain from element to element in a controlled manner from or toward the input or output, respectively.

Still another object of this invention is to provide a circuit in which the direction of transfer of information from one information storage element to another is readily changed and wherein the circuit may be used for both series output and parallel output functions.

Still another object of the present invention is to provide improved signal input apparatus for circuits of the above rnentioned types.

In accordance with this invention, novel transistorized bi-stable information storage circuits are used in various combinations for storing at any instant information that can be indicated by the condition of stability. Such storage circuits are connected in chain-like relationship with one input and plural outputs for effecting parallel output functions or with plural inputs and one output for effecting series output functions. Adjacent storage circuits in the chain may be coupled so that information may be passed successively from circuit to circuit by controlling the condition of stability of each circuit in a manner dependent on the signal elements of the character being hand-led.

Moreover, this invention includes means for further controlling the stability of each circuit in a manner to arbitrarily and cryptographically further code and decode the coded information handled in the chain-like circuits.

The foregoing objects, features and advantages of the present invention will become more obvious from the following description when taken in connection with the accompanying drawing which shows, for purposes of illustration only, several embodiments in accordance with the present invention, and wherein:

FIGURE 1 is a schematic circuit of a bistable signal storage circuit or bascule,

FIGURE 2 illustrates the relationship of the potentials at various points in the circuit of FIGURE 1 during the operation thereof,

FIGURE 3 is a schematic circuit of a parallel output device according to the present invention, and

FIGURE 4 is a schematic circuit of a series output device according to the present invention and further showing in dotted lines means for making the circuit useful for use as a parallel output device.

The first device to be described allows to realize the series recording and the parallel output.

In the similar devices previously realized such functions were assumed either by mechanical or electromechanical organs or by electronic tubes.

The system according to the present invention utilizes a series of bi-stable circuits of a type commonly known as multi-vibrator-s or flip flop circuits each including a pair of transistors.

Prior to considering one specific embodiment of the arrangement according to the present invention, it is believed helpful to analyze the characteristics and mode of operation of one of these elementary bi-stable, multivibrator circuits having two resistors which form the bistable circuit. Such a bi-stable circuit is illustrated in FIGURE 1. It will be observed that the transistorsunder consideration in the following text of this application are of the n-p-n type, it being understood, however, that transistors of the p-n-p type may equally well be utilized since such a substitution only necessitates the use of inverse polarities.

Referring now to FIGURE 1, reference numerals 1 and 2 designate two transistors of which the collector, emitter and base electrodes are connected to the supply and control circuits by respective points of connection. The source of high voltage of any appropriate value, for example, of twenty volts is connected to point 3 of the schematic wiring diagram of FIGURE 1 which constitutes the common point of connection of the two collector electrode terminals 7 and 11, whereby

coupling resistances

4 and 5 are provided for the respective collector electrodes 7 and 11 of the transistors 1 and 2 in the circuits connecting the collector electrodes with point 3. A common source of energy with a relatively lower voltage of any suitable value, for example, of four volts, supplies the two emitter electrodes with such low voltage at common point 6 which may be the common terminal of the two emitter electrodes. The base-emitter circuit of each transistor is closed through ground across resistors 14 and for the transistors I and 2, respectively. The criss-cross connection, characteristic of the Eccles-Jordan type multi-vibrator circuit, is completed in the circuit diagram of FIGURE 1, by the fact that the collector of each transistor is coupled with the base of the other transistor by the intermediary of resistances 9 and 3 for the transistors 1 and 2, respectively.

It will be apparent from the following description that as soon as one of the two transistors, for example, transistor 1 is in the passing or conductive condition, the other transistor, namely the transistor 2 in that case, is cut olf or blocked, that is, non-conducting. In effect, if the transistor 1 passes or is in the conductive condition, the collector emitter voltage is relatively low and the voltage at point 7 is practically that of point 6. The voltage at the point of connection or juncture of resistors 9 and 10 which as a result thereof is lower than that of point 6 is also applied to the base at 8 of the transistor 2, and as a result thereof, the latter cannot start to become conductive but remains blocked under these conditions. The transistor 2 being blocked as a result of the bias voltage thus applied to the base 8, it is the voltage at point 3 which determines the voltage of the point 11 which in turn becomes noticeable or is indicated over the line 25 as a high difference of potential with respect to ground whereas line 22 indicates by a relatively low potential the conducting status of the transistor 1. The resistances 13 and 14 of the voltage dividing network which connects the collector 11 to ground are such that the voltage applied -to the base electrode 12 of the transistor 1 renders the same conductive. The crossed connections between the collector and base electrodes of the two transistors 1 and 2 with respect to each other, therefore, results in effectively maintaining the transistors in the respective status or conditions in which they find themselves unless and until such state is changed by the application of external control voltages.

The circuit of FIGURE 1 is entirely symmetrical in such a manner that if, in contrast, the transistor 2 is in the conducting or passing state, then the voltage at point 11 is at a level close to the potential of point 6 which, transmitted to the base electrode 12 of the other transistor 1 across resistance 13 effectively blocks or biases the same. The transistor 1 is thereby efiectively blocked or cut off whereas the base electrode 3 of the transistor 2 is thereby carried at a level sufficiently high to render the transistor 2 conducting in a stable manner by reason of the interplay of its connection with the resistors 9 and 10. This time, it is line 22 which is carried at a relatively high potential whereas line 25 produces a relatively low potential.

Having thus considered the two opposite conditions or states of which the multi-vibrator circuit of FIGURE 1 is susceptible of assuming in a stable manner, next will be described the means provided to change over the multivibrator circuit of FIGURE 1 from one of its conditions to the other and vice versa.

It will be apparent from what was said hereinabove that the potentials at the junction points of the coupling resistances 9, it or 13, 14 associated with a respective collector electrode of a transistor are the potentials which determine the state or the new state of the other transistor. It is for that reason that the circuit of FIGURE 1 comprises two coupling circuits which enable the appearance at each of these junction points and at a predetermined desired instant, a voltage which entrains or brings about a change-over efiect typical of the flip-flop circuits between the two transistors.

The coupling circuits, as shown in FIGURE 1 are identical and include each a junction point 2.6 and 27 at which terminate the leads of a

resistor

17 and 18, of a line 21 and '23, and of a

condenser

19 and 2%, respectively, the other terminal of each

condenser

19 and 20 being connected, on the other hand, with a line 24. Each of these

points

26 or 27 is separated from the corresponding junction point between

resistors

9, 10 and 13, 14, respectively, which is associated therewith by a unidirectionally

conductive element

15 or 16, such as a rectifier or the like .of which the direct sense, i.e., the anode-cathode direction is toward the

corresponding point

26 or 27, respectively.

If U and U are the relatively low and high voltages which may exist at the collector electrodes of the transistors 1 and 2 when the same are either conducting or non-conducting, respectively, then the voltages U and U are also the voltages at which are simultaneously carried the

lines

21 and 23 whereas at the desired instance for purposes of commutation, a negative pulse of amplitude U U is applied to line 24.

Next will be examined the mode of operation of how the coupling circuit and its effect on the transistors taking into consideration the pro-existing state of the same and the potentials at which the

lines

21 and 23 are carried.

When the voltage at 21 is equal to U the direct voltage at the terminals of the diode 15 is negligible so that the negative pulse U -U applied to line 24 is able to flow through the diode 15, it being assumed that the

resistances

17 and 18 are very much smaller than the resistances offered by

elements

15 and 16 in the opposite sense, i.e., cathode-anode direction. Consequently, regardless of what the pre-existing state of the transistor 1 and 2 may be, the voltage of the junction point of the resistances 9 and 10 which is also applied to the base electrode 8 of the transistor 2 has for its efi'ect to block or maintain the non-conductive or blocked state of this transistor 2.

Since under the assumed operating conditions, line 23 is at the same time at the potential U the direct voltage at the terminals of rectifier 16 do not exceed the voltage of polarization of the diode 16, and consequently, the negative pulse applied at 24 cannot p ss through the diode 16. The potential of the junction point of the resistance 13 and 14 of the voltage divider network of transistor 2 which is blocked is, therefore, freely applied to the base electrode 12 of the transistor 1 which thereby becomes conductive or is maintained in the conducting state thereof, if such state pro-existed.

By reason of the symmetry, the same conclusions as to the operation may be arrived at if it is assumed that line 23 is at the potential of U and line 21 at the potential of U whereupon the negative pulse passes this time through diode 16 in such a manner as to block or maintain transistor 1 blocked whereas diode 1S assures now the electric separation between the point 26 of the other coupling circuit and the base electrode 8 of the transist-or 2.

In all the cases, it may be readily seen that the existing condition of voltage at a given moment existing on the

lines

21 and 23 will also appear on

lines

22 and 25 at the instance at which the negative pulse of commutation is applied to line 24.

Reference may be had to FIGURE 2 on which are represented graphically the correspondences between the diiferent electric states or conditions which line 24,

line

21 or 23, voltage divider networks 9, or 13, 14 and

lines

22 or 25 may assume.

The curve 211 represents a succession of negative pulses applied to line 24.

The curve 212 represents the succession of potentials U and U applied to line 21 or line 23. It is, however, understood, as indicated hereinabove, that at the moment at which line 21 is at the potential U the line 23 is at the potential U and vice versa.

The curve 2c represents the potential applied to the cathode of the rectifier which is the result of the voltages given by curves 2a and 2b and transmitted by the coupling circuit.

The curve 2d represents the potential which appears at the anode of this same diode when it has become passing or conductive.

The curve 2e may be deduced from the curve 2d to represent the potentials applied across the other coupling circuit to the anode of the other diode.

Finally, curve 2 indicates how the existing potentials which exist prior to the negative commutation pulse on line 21 or line 23 appears at the moment of commutation on line 22 or line 25 which corresponds thereto. It may be appropriate to note in connection therewith that the change in the applied voltage at

line

21 or 23 may be effectuated during any interval of time which separates two consecutive commutating pulses. And even if this change arrives at the moment at which the commutating pulse passes into the coupling circuit the change in polarity between the

lines

21 and 23 has no influence over the state taken prior thereto by the

points

26 and 27 by reason of the time constants 0 R and C R of the respective coupling circuits.

It is believed that as a result of the explanations given hereinabove, the invention may be readily understood in all of its details and novelty. According to the present invention, the bi-stable circuit described hereinabove, may play the role of the regenerator-translator element for the telegraphic signals in a system of telegraphic transmission. In fact, if it is assumed that one bi-stable circuit identical to that of FIGURE l, is connected to lines 22 and of the circuit which has been analyzed hereinabove in such a manner that these lines assume for it exactly the same role of

lines

21 and 23 which have been considered in connection with FIGURE ll, it will appear that the commutating pulses of the second circuit will determine the conditions or states of the transistors thereof in such a manner as to reproduce exactly the state or condition of the transistors of the first bi-stable circuit. In the same manner, one may readily imagine the potentials appearing on

lines

21 and 23 of the analyzed bi- 6 stable circuit as transmitted and indicative of the states or conditions of another circuit placed ahead thereof.

Reference will now be had to FIGURE 3 which represents a first embodiment of the storage device according to the present invention.

Reference numerals

601, 602, 501 001, 002 designate pairs of transistors forming part of a chain of circuits analogous to that of FIGURE 1. For example, points 526 and 527 play the same role in the

bi-stable circuit

501, 502 as the

points

26 and 27 of the bi-stable circuit 1, 2, considered in connection with FIGURE 1.

As mentioned hereinabove, the coupling potential at these points 526, 5-27 are derived from the state of the collector electrodes of the

bi-stable circuit

601, 602 which precede the

circuit

501, 502 in the chain. In the same manner, the potentials present on the collector electrodes of the

transistor

501 and 502 are applied across a resistance to the points of junction of the coupling circuits of the

transistor

401, 402 of the following bi-stable circuit. Reference numeral 24 again designates the input line for the commutating pulses which hereinafter will be referred to as advance pulses. In fact, after what has been stated hereinabove, each of these pulses finds on one or the other side of the bi-stable circuits a diode which is conductive having regard for the voltage applied by the transistor which is on the same side in the bi-stable circuit which is ahead of this diode. This advance pulse has, therefore, as its effect to confirm on one or the other side of each circuit, the bi-stable circuit in its existing state or to change its state in the two cases by forcing the same to assume an identical state to that of the bistable circuit preceding the same at the moment of the arrival of the advance pulse. The advance pulse has, therefore, as its net result to make each bi-stable circuit pass over into the state of the bi-stable circuit preceding the same in the chain. It may be observed in connection therewith that of the seven bi-stable circuits, the first one thereof is controlled slightly differently from the other six. In effect, of the two

coupling lines

621 and 623, one line 6-21 is susceptible to assume the values U and U which have been considered hereinabove, that is, the voltages which the

transistors

601, 602, 501, 502

are susceptible to present to the collector electrode when they are either conducting or blocked. As to the other coupling line 623 of the input 'bi-stable circuit at the head of the chain, it is maintained constantly at a potential near that of the source 6, that is, substantially at the supply voltage of the emitter electrodes of the different transistors or practically at the sole potential U On the other hand, the advance pulses are admitted in this input circuit exclusively to the diode associated with the line 623' whereas the other diode receives negative pulses from line 30 which are independent of the advancepulse generator circuit.

It follows from this particular arrangement of the bistable circuit at the input of the system that the advance pulses traverse always the diode which is connected to the base of the transistor 601 in such a manner that this transistor is blocked or maintained blocked during each emission of an advance pulse by line 24.

Furthermore, regardless of the condition or state of the input bi-stable circuit during the interval of time which separates two advance pulses, each pulse received over line 30 has an efiect on the transistor 602 when the voltage on line 621 is equal to U and will be Without elfeet if the potential thereon is U It should also he noted that the advance pulse applied to line 24 had previously blocked and in any state which may exist will again block the transistor 601 thereby rendering the transistor 602 conductive. Consequently, the pulse applied to line 30 which will be referred to hereinafter as test pulse reproduces on the collector electrode of transistor 601 the potential which is present at that moment on line 621, namely reproduces voltage U at the collector electrode, of transistor 601, that is, by rendering transistor 601 conductive if the line 621 is at the potential U or reproduces potential U at the collector electrode of transistor 601, that is, by maintaining transistor 601 blocked if the line 621 is at the potential U The operation of the chain of seven bi-stable circuits will be readily understood in its application to the reproduction of coded telegraphic signals of the arithmetic type. Reference numeral 32 designates in FIGURE 3 the input line for the telegraphic elementary signal of an amplitude and duration essentially constant having either a positive or negative polarity, The line 32 is connected to the control winding of a relay 31 of which the armature determines the polarity of the line 621. The relay 31 is actuated in such a manner that for a polarity of a positive line, the line 621 is carried at the potential U and for a potential of a negative line, the line 621 is carried at the potential U It will be assumed now that test pulses are transmitted over line 30, preferably during the instants corresponding to the center of an elementary signal of any polarity received over line 32. The test pulse, as has been seen hereinabove, has for its purpose to maintain the transistor 601 in the pre-existing blocked condition or to render the same conducting in a condition which corresponds to the polarity taken by 621, that is, to the polarity of the elementary signal over line 32. It will further be assumed for purposes of this discussion that the generator of negative advance pulses which has not been illustrated in FIG- URE 3 since it may be of any suitable well-known type, applies over line 24 advance pulses during intervals situated between two test pulses. Consequently, one advance pulse imparts to the

circuit

501, 502 the same state or condition that presented

circuit

601, 602 once the test pulse is received thereby; at the same time, it affects this

circuit

601, 602 by bringing it back, thanks to the direct current potential of line 623, to a condition thereof in which transistor 601 is blocked and transistor 602 is conductive, in other words, into a state of rest which lends itself readily to the proper reception of the following test pulses.

On the other hand, since line 24 is connected with each of the

circuits

501, 502 to 001, 002 and of the two sides thereof, the advance pulse assures, as indicated hereinabove, that each bi-stable circuit confirms itself in its existing state or change-over its state in such a manner as to adopt the pre-existing state or condition of the bi-stable circuit which precedes the same.

In the arithmetic telegraphic system, the line polarity is normally positive in the absence of transmission. When a series of five elementary signals is transmitted over line 32, it is always preceded by an elementary negative signal which marks the end of the rest state and the beginning of the transmission. Once the five elementary signals have passed, the line returns to the positive polarity characteristic of the permanent rest therof.

In this state of permanent rest, the line 621 is carried at a potential of U Consequently, the

circuit

601, 602 under the influence of the last advance pulse received is in the condition which has been referred to as rest condition in which the transistor 601 is blocked and the transistor 602 conducts or, otherwise stated, in which line 625 posts a high potential U whereas line 622 posts a low potential U In the same manner, the other bi-stable circuits of the chain illustrated in FIGURE 3 are in the rest position thereof since all the coupling circuits associated with the

transistors

501, 401 001 are all under the effect of a potential U at the respective junction points such as point 526 whereas the complementary junction points such as point 527 of the complementary coupling circuits are at the potential U It may thus be seen that when the general circuit is at rest, all of the

lines

625, 525, 425, 325 025 are at the potential U that is, at the potential representative of a polarity of a positive line or of the permanent rest polarity.

When the starting pulse which is always of negative polarity is received over line 32, line 621 is then carried at the polarity U Consequently, the test pulse on line 30 passes through the diode which is associated therewith and the

bi-stable circuit

601, 602 abandons the rest state to assume the inverse state or condition in which transistor 601 is conducting or passing and 602 is blocked. The line 625 thereupon produces a potential U representative of the start signal on line 32. At the instant of the emission or occurrence of the next test signal, the other bi-stable circuits are not affected thereby.

With the appearance of an advance signal subsequent to the test signal, the diode associated with the line 623 which is at the potential U permanently, becomes conductive thereby bringing back the

bi-sta'ble circuit

602, 601 to the rest state thereof. At the same time, since the junction point 527 is now at the high potential U and the junction point 526 at the low potential U the

circuit

501, 502 assumes the state or condition which is lost by the

circuit

602, 601 once brought back to rest. Consequently, line 525 is now following line 625 with a potential U characteristic of the start signal initially received by line 32.

If it is assumed that the first elementary signal received by the line is positive after the appearance of the corresponding test pulse, the line 625 thereupon assumes the polarity U The advance pulse which follows will place line 525 at this potential whereas the line 625 remains at the potential U since the bi-stable circuit at the input is already in the state or condition which corresponds to the rest position thereof. At the same time line 425 which is at the rest potential of U is caused by the advance pulse to assume the pre-existing potential of line 525, that is, the potential U characteristic of the elementary start signal initially received over line 32. With each advance pulse, the signals received by line 32 are represented by a succession of polarities U U appearing successively over

lines

525, 425, 325 025, each new polarity chasing ahead of itself the polarity which precedes the same in this succession of lines. When the polarity U representative of the elementary start signal has replaced on line 025 the polarity U which represented thereat the condition or state of rest, the bi-stable circuits I, II V apply each one of the signals of the received signal in its totality by line 32.

Line 625 of the bi-stable circuit VI which is now brought back to the rest condition thereof, representing by its potential U the condition of permanent rest which follows the emission of a telegraphic signal.

As a consequence the potential of the seven lines 025 to 625 simultaneously reproduces on seven distinct terminals the state of the seven elementary characteristic signals of the sign or telegraphic character which has been just received by the line. As it follows this device realizes r the series recording function through input 621 and the parallel output at the seven

terminals

625, 025. In the state of rest, that is to say, when the polarity in line 625 is positive (polarity of permanent rest), the potential of line 025 is high and stays so until the time of the inversion of bi-stable or multi-vibrator circuit 0 converting the polarity of the start element. The changing of potential of line 025 obviously coincides with the instance when the data (start, I, II, III, IV, V, stop) are available at their terminals.

This changing of potential may be applied to suitable control means in order to:

(a) Make evident, simultaneously and instantaneously in the auxiliary device of translation the nature of the polarities at 025, 125, 525, for instance by the action of devices similar to

circuit

17, 19, 15, 18, 20 and 16 of FIGURE 1,

(b) Bring back instantaneously in its initial state of rest the set of seven bi-stable or flip-flop circuits 0, I, II, III, IV, V, VI when code element information has been adequately employed from I, II, III, IV and V,

(c) Control the cessation functions in the telegraphic receiver, the inversion of bi-stable or multi-vibrator circuit O signalling the end of the reception of the data useful for translating the sign or telegraphic character. The functions (a), (b), (c) are not limited by the ones which can be accomplished by modification of the state of the last bi-stable or multi-vibrator circuit of the series.

The cessation function of the arythmic receiver can only be accomplished when the setting at rest of the set of seven bi-stable or flip-flop circuits has itself been accomplished, the interruption of the receiving device being only controlled when lines 1125, 125, 625 simultaneously present a high tension, the identity of the potential of these lines being sensed for a control function for instance, by devices utilizing rectifiers.

It may thus be seen that the device which has been described hereinabove in connection with FIGURE 3 makes possible an ope-ration of series recording and parallel output. However, the same device may be readily modified in such a manner as to render possible the realization of an inverse functioning, i.e., parallel recording and series output operations. Thus modified, the system according to the present invention lends itself particularly well to the rythmic emission of telegraphic signals.

Reference is made to FIGURE 4 which illustrates a wiring diagram of such second embodiment in accordance with the present invention. Again five bi-stable circuits XI to XV may be readily recognized in FIGURE 4 which are all analogous to the circuit of FIGURE 1, and are connected in a chain-like manner essentially similar to that of the arrangement considered hereinabove in connection with FIGURE 3 wherein diode coupling circuits are controlled over line 24 along which are transmitted negative advance pulses. Nevertheless, the Wiring diagram of FIGURE 4 distinguishes itself from that of FIG- URE 3 in several respects, namely as follows:

Instead of seven bi-stable circuits, as used in FIGURE 3, only five such bi-stable circuits are used in FIGURE 4, which are connected in cascade. In fact in the transmitter device of telegraphic signals with five elementary signals defining each character, there is no need to translate either the start signal or the permanent rest signal by means of special bi-stable circuits. The five elementary signals are recorded in each of the circuits XI to XV by applying to each of the lines 144) to 540 a negative or positive pulse each defining the polarity of an element of the .code in such a manner as to render the transistors 572 to 172 non-conducting or conducting, the base electrodes of which are operativ-ely connected or associated with these lines 140 to 540. Once the

transistors

171, 172 to 57-1, 572 are fixed in the respective state or condition thereof which translates the polarity of the various elementary signals of the telegraphic signal to be recorded and thereupon transmitted, the coupling circuits are the only ones to afiect the state of these transistors by the interplay of the advance signals appearing on line 24 as explained hereinabove in connection with FIGURE 3, and each bi-stable circuit of the chain determines upon reception of an advance signal the state of the bi-stabl-e circuit which follows the same in the chain.

The embodiment of FIGURE 4 presents the following particularities at the end of the chain:

The terminals 61, 62 are called upon to translate the voltages appearing on the collector electrodes of the

transistors

171, 172 of the last bi-stable circuit of the chain. For that purpose one diode 161, 162 is provided between each output terminal and the respective collector electrode. The advance signal is admitted to the cathode of these diodes at 151 and 152 in such a manner that, depending on which transistor is in the conducting state, and, therefore, at the collector electrode of which exists a relatively low voltage U the advance pulse passes through the diode thereof and over one or the other terminals 61 or 62 sets off the emitter system of telegraphic signals connected to these terminals.

It is believed that with this explanation together with 16 the explanation given hereinabove in connection with FIGURE 3, the operation of FIGURE 4 is quite clear and obvious.

The negative advance pulses are supplied at 24 by a suitable auxiliary control device (not shown) only when the state of

points

151, 152, 551, 552, has characterized completely the combination to reproduce. The first advance pulse to appear will pass through rectifier 161 or rectifier 16 2 depending upon whether the potential at 151 is U or U At the same time these advance pulses appear, bi-stable multi-vibrator circuit XI assumes a state presented by bi-stable multivibrator circuit XII. Bi-stable XII assumes a state presented by bi-stable multi-vibrator circuit XIII and so on to bi-stable multi-vibrator circuit XV, the transistor 571 of which is necessarily blocked, the rectifier 661 only presenting at its terminals a negligible biasing voltage from source 6.

The second advance pulse will pass through the rectifier 161 or the rectifier 162 depending upon whether the polarity at 151 is U or U that is to say depending upon whether the initial polarity at 251 was U or U Simultaneously transistors 571 and 471 of bi-stable multivibrator circuits XV and XIV become blocked.

The third advance pulse will pass through rectifier 161 or rectifier 162 depending upon whether the initial polarity at 351 was U or U and so on until the time when all transistors 571, 47.1, 171 are blocked.

At the output, the pulses appear at terminals 62 or 61 after having passed respectively through rectifiers 162 or 161 depending upon whether the code element represented is negative or positive, in this manner said impulsion characterizes successively the

signal elements

1, 2, 3, 4, 5. They constitute the series information at the output of the apparatus. They may be used for instance to define the successive conditions of stability of an additional bi-stable multi-vibrator circuit on one collector of which the voltage reproduces the combination to be transmitted.

When all the data have been recorded at the output terminals, all bi-stable multi-vibrator circuits present an identical state, all odd numbered transistors being blocked. This identity of state may be sensed, for instance, by systems using rectifiers in order to take care of parallel input of the following combination, to take care of stopping functions of the device generating the advance pulse, et cetera.

It is possible to complete the device with additional organs constituted, for example, as seen at bi-stable multivibrator circuit XIII, by

elements

716, 718, 729, 715, 7-17, 719 similar to

elements

16, 18, 21 15, 17, '19 of FIG- URE 1 of which the role for recording the voltages applied at 2.1 and 23 has been already described. This additional disposition is only indicative and may be either omitted or applied to any or all of the bi-stable multivibrator circuits of a device instead of being applied only to bi-stable multi-vibrator circuit XIII.

Some pulses known as conversion pulses appear at 44 in the time interval which separates the last pulse of parallel input from the first advance pulse. If signal element 3 has been characterized as negative, according to the assumption, the transistor 372 is blocked by the input pulse. Consequently, a conversion pulse will block 371 which will have for effect to make 372 passing.

If element 3 has been characterized as positive, transistor 371 is blocked. Consequently, the conversion pulse will block 372, which will have for eifect to make 371 passing.

ceivers and transmitters of telegraphic signals but such an application is not limited. These devices can be employed in all telegraphic apparatus assuming functions other than the transmission and reception of signals, more specifically, the instantaneous and multiple use of data contained in a telegraphic character the duration of which is generally not negligible.

The disclosed devices may be employed in many apparatus other than the ones in telegraphy. More particularly, in the calculating machines they may assume the functions known as information storage, the circuit arrangements being only indicative, any other arrangement could be made concerning the number of stages, the number of inputs and outputs, the nature and the time location of the advance pulses, test pulses, conversion pulses, input and output pulses, these different arrangements can be easily deducted from the ones described.

Accordingly, it is possible to complete each bi-stable multi-vibrator bascule by adding the circuits shown in dotted line on FIGURE 4 which comprises elements similar to the ones designated by 15, 17, 19 and f6, 18, 2% on FIGURE 1 but connected to a second pulse generator 54 allowing a regular progression or transfer of information in an opposite direction with respect to the data transfer described for the series output storage device. In the described circuit, datum for instance recorded by bistable multi-vibrator bascule XIII is transferred successively to bi-stable multi-vibrator circuits XII and XI, while with the considered dotted-circuit arrangement datum recorded by bi-stable multi-vibrator bascu le XIII would be transferred successively either to bi-stable multi-vibrator circuits XII and XI or to bi-stable multivibrator bascule XIV and XV depending upon whether the advance pulses would be supplied by pulse generators connected at 24 or 54, respectively.

Thus it is obvious that the present invention is not limited to the illustrated embodiments but is susceptible of many changes and modifications within the spirit and scope of the present invention, and I, therefore, do not wish to be limited to the illustrated embodiments but intend to cover all such modifications and changes thereof as are encompassed by the scope of the appended claims.

I claim:

1. A bilaterally operable shifting register, comprising, between a source of information and utilization means, a chain of stages of which each stage includes a bistable transistorized multi-vibrator each provided with two inputs and with two outputs and four connecting circuit means;

the four connecting circuit means of a respective stage essentially consisting of two output circuit means and two input circuit means; each output circuit means being constituted by the operative association of a resistance in series with a rectifier and of condenser means having two terminals, one of the two terminals of said condenser means being connected to a common point between a respective resistance and rectifier;

first source means operatively connected with the other of the two terminals of said condenser means for causing shifting of information registered in each stage to a following stage, if any, of the chain by varying the potential of the said other terminal of the condenser means;

each input circuit means being constituted by the operative association of a rectifier in series with a resistance and of condenser means having two terminals, one of the terminals of said last-mentioned condenser means being connected to a common point between a respective resistance and rectifier;

second source means operatively connected with the other of the two terminals of said (last-mentioned condenser means for causing of information registered in each stage to a preceding stage, if any, of

1.2 the chain by varying the potential of the said lastmentioned other condenser terminals;

the potentials simultaneously applied to the condenser means of the input and output circuit means being such that the shifting control of the information takes place in one predetermined direction;

the resistance of one of the two output circuit means being operatively connected with one of the two outputs of the respective stage, and the resistance of the other of the two output circuit means being operatively connected with the other of the two outputs of the respective stage;

the rectifier of one of the two output circuit means being operatively connected to one of the two inputs of a following multi-vibrator stage, and the rectifier of the other output circuit means being operatively connected to the other of the two inputs of a following multi-vibrator stage;

the rectifier of one of the two input circuit means being operatively connected with one of the two inputs of the respective multi-vibrator stage, and the rectifier of the other of the two input circuit means being operatively connected with the other of the two inputs of the respective multi-vibrator stage;

the resistance of one of the two input circuit means bein operatively connected to one of the two inputs of a preceding multi-vibrator stage, if any, and the resistance of the other of the two input circuit means being operatively connected with the other of the two inputs of a preceding multi-vibrator stage, if any, whereby each output of each multi-vibrator stage is connected to two resistances and each input thereof to two rectifiers.

2. A bilaterally operable shifting register, comprising, between a source of information and utilization means, a chain of stages of which each stage includes a bistable transistorized multi-vibrator each provided with two inputs and outputs and six connecting circuit means;

the six connecting circuit means of a respective stage essentially consisting of two output circuit means, two input circuit means and two inversion circuit means; each output circuit means being constituted by the operative association of a resistance in series with a rectifier and of condenser means having two terminals, one of the two terminals of said condenser means being connected to a common point between a respective resistance and rectifier;

second source means operatively connected with the other of the two terminals of said last-mentioned condenser means for causing of information registered in each stage to a preceding stage, if any, of the chain by varying the potential of the said lastmentioned other condenser terminals;

each inversion circuit means being constituted by the operative association of a resistance in series with a rectifier and of further condenser means having two terminals, one of the two terminals of said further condenser means being operatively connected to a 13 common point between a respective resistance and rectifier; external source means operatively with each of the other of the two terminals of said further condenser means of both inversion circuit means of a respective stage to produce inversion of the said multivibrator stage by varying the potential of the said other terminals of the further condenser means which are thus connected in parallel to said external source means, the resistance of one of the two output circuit means being operatively connected with one of the two outputs of the respective stage, and the resistance of the other of the two output circuit means being operatively connected with the other of the two outputs of the respective stage; the rectifier of one of the two output circuit means being operatively connected to one of the two inputs of a following multi-vibrator stage, and the rectifier of the other output circuit means being operatively connected to the other of the two inputs of a following multi-vibrat-or stage;

the rectifier of one of the two input circuit means being operatively connected with one of the two inputs of the respective multi-vibrator stage, and the rectifier of the other of the two input circuit means being operatively connected with the other or the two inputs of the respective multi-vibrator stage;

the resistance of one of the two input circuit means being operatively connected to one of the two inputs of a preceding multi-vibrato-r stage, if any, and the resistance of the other of the two input circuit means being operatively connected with the other of the two inputs of a preceding multi-vibr-ator stage, if y,

the resistance of one of the two inversion circuit means being operatively connected to one of the two outputs of the respective multi-vibrator stage, and the resistance of the other of the two inversion circuit means being operatively connected to the other of the two outputs of the respective multi-vtibrator stage;

and the rectifier of one of the two inversion circuit means being operatively connected to one of the two inputs of the respective multi-vibrator stage, and the rectifier of the other of the two inversion circuit means being operatively connected to the other of the two inputs of the respective multi-vi-brator stage, whereby each out-put of each multi-vi-brator stage is connected to three resistances and each input thereof to three rectifiers.

3. A shifting register according to claim 2, wherein said external source means is common to the inversion circuit means of all stages.

4. A shifting register according to claim 2, wherein said external source means is common to the inversion circuit means of some of said stages.

5. A shifting register according to claim 2, wherein a separate external source means is provided for the inversion circuit means of the respective stages.

6. A bilaterally operable shifting register, comprising, between a source of information and utilization means, a chain of stages of which each stage includes a bistable transistorized multi-vibrator each provided with two inputs and outputs and four connecting circuit means;

the four connecting circuit means of a respective stage essentially consisting of two output circuit means and two inversion circuit means;

each output circuit means being constituted by the operative association of a resistance in series with a rectifier and of condenser means having two terminals, one of the two terminals of said condenser means being connected to a common point between a respective resistance and rectifier;

first source means operatively connected with the other 14 of the two terminals of said condenser means for causing shifting of information registered in each stage to a following stage, if any, of the chain by varying the potential of the said other terminal of the condenser means;

each inversion circuit means being constituted by the operative association of a resistance in series with a rectifier and of further condenser means having two terminals, one of the two terminals of said further condenser means being operatively connected to a common point between a respective resistance and rectifier;

external source means operatively with each of the other of the two terminals of said further condenser means of both inversion circuit means of a respective stage to produce inversion of the said multivibrator stage by varying the potential of the said other terminals of the further condenser means which are thus connected in parallel to said external source means,

the resistance of one of the two inversion circuit means being operatively connected to one of the two outputs of the respective multi-vibrator stage, and the resistance of the other of the two inversion circuit means being operatively connected to the other of the two outputs of the respective multi-vibrator stage;

and the rectifier of one of the two inversion circuit means being operatively connected to one of the two inputs of the respective multi-vibrator stage, and the rectifier of the other of the two inversion circuit means being operatively connected to the other of the two inputs of the respective multi-vibr-ator stage, whereby each output of each multi-vibrator stage is connected to two resistances and each input thereof to two rectifiers.

7. A shifting register according to claim 6, wherein said external source means is common to the inversion circuit means of all stages.

8. A shifting register according to claim 6, wherein said external source means is common to the inversion circuit means of some of said stages.

9. A shifting register according to claim 6, wherein a separate external source means is provided for the inversion circuit means of the respective stages.

10. A bilaterally operable shifting register, comprising, between a source of information and utilization means, a chain of stages of which each stage includes a bistable transistorized multi-vibrator each provided with two inputs and outputs and at least four connecting circuit means;

the at least four connecting circuit means of a respective stage including two output circuit means and two of a plurality of further circuit means consisting of two input circuit means and two inversion circuit means;

each input circuit means being constituted by the operative association of a rectifier in series with a resistance and of condenser means having two terminals, one of the terminals of said lastqnentioned condenser means being connected to a common point between a respective resistance and rectifier;

external source means operatively with each of the other of the two terminals of said further condenser means of both inversion circuit means of a respective stage to produce inversion of the said multivibrator stage without reacting on the other multivibrator stages by varying the potential of the said other terminals of the further condenser means which are thus connected in parallel to said external source means,

the rectifier of one of the two output circuit means being operatively connected .to one of the two inputs of a following multi-vibrator stage, and the rectifier of the other output circuit means being operatively connected to the other of the two inputs of a following multi-vibrator stage;

the resistance of one of the two input circuit means being operatively connected to one of the two inputs of a preceding multi-vibrator stage, if any, and the resistance of the other of the two input circuit means being operatively connected with the other of the two inputs of a preceding multi-vibrator stage, if any.

and the rectifier of one of the two inversions circuit means being operatively connected to one of the inputs of the respective multi-vibrator stage, and the rectifier of the other of the two inversion circuit means being operatively connected to the other of the two inputs of the respective multi-vibrator stage, and the rectifier of the other of the two inversion circuit means being operatively connected to the other of the two inputs of the respective multivibrator stage, whereby each output of each multivibrator stage is connected to at least two resistances and each input thereof to at least two rectifiers.

References Cited in the file of this patent UNITED STATES PATENTS OTHER REFERENCES Digital Computor Components and Circuits by Richards, 1957, Van Nostrand Co., pages 73, 74, 161.

Claims

1. A BILATERALLY OPERABLE SHIFTING REGISTER, COMPRISING BETWEEN A SOURCE OF INFORMATION AND UTILIZATION MEANS, A CHAIN OF STAGES OF WHICH EACH STAGE INCLUDES A BISTABLE TRANSISTORIZED MULTI-VIBRATOR EACH PROVIDED WITH TWO INPUTS AND WITH TWO OUTPUTS AND FOUR CONNECTING CIRCUIT MEANS; THE FOUR CONNECTING CIRCUIT MEANS OF A RESPECTIVE STAGE ESSENTIALLY CONSISTING OF TWO OUTPUT CIRCUIT MEANS AND TWO INPUT CIRCUIT MEANS; EACH OUTPUT CIRCUIT MEANS BEING CONSTITUTED BY THE OPERATIVE ASSOCIATION OF A RESISTANCE IN SERIES WITH A RECTIFIER AND OF CONDENSER MEANS HAVING TWO TERMINALS, ONE OF THE TWO TERMINALS OF SAID CONDENSER MEANS BEING CONNECTED TO A COMMON POINT BETWEEN A RESPECTIVE RESISTANCE AND RECTIFIER; FIRST SOURCE MEANS OPERATIVELY CONNECTED WITH THE OTHER OF THE TWO TERMINALS OF SAID CONDENSER MEANS FOR CAUSING SHIFTING OF INFORMATION REGISTERED IN EACH STAGE TO A FOLLOWING STAGE, IF ANY, OF THE CHAIN BY VARYING THE PONTENTIAL OF TH SAID OTHER TERMINAL OF THE CONDENSER MEANS; EACH INPUT CIRCUIT MEANS BEING CONSTITUTED BY THE OPERATIVE ASSOCIATION OF A RECTIFIER IN SERIES WITH A RESISTANCE AND OF CONDENSER MEANS HAVING TWO TERMINALS, ONE OF THE TERMINALS OF SID LAST-MENTIONED CONDENSER MERANS BEING CONNECTED TO A COMMON POINT BETWEEN A RESPECTIVE RESISTANCE AND RECTIFIER; SECOND SOURCE MEANS OPERATIVELY CONNECTED WITH THE OTHER OF THE TWO TERMINALS OF SAID LAST-MENTIONED CONDENSER MEANS FOR CAUSING OF INFORMATION REGISTERED IN EACH STAGE TO A PRECEDING STAGE, IF ANY, OF THE CHAIN BY VARYING THE POTENTIAL OF THE SAID LASTMENTIONED OTHER CONDENSER TERMINALS; THE POTENTIALS SIMULTANEOUSLY APPLIED TO THE CONDENSER MEANS OF THE INPUT AND OUTPUT CIRCUIT MEANS BEING SUCH THAT THE SHIFTING CONTROL OF THE INFORMATION TAKES PLACE IN ONE PREDETERMINED DIRECTION; THE RESISTANCE OF ONE OF THE TWO OUTPUT CIRCUIT MEANS BEING OPERATIVELY CONNECTED WITH ONE OF THE TWO OUTPUTS OF THE RESPECTIVE STAGE, AND THE RESISTANCE OF THE OTHER OF THE TWO OUTPUT CIRCUIT MEANS BEING OPERATIVELY CONNECTED WITH THE OTHER OF THE TWO OUTPUTS OF THE RESPECTIVE STAGE; THE RECTIFIER OF ONE OF THE TWO OUTPUT CIRCUIT MEANS BEING OPERATIVELY CONNECTED TO ONE OF THE TWO INPUTS OF A FOLLOWING MULTI-VIBRATOR STAGE, AND THE RECTIFIER OF THE OTHER OUTPUT CIRCUIT MEANS BEING OPERTIVELY CONNECTED TO THE OTHER OF THE TWO INPUTS OF A FOLLOWING MULTI-BIBRAWTOR STAGE; THE RECTIFIER OF ONE OF THE TWO INPUT CIRCUIT MEANS BEING OPERATIVELY CONNECTED WITH ONE OF THE TWO INPUTS OF THE RESPECTIVE MULTI-VIBRATOR STAGE, AND THE RECTIFIER OF THE OTHER OF THE TWO INPUT CIRCUIT MEANS BEING OPERATIVELY CONNECTED WITH THE THER OF THE TWO INPUTS OF THE RESPECIVE MULTI-VIBRATOR STAGE; THE RESISTANCE OF ONE OF THE TWO INPUT CIRCUIT MEANS BEING OPERATIVELY CONNECTED TO ONE OF THE TWO INPUTS OF A PRECEDING MULTI-BRIBRATOR STAGE, IF ANY, AND THE RESISTANCE OF THE OTHER OF TWO INPUT CIRCUIT MEANS BEING OPERATIVELY CONNECTED WITH THE OTHER OF THE TWO INPUTS OF A PRECEDING MULTI-VIBRATOR STAGE, IF ANY, WHEREBY EACH OUTPUT OF EACH MULTI-VIBRATOR STAGE IS CONNECTED TO TWO RESISTANCE AND EACH INPUT THEREOF TO TWO RECTIFIERS.