Nothing Special   »   [go: up one dir, main page]

US20140246773A1 - Chip on Chip Attach (Passive IPD and PMIC) Flip Chip BGA Using New Cavity BGA Substrate - Google Patents

Chip on Chip Attach (Passive IPD and PMIC) Flip Chip BGA Using New Cavity BGA Substrate Download PDF

Info

Publication number
US20140246773A1
US20140246773A1 US13/790,437 US201313790437A US2014246773A1 US 20140246773 A1 US20140246773 A1 US 20140246773A1 US 201313790437 A US201313790437 A US 201313790437A US 2014246773 A1 US2014246773 A1 US 2014246773A1
Authority
US
United States
Prior art keywords
die
substrate
daughter
active surface
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/790,437
Inventor
Ian Kent
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dialog Semiconductor GmbH
Original Assignee
Dialog Semiconductor GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dialog Semiconductor GmbH filed Critical Dialog Semiconductor GmbH
Assigned to DIALOG SEMICONDUCTOR GMBH reassignment DIALOG SEMICONDUCTOR GMBH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KENT, IAN
Publication of US20140246773A1 publication Critical patent/US20140246773A1/en
Priority to US15/299,910 priority Critical patent/US9929130B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19011—Structure including integrated passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1905—Shape
    • H01L2924/19051—Impedance matching structure [e.g. balun]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Definitions

  • This disclosure is related to flip chip attachment of Mother die and Daughter Integrated Passive Device die, and more particularly, to methods of flip chip attachment of Mother die and Daughter Integrated Passive Device die in an inverted pyramid die stack, using a laser drilled cavity laminate Ball Grid Array/Land Grid Array substrate to accommodate the protruding Daughter die.
  • Passive device integration is typically done by:
  • substrate technologies were limited with respect to the ability to laser or mechanically drill a cavity into a laminate substrate having a Bismaleimide Triazine (BT) core while maintaining mechanical and reliability integrity.
  • BT Bismaleimide Triazine
  • Yet another objective is to use a die on die attachment to produce direct contact of a Mother die to a Daughter die.
  • a method of fabricating a mother and daughter integrated circuit is achieved.
  • a mother die and a daughter die, wherein the daughter die is smaller than the mother die, are directly connected, active surface to active surface, resulting in a die stack.
  • the die stack is flip-chip attached to a substrate having a cavity drilled therein wherein the daughter die fits into the cavity.
  • a method of fabricating an integrated passive device is achieved.
  • An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a die stack.
  • the die stack is flip-chip attached to a substrate having a cavity drilled therein wherein the smaller die fits into the cavity.
  • an mother and daughter integrated circuit is achieved.
  • a mother die and a daughter die, wherein the daughter die is smaller than the mother die, are directly connected, active surface to active surface, resulting in a pyramid die stack.
  • the pyramid die stack is flip-chip attached to a substrate having a cavity drilled therein wherein the daughter die fits into the cavity.
  • FIG. 1 is a top view of a substrate having a cavity therein.
  • FIG. 2 is a cross-sectional representation of the substrate in FIG. 1 , having the cavity therein.
  • FIG. 3 is a cross-sectional representation of a die stack showing die to die interconnection.
  • FIG. 4 is a cross-sectional representation of a flip chip attachment of the substrate and the die stack of FIGS. 2 and 3 , respectively.
  • FIG. 5 is an enlarged cross-sectional representation of a portion of FIG. 4 .
  • the present disclosure is a process integration method of fabricating chip on chip using flip chip attachment and a cavity substrate.
  • this method can be used for passive and power management integrated circuit (PMIC) devices.
  • the Daughter die such as an integrated passive device (IPD) chip
  • IPD integrated passive device
  • the Mother die such as a power management chip
  • the daughter chip protrudes below the interconnects of the mother chip, it needs a cavity substrate for flip chip attachment.
  • the die on die attach capability produces direct contact between the mother and daughter chips.
  • FIGS. 1-5 a preferred integration method will be described.
  • the present disclosure provides a new process integration for fabricating chip on chip using flip chip attachment and a cavity substrate.
  • these may be passive and power management integrated circuit (PMIC) devices, but the method is not limited to only these types of devices.
  • PMIC passive and power management integrated circuit
  • the mother chip will be a power management chip and the daughter chip will be an integrated passive device, for example.
  • the IPD chip could be a capacitor array or other passives such as resistors, inductors, baluns, or filters, or the like.
  • the direct electrical connections between the active surfaces of the two dies 10 and 14 , using micro bump 33 result in better electrical performance than non-direct connections, such as wire bonding or passive surface mount and connection via laminate substrate copper trace.
  • the die on die attach results in the flip chip attach of the pyramid die stack as shown in FIG. 4 .
  • the IPD die is smaller than the PMIC die in all dimensions, i.e. length, width, and height directions.
  • the IPD die size can vary depending upon the number of passives required.
  • FIG. 2 illustrates a laminate substrate 20 having solder balls 30 on the underside of the substrate. Solder balls are required for BGA packages, but this cavity substrate technology is also applicable for LGA packages where solder balls are not attached.
  • the substrate 20 has been laser drilled to form cavity 25 .
  • Advancements in substrate drilling techniques and tools allow for the laser drilling of this small cavity 25 without increasing the package dimension and without causing mechanical damage or substrate layer separation.
  • FIG. 1 illustrates a top view of the substrate shown in cross-section view A-A′ in FIG. 2 . Cavity 25 is shown.
  • the die on die attached chips shown in FIG. 3 are flipped resulting in an inverted pyramid die stack 22 as shown in FIG. 4 .
  • the die stack 22 is connected to the BGA substrate 20 via the copper pillars 35 using a flip chip attach method.
  • the passive IPD die 14 protrudes below the interconnects 35 of the mother die 10 , but it fits into the cavity 25 drilled into the substrate 20 .
  • This method can be applied for some existing products by re-routing substrate metal traces in the laminate substrate to make space available for the cavity. This is only a slight change as compared to the standard substrate.
  • the cavity can be designed into new laminate substrates.
  • FIG. 5 is an enlarged portion of the cross-section of FIG. 4 . There is shown:

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a pyramid die stack. The die stack is flip-chip attached to a laminate substrate having a cavity drilled therein wherein the smaller die fits into the cavity. The die to die attach is not limited to IPD and PMIC and can be used for other die types as required.

Description

    TECHNICAL FIELD
  • This disclosure is related to flip chip attachment of Mother die and Daughter Integrated Passive Device die, and more particularly, to methods of flip chip attachment of Mother die and Daughter Integrated Passive Device die in an inverted pyramid die stack, using a laser drilled cavity laminate Ball Grid Array/Land Grid Array substrate to accommodate the protruding Daughter die.
    • BACKGROUND
  • Passive device integration is typically done by:
      • 1) Back side on active side die stacking with wire bond interconnection,
      • 2) Surface Mount of the passive to the top layer of a laminate substrate, or
      • 3) Embedding large passive components into a printed circuit board.
  • The limitations of these methods prevent direct electrical connection between mother and daughter die, followed by the flip chip attach of the resulting inverted die stack onto a Ball Grid Array (BGA) or Land Grid Array (LGA) laminate substrate. Direct connection would allow for better electrical performance and printed circuit board (PCB) real estate reduction by integrating passives off the PCB and into the package.
  • In the past, substrate technologies were limited with respect to the ability to laser or mechanically drill a cavity into a laminate substrate having a Bismaleimide Triazine (BT) core while maintaining mechanical and reliability integrity. With the advancements in substrate manufacturing technology, it is now possible to manufacture substrates with mechanically drilled or lasered cavities.
  • U.S. Pat. No. 7,915,084 (Hong), U.S. Pat. No. 8,222,717 (Shim et al), and U.S. Pat. No. 7,835,157 (Tilmans) discuss integrated passive devices, but these are completely different die stacking and die to substrate interconnection and package types from those in the present disclosure.
    • SUMMARY
  • It is the primary objective of the present disclosure to provide a new integration method for inverted pyramid die stack using flip chip attachment to a BGA or LGA laminate cavity substrate.
  • Yet another objective is to use a die on die attachment to produce direct contact of a Mother die to a Daughter die.
  • In accordance with the objectives of the present disclosure, a method of fabricating a mother and daughter integrated circuit is achieved. A mother die and a daughter die, wherein the daughter die is smaller than the mother die, are directly connected, active surface to active surface, resulting in a die stack. The die stack is flip-chip attached to a substrate having a cavity drilled therein wherein the daughter die fits into the cavity.
  • Also in accordance with the objectives of the present disclosure, a method of fabricating an integrated passive device is achieved. An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a die stack. The die stack is flip-chip attached to a substrate having a cavity drilled therein wherein the smaller die fits into the cavity.
  • Also in accordance with the objectives of the present disclosure, an mother and daughter integrated circuit is achieved. A mother die and a daughter die, wherein the daughter die is smaller than the mother die, are directly connected, active surface to active surface, resulting in a pyramid die stack. The pyramid die stack is flip-chip attached to a substrate having a cavity drilled therein wherein the daughter die fits into the cavity.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • In the accompanying drawings forming a material part of this description, there is shown:
  • FIG. 1 is a top view of a substrate having a cavity therein.
  • FIG. 2 is a cross-sectional representation of the substrate in FIG. 1, having the cavity therein.
  • FIG. 3 is a cross-sectional representation of a die stack showing die to die interconnection.
  • FIG. 4 is a cross-sectional representation of a flip chip attachment of the substrate and the die stack of FIGS. 2 and 3, respectively.
  • FIG. 5 is an enlarged cross-sectional representation of a portion of FIG. 4.
    •  DETAILED DESCRIPTION
  • The present disclosure is a process integration method of fabricating chip on chip using flip chip attachment and a cavity substrate. For example, this method can be used for passive and power management integrated circuit (PMIC) devices. The Daughter die, such as an integrated passive device (IPD) chip, is attached under the Mother die, such as a power management chip, resulting in an inverted pyramid die stack once flipped onto the cavity substrate. Since the daughter chip protrudes below the interconnects of the mother chip, it needs a cavity substrate for flip chip attachment. The die on die attach capability produces direct contact between the mother and daughter chips.
  • This package technology has recently become viable due to:
      • 1) Availability of the IPD die, and
      • 2) Laminate cavity substrate
        as opposed to the use of standard surface mount passives.
  • Higher accuracy drilling capabilities of substrate suppliers are essential to this technology. Higher drilling accuracy minimizes cavity sizes to prevent potential package XY dimension increase for integration into existing products. Package XY dimension is critical in order to reduce end printed circuit board (PCB) space which is at a premium and very cost sensitive.
  • Advancements in substrate drilling systems and tools prevent mechanical vibration resulting in mechanical damage and substrate layer separation which can lead to package delamination and reliability failures and permits the laser drilling of cavities in laminate substrates.
  • Referring now more particularly to FIGS. 1-5, a preferred integration method will be described.
  • The present disclosure provides a new process integration for fabricating chip on chip using flip chip attachment and a cavity substrate. For example, these may be passive and power management integrated circuit (PMIC) devices, but the method is not limited to only these types of devices. For illustration purposes, the mother chip will be a power management chip and the daughter chip will be an integrated passive device, for example.
  • Referring now to FIG. 3, there is shown
      • 1) Mother chip 10, which may be a power management chip.
      • 2) Daughter chip 14, which may be an IPD chip.
      • 3) Active surface of the IPD chip 16 being attached to the active surface of the power management chip 12 using micro bump 33.
      • 4) The copper pillar interconnect 35 for the power management chip to attach the pyramid die stack to the laminate substrate 20 (FIG. 2).
  • The IPD chip could be a capacitor array or other passives such as resistors, inductors, baluns, or filters, or the like. The direct electrical connections between the active surfaces of the two dies 10 and 14, using micro bump 33, result in better electrical performance than non-direct connections, such as wire bonding or passive surface mount and connection via laminate substrate copper trace. The die on die attach results in the flip chip attach of the pyramid die stack as shown in FIG. 4.
  • The IPD die is smaller than the PMIC die in all dimensions, i.e. length, width, and height directions. The IPD die size can vary depending upon the number of passives required. The smaller IPD die, when attached to the PMIC die, then results in a pyramid die stack configuration.
  • FIG. 2. illustrates a laminate substrate 20 having solder balls 30 on the underside of the substrate. Solder balls are required for BGA packages, but this cavity substrate technology is also applicable for LGA packages where solder balls are not attached. The substrate 20 has been laser drilled to form cavity 25.
  • Advancements in substrate drilling techniques and tools allow for the laser drilling of this small cavity 25 without increasing the package dimension and without causing mechanical damage or substrate layer separation.
  • FIG. 1 illustrates a top view of the substrate shown in cross-section view A-A′ in FIG. 2. Cavity 25 is shown.
  • The die on die attached chips shown in FIG. 3 are flipped resulting in an inverted pyramid die stack 22 as shown in FIG. 4. Now the die stack 22 is connected to the BGA substrate 20 via the copper pillars 35 using a flip chip attach method. The passive IPD die 14 protrudes below the interconnects 35 of the mother die 10, but it fits into the cavity 25 drilled into the substrate 20.
  • This method can be applied for some existing products by re-routing substrate metal traces in the laminate substrate to make space available for the cavity. This is only a slight change as compared to the standard substrate. Alternatively, the cavity can be designed into new laminate substrates.
  • FIG. 5 is an enlarged portion of the cross-section of FIG. 4. There is shown:
      • 1) Laminate substrate 20
      • 2) Power management chip 10.
      • 3) IPD chip 14.
      • 4) Power management to substrate interconnect via flip chip attach 35.
      • 5) IPD to power management interconnect micro bumps 33.
      • 6) Flip Chip attach underfill 32.
      • 7) Epoxy Molding Compound 34.
      • 8) Substrate cavity 25.
      • 9) BGA solder balls 30.
  • Although the preferred embodiment of the present disclosure has been illustrated, and that form has been described in detail, it will be readily understood by those skilled in the art that various modifications may be made therein without departing from the spirit of the disclosure or from the scope of the appended claims.

Claims (20)

What is claimed is:
1. A method of fabricating a mother and daughter integrated circuit device comprising:
providing a mother die having an active surface;
providing a daughter die having an active surface wherein said daughter die is smaller than said mother die in all dimensions;
directly connecting said active surface of said daughter die to said active surface of said mother die resulting in a pyramid die stack;
providing a substrate having a cavity drilled therein wherein said cavity corresponds to a size and position of said daughter die in relation to said mother die; and
attaching said pyramid die stack to said substrate using a flip chip method wherein said daughter die fits into said cavity.
2. The method according to claim 1 wherein said mother die is a power management circuit chip.
3. The method according to claim 1 wherein said daughter die is an integrated passive device containing at least one passive device.
4. The method according to claim 3 wherein said at least one passive device is chosen from the group containing a capacitor, a resistor, an inductor, a balun, and a filter.
5. The method according to claim 1 wherein said directly connecting said active surface of said daughter die to said active surface of said mother die comprises micro bumps.
6. The method according to claim 1 wherein said cavity is drilled by a mechanical drilling process or a laser drilling process.
7. The method according to claim 1 wherein said substrate is a ball grid array or a land grid array substrate.
8. The method according to claim 1 wherein said attaching said pyramid die stack to said substrate comprises copper pillar interconnects.
9. A method of fabricating an integrated passive device comprising:
providing a first die containing at least one power management device;
providing a second die containing at least one passive device wherein said second die is smaller than said first die;
directly connecting an active surface of said second die to an active surface of said first die resulting in a die stack;
providing a substrate having a cavity drilled therein wherein said cavity corresponds to a size and position of said second die in relation to said first die; and
attaching said die stack to said substrate using a flip chip method wherein said second die fits into said cavity.
10. The method according to claim 9 wherein said at least one passive device is chosen from the group containing a capacitor, a resistor, an inductor, a balun, and a filter.
11. The method according to claim 9 wherein said directly connecting said active surface of said second die to said active surface of said first die comprises micro bumps.
12. The method according to claim 9 wherein said cavity is drilled by a mechanical drilling process or by a laser drilling process.
13. The method according to claim 9 wherein said substrate is a ball grid array or a land grid array substrate.
14. The method according to claim 9 wherein said attaching said die stack to said substrate comprises copper pillar interconnects.
15. A mother and daughter integrated circuit comprising:
a mother die having an active surface;
a daughter die having an active surface wherein said daughter die is smaller than said mother die and wherein an active surface of said daughter die is directly connected to an active surface of said mother die resulting in a pyramid die stack; and
a substrate having a cavity drilled therein wherein said pyramid die stack is flip-chip attached to said substrate wherein said daughter die fits into said cavity.
16. The device according to claim 15 wherein said mother die is a power management circuit chip.
17. The device according to claim 15 wherein said daughter die is an integrated passive device containing at least one passive device.
18. The device according to claim 17 wherein said at least one passive device is chosen from the group containing a capacitor, a resistor, an inductor, a balun, and a filter.
19. The device according to claim 15 wherein said substrate is laminate substrate.
20. The device according to claim 15 wherein said substrate is a ball grid array or a land grid array substrate.
US13/790,437 2013-03-04 2013-03-08 Chip on Chip Attach (Passive IPD and PMIC) Flip Chip BGA Using New Cavity BGA Substrate Abandoned US20140246773A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/299,910 US9929130B2 (en) 2013-03-04 2016-10-21 Chip on chip attach (passive IPD and PMIC) flip chip BGA using new cavity BGA substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP13368005.8A EP2775523A1 (en) 2013-03-04 2013-03-04 Chip on chip attach (passive IPD and PMIC) flip chip BGA using new cavity BGA substrate
EP13368005.8 2013-03-04

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/299,910 Division US9929130B2 (en) 2013-03-04 2016-10-21 Chip on chip attach (passive IPD and PMIC) flip chip BGA using new cavity BGA substrate

Publications (1)

Publication Number Publication Date
US20140246773A1 true US20140246773A1 (en) 2014-09-04

Family

ID=48050636

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/790,437 Abandoned US20140246773A1 (en) 2013-03-04 2013-03-08 Chip on Chip Attach (Passive IPD and PMIC) Flip Chip BGA Using New Cavity BGA Substrate
US15/299,910 Active US9929130B2 (en) 2013-03-04 2016-10-21 Chip on chip attach (passive IPD and PMIC) flip chip BGA using new cavity BGA substrate

Family Applications After (1)

Application Number Title Priority Date Filing Date
US15/299,910 Active US9929130B2 (en) 2013-03-04 2016-10-21 Chip on chip attach (passive IPD and PMIC) flip chip BGA using new cavity BGA substrate

Country Status (2)

Country Link
US (2) US20140246773A1 (en)
EP (2) EP2775523A1 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017142637A1 (en) * 2016-02-16 2017-08-24 Xilinx, Inc. Chip package assembly with power management integrated circuit and integrated circuit die
US10367415B1 (en) 2018-08-28 2019-07-30 Ferric Inc. Processor module with integrated packaged power converter
CN110828496A (en) * 2019-11-15 2020-02-21 华天科技（昆山）电子有限公司 Semiconductor device and method for manufacturing the same
WO2020046276A1 (en) * 2018-08-28 2020-03-05 Ferric Inc. Processor module with integrated packaged power converter
US10658331B2 (en) 2018-08-28 2020-05-19 Ferric Inc. Processor module with integrated packaged power converter
CN112510020A (en) * 2020-03-02 2021-03-16 谷歌有限责任公司 Deep trench capacitor embedded in package substrate
US20210375845A1 (en) * 2020-05-27 2021-12-02 Qualcomm Incorporated Package cavity for enhanced device performance with an integrated passive device
US11929673B2 (en) 2021-10-29 2024-03-12 Ferric Inc. Two-stage voltage converters for microprocessors

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10580710B2 (en) 2017-08-31 2020-03-03 Micron Technology, Inc. Semiconductor device with a protection mechanism and associated systems, devices, and methods
US10381329B1 (en) 2018-01-24 2019-08-13 Micron Technology, Inc. Semiconductor device with a layered protection mechanism and associated systems, devices, and methods
US10475771B2 (en) 2018-01-24 2019-11-12 Micron Technology, Inc. Semiconductor device with an electrically-coupled protection mechanism and associated systems, devices, and methods
US10775424B2 (en) 2018-08-31 2020-09-15 Micron Technology, Inc. Capacitive voltage divider for monitoring multiple memory components
US10453541B1 (en) 2018-08-31 2019-10-22 Micron Technology, Inc. Capacitive voltage divider for power management
US10872640B2 (en) 2018-08-31 2020-12-22 Micron Technology, Inc. Capacitive voltage dividers coupled to voltage regulators
US10482979B1 (en) 2018-08-31 2019-11-19 Micron Technology, Inc. Capacitive voltage modifier for power management
US11581289B2 (en) 2019-07-30 2023-02-14 Stmicroelectronics Pte Ltd Multi-chip package

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5578869A (en) * 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US6084308A (en) * 1998-06-30 2000-07-04 National Semiconductor Corporation Chip-on-chip integrated circuit package and method for making the same
US6232667B1 (en) * 1999-06-29 2001-05-15 International Business Machines Corporation Technique for underfilling stacked chips on a cavity MLC module
US6239484B1 (en) * 1999-06-09 2001-05-29 International Business Machines Corporation Underfill of chip-under-chip semiconductor modules
US6659512B1 (en) * 2002-07-18 2003-12-09 Hewlett-Packard Development Company, L.P. Integrated circuit package employing flip-chip technology and method of assembly
US6825567B1 (en) * 2003-08-19 2004-11-30 Advanced Semiconductor Engineering, Inc. Face-to-face multi-chip flip-chip package
US7573136B2 (en) * 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
US7842542B2 (en) * 2008-07-14 2010-11-30 Stats Chippac, Ltd. Embedded semiconductor die package and method of making the same using metal frame carrier
US20120077317A1 (en) * 2005-10-14 2012-03-29 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US20140191391A1 (en) * 2013-01-07 2014-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bump structures in package structure

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6272020B1 (en) * 1997-10-16 2001-08-07 Hitachi, Ltd. Structure for mounting a semiconductor device and a capacitor device on a substrate
US6265771B1 (en) * 1999-01-27 2001-07-24 International Business Machines Corporation Dual chip with heat sink
DE60219712T2 (en) 2001-04-19 2008-02-28 Interuniversitair Microelektronica Centrum Vzw Manufacture of integrated tunable / switchable passive micro and millimeter wave modules
US6477034B1 (en) * 2001-10-03 2002-11-05 Intel Corporation Interposer substrate with low inductance capacitive paths
US20050104211A1 (en) * 2002-05-07 2005-05-19 Shinji Baba Semiconductor device having semiconductor chips mounted on package substrate
JP2004221176A (en) * 2003-01-10 2004-08-05 Matsushita Electric Ind Co Ltd Wiring board with built-in solid state electrolytic capacitor and method of manufacturing the same
US7763963B2 (en) 2005-05-04 2010-07-27 Stats Chippac Ltd. Stacked package semiconductor module having packages stacked in a cavity in the module substrate
US8264846B2 (en) * 2006-12-14 2012-09-11 Intel Corporation Ceramic package substrate with recessed device
JP2010098225A (en) * 2008-10-20 2010-04-30 Toshiba Corp Semiconductor device
US20100244276A1 (en) * 2009-03-25 2010-09-30 Lsi Corporation Three-dimensional electronics package
US8227904B2 (en) * 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5578869A (en) * 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US6084308A (en) * 1998-06-30 2000-07-04 National Semiconductor Corporation Chip-on-chip integrated circuit package and method for making the same
US6239484B1 (en) * 1999-06-09 2001-05-29 International Business Machines Corporation Underfill of chip-under-chip semiconductor modules
US6232667B1 (en) * 1999-06-29 2001-05-15 International Business Machines Corporation Technique for underfilling stacked chips on a cavity MLC module
US7573136B2 (en) * 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
US6659512B1 (en) * 2002-07-18 2003-12-09 Hewlett-Packard Development Company, L.P. Integrated circuit package employing flip-chip technology and method of assembly
US6825567B1 (en) * 2003-08-19 2004-11-30 Advanced Semiconductor Engineering, Inc. Face-to-face multi-chip flip-chip package
US20120077317A1 (en) * 2005-10-14 2012-03-29 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US7842542B2 (en) * 2008-07-14 2010-11-30 Stats Chippac, Ltd. Embedded semiconductor die package and method of making the same using metal frame carrier
US20140191391A1 (en) * 2013-01-07 2014-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bump structures in package structure

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017142637A1 (en) * 2016-02-16 2017-08-24 Xilinx, Inc. Chip package assembly with power management integrated circuit and integrated circuit die
US10665579B2 (en) 2016-02-16 2020-05-26 Xilinx, Inc. Chip package assembly with power management integrated circuit and integrated circuit die
US10367415B1 (en) 2018-08-28 2019-07-30 Ferric Inc. Processor module with integrated packaged power converter
WO2020046276A1 (en) * 2018-08-28 2020-03-05 Ferric Inc. Processor module with integrated packaged power converter
US10658331B2 (en) 2018-08-28 2020-05-19 Ferric Inc. Processor module with integrated packaged power converter
CN110828496A (en) * 2019-11-15 2020-02-21 华天科技（昆山）电子有限公司 Semiconductor device and method for manufacturing the same
CN112510020A (en) * 2020-03-02 2021-03-16 谷歌有限责任公司 Deep trench capacitor embedded in package substrate
US20210273042A1 (en) * 2020-03-02 2021-09-02 Google Llc Deep trench capacitors embedded in package substrate
US11784215B2 (en) * 2020-03-02 2023-10-10 Google Llc Deep trench capacitors embedded in package substrate
US20230420494A1 (en) * 2020-03-02 2023-12-28 Google Llc Deep trench capacitors embedded in package substrate
US20210375845A1 (en) * 2020-05-27 2021-12-02 Qualcomm Incorporated Package cavity for enhanced device performance with an integrated passive device
US11929673B2 (en) 2021-10-29 2024-03-12 Ferric Inc. Two-stage voltage converters for microprocessors

Also Published As

Publication number Publication date
EP2775523A1 (en) 2014-09-10
US20170040309A1 (en) 2017-02-09
US9929130B2 (en) 2018-03-27
EP3133645A1 (en) 2017-02-22

Similar Documents

Publication Publication Date Title
US9929130B2 (en) Chip on chip attach (passive IPD and PMIC) flip chip BGA using new cavity BGA substrate
US10854575B2 (en) Three-dimensional (3D) package structure having an epoxy molding compound layer between a discrete inductor and an encapsulating connecting structure
US11309304B2 (en) Stackable electronic package and method of fabricating same
TWI303096B (en)
US8642393B1 (en) Package on package devices and methods of forming same
US10199320B2 (en) Method of fabricating electronic package
US20180114786A1 (en) Method of forming package-on-package structure
US9024447B2 (en) Stackable electronic package and method of making same
US9806061B2 (en) Bumpless wafer level fan-out package
US10002823B2 (en) Packaging substrate and method of fabricating the same
KR20140043651A (en) Apparatus and method for a component package
CN104377171A (en) Packages with Interposers and Methods for Forming the Same
TWI628775B (en) Semiconductor package, semiconductor device using the same and manufacturing method thereof
KR20100133303A (en) Semiconductor device and method of manufacturing the same
US9324683B2 (en) Semiconductor package and method of manufacturing the same
TWI672768B (en) Package substrate
TWI435667B (en) Print circuit board assembly
US20160104652A1 (en) Package structure and method of fabricating the same
JP2014026997A (en) Semiconductor device
JP2008021842A (en) Semiconductor module, and manufacturing method of semiconductor module

Legal Events

Date Code Title Description
AS Assignment

Owner name: DIALOG SEMICONDUCTOR GMBH, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KENT, IAN;REEL/FRAME:030472/0269

Effective date: 20130219

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION