US20100235548A1 - Data processing system having a channel adapter shared by multiple operating systems - Google Patents
Data processing system having a channel adapter shared by multiple operating systems Download PDFInfo
- Publication number
- US20100235548A1 US20100235548A1 US12/721,964 US72196410A US2010235548A1 US 20100235548 A1 US20100235548 A1 US 20100235548A1 US 72196410 A US72196410 A US 72196410A US 2010235548 A1 US2010235548 A1 US 2010235548A1
- Authority
- US
- United States
- Prior art keywords
- input
- channel
- output process
- data
- adaptor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
Definitions
- the present invention relates to a data processing system for transferring data, and more particularly to a computer system which runs a plurality of operating systems (OS's) and executes processes of OS's at the same time by using a single channel adaptor.
- OS's operating systems
- JP-A-2002-41306 An example of a system supporting the LPAR function is disclosed in JP-A-2002-41306. Although a plurality of OS's can run on one system, a PCI I/O adaptor having a PCI bus as an interface cannot be shared by a plurality of OS's so that a PCI I/O adaptor is provided to each OS.
- FIG. 10 Another example is disclosed in JP-A-2002-99437 which realizes an LPAR function in a main frame or the like.
- the outline of this example is shown in FIG. 10 .
- a controller 1001 and a local memory 1002 are mounted on a LAN package 1000 having a LAN adaptor 1003 as a PCI I/O device to share the LAN adaptor by a plurality of OS's.
- the controller 1001 has a driver 1005 for the LAN adaptor.
- the controller 1001 is connected to a bus 1007 such as a PCI bus or a system specific bus, and to the LAN adaptor 1003 via a PCI bus 1004 .
- controller 1001 receives an input/output process activated from an OS 1
- transfer data 1105 of OS 1 in a system memory is buffered in the local memory 1002
- input/output process control data 1103 of OS 1 is stored in the local memory 1002 as input/output process control data for the LAN adaptor.
- control data and transfer data for an input/output process activated from OS 2 are stored in the local memory 1002 .
- the LAN adaptor 1003 transfers data by accessing not the system memory but the local memory 1002 .
- the control data is newly written in the local memory of the LAN package and the transfer data is buffered in the local memory so that the performance of the system is influenced and a development cost is required.
- the open source server cannot realize that a plurality of OS's share a PCI I/O device having a PCI bus interface supported by the open source server, whereas although the main frame can realize that a plurality of OS's share a PCI I/O device, the local memory for a data buffer and input/output process control data and the controller for the data buffer and input/output process control data are mounted on the package. Use of the controller and local memory results in degraded performance and increased cost.
- a channel driver as an interface between each OS and the channel adaptor for controlling the input/output process control data acquires from a control program a virtual computer number representative of an OS identifier of each OS operating the channel driver, the channel driver uses the virtual computer number and the input/output process control data having an identifier decided in system configuration information to be usable for the virtual computer number, and a plurality of OS's use input/output process control data having different identifiers for the channel adaptor to execute the input/output process without sharing the input/output process control data for the channel adaptor by different OS's.
- an address indicating the input/output process control data is a virtual address and the input/output process is executed by using an address translation table for translating the virtual address to a physical address
- the channel driver generates the address translation table of the usable input/output process control data by using the virtual computer number acquired from the control program and the identifier of the usable input/output process control data obtained from the configuration information
- the data processing system includes means for generating a virtual address translation table from a plurality of address translation tables generated by the channel driver of each OS, and the channel adaptor processes the input/output process control data of a plurality of OS's by using the virtual address translation table to execute the input/output process for a plurality of OS's without changing the input/output process control data generated by each OS.
- a channel adaptor can be provided which can execute an input/output (I/O) process requested from a plurality of OS's at the same time.
- I/O input/output
- FIG. 1 is a diagram showing the configuration of a data processing system according to an embodiment of the present invention.
- FIG. 2 is a diagram showing an example of the configuration of a data processing system.
- FIG. 3 is a diagram showing the contents of a channel control register in a channel adaptor.
- FIG. 4 is a diagram showing Queue Pair and Completion Queue as I/O process control data and an address translation table.
- FIG. 5 is a diagram showing Send Queues as I/O process control data used by the embodiment of the present invention.
- FIG. 6 is a diagram showing the configuration of a data processing system.
- FIG. 7 is a table showing a correspondence between LPAR numbers and usable QPs and CQs.
- FIG. 8 is a diagram showing TPTs generated by each OS and a virtual TPT.
- FIG. 9 is a diagram showing the configuration of a data processing system according to an embodiment of the invention.
- FIG. 10 is a diagram showing the outline of a conventional system.
- FIG. 11 is a diagram showing the details of the conventional system.
- Sharing a PCI I/O device by a plurality of OS's is realized by software without using a controller and a local memory for controlling the PCI I/O device.
- Fibre Channel adaptors in conformity with business standard specifications supported by an open source server include Fibre Channel defined by ANSI (American National Standards Institute), InfiniBand defined by IBTA (InfiniBand Trade Association) and the like.
- a channel adaptor is assumed to use Que Pair constituted of Send Queue and Receive Queue, and Completion Queue used by InfiniBand or the like as input/output process control data for executing input/output process, a virtual address, and an address translation table (TPT) for translating a virtual address to a physical address.
- Que Pair constituted of Send Queue and Receive Queue, and Completion Queue used by InfiniBand or the like
- TPT address translation table
- FIG. 2 shows an example of the configuration of a data processing system.
- a memory access control chip 203 mainly controls an access to a main storage (MS) 200 from processors 204 and 205 and a channel adaptor 206 .
- the memory access control chip 203 is connected to the channel adaptor 206 via a PCI bus.
- the memory access control chip 203 is connected to the processors 204 and 205 via a system specific host bus.
- the channel adaptor 206 has one port which is connected to an I/O device 208 via a switch 207 .
- This data processing system supporting an LPAR function allocates, for example, 2 MB of MS 200 to each LPAR, and each OS in each LPAR runs by using a memory of 2 MB.
- the channel adaptor 206 of the data processing system using the PCI bus has a PCI configuration register as a standard component of a PCI bus connected device, and a channel control register for controlling the channel adaptor.
- the contents of the channel control resister are shown in FIG. 3 , the details thereof being described later.
- Each OS performs data transfer by using Queue Pair (QP) constituted of Send Queue and Receive Queue, and Completion Queue (CQ) for queuing an identifier of a processed QP.
- QP Queue Pair
- CQ Completion Queue
- a channel driver in OS generates QP, controls CQ, and executes processes such as activating a data transfer process for the channel adaptor.
- FIG. 4 shows the outline of QP and CQ.
- Send Queue and Receive Queue are each constituted of Descriptor and a data buffer, Descriptor containing an address of the data buffer. Before data is transmitted, a physical address of a data buffer 403 storing transmission data of Send Queue is set to Descriptor 401 .
- a physical address of a data buffer 405 storing reception data of Receive Queue is set to Descriptor 404 .
- Each Queue Pair has an identifier.
- Queue Pair has an identifier of # 100 (QP 100 ).
- the channel adaptor can execute processes of a plurality of QPs at the same time.
- TPT address translation table 406 .
- TPT is one physically continuous area and stores Send Queue Descriptor addresses and Receive Queue Descriptor addresses of all QPs to be used by the channel adaptor.
- Each of the Send Queue Descriptor address and Receive Queue Descriptor address has 16 bytes. The value “1” of the most significant bit indicates that the Descriptor address is valid, and the lower 8 bytes indicate the physical address of Descriptor.
- Each CQ has an identifier of QP processed by the channel adaptor, the identifier containing information on which of Send Queue and Receive Queue was processed.
- Each entry of CQ has 16 bytes. If the most significant bit of upper 8 bytes is “1”, it means that the entry is valid. The upper 4 bytes of lower 8 bytes are an identifier of processed QP. If the most significant bit of lower 4 bytes of the lower 8 bytes is “1”, it means that Send Queue was processed, whereas if the most significant bit is “0”, it means that Receive Queue was processed.
- TPT base address register 303 defined in the channel control register 300 shown in FIG. 3 indicates a start address (physical address) of the address translation table (TPT) 406 , this address being set by the channel driver.
- the channel adaptor accesses the address translation table (TPT) 406 by using the value in the TPT base address register 303 .
- FIG. 5 shows the detailed data structure of Send Queue.
- DB-AD 601 is made of an 8-byte area indicating the start address (physical address) of a data buffer address area.
- FLAG 503 includes information on whether an I/O process is normally completed or erroneously completed, error information indicating a type of an occurred error, information on whether there is Descriptor to be next processed (presence/absence of Next Descriptor), a QP number of a data transfer partner, a related Q identifier (CQ#) and a physical address of CQ. If there is Descriptor to be next processed, a start address (physical address) of the next Descriptor is set to Next Descriptor 502 of an 8-byte length.
- FIG. 5 shows the format of Send Queue.
- the format of Receive Queue is the same as that of Send Queue and reception data is stored in an area indicated by DB-AD.
- An activation method for an I/O process is assumed: that the channel driver sets an identifier (QP#) of QP to be processed to a QP# register 302 defined in the channel control register 300 , and sets information on which one of Send Queue and Receive Queue to a Send/Receive register 306 ; that an area where QP Descriptor address as a virtual address is stored is set to a TPT offset address register 304 ; and that the channel adaptor is instructed to activate an I/O process by setting an offset address from the TPT base address and writing “1” in an I/O process enable register 305 .
- the channel driver sets a physical address to DB-AD 501 and sets a command area (256 bytes) 504 to the area indicated by DB-AD.
- the command area contains, in addition to a command, information on a target ID indicating a partner port for the I/O process, a LUN indicating a device under the port and the like.
- a 256-byte area following the command area of 256 bytes is used as a command response information area 505 for storing a response frame to the command.
- Another Descriptor 510 is defined, and the start address of Descriptor 510 is set to Next Descriptor 502 .
- the transmission data buffer 506 is at the address of DB_AD 507 of Descriptor 510 . If the data buffer is made to have a variable length, information on the data length is stored in FLAG 509 . In this embodiment, for the simplicity of description, the data buffer is made to have a fixed length of 4 K bytes and the data length is not set.
- the channel driver generates Send Queue and activates an I/O process. Although the partner QP number, related CQ# and physical address of CQ# are defined in FLAG of each Descriptor, it is assumed that the values in FLAG in the top Descriptor are valid.
- the channel adaptor When the channel adaptor recognizes an I/O process activation from the channel driver, it acquires the start address (physical address) of Descriptor in accordance with an offset (virtual address) set to the TPT offset address register 304 in the channel control register and an address translation table (TPT) 406 .
- TPT address translation table
- a fetch process for Descriptor is executed, and in accordance with fetched Descriptor information, the command area 504 and transmission data buffer 506 are fetched. Data is transferred to a target ID designated in the command area 504 and the partner QP# designated in FLAG 503 .
- the response frame When a response frame indicating a process completion is received from the partner, the response frame is stored in the command response information area 505 .
- an identifier of processed QP After the response frame is stored, in accordance with the information in FLAG 503 , an identifier of processed QP, information on Send Queue, a valid bit of the entry are set to Completion Queue # 1 (CQ 1 ) 407 , CQ# “1” is set to a completion CQ register 308 in the channel control register, and an I/O interrupt representative of completion of an I/O process is issued to OS.
- error information is set to FLAG 503 .
- the channel driver of OS recognizes the I/O interrupt, reads the completion CQ register 308 and executes a completion process of the I/O process activated to the channel adaptor in accordance with the contents of CQ 1 .
- the outline of the I/O process has been described above.
- FIG. 6 illustrates the relation between software and the channel adaptor in which the I/O process is executed by using 1000 QPs from QP 000 to QP 999 604 and 100 CQs from CQ 00 to CQ 99 607 .
- FIG. 1 shows the embodiment characteristic to the present invention.
- two OS's share one channel adaptor.
- LPAR# 1 and LPAR# 2 In the data processing system shown in FIG. 1 , under the control of a LPAR control program 101 , two LPARs, LPAR# 1 and LPAR# 2 , start up, OS 1 105 runs in LPAR# 1 and OS 2 106 runs in LPAR# 2 .
- each channel driver has a function which acquires LPAR# in which the channel driver runs.
- acquired information is that a channel driver 112 runs in LPAR# 1 and a channel driver 113 runs in LPAR# 2 .
- a virtual channel driver 102 is a driver which actually controls a channel adaptor 100 .
- the LPAR control program 101 intercepts the access function, and the virtual driver 102 accesses the channel control register 114 .
- the identifiers and numbers of Queue Pairs (QPs) and Completion Queues (CQs) capable of being used by each OS are defined as a portion of configuration information.
- the channel adaptor has been described above as being capable of processing 1000 QPs from QP 000 to QP 999 and 100 CQs from CQ 00 to CQ 99 .
- These resources are distributed to each OS, and the configuration information is defined in such a manner that QPs or CQs having the same identifier are not shared by different OS's.
- FIG. 7 the identifiers and numbers of Queue Pairs (QPs) and Completion Queues (CQs) capable of being used by each OS are defined as a portion of configuration information.
- the channel adaptor has been described above as being capable of processing 1000 QPs from QP 000 to QP 999 and 100 CQs from CQ 00 to CQ 99 .
- LPAR# 1 can use 100 QPs from QP 100 , i.e., QP 100 to QP 199 and can use only one CQ 1 .
- LPAR# 2 can use 100 QPs from QP 200 , i.e., QP 200 to QP 299 and can use only one CQ 2 .
- the channel driver acquires information on usable QP# and CQ# from the configuration information in LPAR# in which the channel driver runs, by using a kernel function or the like.
- the LPAR control program acquires information on LPAR#, QP# and CQ# used by each LPAR from the configuration information by using the kernel function or the like.
- the channel driver 112 controls QP 100 to QP 199 , sets only Descriptor addresses of Send Queues and Receive Queues of QP 100 to QP 199 to TPT 110 , and sets “1” to the address valid bit of the most significant bit. After the address of each Descriptor is set to TPT 110 , the channel driver 112 writes the start address of TPT 110 in the TPT base address register 303 in the channel control register 114 , and writes “1” in the TPT valid register 307 to notify that TPT is valid.
- the LPAR control program 101 intercepts a function which makes the channel driver 112 write a value in the TPT base address register 303 , and the virtual channel driver 102 writes a start address of a virtual address translation table (VTPT) 103 different from TPT 110 in the TPT base address register 303 of the channel control register 114 .
- the LPAR control program also intercepts a function which makes the channel driver 112 write a value in the TPT valid register 307 , the virtual channel driver 102 copies the address corresponding to the address valid bit “1” in TPT 110 to VTPT 103 , and the LPAR control program 101 writes “1” in the TPT valid register 307 .
- the channel driver 113 controls QP 200 to QP 299 , sets only Descriptor addresses of Send Queues and Receive Queues of QP 200 to QP 299 to TPT 111 , and sets “1” to the address valid bit of the most significant bit. After the address of each Descriptor is set to TPT 110 , the channel driver 113 writes the start address of TPT in the TPT base address register 303 in the channel control register 114 , and writes “1” in the TPT valid register 307 to notify that TPT is valid.
- the LPAR control program 101 intercepts a function which makes the channel driver 113 write a value in the TPT base address register 303 , and the virtual channel driver 102 writes a start address of VTPT 103 in the TPT base address register 303 of the channel control register 114 (if the value is already set, the same value is overwritten).
- the LPAR control program 101 also intercepts a function which makes the channel driver 113 write a value in the TPT valid register 307 , the virtual channel driver 102 copies the address corresponding to the address valid bit “1” in TPT 111 to VTPT 103 , and the LPAR control program 101 writes “1” in the TPT valid register.
- the channel driver 112 sets values of only Descriptors of QP 100 to QP 199 to TPT 110 and the channel driver 113 sets values of only Descriptors of QP 200 to QP 299 to TPT 111 . Therefore, each OS uses a different Descriptor and does not share the same Descriptor, and an offset from the top of each TPT is displaced.
- the virtual channel driver 102 generates VTPT 103 , the values of TPT 110 and TPT 111 can be easily copied without changing the offset from the TPT base address and only VTPT 103 is newly generated without copying transfer data and without changing other I/O control data such as Descriptor.
- OS 3 901 may run in LPAR# 3 to run the virtual channel driver 102 in OS 3 901 and generate VTPT 103 in an OS 3 control memory.
- the channel adaptor 100 fetches and holds VTPT to use the latest VTPT. Since the start address of VTPT 103 is set as the value of the TPT base address register 303 in the channel control register 114 , the channel adaptor 100 uses VTPT 103 .
- the channel driver 112 sets a physical address to DB_AD 501 of Send Queue of QP 100 , and sets the command area (256 bytes) to the area indicated by DB_AD 501 .
- the channel driver also defines another Descriptor 510 , sets the start address of Descriptor to Next Descriptor 502 , and sets the transmission data buffer 506 at the address indicated by DB_AD 507 of Descriptor 510 .
- the channel driver 112 sets # 1 as the related CQ# and the start address of CQ 1 to FLAG 509 , and writes a value in the TPT offset address register 304 in the channel control register 114 for I/O process activation by using a kernel function.
- the LPAR control program 101 intercepts the function, and the virtual channel driver 102 writes a value in the TPT offset address register 304 .
- the channel driver 112 sets QP# to the QP# register 302 in the channel control register 114 and sets “1” to the I/O process enable register 305 , by using the kernel function.
- the LPAR control program 101 intercepts the function, and the virtual channel driver 102 writes QP# in the QP# register 302 and “1” in the I/O process enable register 305 .
- the channel adaptor 100 When the channel adaptor 100 recognizes an I/O process activation from the virtual channel driver 102 , the channel adaptor 100 acquires the start address of Descriptor in accordance with an offset set to the TPT offset address register 304 in the channel control register 114 and in accordance with VTPT 103 . By using the start address, a fetch process for Descriptor is executed, in accordance with the fetched Descriptor information, the command area 504 and transmission data buffer 506 are fetched, and data is transferred to the target ID designated in the command area 504 and the partner QP# designated in FLAG 503 . Data transfer is executed in accordance with a protocol, and when a response frame is received from the partner, the response frame is stored in the command response information area 505 .
- the LPAR control program 101 intercepts the I/O interrupt, and the virtual channel driver 102 reads the value in the completion CQ register 308 in the channel control register to recognize completion of the process for CQ 1 and know that the process was for LPAR# 1 , and issues the intercepted I/O interrupt to OS 1 .
- the channel driver 112 of OS 1 recognizes the I/O interrupt, reads the contents of CQ 1 and executes a completion process for the I/O process.
- the channel driver 113 of OS 2 106 executes the I/O process by using QP 200 to QP 299 and CQ 2 .
- the outline of other I/O processes is similar to that executed by OS 1 105 .
- a designated QP# is contained in a received frame, and an I/O process is executed by using Receive Queue of the designated QP.
- a channel adaptor having a PCI bus interface can be shared by a plurality of OS's by acquiring the number of a virtual computer running a channel driver and generating only a table for translating a virtual address to a physical address, without using a hardware controller and local memory, without copying transfer data and without changing input/output control data.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Computer And Data Communications (AREA)
Abstract
Description
- This is a continuation of U.S. application Ser. No. 11/224,965, filed Sep. 14, 2005. This application relates to and claims priority from Japanese Patent Application No. 2004-269111, filed on Sep. 16, 2004. The entirety of the contents and subject matter of all of the above is incorporated herein by reference.
- The present invention relates to a data processing system for transferring data, and more particularly to a computer system which runs a plurality of operating systems (OS's) and executes processes of OS's at the same time by using a single channel adaptor.
- Only a main frame has supported heretofore an LPAR (Logical Partition) function of running a plurality of OS's in one system under a control program. Recently, not only a main frame but also an open source server supports the LPAR function. An input/output channel adaptor is inserted into a slot of an open source server supporting the LPAR function. As a business standard specification means for connecting the channel adaptor to a host processor, a PCI (Peripheral Component Interchange) bus stipulated by PCI-SIG (Special Interest Group) has been used widely. In the case of the PCI bus, a PCI configuration register is provided as a standard component for each device such as a channel adaptor. It is difficult to share the device by a plurality of OS's, because only one control register is provided for controlling the device, and other reasons.
- An example of a system supporting the LPAR function is disclosed in JP-A-2002-41306. Although a plurality of OS's can run on one system, a PCI I/O adaptor having a PCI bus as an interface cannot be shared by a plurality of OS's so that a PCI I/O adaptor is provided to each OS.
- Another example is disclosed in JP-A-2002-99437 which realizes an LPAR function in a main frame or the like. The outline of this example is shown in
FIG. 10 . Acontroller 1001 and alocal memory 1002 are mounted on aLAN package 1000 having aLAN adaptor 1003 as a PCI I/O device to share the LAN adaptor by a plurality of OS's. Thecontroller 1001 has adriver 1005 for the LAN adaptor. Thecontroller 1001 is connected to abus 1007 such as a PCI bus or a system specific bus, and to theLAN adaptor 1003 via a PCI bus 1004. - With reference to
FIG. 11 , the details of an operation of this system will be described. When thecontroller 1001 receives an input/output process activated from an OS1,transfer data 1105 of OS1 in a system memory is buffered in thelocal memory 1002, and input/outputprocess control data 1103 of OS1 is stored in thelocal memory 1002 as input/output process control data for the LAN adaptor. Similarly, control data and transfer data for an input/output process activated from OS2 are stored in thelocal memory 1002. TheLAN adaptor 1003 transfers data by accessing not the system memory but thelocal memory 1002. The control data is newly written in the local memory of the LAN package and the transfer data is buffered in the local memory so that the performance of the system is influenced and a development cost is required. - Although the LPAR function is supported recently by an open source server, there is a limit in the number of slots capable of being mounted. It is therefore desired to share one channel adaptor by a plurality of OS's.
- It is also desired to share a channel adaptor without using a hardware controller and local memory in order to reduce a cost.
- According to the above-described techniques, the open source server cannot realize that a plurality of OS's share a PCI I/O device having a PCI bus interface supported by the open source server, whereas although the main frame can realize that a plurality of OS's share a PCI I/O device, the local memory for a data buffer and input/output process control data and the controller for the data buffer and input/output process control data are mounted on the package. Use of the controller and local memory results in degraded performance and increased cost.
- It is an object of the present invention to share one channel adaptor by a plurality of OS's by using a standard specification bus such as PCI.
- It is another object of the present invention to share one channel adaptor, such as a device having a PCI bus interface, by a plurality of OS's without using a hardware controller and local memory.
- In a data processing system for executing an input/output process between each OS and a channel adaptor by using input/output process control data having an identifier, a channel driver as an interface between each OS and the channel adaptor for controlling the input/output process control data acquires from a control program a virtual computer number representative of an OS identifier of each OS operating the channel driver, the channel driver uses the virtual computer number and the input/output process control data having an identifier decided in system configuration information to be usable for the virtual computer number, and a plurality of OS's use input/output process control data having different identifiers for the channel adaptor to execute the input/output process without sharing the input/output process control data for the channel adaptor by different OS's.
- In an interface between the channel driver and the channel adaptor, an address indicating the input/output process control data is a virtual address and the input/output process is executed by using an address translation table for translating the virtual address to a physical address, the channel driver generates the address translation table of the usable input/output process control data by using the virtual computer number acquired from the control program and the identifier of the usable input/output process control data obtained from the configuration information, the data processing system includes means for generating a virtual address translation table from a plurality of address translation tables generated by the channel driver of each OS, and the channel adaptor processes the input/output process control data of a plurality of OS's by using the virtual address translation table to execute the input/output process for a plurality of OS's without changing the input/output process control data generated by each OS.
- According to the present invention, a channel adaptor can be provided which can execute an input/output (I/O) process requested from a plurality of OS's at the same time.
- Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.
-
FIG. 1 is a diagram showing the configuration of a data processing system according to an embodiment of the present invention. -
FIG. 2 is a diagram showing an example of the configuration of a data processing system. -
FIG. 3 is a diagram showing the contents of a channel control register in a channel adaptor. -
FIG. 4 is a diagram showing Queue Pair and Completion Queue as I/O process control data and an address translation table. -
FIG. 5 is a diagram showing Send Queues as I/O process control data used by the embodiment of the present invention. -
FIG. 6 is a diagram showing the configuration of a data processing system. -
FIG. 7 is a table showing a correspondence between LPAR numbers and usable QPs and CQs. -
FIG. 8 is a diagram showing TPTs generated by each OS and a virtual TPT. -
FIG. 9 is a diagram showing the configuration of a data processing system according to an embodiment of the invention. -
FIG. 10 is a diagram showing the outline of a conventional system. -
FIG. 11 is a diagram showing the details of the conventional system. - Sharing a PCI I/O device by a plurality of OS's is realized by software without using a controller and a local memory for controlling the PCI I/O device.
- Channel adaptors in conformity with business standard specifications supported by an open source server include Fibre Channel defined by ANSI (American National Standards Institute), InfiniBand defined by IBTA (InfiniBand Trade Association) and the like.
- In embodiments, a channel adaptor is assumed to use Que Pair constituted of Send Queue and Receive Queue, and Completion Queue used by InfiniBand or the like as input/output process control data for executing input/output process, a virtual address, and an address translation table (TPT) for translating a virtual address to a physical address.
- Description will be made first on the outline of an input/output process.
-
FIG. 2 shows an example of the configuration of a data processing system. A memoryaccess control chip 203 mainly controls an access to a main storage (MS) 200 fromprocessors channel adaptor 206. The memoryaccess control chip 203 is connected to thechannel adaptor 206 via a PCI bus. The memoryaccess control chip 203 is connected to theprocessors channel adaptor 206 has one port which is connected to an I/O device 208 via aswitch 207. This data processing system supporting an LPAR function allocates, for example, 2 MB ofMS 200 to each LPAR, and each OS in each LPAR runs by using a memory of 2 MB. - The
channel adaptor 206 of the data processing system using the PCI bus has a PCI configuration register as a standard component of a PCI bus connected device, and a channel control register for controlling the channel adaptor. The contents of the channel control resister are shown inFIG. 3 , the details thereof being described later. - Next, description will be made on an interface of software and hardware for an input/output process (I/O process).
- Each OS performs data transfer by using Queue Pair (QP) constituted of Send Queue and Receive Queue, and Completion Queue (CQ) for queuing an identifier of a processed QP. A channel driver in OS generates QP, controls CQ, and executes processes such as activating a data transfer process for the channel adaptor.
FIG. 4 shows the outline of QP and CQ. Send Queue and Receive Queue are each constituted of Descriptor and a data buffer, Descriptor containing an address of the data buffer. Before data is transmitted, a physical address of adata buffer 403 storing transmission data of Send Queue is set toDescriptor 401. Before data is received, a physical address of adata buffer 405 storing reception data of Receive Queue is set toDescriptor 404. Each Queue Pair has an identifier. In the example shown inFIG. 4 , Queue Pair has an identifier of #100 (QP100). The channel adaptor can execute processes of a plurality of QPs at the same time. - The physical address indicating each Descriptor is stored in an address translation table (TPT) 406. TPT is one physically continuous area and stores Send Queue Descriptor addresses and Receive Queue Descriptor addresses of all QPs to be used by the channel adaptor. Each of the Send Queue Descriptor address and Receive Queue Descriptor address has 16 bytes. The value “1” of the most significant bit indicates that the Descriptor address is valid, and the lower 8 bytes indicate the physical address of Descriptor.
- Each CQ has an identifier of QP processed by the channel adaptor, the identifier containing information on which of Send Queue and Receive Queue was processed. Each entry of CQ has 16 bytes. If the most significant bit of upper 8 bytes is “1”, it means that the entry is valid. The upper 4 bytes of lower 8 bytes are an identifier of processed QP. If the most significant bit of lower 4 bytes of the lower 8 bytes is “1”, it means that Send Queue was processed, whereas if the most significant bit is “0”, it means that Receive Queue was processed.
- The value of a TPT base address register 303 defined in the channel control register 300 shown in
FIG. 3 indicates a start address (physical address) of the address translation table (TPT) 406, this address being set by the channel driver. The channel adaptor accesses the address translation table (TPT) 406 by using the value in the TPTbase address register 303. -
FIG. 5 shows the detailed data structure of Send Queue. InFIG. 5 , DB-AD 601 is made of an 8-byte area indicating the start address (physical address) of a data buffer address area.FLAG 503 includes information on whether an I/O process is normally completed or erroneously completed, error information indicating a type of an occurred error, information on whether there is Descriptor to be next processed (presence/absence of Next Descriptor), a QP number of a data transfer partner, a related Q identifier (CQ#) and a physical address of CQ. If there is Descriptor to be next processed, a start address (physical address) of the next Descriptor is set toNext Descriptor 502 of an 8-byte length. In this embodiment, it is assumed that DB-AD of thefirst Descriptor 500 indicates a command area, and DB-ADs of the second andsubsequent Descriptors 510 indicate data buffers 506.FIG. 5 shows the format of Send Queue. The format of Receive Queue is the same as that of Send Queue and reception data is stored in an area indicated by DB-AD. - An activation method for an I/O process is assumed: that the channel driver sets an identifier (QP#) of QP to be processed to a
QP# register 302 defined in thechannel control register 300, and sets information on which one of Send Queue and Receive Queue to a Send/Receiveregister 306; that an area where QP Descriptor address as a virtual address is stored is set to a TPT offsetaddress register 304; and that the channel adaptor is instructed to activate an I/O process by setting an offset address from the TPT base address and writing “1” in an I/O process enableregister 305. - Before an I/O process is executed, the channel driver sets a physical address to DB-
AD 501 and sets a command area (256 bytes) 504 to the area indicated by DB-AD. The command area contains, in addition to a command, information on a target ID indicating a partner port for the I/O process, a LUN indicating a device under the port and the like. A 256-byte area following the command area of 256 bytes is used as a commandresponse information area 505 for storing a response frame to the command. - Next, information of
FLAG 503 is set. A partner QP# and CQ1 as CQ# related to Descriptor are set, and the start address (physical address) of CQ1 is set. - Another
Descriptor 510 is defined, and the start address ofDescriptor 510 is set toNext Descriptor 502. Thetransmission data buffer 506 is at the address ofDB_AD 507 ofDescriptor 510. If the data buffer is made to have a variable length, information on the data length is stored inFLAG 509. In this embodiment, for the simplicity of description, the data buffer is made to have a fixed length of 4 K bytes and the data length is not set. As described above, the channel driver generates Send Queue and activates an I/O process. Although the partner QP number, related CQ# and physical address of CQ# are defined in FLAG of each Descriptor, it is assumed that the values in FLAG in the top Descriptor are valid. - When the channel adaptor recognizes an I/O process activation from the channel driver, it acquires the start address (physical address) of Descriptor in accordance with an offset (virtual address) set to the TPT offset
address register 304 in the channel control register and an address translation table (TPT) 406. By using the physical address, a fetch process for Descriptor is executed, and in accordance with fetched Descriptor information, thecommand area 504 andtransmission data buffer 506 are fetched. Data is transferred to a target ID designated in thecommand area 504 and the partner QP# designated inFLAG 503. When a response frame indicating a process completion is received from the partner, the response frame is stored in the commandresponse information area 505. After the response frame is stored, in accordance with the information inFLAG 503, an identifier of processed QP, information on Send Queue, a valid bit of the entry are set to Completion Queue #1 (CQ1) 407, CQ# “1” is set to acompletion CQ register 308 in the channel control register, and an I/O interrupt representative of completion of an I/O process is issued to OS. When an error occurs, error information is set to FLAG 503. The channel driver of OS recognizes the I/O interrupt, reads thecompletion CQ register 308 and executes a completion process of the I/O process activated to the channel adaptor in accordance with the contents of CQ1. The outline of the I/O process has been described above. -
FIG. 6 illustrates the relation between software and the channel adaptor in which the I/O process is executed by using 1000 QPs from QP000 to QP999 604 and 100 CQs from CQ00 toCQ99 607. Next, an embodiment of the present invention will be described. -
FIG. 1 shows the embodiment characteristic to the present invention. In this embodiment, two OS's share one channel adaptor. - In the data processing system shown in
FIG. 1 , under the control of aLPAR control program 101, two LPARs,LPAR# 1 andLPAR# 2, start up,OS1 105 runs inLPAR# 1 andOS2 106 runs inLPAR# 2. - It is assumed that each channel driver has a function which acquires LPAR# in which the channel driver runs. In this embodiment, acquired information is that a
channel driver 112 runs inLPAR# 1 and achannel driver 113 runs inLPAR# 2. Avirtual channel driver 102 is a driver which actually controls achannel adaptor 100. When thechannel drivers channel adaptor 100 or perform other operations, theLPAR control program 101 intercepts the access function, and thevirtual driver 102 accesses thechannel control register 114. - In the data processing system, as shown in
FIG. 7 , the identifiers and numbers of Queue Pairs (QPs) and Completion Queues (CQs) capable of being used by each OS are defined as a portion of configuration information. The channel adaptor has been described above as being capable of processing 1000 QPs from QP000 to QP999 and 100 CQs from CQ00 to CQ99. These resources are distributed to each OS, and the configuration information is defined in such a manner that QPs or CQs having the same identifier are not shared by different OS's. In the example ofFIG. 7 ,LPAR# 1 can use 100 QPs from QP100, i.e., QP100 to QP199 and can use only one CQ1. Similarly,LPAR# 2 can use 100 QPs from QP200, i.e., QP200 to QP299 and can use only one CQ2. - The channel driver acquires information on usable QP# and CQ# from the configuration information in LPAR# in which the channel driver runs, by using a kernel function or the like. Similarly, the LPAR control program acquires information on LPAR#, QP# and CQ# used by each LPAR from the configuration information by using the kernel function or the like.
- The
channel driver 112 controls QP100 to QP199, sets only Descriptor addresses of Send Queues and Receive Queues of QP100 to QP199 toTPT 110, and sets “1” to the address valid bit of the most significant bit. After the address of each Descriptor is set toTPT 110, thechannel driver 112 writes the start address ofTPT 110 in the TPTbase address register 303 in thechannel control register 114, and writes “1” in the TPTvalid register 307 to notify that TPT is valid. - The
LPAR control program 101 intercepts a function which makes thechannel driver 112 write a value in the TPTbase address register 303, and thevirtual channel driver 102 writes a start address of a virtual address translation table (VTPT) 103 different fromTPT 110 in the TPT base address register 303 of thechannel control register 114. The LPAR control program also intercepts a function which makes thechannel driver 112 write a value in the TPTvalid register 307, thevirtual channel driver 102 copies the address corresponding to the address valid bit “1” inTPT 110 toVTPT 103, and theLPAR control program 101 writes “1” in the TPTvalid register 307. - Similarly, the
channel driver 113 controls QP200 to QP299, sets only Descriptor addresses of Send Queues and Receive Queues of QP200 to QP299 toTPT 111, and sets “1” to the address valid bit of the most significant bit. After the address of each Descriptor is set toTPT 110, thechannel driver 113 writes the start address of TPT in the TPTbase address register 303 in thechannel control register 114, and writes “1” in the TPTvalid register 307 to notify that TPT is valid. Similar to the above description, theLPAR control program 101 intercepts a function which makes thechannel driver 113 write a value in the TPTbase address register 303, and thevirtual channel driver 102 writes a start address ofVTPT 103 in the TPT base address register 303 of the channel control register 114 (if the value is already set, the same value is overwritten). TheLPAR control program 101 also intercepts a function which makes thechannel driver 113 write a value in the TPTvalid register 307, thevirtual channel driver 102 copies the address corresponding to the address valid bit “1” inTPT 111 toVTPT 103, and theLPAR control program 101 writes “1” in the TPT valid register. - As shown in
FIG. 8 , thechannel driver 112 sets values of only Descriptors of QP100 to QP199 toTPT 110 and thechannel driver 113 sets values of only Descriptors of QP200 to QP299 toTPT 111. Therefore, each OS uses a different Descriptor and does not share the same Descriptor, and an offset from the top of each TPT is displaced. When thevirtual channel driver 102 generatesVTPT 103, the values ofTPT 110 andTPT 111 can be easily copied without changing the offset from the TPT base address and onlyVTPT 103 is newly generated without copying transfer data and without changing other I/O control data such as Descriptor. - In this embodiment, although the
virtual channel driver 102 exists in theLPAR control program 101, as shown inFIG. 9 ,OS3 901 may run inLPAR# 3 to run thevirtual channel driver 102 inOS3 901 and generateVTPT 103 in an OS3 control memory. - When “1” is set to the TPT valid register, the
channel adaptor 100 fetches and holds VTPT to use the latest VTPT. Since the start address ofVTPT 103 is set as the value of the TPTbase address register 303 in thechannel control register 114, thechannel adaptor 100 usesVTPT 103. - Next, description will be made on a data transmission process to be executed by the
channel driver 112 ofOS1 105 by using QP100 and CQ1 shown inFIGS. 4 and 5 . Thechannel driver 112 sets a physical address to DB_AD 501 of Send Queue of QP100, and sets the command area (256 bytes) to the area indicated byDB_AD 501. The channel driver also defines anotherDescriptor 510, sets the start address of Descriptor toNext Descriptor 502, and sets thetransmission data buffer 506 at the address indicated byDB_AD 507 ofDescriptor 510. Thechannel driver 112 sets #1 as the related CQ# and the start address of CQ1 to FLAG 509, and writes a value in the TPT offsetaddress register 304 in the channel control register 114 for I/O process activation by using a kernel function. In this case, theLPAR control program 101 intercepts the function, and thevirtual channel driver 102 writes a value in the TPT offsetaddress register 304. Next, thechannel driver 112 sets QP# to theQP# register 302 in thechannel control register 114 and sets “1” to the I/O process enableregister 305, by using the kernel function. In this case, theLPAR control program 101 intercepts the function, and thevirtual channel driver 102 writes QP# in theQP# register 302 and “1” in the I/O process enableregister 305. - When the
channel adaptor 100 recognizes an I/O process activation from thevirtual channel driver 102, thechannel adaptor 100 acquires the start address of Descriptor in accordance with an offset set to the TPT offsetaddress register 304 in thechannel control register 114 and in accordance withVTPT 103. By using the start address, a fetch process for Descriptor is executed, in accordance with the fetched Descriptor information, thecommand area 504 andtransmission data buffer 506 are fetched, and data is transferred to the target ID designated in thecommand area 504 and the partner QP# designated inFLAG 503. Data transfer is executed in accordance with a protocol, and when a response frame is received from the partner, the response frame is stored in the commandresponse information area 505. After the response frame is stored, information representative of QP100 and Send Queue is set to CQ1, and CP# “1” is set to thecompletion CQ register 308 in thechannel control register 114. Thereafter, an I/O interrupt indicating an I/O process completion is issued to OS. - The
LPAR control program 101 intercepts the I/O interrupt, and thevirtual channel driver 102 reads the value in thecompletion CQ register 308 in the channel control register to recognize completion of the process for CQ1 and know that the process was forLPAR# 1, and issues the intercepted I/O interrupt to OS1. Thechannel driver 112 of OS1 recognizes the I/O interrupt, reads the contents of CQ1 and executes a completion process for the I/O process. - The
channel driver 113 ofOS2 106 executes the I/O process by using QP200 to QP299 and CQ2. The outline of other I/O processes is similar to that executed byOS1 105. - Data transmission has been described in this embodiment. For data reception, a designated QP# is contained in a received frame, and an I/O process is executed by using Receive Queue of the designated QP.
- The embodiment of the present invention has been described above. A channel adaptor having a PCI bus interface can be shared by a plurality of OS's by acquiring the number of a virtual computer running a channel driver and generating only a table for translating a virtual address to a physical address, without using a hardware controller and local memory, without copying transfer data and without changing input/output control data.
- It should be further understood by those skilled in the art that although the foregoing description has been made on embodiments of the invention, the invention is not limited thereto and various changes and modifications may be made without departing from the spirit of the invention and the scope of the appended claims.
Claims (1)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/721,964 US7877526B2 (en) | 2004-09-16 | 2010-03-11 | Data processing system having a channel adapter shared by multiple operating systems |
US13/008,195 US8312182B2 (en) | 2004-09-16 | 2011-01-18 | Data processing system having a channel adapter shared by multiple operating systems |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004269111A JP4788124B2 (en) | 2004-09-16 | 2004-09-16 | Data processing system |
JP2004-269111 | 2004-09-16 | ||
US11/224,965 US7680965B2 (en) | 2004-09-16 | 2005-09-14 | Data processing system having a channel adapter shared by multiple operating systems |
US12/721,964 US7877526B2 (en) | 2004-09-16 | 2010-03-11 | Data processing system having a channel adapter shared by multiple operating systems |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/224,965 Continuation US7680965B2 (en) | 2004-09-16 | 2005-09-14 | Data processing system having a channel adapter shared by multiple operating systems |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/008,195 Continuation US8312182B2 (en) | 2004-09-16 | 2011-01-18 | Data processing system having a channel adapter shared by multiple operating systems |
Publications (2)
Publication Number | Publication Date |
---|---|
US20100235548A1 true US20100235548A1 (en) | 2010-09-16 |
US7877526B2 US7877526B2 (en) | 2011-01-25 |
Family
ID=36035447
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/224,965 Expired - Fee Related US7680965B2 (en) | 2004-09-16 | 2005-09-14 | Data processing system having a channel adapter shared by multiple operating systems |
US12/721,964 Expired - Fee Related US7877526B2 (en) | 2004-09-16 | 2010-03-11 | Data processing system having a channel adapter shared by multiple operating systems |
US13/008,195 Active US8312182B2 (en) | 2004-09-16 | 2011-01-18 | Data processing system having a channel adapter shared by multiple operating systems |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/224,965 Expired - Fee Related US7680965B2 (en) | 2004-09-16 | 2005-09-14 | Data processing system having a channel adapter shared by multiple operating systems |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/008,195 Active US8312182B2 (en) | 2004-09-16 | 2011-01-18 | Data processing system having a channel adapter shared by multiple operating systems |
Country Status (3)
Country | Link |
---|---|
US (3) | US7680965B2 (en) |
JP (1) | JP4788124B2 (en) |
CN (2) | CN101308466B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016206012A1 (en) * | 2015-06-24 | 2016-12-29 | Intel Corporation | Systems and methods for isolating input/output computing resources |
CN107153527A (en) * | 2017-05-17 | 2017-09-12 | 北京环境特性研究所 | A kind of parallel radar data processing method based on message queue |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8769168B2 (en) | 2006-10-17 | 2014-07-01 | International Business Machines Corporation | Method for communicating with a network adapter using a queue data structure and cached address translations |
US7590817B2 (en) * | 2006-10-17 | 2009-09-15 | International Business Machines Corporation | Communicating with an I/O device using a queue data structure and pre-translated addresses |
US7506084B2 (en) * | 2006-10-17 | 2009-03-17 | International Business Machines Corporation | Method for communicating with an I/O adapter using cached address translations |
JP2008158710A (en) * | 2006-12-22 | 2008-07-10 | Hitachi Ltd | Computer system |
US7913077B2 (en) * | 2007-02-13 | 2011-03-22 | International Business Machines Corporation | Preventing IP spoofing and facilitating parsing of private data areas in system area network connection requests |
JP5477707B2 (en) | 2007-08-23 | 2014-04-23 | 日本電気株式会社 | I / O system and I / O control method |
JP2009294758A (en) * | 2008-06-03 | 2009-12-17 | Hitachi Ltd | Virtual computer system and driver program for host bus adapter |
US9342352B2 (en) | 2010-06-23 | 2016-05-17 | International Business Machines Corporation | Guest access to address spaces of adapter |
US8635430B2 (en) | 2010-06-23 | 2014-01-21 | International Business Machines Corporation | Translation of input/output addresses to memory addresses |
US8615645B2 (en) | 2010-06-23 | 2013-12-24 | International Business Machines Corporation | Controlling the selectively setting of operational parameters for an adapter |
US9213661B2 (en) * | 2010-06-23 | 2015-12-15 | International Business Machines Corporation | Enable/disable adapters of a computing environment |
US9195623B2 (en) | 2010-06-23 | 2015-11-24 | International Business Machines Corporation | Multiple address spaces per adapter with address translation |
CN103064734B (en) * | 2011-10-24 | 2016-08-17 | 联想(北京)有限公司 | Terminal unit and multisystem input changing method |
US9122515B2 (en) * | 2012-12-19 | 2015-09-01 | Dell Products L.P. | Completion notification for a storage device |
US9323715B2 (en) * | 2013-11-14 | 2016-04-26 | Cavium, Inc. | Method and apparatus to represent a processor context with fewer bits |
FR3032537B1 (en) * | 2015-02-09 | 2018-03-16 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR EXECUTING A DATA EXCHANGE REQUEST BETWEEN FIRST AND SECOND PHYSICAL ADDRESSING SPACES DISCHARGED FROM CIRCUITS ON CARD OR CHIP |
US10310974B2 (en) | 2015-09-25 | 2019-06-04 | Intel Corporation | Systems and methods for input/output computing resource control |
WO2017209876A1 (en) | 2016-05-31 | 2017-12-07 | Brocade Communications Systems, Inc. | Buffer manager |
US20180088978A1 (en) * | 2016-09-29 | 2018-03-29 | Intel Corporation | Techniques for Input/Output Access to Memory or Storage by a Virtual Machine or Container |
JP6615302B1 (en) * | 2018-11-06 | 2019-12-04 | 三菱電機株式会社 | Electronic control unit |
CN112631969B (en) * | 2020-12-30 | 2024-01-30 | 凌云光技术股份有限公司 | Virtual multichannel data transmission method and system based on PCIE interface |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5414851A (en) * | 1992-06-15 | 1995-05-09 | International Business Machines Corporation | Method and means for sharing I/O resources by a plurality of operating systems |
US6125411A (en) * | 1995-09-13 | 2000-09-26 | Hitachi, Ltd. | System storing plural I/O arrangement information wherein each I/O arrangement information corresponding to each operating system is created in response to more than two operating systems |
US20030154337A1 (en) * | 2000-06-01 | 2003-08-14 | Hiroshi Ohno | Multiple operating system control method |
US6615303B1 (en) * | 1999-05-21 | 2003-09-02 | Hitachi, Ltd. | Computer system with multiple operating system operation |
US6658521B1 (en) * | 2000-12-22 | 2003-12-02 | International Business Machines Corporation | Method and apparatus for address translation on PCI bus over infiniband network |
US6745259B2 (en) * | 1995-06-22 | 2004-06-01 | Datascape, Inc. | Open network system for i/o operation including a common gateway interface and an extended open network protocol with non-standard i/o devices utilizing device and identifier for operation to be performed with device |
US6877158B1 (en) * | 2000-06-08 | 2005-04-05 | International Business Machines Corporation | Logical partitioning via hypervisor mediated address translation |
US6996828B1 (en) * | 1997-09-12 | 2006-02-07 | Hitachi, Ltd. | Multi-OS configuration method |
US7272671B2 (en) * | 2000-11-16 | 2007-09-18 | International Business Machines Corporation | Means of control bits protection in a logical partition environment having a first and second distinct operating system |
US20080168193A1 (en) * | 2007-01-10 | 2008-07-10 | International Business Machines Corporation | Use of unique identifiers for each data format supported by a multi-format data store |
US7493409B2 (en) * | 2003-04-10 | 2009-02-17 | International Business Machines Corporation | Apparatus, system and method for implementing a generalized queue pair in a system area network |
US7617340B2 (en) * | 2007-01-09 | 2009-11-10 | International Business Machines Corporation | I/O adapter LPAR isolation with assigned memory space |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0619747B2 (en) * | 1984-01-18 | 1994-03-16 | 株式会社日立製作所 | I / O instruction execution method, I / O interrupt processing method, and computer system using them |
JP2886973B2 (en) * | 1990-04-09 | 1999-04-26 | オリンパス光学工業株式会社 | Ultrasonic diagnostic device in body cavity |
US5412782A (en) * | 1992-07-02 | 1995-05-02 | 3Com Corporation | Programmed I/O ethernet adapter with early interrupts for accelerating data transfer |
JP3490212B2 (en) * | 1996-04-08 | 2004-01-26 | 株式会社日立製作所 | Input / output channel expansion method for information processing device |
WO2001093032A1 (en) * | 2000-05-31 | 2001-12-06 | Hitachi, Ltd. | Computer system, method of controlling computer, and medium storing control program |
WO2001095098A2 (en) * | 2000-06-02 | 2001-12-13 | Inrange Technologies Corporation | Enhanced channel adapter |
US6990663B1 (en) | 2000-06-08 | 2006-01-24 | International Business Machines Corporation | Hypervisor virtualization of OS console and operator panel |
US7272571B2 (en) * | 2000-07-07 | 2007-09-18 | Mars Incorporated | Method and apparatus for effective distribution and delivery of goods ordered on the World-Wide-Web |
JP4205843B2 (en) | 2000-09-22 | 2009-01-07 | 株式会社日立製作所 | Control method of network connection device |
DE60142152D1 (en) * | 2000-12-15 | 2010-07-01 | Ibm | Virtualization of I / O adapter resources |
US7593413B2 (en) * | 2002-12-20 | 2009-09-22 | International Business Machines Corporation | Secure system and method for SAN management in a non-trusted server environment |
US7174550B2 (en) * | 2003-05-12 | 2007-02-06 | International Business Machines Corporation | Sharing communications adapters across a plurality of input/output subsystem images |
US7979548B2 (en) * | 2003-09-30 | 2011-07-12 | International Business Machines Corporation | Hardware enforcement of logical partitioning of a channel adapter's resources in a system area network |
US7506343B2 (en) * | 2004-08-19 | 2009-03-17 | International Business Machines Corporation | System and method for passing information from one device driver to another |
-
2004
- 2004-09-16 JP JP2004269111A patent/JP4788124B2/en not_active Expired - Fee Related
-
2005
- 2005-09-14 US US11/224,965 patent/US7680965B2/en not_active Expired - Fee Related
- 2005-09-15 CN CN2008100925384A patent/CN101308466B/en active Active
- 2005-09-15 CN CNB200510103403XA patent/CN100405303C/en active Active
-
2010
- 2010-03-11 US US12/721,964 patent/US7877526B2/en not_active Expired - Fee Related
-
2011
- 2011-01-18 US US13/008,195 patent/US8312182B2/en active Active
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5414851A (en) * | 1992-06-15 | 1995-05-09 | International Business Machines Corporation | Method and means for sharing I/O resources by a plurality of operating systems |
US6745259B2 (en) * | 1995-06-22 | 2004-06-01 | Datascape, Inc. | Open network system for i/o operation including a common gateway interface and an extended open network protocol with non-standard i/o devices utilizing device and identifier for operation to be performed with device |
US6125411A (en) * | 1995-09-13 | 2000-09-26 | Hitachi, Ltd. | System storing plural I/O arrangement information wherein each I/O arrangement information corresponding to each operating system is created in response to more than two operating systems |
US6996828B1 (en) * | 1997-09-12 | 2006-02-07 | Hitachi, Ltd. | Multi-OS configuration method |
US6615303B1 (en) * | 1999-05-21 | 2003-09-02 | Hitachi, Ltd. | Computer system with multiple operating system operation |
US20030154337A1 (en) * | 2000-06-01 | 2003-08-14 | Hiroshi Ohno | Multiple operating system control method |
US6877158B1 (en) * | 2000-06-08 | 2005-04-05 | International Business Machines Corporation | Logical partitioning via hypervisor mediated address translation |
US7272671B2 (en) * | 2000-11-16 | 2007-09-18 | International Business Machines Corporation | Means of control bits protection in a logical partition environment having a first and second distinct operating system |
US6658521B1 (en) * | 2000-12-22 | 2003-12-02 | International Business Machines Corporation | Method and apparatus for address translation on PCI bus over infiniband network |
US7493409B2 (en) * | 2003-04-10 | 2009-02-17 | International Business Machines Corporation | Apparatus, system and method for implementing a generalized queue pair in a system area network |
US7617340B2 (en) * | 2007-01-09 | 2009-11-10 | International Business Machines Corporation | I/O adapter LPAR isolation with assigned memory space |
US20080168193A1 (en) * | 2007-01-10 | 2008-07-10 | International Business Machines Corporation | Use of unique identifiers for each data format supported by a multi-format data store |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016206012A1 (en) * | 2015-06-24 | 2016-12-29 | Intel Corporation | Systems and methods for isolating input/output computing resources |
US10853277B2 (en) | 2015-06-24 | 2020-12-01 | Intel Corporation | Systems and methods for isolating input/output computing resources |
CN107153527A (en) * | 2017-05-17 | 2017-09-12 | 北京环境特性研究所 | A kind of parallel radar data processing method based on message queue |
Also Published As
Publication number | Publication date |
---|---|
US20110138089A1 (en) | 2011-06-09 |
US20060059328A1 (en) | 2006-03-16 |
CN101308466A (en) | 2008-11-19 |
US7680965B2 (en) | 2010-03-16 |
CN100405303C (en) | 2008-07-23 |
CN101308466B (en) | 2011-07-06 |
JP2006085400A (en) | 2006-03-30 |
US8312182B2 (en) | 2012-11-13 |
US7877526B2 (en) | 2011-01-25 |
CN1749967A (en) | 2006-03-22 |
JP4788124B2 (en) | 2011-10-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7877526B2 (en) | Data processing system having a channel adapter shared by multiple operating systems | |
US20200278880A1 (en) | Method, apparatus, and system for accessing storage device | |
US10152433B2 (en) | Inline PCI-IOV adapter | |
US8850098B2 (en) | Direct memory access (DMA) address translation between peer input/output (I/O) devices | |
US7890669B2 (en) | Computer system for sharing I/O device | |
US9727503B2 (en) | Storage system and server | |
US8645663B2 (en) | Network interface controller with flexible memory handling | |
US11757796B2 (en) | Zero-copy processing | |
JP3403284B2 (en) | Information processing system and control method thereof | |
US8607214B2 (en) | Data processing system running on a plurality of operating systems (OS) and enabling a channel device to simultaneously perform processing associated with the plurality of operating systems | |
US6779062B1 (en) | Streamlining ATA device initialization | |
US6324595B1 (en) | Dedication of space in descriptor for minimizing data processing during communications between a peripheral device and a host system | |
US20220335109A1 (en) | On-demand paging support for confidential computing | |
JP4894963B2 (en) | Data processing system | |
US7917659B2 (en) | Variable length command pull with contiguous sequential layout | |
US20230350824A1 (en) | Peripheral component interconnect express device and operating method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20190125 |