Nothing Special   »   [go: up one dir, main page]

US20100128802A1 - Video processing ciucuit and related method for merging video output streams with graphical stream for transmission - Google Patents

Video processing ciucuit and related method for merging video output streams with graphical stream for transmission Download PDF

Info

Publication number
US20100128802A1
US20100128802A1 US12/276,422 US27642208A US2010128802A1 US 20100128802 A1 US20100128802 A1 US 20100128802A1 US 27642208 A US27642208 A US 27642208A US 2010128802 A1 US2010128802 A1 US 2010128802A1
Authority
US
United States
Prior art keywords
video
stream
video output
output stream
graphical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/276,422
Inventor
Yang-Hung Shih
Hung-Der Lin
Tang-Hung Po
Sau-Kwo Chiu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US12/276,422 priority Critical patent/US20100128802A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIU, SAU-KWO, LIN, HUNG-DER, PO, TANG-HUNG, SHIH, YANG-HUNG
Priority to TW98127839A priority patent/TWI380682B/en
Priority to CN2009101714258A priority patent/CN101742167B/en
Publication of US20100128802A1 publication Critical patent/US20100128802A1/en
Priority to US13/907,983 priority patent/US9137458B2/en
Priority to US14/807,900 priority patent/US9509921B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/265—Mixing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/44016—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving splicing one content stream with another content stream, e.g. for substituting a video clip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
    • H04N7/0806—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division the signals being two or more video signals

Definitions

  • the present disclosure relates to a video processing circuit and related method thereof, and more particularly, to a processing circuit and related method for merging video output streams with a graphical stream for transmission.
  • FIG. 1 is a diagram of a first conventional video processing circuit 100 .
  • the video processing circuit 100 includes a video processing chip 110 and a video output device 130 , whereof the video processing chip 110 includes a video generating unit 112 , an OSD encoder 114 , a mixer 116 , and a first signal transmitter 118 .
  • the generating unit 112 is utilized for generating a video output stream S OUT according to a video input stream S IN .
  • the OSD encoder 114 is utilized for generating an encoded auxiliary graphic data D 1 .
  • the mixer 116 is coupled to the video generating unit 112 and the OSD encoder 114 for mixing the video output stream S OUT with the graphic data D 1 to generate a single mixed data D MIX , and then the first signal transmitter 118 transmits the mixed data D MIX to the video output device 130 through a low voltage differential signal (LVDS) interface.
  • the video processing chip 110 is a TV chip installed in a digital TV, and the video output device can be a recorder or a flat panel display (FPD), such as a plasma panel.
  • FPD flat panel display
  • FIG. 2 is a diagram of a second conventional video processing circuit 200 .
  • elements with the same reference numerals as that in FIG. 1 refer to the same elements, and further detailed description is omitted herein for brevity.
  • the difference between the video processing circuit 200 and the video processing circuit 100 is that the video processing circuit 200 further includes a video post-processing chip 220 coupled between the video processing chip 110 and the video output device 130 .
  • the video post-processing chip 22 includes a first signal receiver 222 , a video post-processing unit 224 , and a second signal transmitter 226 .
  • the first signal receiver 222 is coupled to the first signal transmitter 118 for receiving the mixed data D MIX
  • the video post-processing unit 224 is coupled to the first signal receiver 222 for receiving and post-processing the mixed data D MIX to generate a processed mixed data D PMIX
  • the second signal transmitter 226 transmits the processed mixed data D PMIX to the video output device 130 through a low voltage differential signal (LVDS) interface.
  • LVDS low voltage differential signal
  • both the video output stream S OUT and the graphic data D 1 are post-processed by the video post-processing unit 224 by the same scheme for enhancing the video quality thereof.
  • the quality around edges of the graphic data D 1 area may be poor as the video enhancement is applied to the mixed data D MIX including contents of the graphic data D 1 which replace an overlapped portion within the contents originally carried by the video output stream S OUT and are far different from remaining contents corresponding to the video output stream S OUT .
  • FIG. 3 is a diagram of a third conventional video processing circuit 300 .
  • the video processing circuit 300 includes a video processing chip 310 , a video post-processing chip 320 , and the video output device 130 .
  • the differences between the video processing circuit 300 in FIG. 3 and the video processing circuit 200 in FIG. 2 are described in the following.
  • the video output stream S OUT and the graphic data D 1 are not mixed and are respectively transmitted to the first signal transmitter 118 .
  • the video output stream S OUT is post-processed by the video post-processing unit 224 to generate a processed video output stream S POUT for enhancing the video quality.
  • the graphic data D 1 is directly transmitted to a mixer 318 without being post-processed by the video post-processing unit 224 .
  • the processed video output stream S POUT and the graphic data D 1 are mixed by the mixer 318 to generate a second mixed signal D PMIX2 .
  • the quality around edges of the graphic data D 1 area can be improved but extra I/O pins are needed to transmit the graphic data D 1 to the first signal receiver 222 .
  • main video data e.g., display data
  • auxiliary video data e.g., OSD data
  • a video processing circuit includes a video generating unit, a graphic generating unit, and a communication interface circuit.
  • the video generating unit generates a video output stream according to a video input stream.
  • the graphic generating unit provides a graphical stream.
  • the communication interface circuit is coupled to the video generating unit and the graphic generating unit.
  • the communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel, wherein the mixed video output stream is generated by combining contents of the video output stream and the graphical stream and the first merged signal is generated by putting the video output stream and the graphical stream in the channel.
  • the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase a bandwidth of the channel, by using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and by compressing the video output stream.
  • the video processing circuit further includes a first signal receiver, a video post-processing unit, a decoding unit, a mixer, and a second signal transmitter.
  • the first signal receiver is coupled to the communication interface circuit for receiving the first merged signal and extracting the video output stream and the graphical stream from the first merged signal.
  • the a video post-processing unit is coupled to the first signal receiver for receiving and post-processing the video output stream extracted from the first merged signal to generate a processed video output stream.
  • the decoding unit is coupled to the first signal receiver for decoding the graphical stream to generate a decoded graphical stream.
  • the mixer is coupled to the video post-processing unit and the decoding unit for mixing the processed video output stream with the decoded graphical stream to generate a second merged signal.
  • the second signal transmitter is coupled to the mixer for outputting the second merged signal.
  • the video generating unit, the graphic generating unit, and the communication interface circuit are disposed in a video processing chip; and the first signal receiver, the video post-processing unit, the decoding unit mixer, and the second signal transmitter are disposed in a post-processing chip coupled to the video processing chip.
  • the graphic generating unit is an on-screen display (OSD) encoder for generating the graphical stream.
  • OSD on-screen display
  • the graphic generating unit is an external storage device of the video processing chip for storing and providing the graphical stream.
  • the communication interface circuit is a low voltage differential signal (LVDS) interface circuit.
  • LVDS low voltage differential signal
  • the graphical stream comprises an on-screen display (OSD) data.
  • OSD on-screen display
  • a method for merging video output streams with a graphical stream for transmission includes generating a video output stream according to a video input stream, providing a graphical stream, and providing a first mode for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and providing a second mode for merging the video output stream and the graphical stream to transmit a first merged signal to a post-processing chip through the channel, wherein the mixed video output stream is generated by combining contents of the video output stream and the graphical stream and the first merged signal is generated by putting the video output stream and the graphical stream in the channel.
  • the method further includes receiving the first merged signal and extracting the video output stream and the graphical stream from the first merged signal, receiving and post-processing the video output stream extracted from the first merged signal to generate a processed video output stream, decoding the graphical stream to generate a decoded graphical stream, mixing the processed video output stream with the decoded graphical stream to generate a second merged signal, and outputting the second merged signal.
  • the first merged signal is a low voltage differential signal (LVDS).
  • LVDS low voltage differential signal
  • the video output stream and the graphical stream are merged by increasing a working frequency of the communication interface circuit to increase a bandwidth of the channel, by using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and by compressing the video output stream.
  • FIG. 1 is a diagram of a first conventional video processing circuit.
  • FIG. 2 is a diagram of a second conventional video processing circuit.
  • FIG. 3 is a diagram of a third conventional video processing circuit.
  • FIG. 4 is a diagram of a video processing circuit according to a first embodiment of the present disclosure.
  • FIG. 5 is a diagram of a video processing circuit according to a second embodiment of the present disclosure.
  • FIG. 6 is a diagram of a video processing circuit according to a third embodiment of the present disclosure.
  • FIG. 7 is a diagram showing a conventional LVDS signal encoding.
  • FIG. 8 is a diagram showing a first exemplary embodiment of a novel LVDS signal encoding according to the present disclosure.
  • FIG. 9 is a diagram showing a second exemplary embodiment of the novel LVDS signal encoding according to the present disclosure.
  • FIG. 10 is a diagram showing a third exemplary embodiment of the novel LVDS signal encoding according to the present disclosure.
  • FIG. 11 is a flow chart of a method for merging video output streams with a graphical stream for transmission according to an embodiment of the present disclosure.
  • FIG. 12 is a flow chart of a method for merging video output streams with a graphical stream for transmission according to another embodiment of the present disclosure.
  • FIG. 4 is a diagram of a video processing circuit 400 according to a first embodiment of the present disclosure.
  • the video processing circuit 400 includes, but not limited to, a video processing chip 410 , a video post-processing chip 420 , and a video output device 430 .
  • a video generating unit 412 , a graphic generating unit 414 , and a communication interface circuit 416 are disposed in the video processing chip 410 ; and a first signal receiver 422 , a video post-processing unit 424 , a decoding unit 426 , a mixer 428 , and a second signal transmitter 429 are disposed in the post-processing chip 420 coupled to the video processing chip 410 .
  • the video generating unit 412 is utilized for generating a video output stream S OUT according to a video input stream S IN
  • the graphic generating unit 414 is utilized for providing a graphical stream PD 1
  • the communication interface circuit 416 is coupled to the video generating unit 412 and to the graphic generating unit 414 .
  • the communication interface circuit 416 has a first mode (as shown in 4 A) and a second mode (as shown in 4 B).
  • the first mode is provided for mixing the video output stream S OUT and the graphical stream PD 1 to transmit a mixed video output stream S MOUT through a channel LVDS and the second mode provided for merging the video output stream S OUT and the graphical stream PD 1 to transmit a first merged signal S M1 through the channel LVDS, wherein the mixed video output stream S MOUT is generated by combining contents of the video output stream S OUT and the graphical stream PD 1 and the first merged signal S M1 is generated by putting the video output stream S OUT and the graphical stream PD 1 in the channel LVDS.
  • the merging operation stated hereinafter is different from the aforementioned mixing operation as the merged result (e.g., the first merged signal S M1 ) contains complete raw data of two input signals to be merged.
  • the disclosed merging operation is to incorporate the graphical stream PD 1 into the video output stream S OUT , rather than replacing an overlapped portion (e.g., the original video data corresponding to a display area overlaid by the OSD area) in the video output stream S OUT with the graphical stream PD 1 .
  • the communication interface circuit 416 is in the first mode, whereof the first mode is provided for mixing the video output stream S OUT and the graphical stream PD 1 to transmit the mixed video output stream S MOUT through the channel LVDS.
  • the video processing chip 410 is directly coupled to a video output device 530 .
  • the communication interface circuit 416 is in the second mode, whereof the second mode provided for merging the video output stream S OUT and the graphical stream PD 1 to transmit a first merged signal S M1 through the channel LVDS.
  • the first merged signal S M1 is transmitted to the first signal receiver 422 .
  • the first signal receiver 422 receives the first merged signal S M1 and extracts the video output stream S OUT and the graphical stream PD 1 from the first merged signal S M1 .
  • the video post-processing unit 424 is coupled to the first signal receiver 422 for receiving and post-processing the video output stream S OUT extracted from the first merged signal S M1 to generate a processed video output stream S POUT .
  • the decoding unit 426 is coupled to the first signal receiver 422 for decoding the graphical stream to generate a decoded graphical stream PD 2 .
  • the mixer 428 receives and mixes the processed video output stream S POUT with the decoded graphical stream PD 2 to generate a second merged signal S M2 .
  • the second signal transmitter outputs the second merged signal S M2 to the video output device 430 through a low voltage differential signal (LVDS) interface for display.
  • LVDS low voltage differential signal
  • the video processing circuit 400 is installed in a digital television (TV). It should be noted that although the video processing circuit 400 of this embodiment is installed in the digital TV as mentioned above, those skilled in the art will readily appreciate that the video processing circuit 400 can be applied to other products requiring similar video processing.
  • the video output device 430 can be a recorder or a flat panel display (FPD), such as a DVD recorder or a plasma panel.
  • the second signal transmitter 429 is a low voltage differential signal (LVDS) transmitter
  • the first signal receiver 422 is an LVDS receiver.
  • the first merged signal S M1 and the second merged signal S M2 are transmitted through an LVDS interface, but this for illustrative purpose only and is not meant to be a limitation of the present disclosure.
  • the first merged signal S M1 and the second merged signal S M2 can be transmitted through other interfaces, e.g. a transistor-transistor logic (TTL) interface, which is well-known to the one skilled in the art and is not described in detail herein.
  • TTL transistor-transistor logic
  • the graphic generating unit 414 can be an on-screen display (OSD) encoder disposed in the video processing chip 410 or an external storage device of the video processing chip 410 , or other elements. Detail descriptions are disclosed in the following embodiments.
  • OSD on-screen display
  • FIG. 5 is a diagram of a video processing circuit 500 according to a second embodiment of the present disclosure.
  • the graphic generating unit is an OSD encoder 514 and is disposed in a video processing chip 510
  • the decoding unit is an OSD decoder 526 disposed in a video post-processing chip 520 .
  • the communication interface circuit 416 is in the second mode.
  • the OSD encoder 514 generates the graphical stream PD 1 (that is to say an OSD data herein), and the communication interface circuit 416 then merges the video output stream S OUT and the graphical stream PD 1 (i.e., the OSD data) to generate a first merged signal S M1 .
  • the OSD decoder 526 decodes graphical stream PD 1 (the OSD data) to generate the decoded graphical stream PD 2 (a decoded OSD data).
  • FIG. 6 is a diagram of a video processing circuit 600 according to a third embodiment of the present disclosure.
  • the graphic generating unit is an external storage device 614 of a video processing chip 610
  • a video post-processing chip 620 further includes a second storage device 625 coupled to the decoding unit 426 .
  • the external storage device 614 is not disposed in the video processing chip 610 , and acts as an external data source for storing and providing the graphical stream PD 1 .
  • the graphical stream PD 1 can be a table, an index, a program code, or other data used in certain video applications, but this is for illustrative purpose only and is not meant to be a limitation of the present disclosure.
  • the communication interface circuit 416 is in the second mode.
  • the external storage device 614 provides the graphical stream PD 1 to the communication interface circuit 416 , and the communication interface circuit 416 merges the video output stream S OUT and the graphical stream PD 1 , such as a program code, to generate a first merged signal S M1 .
  • the decoding unit 426 After the first signal receiver 422 receives the first merged signal S M1 and extracts the video output stream S OUT and the graphical stream PD 1 (i.e., the program code) from the first merged signal S M1 , the decoding unit 426 then decodes graphical stream PD 1 (i.e., the program code) to generate the decoded graphical stream PD 2 (i.e., a decoded program code). The graphical stream PD 2 is then stored into the second storage device 625 .
  • the second storage device 625 can comprise, but not limited to, a DRAM, an SRAM, or a register file.
  • the graphic generating unit 414 can be an internal element disposed in the video processing chip or an external element positioned outside the video processing chip.
  • the graphical stream PD 1 can be an OSD data, a table, an index, a program code, or other data, but this for illustrative purpose only and is not meant to be a limitation of the present disclosure. It will be obvious to those skilled in the art that various modifications may be made without departing from the spirit of the present disclosure.
  • FIG. 7 is a diagram showing a conventional LVDS signal encoding. As shown in FIG. 7 , it represents an LVDS transmission for 8-bit RGB format and 2 channels. In each channel, 24 bits for R/G/B signals (each signal has 8 bits), 1 bit for Hsync control signal, 1 bit for Vsync control signal, 1 bit for data enable signal, and 1 reserved bit are included, which represent the video output stream S OUT . Thus the LVDS transmission totally has 56 bits in these two channels. Assume that the LVDS transmission runs at 75 Hz (or 60 Hz for Full-HD) and all the signals are transmitted by buses A 0 -A 8 . During a cycle (such as the current cycle in FIG.
  • the bits GU 0 , RU 5 , . . . , RU 1 , and RU 0 are transmitted by the bus A 0
  • the bits BU 1 , BU 0 , . . . , GU 2 , and GU 0 are transmitted by the bus A 1 , and so on. Therefore, all the 56 bits can be transmitted during the current cycle through the LVDS transmission.
  • FIG. 8 is a diagram showing a first exemplary embodiment of a novel LVDS signal encoding according to the present disclosure. As shown in FIG. 8 , it represents an LVDS transmission for 8-bit RGB format and 2 channels. In FIG. 8 , like the LVDS transmission in FIG. 7 , each channel includes 28 bits and the LVDS transmission totally has 56 bits, which represent the video output stream S OUT . In this embodiment, the communication interface circuit 416 is in the second mode and merges the video output stream S OUT and the graphical stream PD 1 by increasing a working frequency of the communication interface circuit 416 to increase a bandwidth of the channel LVDS. Assume that the LVDS transmission in FIG.
  • FIG. 9 is a diagram showing a second exemplary embodiment of a novel LVDS signal encoding according to the present disclosure. As shown in FIG. 9 , it represents an LVDS transmission for YC 4:2:2 format and 2 channels.
  • the communication interface circuit 416 is in the second mode and merges the video output stream S OUT and the graphical stream PD 1 by compressing the video output stream S OUT .
  • Each channel includes 8 bits for Y signal (i.e., a luminance signal) and 8 bits for C signal (i.e., a chrominance signal), 1 bit for Hsync signal, 1 bit for Vsync signal, 1 bit for data enable signal, and 1 reserved bit.
  • the LVDS transmission also runs at 75 Hz (or 60 Hz for Full-HD) and all the signals are transmitted by buses A 0 -A 8 .
  • the video output stream S OUT only has 40 bits to be transmitted through the LVDS transmission due to the employed YC 4:2:2 format, the spare bandwidth can be utilized for transmitting extra 16 bits data of the graphical stream PD 1 (marked as OSDU 0 -OSD 7 and OSDL 0 -OSDL 7 ).
  • the communication interface circuit 416 compresses the video output stream S OUT by transferring the video output stream S OUT from a first color depth format (R/G/B) to a second color depth format (Y/C).
  • R/G/B first color depth format
  • Y/C second color depth format
  • the communication interface circuit 416 can be configured to compress the video output stream S OUT by replacing actual color values of the video output stream S OUT with color indexes of the video output stream S OUT , or transferring the video output stream S OUT into a packet format. Due to the operation of compressing the video output stream S OUT being well-known to those skilled in the art, it is not described in detail herein for brevity.
  • FIG. 10 is a diagram showing a third exemplary embodiment of a novel LVDS signal encoding according to the present disclosure. As shown in FIG. 10 , it represents an LVDS transmission for 8-bit RGB format and 2 channels.
  • the communication interface circuit 416 is in the second mode and merges the video output stream S OUT and the graphical stream PD 1 by using positions for transmitting a portion of video control signals in the video output stream S OUT to transmit the graphical stream PD 1 .
  • Each channel includes 24 bits for R/G/B (each signal has 8 bits), but only one channel needs to transmit the video control signals, e.g.
  • FIG. 11 is a flow chart of a method for merging video output streams with a graphical stream for transmission according to an embodiment of the present disclosure. The method includes the following steps:
  • Step 1102 Generate a video output stream S OUT according to a video input stream S IN ;
  • Step 1104 Provide a graphical stream PD 1 ;
  • Step 1106 Determine whether the communication interface circuit 416 is in the first mode or second mode. If the communication interface circuit 416 is in the first mode, process goes to step 1108 ; otherwise, process goes to step 1112 .
  • Step 1108 The video output stream S OUT and the graphical stream PD 1 are mixed to transmit the mixed video output stream S MOUT through the channel LVDS.
  • Step 1110 Receive and display video images according to the mixed video output stream S MOUT .
  • Step 1112 Receive and merge the video output stream S OUT and the graphical stream PD 1 to transmit a first merged signal S M1 through the channel LVDS;
  • Step 1114 Receive the first merged signal S M1 and extract the video output stream S OUT and the graphical stream PD 1 from the first merged signal S M1 ;
  • Step 1116 Receive and post-process the video output stream S OUT extracted from the first merged signal S M1 to generate a processed video output stream S POUT ;
  • Step 1118 Decode the graphical stream PD 1 to generate a decoded graphical stream PD 2 ;
  • Step 1120 Mix the processed video output stream S POUT with the decoded graphical stream PD 2 to generate a second merged signal S M2 ;
  • Step 1122 Output the second merged signal S M2 ;
  • Step 1124 Receive and display video images according to the second merged signal S M2 .
  • the video generating unit 412 generates the video output stream S OUT according to the video input signal S IN (Step 1102 ), and the graphic generating unit 414 provides the graphical stream PD 1 (Step 1104 ).
  • Step 1106 whether the communication interface circuit 416 is in the first mode or the second mode is determined. In the following, the flow is divided into two cases for illustration. If the communication interface circuit 416 is in the first mode, the steps 1108 - 1110 are executed. If the communication interface circuit 416 is in the second mode, the steps 1112 - 1124 are executed.
  • the video output stream S OUT and the graphical stream PD 1 are mixed to transmit the mixed video output stream S MOUT through the channel LVDS (Step 1108 ), and then the video output device 530 receives and displays video images according to the mixed video output stream S MOUT .
  • the communication interface circuit 416 When the communication interface circuit 416 is in the second mode (as shown in 4 B), the communication interface circuit 416 receives and merges the video output stream S OUT and the graphical stream PD 1 to transmit the first merged signal S M1 (Step 1112 ), and the first signal receiver 422 then receives the first merged signal S M1 and extracts the video output stream S OUT and the graphical stream PD 1 from the first merged signal S M1 (Step 1114 ).
  • the video output stream S OUT extracted from the first merged signal S M1 is received and post-processed by the video post-processing unit 424 to generate the processed video output stream S- POUT (Step 1116 ), and the graphical stream PD 1 is decoded by the decoding unit 426 to generate the decoded graphical stream PD 2 (Step 1118 ).
  • the processed video output stream S POUT and the decoded graphical stream PD 2 are mixed by the mixer 428 to generate the second merged signal S M2 .
  • the second merged signal S M2 is outputted by the second signal transmitter 429 through an LVDS interface to the video output device 430 for displaying video images according to the second merged signal S M2 (the steps 1122 - 1124 ).
  • Step 1112 the video output stream S OUT and the graphical stream PD 1 are merged by increasing a working frequency of the communication interface circuit 416 to increase a bandwidth of the channel, by using positions for transmitting a portion of video control signals in the video output stream S OUT to transmit the graphical stream PD 1 , by compressing the video output stream, or any combination of the abovementioned operations.
  • the detail description has already been disclosed in the above-mentioned embodiments ( FIG. 8-FIG . 10 ), and further detailed description is omitted herein for the sake of brevity.
  • the operation of compressing the video output stream S OUT can be performed by transferring the video output stream S OUT from a first color depth format to a second color depth format, replacing actual color values of the video output stream with color indexes of the video output stream, or transferring the video output stream into a packet format (see the embodiment in FIG. 9 ).
  • This is only a preferred embodiment for describing the present disclosure and is not meant to be a limitation of the present disclosure.
  • specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that other modified designs obeying the spirit of the disclosure are possible and also fall into the scope of the disclosure.
  • FIG. 12 is a flow chart of a method for merging video signals with a graphical stream for transmission according to another embodiment of the present disclosure. The method includes, but is not limited to, the following steps:
  • Step 1202 Generate a video output stream S OUT according to a video input stream S IN ;
  • Step 1204 Store and provide a graphical stream PD 1 ;
  • Step 1206 Determine whether the communication interface circuit 416 is in the first mode or second mode. If the communication interface circuit 416 is in the first mode, process goes to step 1208 ; otherwise, process goes to step 1212 .
  • Step 1208 The video output stream S OUT and the graphical stream PD 1 are mixed to transmit the mixed video output stream S MOUT through the channel LVDS.
  • Step 1210 Receive and displayvideo images according to the mixed video output stream S MOUT .
  • Step 1212 Receive and merge the video output stream S OUT and the graphical stream PD 1 to transmit a first merged signal S M1 ;
  • Step 1214 Receive the first merged signal S M1 and extract the video output stream S OUT and the graphical stream PD 1 from the first merged signal S M1 ;
  • Step 1216 Receive and post-process the video output stream S OUT extracted from the first merged signal S M1 to generate a processed video output stream S POUT ;
  • Step 1218 Decode the graphical stream PD 1 to generate a decoded graphical stream PD 2 ;
  • Step 1219 Store the decoded graphical stream PD 2 ;
  • Step 1220 Mix the processed video output stream S POUT with the decoded graphical stream PD 2 to generate a second merged signal S M2 ;
  • Step 1222 Output the second merged signal S M2 ;
  • Step 1224 Receive and display video images according to the second merged signal S M2 .
  • the graphical stream PD 1 is stored and provided by the external storage device 614 .
  • the external storage device 614 can be a DRAM and is not disposed in the video processing chip 610 .
  • the graphical stream PD 1 can be a table, an index, or a program code stored in the external storage device 610 .
  • the graphical stream PD 1 is provided by the graphic generating unit 414 , which is disposed in the video processing chip 610 .
  • the graphical stream PD 1 is decoded by the decoding unit 426 to generate a decoded graphical stream PD 2 , and the decoded graphical stream PD 2 is then stored into the second storage device 625 , whereof the second storage device 625 can be a SRAM, a DRAM, or a register file. But in Step 1112 of FIG. 11 , graphical stream PD 2 is not stored.
  • the first merged signal S M1 and the second merged signal S M2 are transmitted through an LVDS interface, but this is for illustrative purpose only and is not meant as a limitation of the present disclosure.
  • the first merged signal S M1 and the second merged signal S M2 can be transmitted through other interfaces, e.g. a transistor-transistor logic (TTL) interface.
  • TTL transistor-transistor logic
  • the communication interface circuit 416 can be operated in the first mode or the second mode.
  • the first mode is provided for mixing the video output stream S OUT and the graphical stream PD 1 to transmit the mixed video output stream S MOUT through the channel LVDS, and the video processing chip 410 is directly coupled to a video output device 530 .
  • the second mode is provided for merging the video output stream S OUT and the graphical stream PD 1 to transmit a first merged signal S M1 through the channel LVDS, and the video processing chip 410 is coupled to a post-processing chip 420 and then coupled to the video output device 430 .
  • the graphic generating unit 414 can be an on-screen display (OSD) encoder disposed in the video processing chip 410 , an external storage device of the video processing chip 410 , or other elements, and is not limited to them only.
  • OSD on-screen display
  • the graphical stream PD 1 can be an OSD data, a table, an index, a program code, or other data, but this for example only and is not meant as a limitation of the present disclosure.
  • the video output stream S OUT and the graphical stream PD 1 are merged by increasing a working frequency of the communication interface circuit 416 to increase a bandwidth of the channel, by using positions for transmitting a portion of video control signals in the video output stream S OUT to transmit the graphical stream PD 1 , by compressing the video output stream, or any combination of the abovementioned operations.
  • the operation of compressing the video output stream S OUT can be performed by transferring the video output stream S OUT from a first color depth format to a second color depth format, replacing actual color values of the video output stream with color indexes of the video output stream, or transferring the video output stream into a packet format.
  • the present disclosure provides a processing system and related method for merging video output streams with a graphical stream for transmission.
  • the second mode due to the video output stream S OUT and the graphical stream PD 1 being merged by the communication interface circuit 416 for transmission, no extra I/O pins are needed to transmit the graphical stream PD 1 , which is economical for cost.
  • only the video output stream S OUT extracted from the first merged signal S M1 is post-processed by the video post-processing unit 424 , therefore, not only the video quality of the video output stream S OUT is enhanced but also the quality around the graphical stream PD 1 area maintains good.
  • the graphical stream PD 1 in various types can be transmitted through the video processing circuit of the present disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

A video processing circuit includes a video generating unit for generating a video output stream, a graphic generating unit for providing a graphical stream, and a communication interface circuit coupled to the video generating unit and the graphic generating unit. The communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel. In the second mode, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and compressing the video output stream.

Description

    BACKGROUND
  • The present disclosure relates to a video processing circuit and related method thereof, and more particularly, to a processing circuit and related method for merging video output streams with a graphical stream for transmission.
  • In a typical digital TV chip application, auxiliary graphics, e.g. on screen display (OSD) information, are usually overlaid on video output streams as user interfaces or user menus. Generally, the graphics and the video output streams are mixed into a single mixed data by a conventional mixer, and the mixed data is then transmitted to a display panel for further display. Please refer to FIG. 1. FIG. 1 is a diagram of a first conventional video processing circuit 100. The video processing circuit 100 includes a video processing chip 110 and a video output device 130, whereof the video processing chip 110 includes a video generating unit 112, an OSD encoder 114, a mixer 116, and a first signal transmitter 118. The generating unit 112 is utilized for generating a video output stream SOUT according to a video input stream SIN. The OSD encoder 114 is utilized for generating an encoded auxiliary graphic data D1. The mixer 116 is coupled to the video generating unit 112 and the OSD encoder 114 for mixing the video output stream SOUT with the graphic data D1 to generate a single mixed data DMIX, and then the first signal transmitter 118 transmits the mixed data DMIX to the video output device 130 through a low voltage differential signal (LVDS) interface. More particularly, the video processing chip 110 is a TV chip installed in a digital TV, and the video output device can be a recorder or a flat panel display (FPD), such as a plasma panel.
  • In order to enhance video quality, a post-processing chip is necessary for the typical digital TV chip application. Please refer to FIG. 2. FIG. 2 is a diagram of a second conventional video processing circuit 200. In FIG. 2, elements with the same reference numerals as that in FIG. 1 refer to the same elements, and further detailed description is omitted herein for brevity. The difference between the video processing circuit 200 and the video processing circuit 100 is that the video processing circuit 200 further includes a video post-processing chip 220 coupled between the video processing chip 110 and the video output device 130. The video post-processing chip 22 includes a first signal receiver 222, a video post-processing unit 224, and a second signal transmitter 226. The first signal receiver 222 is coupled to the first signal transmitter 118 for receiving the mixed data DMIX, and the video post-processing unit 224 is coupled to the first signal receiver 222 for receiving and post-processing the mixed data DMIX to generate a processed mixed data DPMIX. Then, the second signal transmitter 226 transmits the processed mixed data DPMIX to the video output device 130 through a low voltage differential signal (LVDS) interface.
  • Due to the video output stream SOUT being mixed with the auxiliary graphic data D1 to generate the mixed data DMIX, both the video output stream SOUT and the graphic data D1 are post-processed by the video post-processing unit 224 by the same scheme for enhancing the video quality thereof. Thus the quality around edges of the graphic data D1 area may be poor as the video enhancement is applied to the mixed data DMIX including contents of the graphic data D1 which replace an overlapped portion within the contents originally carried by the video output stream SOUT and are far different from remaining contents corresponding to the video output stream SOUT.
  • Please refer to FIG. 3. FIG. 3 is a diagram of a third conventional video processing circuit 300. In FIG. 3, elements with the same reference numerals as that in FIG. 2 refer to the same elements, and further detailed description is omitted herein for brevity. Also, the video processing circuit 300 includes a video processing chip 310, a video post-processing chip 320, and the video output device 130. The differences between the video processing circuit 300 in FIG. 3 and the video processing circuit 200 in FIG. 2 are described in the following. During the operation of the video processing chip 310, the video output stream SOUT and the graphic data D1 are not mixed and are respectively transmitted to the first signal transmitter 118. At this time, only the video output stream SOUT is post-processed by the video post-processing unit 224 to generate a processed video output stream SPOUT for enhancing the video quality. The graphic data D1 is directly transmitted to a mixer 318 without being post-processed by the video post-processing unit 224. Afterwards, the processed video output stream SPOUT and the graphic data D1 are mixed by the mixer 318 to generate a second mixed signal DPMIX2. In this situation, as the whole video contents carried by the video output stream SOUT undergo the video enhancement processing before mixed with the auxiliary graphic data D1, the quality around edges of the graphic data D1 area can be improved but extra I/O pins are needed to transmit the graphic data D1 to the first signal receiver 222.
  • Presently, most video processing circuits often add a post-processing chip to enhance the video quality. However, if the video output stream SOUT and the graphic data D1 are mixed during the operation of the video processing chip, both the video output stream SOUT and the graphic data D1 are post-processed by the video post-processing chip, resulting in a poor quality around the graphic data D1 area as the mixing process occurs prior to the post-processing process. If the video output stream SOUT and the graphic data D1 are mixed during the operation of the video post-processing chip (i.e., the post-processing process occurs prior to the mixing process), only the video output stream SOUT is post-processed by the video post-processing chip for enhancing the video quality. The disadvantage of this case is that extra I/O pins are needed to transmit the graphic data D1, which is not economical for cost.
    • SUMMARY OF THE DISCLOSURE
  • It is one of the objectives of the claimed disclosure to provide a video processing circuit and related method for merging video output streams with a graphical stream for transmission, thereby reducing the number of pins assigned for transmitting the main video data (e.g., display data) and the auxiliary video data (e.g., OSD data).
  • According to an embodiment of the present disclosure, a video processing circuit is disclosed. The video processing circuit includes a video generating unit, a graphic generating unit, and a communication interface circuit. The video generating unit generates a video output stream according to a video input stream. The graphic generating unit provides a graphical stream. The communication interface circuit is coupled to the video generating unit and the graphic generating unit. The communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel, wherein the mixed video output stream is generated by combining contents of the video output stream and the graphical stream and the first merged signal is generated by putting the video output stream and the graphical stream in the channel.
  • In one embodiment, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase a bandwidth of the channel, by using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and by compressing the video output stream.
  • In one embodiment, the video processing circuit further includes a first signal receiver, a video post-processing unit, a decoding unit, a mixer, and a second signal transmitter. The first signal receiver is coupled to the communication interface circuit for receiving the first merged signal and extracting the video output stream and the graphical stream from the first merged signal. The a video post-processing unit is coupled to the first signal receiver for receiving and post-processing the video output stream extracted from the first merged signal to generate a processed video output stream. The decoding unit is coupled to the first signal receiver for decoding the graphical stream to generate a decoded graphical stream. The mixer is coupled to the video post-processing unit and the decoding unit for mixing the processed video output stream with the decoded graphical stream to generate a second merged signal. The second signal transmitter is coupled to the mixer for outputting the second merged signal.
  • In one embodiment, the video generating unit, the graphic generating unit, and the communication interface circuit are disposed in a video processing chip; and the first signal receiver, the video post-processing unit, the decoding unit mixer, and the second signal transmitter are disposed in a post-processing chip coupled to the video processing chip.
  • In one embodiment, the graphic generating unit is an on-screen display (OSD) encoder for generating the graphical stream.
  • In one embodiment, the graphic generating unit is an external storage device of the video processing chip for storing and providing the graphical stream.
  • In one embodiment, the communication interface circuit is a low voltage differential signal (LVDS) interface circuit.
  • In one embodiment, the graphical stream comprises an on-screen display (OSD) data.
  • It is an objective of the claimed disclosure to provide a method for merging video output streams with a graphical stream for transmission.
  • According to an embodiment of the present disclosure, a method for merging video output streams with a graphical stream for transmission is disclosed. The method includes generating a video output stream according to a video input stream, providing a graphical stream, and providing a first mode for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and providing a second mode for merging the video output stream and the graphical stream to transmit a first merged signal to a post-processing chip through the channel, wherein the mixed video output stream is generated by combining contents of the video output stream and the graphical stream and the first merged signal is generated by putting the video output stream and the graphical stream in the channel.
  • The method further includes receiving the first merged signal and extracting the video output stream and the graphical stream from the first merged signal, receiving and post-processing the video output stream extracted from the first merged signal to generate a processed video output stream, decoding the graphical stream to generate a decoded graphical stream, mixing the processed video output stream with the decoded graphical stream to generate a second merged signal, and outputting the second merged signal.
  • In one embodiment, the first merged signal is a low voltage differential signal (LVDS).
  • In one embodiment, the video output stream and the graphical stream are merged by increasing a working frequency of the communication interface circuit to increase a bandwidth of the channel, by using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and by compressing the video output stream.
  • These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram of a first conventional video processing circuit.
  • FIG. 2 is a diagram of a second conventional video processing circuit.
  • FIG. 3 is a diagram of a third conventional video processing circuit.
  • FIG. 4 is a diagram of a video processing circuit according to a first embodiment of the present disclosure.
  • FIG. 5 is a diagram of a video processing circuit according to a second embodiment of the present disclosure.
  • FIG. 6 is a diagram of a video processing circuit according to a third embodiment of the present disclosure.
  • FIG. 7 is a diagram showing a conventional LVDS signal encoding.
  • FIG. 8 is a diagram showing a first exemplary embodiment of a novel LVDS signal encoding according to the present disclosure.
  • FIG. 9 is a diagram showing a second exemplary embodiment of the novel LVDS signal encoding according to the present disclosure.
  • FIG. 10 is a diagram showing a third exemplary embodiment of the novel LVDS signal encoding according to the present disclosure.
  • FIG. 11 is a flow chart of a method for merging video output streams with a graphical stream for transmission according to an embodiment of the present disclosure.
  • FIG. 12 is a flow chart of a method for merging video output streams with a graphical stream for transmission according to another embodiment of the present disclosure.
    •  DETAILED DESCRIPTION
  • Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
  • Please refer to FIG. 4. FIG. 4 is a diagram of a video processing circuit 400 according to a first embodiment of the present disclosure. The video processing circuit 400 includes, but not limited to, a video processing chip 410, a video post-processing chip 420, and a video output device 430. In one embodiment, a video generating unit 412, a graphic generating unit 414, and a communication interface circuit 416 are disposed in the video processing chip 410; and a first signal receiver 422, a video post-processing unit 424, a decoding unit 426, a mixer 428, and a second signal transmitter 429 are disposed in the post-processing chip 420 coupled to the video processing chip 410.
  • Please continue referring to FIG. 4. The video generating unit 412 is utilized for generating a video output stream SOUT according to a video input stream SIN, and the graphic generating unit 414 is utilized for providing a graphical stream PD1. The communication interface circuit 416 is coupled to the video generating unit 412 and to the graphic generating unit 414. The communication interface circuit 416 has a first mode (as shown in 4A) and a second mode (as shown in 4B). The first mode is provided for mixing the video output stream SOUT and the graphical stream PD1 to transmit a mixed video output stream SMOUT through a channel LVDS and the second mode provided for merging the video output stream SOUT and the graphical stream PD1 to transmit a first merged signal SM1 through the channel LVDS, wherein the mixed video output stream SMOUT is generated by combining contents of the video output stream SOUT and the graphical stream PD1 and the first merged signal SM1 is generated by putting the video output stream SOUT and the graphical stream PD1 in the channel LVDS. It should be note that the merging operation stated hereinafter is different from the aforementioned mixing operation as the merged result (e.g., the first merged signal SM1) contains complete raw data of two input signals to be merged. In other words, the disclosed merging operation is to incorporate the graphical stream PD1 into the video output stream SOUT, rather than replacing an overlapped portion (e.g., the original video data corresponding to a display area overlaid by the OSD area) in the video output stream SOUT with the graphical stream PD1.
  • As shown in 4A, the communication interface circuit 416 is in the first mode, whereof the first mode is provided for mixing the video output stream SOUT and the graphical stream PD1 to transmit the mixed video output stream SMOUT through the channel LVDS. Under this situation, the video processing chip 410 is directly coupled to a video output device 530.
  • As shown in 4B, the communication interface circuit 416 is in the second mode, whereof the second mode provided for merging the video output stream SOUT and the graphical stream PD1 to transmit a first merged signal SM1 through the channel LVDS. After the signal merging, the first merged signal SM1 is transmitted to the first signal receiver 422. The first signal receiver 422 receives the first merged signal SM1 and extracts the video output stream SOUT and the graphical stream PD1 from the first merged signal SM1. The video post-processing unit 424 is coupled to the first signal receiver 422 for receiving and post-processing the video output stream SOUT extracted from the first merged signal SM1 to generate a processed video output stream SPOUT. The decoding unit 426 is coupled to the first signal receiver 422 for decoding the graphical stream to generate a decoded graphical stream PD2. At this time, the mixer 428 receives and mixes the processed video output stream SPOUT with the decoded graphical stream PD2 to generate a second merged signal SM2. Finally, the second signal transmitter outputs the second merged signal SM2 to the video output device 430 through a low voltage differential signal (LVDS) interface for display.
  • In one embodiment, the video processing circuit 400 is installed in a digital television (TV). It should be noted that although the video processing circuit 400 of this embodiment is installed in the digital TV as mentioned above, those skilled in the art will readily appreciate that the video processing circuit 400 can be applied to other products requiring similar video processing. Please note that, the video output device 430 can be a recorder or a flat panel display (FPD), such as a DVD recorder or a plasma panel.
  • In this embodiment, the second signal transmitter 429is a low voltage differential signal (LVDS) transmitter, and the first signal receiver 422 is an LVDS receiver. Thus, the first merged signal SM1 and the second merged signal SM2 are transmitted through an LVDS interface, but this for illustrative purpose only and is not meant to be a limitation of the present disclosure. The first merged signal SM1 and the second merged signal SM2 can be transmitted through other interfaces, e.g. a transistor-transistor logic (TTL) interface, which is well-known to the one skilled in the art and is not described in detail herein.
  • Please note that, the graphic generating unit 414 can be an on-screen display (OSD) encoder disposed in the video processing chip 410 or an external storage device of the video processing chip 410, or other elements. Detail descriptions are disclosed in the following embodiments.
  • Please refer to FIG. 5. FIG. 5 is a diagram of a video processing circuit 500 according to a second embodiment of the present disclosure. In FIG. 5, elements with the same reference numerals as that in FIG. 4 refer to the same elements, further detailed description is omitted herein. In this embodiment, the graphic generating unit is an OSD encoder 514 and is disposed in a video processing chip 510, and the decoding unit is an OSD decoder 526 disposed in a video post-processing chip 520. In this embodiment, the communication interface circuit 416 is in the second mode. The OSD encoder 514 generates the graphical stream PD1 (that is to say an OSD data herein), and the communication interface circuit 416 then merges the video output stream SOUT and the graphical stream PD1 (i.e., the OSD data) to generate a first merged signal SM1. After the first signal receiver 422 receives the first merged signal SM1 and extracts the video output stream SOUT and the graphical stream PD1 (the OSD data) from the first merged signal SM1, the OSD decoder 526 decodes graphical stream PD1 (the OSD data) to generate the decoded graphical stream PD2 (a decoded OSD data).
  • FIG. 6 is a diagram of a video processing circuit 600 according to a third embodiment of the present disclosure. In FIG. 5, elements with the same reference numerals as that in FIG. 4 refer to the same elements, further detailed description is omitted herein. In this embodiment, the graphic generating unit is an external storage device 614 of a video processing chip 610, and a video post-processing chip 620 further includes a second storage device 625 coupled to the decoding unit 426. Please note that, the external storage device 614 is not disposed in the video processing chip 610, and acts as an external data source for storing and providing the graphical stream PD1. In this case, the graphical stream PD1 can be a table, an index, a program code, or other data used in certain video applications, but this is for illustrative purpose only and is not meant to be a limitation of the present disclosure. In this embodiment, the communication interface circuit 416 is in the second mode. The external storage device 614 provides the graphical stream PD1 to the communication interface circuit 416, and the communication interface circuit 416 merges the video output stream SOUT and the graphical stream PD1, such as a program code, to generate a first merged signal SM1. After the first signal receiver 422 receives the first merged signal SM1 and extracts the video output stream SOUT and the graphical stream PD1 (i.e., the program code) from the first merged signal SM1, the decoding unit 426 then decodes graphical stream PD1 (i.e., the program code) to generate the decoded graphical stream PD2 (i.e., a decoded program code). The graphical stream PD2 is then stored into the second storage device 625. In one embodiment, the second storage device 625 can comprise, but not limited to, a DRAM, an SRAM, or a register file.
  • Please note that, the graphic generating unit 414 can be an internal element disposed in the video processing chip or an external element positioned outside the video processing chip. The graphical stream PD1 can be an OSD data, a table, an index, a program code, or other data, but this for illustrative purpose only and is not meant to be a limitation of the present disclosure. It will be obvious to those skilled in the art that various modifications may be made without departing from the spirit of the present disclosure.
  • In the following embodiments, methods and operations about the communication interface circuit 416 merging the video output stream SOUT and the graphical stream PD1 in the second mode are disclosed.
  • Please refer to FIG. 7. FIG. 7 is a diagram showing a conventional LVDS signal encoding. As shown in FIG. 7, it represents an LVDS transmission for 8-bit RGB format and 2 channels. In each channel, 24 bits for R/G/B signals (each signal has 8 bits), 1 bit for Hsync control signal, 1 bit for Vsync control signal, 1 bit for data enable signal, and 1 reserved bit are included, which represent the video output stream SOUT. Thus the LVDS transmission totally has 56 bits in these two channels. Assume that the LVDS transmission runs at 75 Hz (or 60 Hz for Full-HD) and all the signals are transmitted by buses A0-A8. During a cycle (such as the current cycle in FIG. 7), the bits GU0, RU5, . . . , RU1, and RU0 are transmitted by the bus A0, and the bits BU1, BU0, . . . , GU2, and GU0 are transmitted by the bus A1, and so on. Therefore, all the 56 bits can be transmitted during the current cycle through the LVDS transmission.
  • Please refer to FIG. 8. FIG. 8 is a diagram showing a first exemplary embodiment of a novel LVDS signal encoding according to the present disclosure. As shown in FIG. 8, it represents an LVDS transmission for 8-bit RGB format and 2 channels. In FIG. 8, like the LVDS transmission in FIG. 7, each channel includes 28 bits and the LVDS transmission totally has 56 bits, which represent the video output stream SOUT. In this embodiment, the communication interface circuit 416 is in the second mode and merges the video output stream SOUT and the graphical stream PD1 by increasing a working frequency of the communication interface circuit 416 to increase a bandwidth of the channel LVDS. Assume that the LVDS transmission in FIG. 8 runs at 150 Hz and all the signals are transmitted by buses A0-A8. During a cycle (such as the current cycle in FIG. 8), totally 112 bits can be transmitted through the LVDS transmission due to running at 150 Hz. Therefore, besides the 56 bits of the video output stream SOUT can be transmitted through the LVDS transmission, the extra bandwidth induced by the boosted clock rate can be utilized for transmitting extra 56 bits data of the graphical stream PD1 (marked as OSDU0-OSDU27 and OSDL0-OSDL27), such as an OSD data, table, index, or program code.
  • Please refer to FIG. 9. FIG. 9 is a diagram showing a second exemplary embodiment of a novel LVDS signal encoding according to the present disclosure. As shown in FIG. 9, it represents an LVDS transmission for YC 4:2:2 format and 2 channels. In this embodiment, the communication interface circuit 416 is in the second mode and merges the video output stream SOUT and the graphical stream PD1 by compressing the video output stream SOUT. Each channel includes 8 bits for Y signal (i.e., a luminance signal) and 8 bits for C signal (i.e., a chrominance signal), 1 bit for Hsync signal, 1 bit for Vsync signal, 1 bit for data enable signal, and 1 reserved bit. Assume that the LVDS transmission also runs at 75 Hz (or 60 Hz for Full-HD) and all the signals are transmitted by buses A0-A8. During a cycle (such as the current cycle in FIG. 9), totally 56 bits can be transmitted through the LVDS transmission. However, the video output stream SOUT only has 40 bits to be transmitted through the LVDS transmission due to the employed YC 4:2:2 format, the spare bandwidth can be utilized for transmitting extra 16 bits data of the graphical stream PD1 (marked as OSDU0-OSD7 and OSDL0-OSDL7).
  • Please note that, in the above-mentioned embodiment, the communication interface circuit 416 compresses the video output stream SOUT by transferring the video output stream SOUT from a first color depth format (R/G/B) to a second color depth format (Y/C). This embodiment is presented merely for describing features of the present disclosure, and in no way should be considered to be limitations of the scope of the present disclosure. For example, in other alternative designs, the communication interface circuit 416 can be configured to compress the video output stream SOUT by replacing actual color values of the video output stream SOUT with color indexes of the video output stream SOUT, or transferring the video output stream SOUT into a packet format. Due to the operation of compressing the video output stream SOUT being well-known to those skilled in the art, it is not described in detail herein for brevity.
  • Please refer to FIG. 10. FIG. 10 is a diagram showing a third exemplary embodiment of a novel LVDS signal encoding according to the present disclosure. As shown in FIG. 10, it represents an LVDS transmission for 8-bit RGB format and 2 channels. In this embodiment, the communication interface circuit 416 is in the second mode and merges the video output stream SOUT and the graphical stream PD1 by using positions for transmitting a portion of video control signals in the video output stream SOUT to transmit the graphical stream PD1. Each channel includes 24 bits for R/G/B (each signal has 8 bits), but only one channel needs to transmit the video control signals, e.g. 1 bit for Hsync control signal, 1 bit for Vsync control signal, 1 bit for data enable signal. Assume that the LVDS transmission also runs at 75 Hz (or 60 Hz for Full HD) and all the signals are transmitted by buses A0-A8. During a cycle (such as the current cycle in FIG. 9), totally 56 bits can be transmitted through the LVDS transmission. However, the video output stream SOUT only has 51 bits to be transmitted through the LVDS transmission, the spare bandwidth can be utilized for transmitting extra 5 bits data of the graphical stream PD1 (marked as OSDU0 and OSDL0-OSDL3).
  • Please note that, although the above embodiments bring up three schemes as examples to introduce the spirit of the present disclosure, this is not meant to be limitations of the implementation of the present disclosure. Other embodiments obeying the spirit of the present invention are possible. For example, any combination of the abovementioned schemes shown in FIGS. 8-10 can be utilized, and this still falls in the scope of the present disclosure.
  • Please refer to FIG. 11. FIG. 11 is a flow chart of a method for merging video output streams with a graphical stream for transmission according to an embodiment of the present disclosure. The method includes the following steps:
  • Step 1102: Generate a video output stream SOUT according to a video input stream SIN;
  • Step 1104: Provide a graphical stream PD1;
  • Step 1106: Determine whether the communication interface circuit 416 is in the first mode or second mode. If the communication interface circuit 416 is in the first mode, process goes to step 1108; otherwise, process goes to step 1112.
  • Step 1108: The video output stream SOUT and the graphical stream PD1 are mixed to transmit the mixed video output stream SMOUT through the channel LVDS.
  • Step 1110: Receive and display video images according to the mixed video output stream SMOUT.
  • Step 1112: Receive and merge the video output stream SOUT and the graphical stream PD1 to transmit a first merged signal SM1 through the channel LVDS;
  • Step 1114: Receive the first merged signal SM1 and extract the video output stream SOUT and the graphical stream PD1 from the first merged signal SM1;
  • Step 1116: Receive and post-process the video output stream SOUT extracted from the first merged signal SM1 to generate a processed video output stream SPOUT;
  • Step 1118: Decode the graphical stream PD1 to generate a decoded graphical stream PD2;
  • Step 1120: Mix the processed video output stream SPOUT with the decoded graphical stream PD2 to generate a second merged signal SM2;
  • Step 1122: Output the second merged signal SM2; and
  • Step 1124: Receive and display video images according to the second merged signal SM2.
  • Please refer to FIG. 4 in conjunction with FIG. 11. The video generating unit 412 generates the video output stream SOUT according to the video input signal SIN (Step 1102), and the graphic generating unit 414 provides the graphical stream PD1 (Step 1104). At this time, whether the communication interface circuit 416 is in the first mode or the second mode is determined (Step 1106). In the following, the flow is divided into two cases for illustration. If the communication interface circuit 416 is in the first mode, the steps 1108-1110 are executed. If the communication interface circuit 416 is in the second mode, the steps 1112-1124 are executed. When the communication interface circuit 416 is in the first mode (as shown in 4A), the video output stream SOUT and the graphical stream PD1 are mixed to transmit the mixed video output stream SMOUT through the channel LVDS (Step 1108), and then the video output device 530 receives and displays video images according to the mixed video output stream SMOUT. When the communication interface circuit 416 is in the second mode (as shown in 4B), the communication interface circuit 416 receives and merges the video output stream SOUT and the graphical stream PD1 to transmit the first merged signal SM1 (Step 1112), and the first signal receiver 422 then receives the first merged signal SM1 and extracts the video output stream SOUT and the graphical stream PD1 from the first merged signal SM1 (Step 1114). Afterwards, the video output stream SOUT extracted from the first merged signal SM1 is received and post-processed by the video post-processing unit 424 to generate the processed video output stream S-POUT (Step 1116), and the graphical stream PD1 is decoded by the decoding unit 426 to generate the decoded graphical stream PD2 (Step 1118). In Step 1120, the processed video output stream SPOUT and the decoded graphical stream PD2 are mixed by the mixer 428 to generate the second merged signal SM2. Finally, the second merged signal SM2 is outputted by the second signal transmitter 429 through an LVDS interface to the video output device 430 for displaying video images according to the second merged signal SM2 (the steps 1122-1124).
  • Please note that, in Step 1112, the video output stream SOUT and the graphical stream PD1 are merged by increasing a working frequency of the communication interface circuit 416 to increase a bandwidth of the channel, by using positions for transmitting a portion of video control signals in the video output stream SOUT to transmit the graphical stream PD1, by compressing the video output stream, or any combination of the abovementioned operations. The detail description has already been disclosed in the above-mentioned embodiments (FIG. 8-FIG. 10), and further detailed description is omitted herein for the sake of brevity. In addition, the operation of compressing the video output stream SOUT can be performed by transferring the video output stream SOUT from a first color depth format to a second color depth format, replacing actual color values of the video output stream with color indexes of the video output stream, or transferring the video output stream into a packet format (see the embodiment in FIG. 9). This is only a preferred embodiment for describing the present disclosure and is not meant to be a limitation of the present disclosure. Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that other modified designs obeying the spirit of the disclosure are possible and also fall into the scope of the disclosure.
  • Please refer to FIG. 12. FIG. 12 is a flow chart of a method for merging video signals with a graphical stream for transmission according to another embodiment of the present disclosure. The method includes, but is not limited to, the following steps:
  • Step 1202: Generate a video output stream SOUT according to a video input stream SIN;
  • Step 1204: Store and provide a graphical stream PD1;
  • Step 1206: Determine whether the communication interface circuit 416 is in the first mode or second mode. If the communication interface circuit 416 is in the first mode, process goes to step 1208; otherwise, process goes to step 1212.
  • Step 1208: The video output stream SOUT and the graphical stream PD1 are mixed to transmit the mixed video output stream SMOUT through the channel LVDS.
  • Step 1210: Receive and displayvideo images according to the mixed video output stream SMOUT.
  • Step 1212: Receive and merge the video output stream SOUT and the graphical stream PD1 to transmit a first merged signal SM1;
  • Step 1214: Receive the first merged signal SM1 and extract the video output stream SOUT and the graphical stream PD1 from the first merged signal SM1;
  • Step 1216: Receive and post-process the video output stream SOUT extracted from the first merged signal SM1 to generate a processed video output stream SPOUT;
  • Step 1218: Decode the graphical stream PD1 to generate a decoded graphical stream PD2;
  • Step 1219: Store the decoded graphical stream PD2;
  • Step 1220: Mix the processed video output stream SPOUT with the decoded graphical stream PD2 to generate a second merged signal SM2;
  • Step 1222: Output the second merged signal SM2; and
  • Step 1224: Receive and display video images according to the second merged signal SM2.
  • Please refer to FIG. 6 in conjunction with FIG. 12, and compare FIG. 11 with FIG. 12. The difference between FIG. 11 and FIG. 12 is described in the following. In Step 1204, the graphical stream PD1 is stored and provided by the external storage device 614. In this case, the external storage device 614 can be a DRAM and is not disposed in the video processing chip 610. Thus the graphical stream PD1 can be a table, an index, or a program code stored in the external storage device 610. But in Step 1104 of FIG. 11, the graphical stream PD1 is provided by the graphic generating unit 414, which is disposed in the video processing chip 610. In the steps 1218-1219, the graphical stream PD1 is decoded by the decoding unit 426 to generate a decoded graphical stream PD2, and the decoded graphical stream PD2 is then stored into the second storage device 625, whereof the second storage device 625 can be a SRAM, a DRAM, or a register file. But in Step 1112 of FIG. 11, graphical stream PD2 is not stored.
  • The abovementioned embodiments are presented merely for describing features of the present disclosure, and in no way should be considered to be limitations of the scope of the present disclosure. In the above embodiments, the first merged signal SM1 and the second merged signal SM2 are transmitted through an LVDS interface, but this is for illustrative purpose only and is not meant as a limitation of the present disclosure. The first merged signal SM1 and the second merged signal SM2 can be transmitted through other interfaces, e.g. a transistor-transistor logic (TTL) interface. In addition, the communication interface circuit 416 can be operated in the first mode or the second mode. The first mode is provided for mixing the video output stream SOUT and the graphical stream PD1 to transmit the mixed video output stream SMOUT through the channel LVDS, and the video processing chip 410 is directly coupled to a video output device 530. The second mode is provided for merging the video output stream SOUT and the graphical stream PD1 to transmit a first merged signal SM1 through the channel LVDS, and the video processing chip 410 is coupled to a post-processing chip 420 and then coupled to the video output device 430. Please note that, the graphic generating unit 414 can be an on-screen display (OSD) encoder disposed in the video processing chip 410, an external storage device of the video processing chip 410, or other elements, and is not limited to them only. In addition, the graphical stream PD1 can be an OSD data, a table, an index, a program code, or other data, but this for example only and is not meant as a limitation of the present disclosure. Please note that again, in above embodiments, the video output stream SOUT and the graphical stream PD1 are merged by increasing a working frequency of the communication interface circuit 416 to increase a bandwidth of the channel, by using positions for transmitting a portion of video control signals in the video output stream SOUT to transmit the graphical stream PD1, by compressing the video output stream, or any combination of the abovementioned operations. In addition, the operation of compressing the video output stream SOUT can be performed by transferring the video output stream SOUT from a first color depth format to a second color depth format, replacing actual color values of the video output stream with color indexes of the video output stream, or transferring the video output stream into a packet format. This is only a preferred embodiment for describing the present disclosure and is not meant to be a limitation of the present disclosure.
  • In summary, the present disclosure provides a processing system and related method for merging video output streams with a graphical stream for transmission. In the second mode, due to the video output stream SOUT and the graphical stream PD1 being merged by the communication interface circuit 416 for transmission, no extra I/O pins are needed to transmit the graphical stream PD1, which is economical for cost. In addition, only the video output stream SOUT extracted from the first merged signal SM1 is post-processed by the video post-processing unit 424, therefore, not only the video quality of the video output stream SOUT is enhanced but also the quality around the graphical stream PD1 area maintains good. Furthermore, the graphical stream PD1 in various types can be transmitted through the video processing circuit of the present disclosure.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (23)

1. A video processing circuit, comprising:
a video generating unit for generating a video output stream according to a video input stream;
a graphic generating unit for providing a graphical stream; and
a communication interface circuit, coupled to the video generating unit and the graphic generating unit, the communication interface circuit having a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel, wherein the mixed video output stream is generated by combining contents of the video output stream and the graphical stream and the first merged signal is generated by putting the video output stream and the graphical stream in the channel.
2. The video processing circuit of claim 1, further comprising:
a video output device, coupled to the communication interface circuit, for receiving the mixed video output stream through the channel in the first mode; or
a post-processing device, coupled to the communication interface circuit, for receiving the first merged signal through the channel in the second mode.
3. The video processing circuit of claim 1, wherein in the second mode, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase a bandwidth of the channel.
4. The video processing circuit of claim 1, wherein in the second mode, the communication interface circuit merges the video output stream and the graphical stream by using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream.
5. The video processing circuit of claim 1, wherein in the second mode, the communication interface circuit merges the video output stream and the graphical stream by compressing the video output stream.
6. The video processing circuit of claim 5, wherein the communication interface circuit compresses the video output stream by:
transferring the video output stream from a first color depth format to a second color depth format;
replacing actual color values of the video output stream with color indexes of the video output stream; or
transferring the video output stream into a packet format.
7. The video processing circuit of claim 1, wherein the communication interface circuit is a low voltage differential signal (LVDS) interface circuit.
8. The video processing circuit of claim 1, wherein graphical stream comprises an on-screen display (OSD) data.
9. The video processing circuit of claim 1, wherein the video generating unit and the communication interface circuit are disposed in a video processing chip.
10. The video processing circuit of claim 9, wherein the graphic generating unit is an on-screen display (OSD) encoder, disposed in the video processing chip, for generating the graphical stream.
11. The video processing circuit of claim 9, wherein the graphic generating unit is an external storage device of the video processing chip for storing and providing the graphical stream.
12. The video processing circuit of claim 1, further comprising:
a first signal receiver, coupled to the communication interface circuit, for receiving the first merged signal and extracting the video output stream and the graphical stream from the first merged signal;
a video post-processing unit, coupled to the first signal receiver, for receiving and post-processing the video output stream extracted from the first merged signal to generate a processed video output stream;
a decoding unit, coupled to the first signal receiver, for decoding the graphical stream to generate a decoded graphical stream;
a mixer, coupled to the video post-processing unit and the decoding unit, for mixing the processed video output stream with the decoded graphical stream to generate a second merged signal; and
a second signal transmitter, coupled to the mixer, for outputting the second merged signal.
13. The video processing circuit of claim 12, wherein the video generating unit, the graphic generating unit, and the communication interface circuit are disposed in a video processing chip; and the first signal receiver, the video post-processing unit, the decoding unit mixer, and the second signal transmitter are disposed in a post-processing chip coupled to the video processing chip.
14. The video processing circuit of claim 13, further comprising:
a video output device, coupled to the second signal transmitter, for receiving the second merged signal and displaying video images according to the second merged signal.
15. The video processing circuit of claim 12, further comprising:
a storage device, coupled to the decoding unit, for storing the decoded graphical stream.
16. A method for merging video output streams with a graphical stream for transmission, the method comprising:
generating a video output stream according to a video input stream;
providing a graphical stream; and
providing a first mode for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and providing a second mode for merging the video output stream and the graphical stream to transmit a first merged signal to a post-processing chip through the channel, wherein the mixed video output stream is generated by combining contents of the video output stream and the graphical stream and the first merged signal is generated by putting the video output stream and the graphical stream in the channel.
17. The method of claim 16, wherein in the second mode, the step of merging the video output stream and the graphical stream comprises:
increasing a working frequency of the communication interface circuit to increase a bandwidth of the channel.
18. The method of claim 16, wherein in the second mode, the step of merging the video output stream and the graphical stream comprises:
using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream.
19. The method of claim 16, wherein in the second mode, the step of merging the video output stream and the graphical stream comprises:
compressing the video output stream.
20. The video processing circuit of claim 19, wherein the step of compressing the video output stream comprises:
transferring the video output stream from a first color depth format to a second color depth format;
replacing actual color values of the video output stream with color indexes of the video output stream; or
transferring the video output stream into a packet format.
21. The method of claim 16, wherein the first merged signal is a low voltage differential signal (LVDS).
22. The method of claim 16, wherein graphical stream comprises an on-screen display (OSD) data.
23. The method of claim 16, further comprising:
receiving the first merged signal and extracting the video output stream and the graphical stream from the first merged signal;
receiving and post-processing the video output stream extracted from the first merged signal to generate a processed video output stream;
decoding the graphical stream to generate a decoded graphical stream;
mixing the processed video output stream with the decoded graphical stream to generate a second merged signal; and
outputting the second merged signal.
US12/276,422 2008-11-24 2008-11-24 Video processing ciucuit and related method for merging video output streams with graphical stream for transmission Abandoned US20100128802A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US12/276,422 US20100128802A1 (en) 2008-11-24 2008-11-24 Video processing ciucuit and related method for merging video output streams with graphical stream for transmission
TW98127839A TWI380682B (en) 2008-11-24 2009-08-19 Video processing ciucuit and related method for merging video output streams with graphical stream for transmission
CN2009101714258A CN101742167B (en) 2008-11-24 2009-08-28 Video processing circuit and related method for merging video output streams with graphical stream for transmission
US13/907,983 US9137458B2 (en) 2008-11-24 2013-06-03 Video processing circuit and related method for merging video output streams with graphical stream for transmission
US14/807,900 US9509921B2 (en) 2008-11-24 2015-07-24 Video processing circuit and related method for merging video output streams with data stream for transmission

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/276,422 US20100128802A1 (en) 2008-11-24 2008-11-24 Video processing ciucuit and related method for merging video output streams with graphical stream for transmission

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/907,983 Continuation US9137458B2 (en) 2008-11-24 2013-06-03 Video processing circuit and related method for merging video output streams with graphical stream for transmission

Publications (1)

Publication Number Publication Date
US20100128802A1 true US20100128802A1 (en) 2010-05-27

Family

ID=42196242

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/276,422 Abandoned US20100128802A1 (en) 2008-11-24 2008-11-24 Video processing ciucuit and related method for merging video output streams with graphical stream for transmission
US13/907,983 Active 2029-08-15 US9137458B2 (en) 2008-11-24 2013-06-03 Video processing circuit and related method for merging video output streams with graphical stream for transmission

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/907,983 Active 2029-08-15 US9137458B2 (en) 2008-11-24 2013-06-03 Video processing circuit and related method for merging video output streams with graphical stream for transmission

Country Status (3)

Country Link
US (2) US20100128802A1 (en)
CN (1) CN101742167B (en)
TW (1) TWI380682B (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100238357A1 (en) * 2009-03-23 2010-09-23 Himax Media Solutions, Inc. Audio/video signal processor
US20130194397A1 (en) * 2012-01-27 2013-08-01 Samsung Electronics Co., Ltd. Display apparatus, apparatus for upgrading display apparatus, display system and data processing method of display system
CN103853515A (en) * 2012-12-05 2014-06-11 宏碁股份有限公司 Electronic device and processing method for displayed data thereof
EP2700035A4 (en) * 2011-04-18 2016-03-09 Supponor Oy Detection of graphics added to a video signal
US9373039B2 (en) 2011-04-18 2016-06-21 Supponor Oy Detection of graphics added to a video signal
CN113840170A (en) * 2020-06-23 2021-12-24 武汉斗鱼网络科技有限公司 Live wheat-connecting method and device
US20220385983A1 (en) * 2012-07-11 2022-12-01 Google Llc Adaptive content control and display for internet media
US12141418B2 (en) * 2023-05-25 2024-11-12 Google Llc Adaptive content control and display for internet media

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103856784B (en) * 2012-12-03 2019-02-05 联想(北京)有限公司 Data sending, receiving method and electronic equipment
CN106713922B (en) * 2017-01-13 2020-03-06 京东方科技集团股份有限公司 Image processing method and electronic device
CN108769564B (en) * 2018-06-25 2020-05-22 河南思维轨道交通技术研究院有限公司 Image acquisition system and image data processing method
US20230379525A1 (en) * 2022-05-18 2023-11-23 Mediatek Inc. Video stream processing system and video stream processing method

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010022889A1 (en) * 2000-03-15 2001-09-20 Masashi Ohta Video recording and playback apparatus and method
US20020126703A1 (en) * 2001-03-06 2002-09-12 Kovacevic Branko D. System for digitized audio stream synchronization and method thereof
US6519283B1 (en) * 1999-01-25 2003-02-11 International Business Machines Corporation Integrated video processing system having multiple video sources and implementing picture-in-picture with on-screen display graphics
US20030085903A1 (en) * 1998-06-15 2003-05-08 International Business Machines Corporation Color mapped and direct color OSD region processor with support for 4:2:2 profile decode function
US6570626B1 (en) * 1998-06-26 2003-05-27 Lsi Logic Corporation On-screen display format reduces memory bandwidth for on-screen display systems
US20040109504A1 (en) * 2002-12-04 2004-06-10 Seo Byeong Chan MPEG video decoding system
US7411613B2 (en) * 2003-12-19 2008-08-12 Canon Kabushiki Kaisha Video signal processing apparatus
US20080239149A1 (en) * 2007-03-30 2008-10-02 Innocom Technology (Shenzhen) Co., Ltd. OSD system having colorful and dynamic OSD menu and method for controlling same
US20080247455A1 (en) * 2003-07-09 2008-10-09 Mediatek Inc. Video signal processing apparatus to generate both progressive and interlace video signals
US20090043928A1 (en) * 2007-08-08 2009-02-12 Tony Lou Interface device and master device of a kvm switch system and a related method thereof
US7548586B1 (en) * 2002-02-04 2009-06-16 Mimar Tibet Audio and video processing apparatus
US20110179451A1 (en) * 2007-10-19 2011-07-21 British Sky Broadcasting Ltd. Television Display

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202765A (en) * 1991-05-06 1993-04-13 Thomson Consumer Electronics, Inc. Television receiver with picture in picture and non-linear processing
US6741794B1 (en) * 1999-01-29 2004-05-25 Sony Corporation System and method for flexibly blending multiple image planes in a video device
JP4618956B2 (en) 2001-12-10 2011-01-26 ソニー株式会社 Signal processing apparatus, signal processing method, signal processing system, program, and medium
EP1404130A1 (en) * 2002-09-24 2004-03-31 Matsushita Electric Industrial Co., Ltd. Method and apparatus for processing a video signal mixed with an additional image signal
WO2004090860A1 (en) 2003-04-01 2004-10-21 Matsushita Electric Industrial Co., Ltd. Video combining circuit
KR100609916B1 (en) * 2004-11-25 2006-08-08 삼성전자주식회사 Display and control method thereof

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030085903A1 (en) * 1998-06-15 2003-05-08 International Business Machines Corporation Color mapped and direct color OSD region processor with support for 4:2:2 profile decode function
US6570626B1 (en) * 1998-06-26 2003-05-27 Lsi Logic Corporation On-screen display format reduces memory bandwidth for on-screen display systems
US6519283B1 (en) * 1999-01-25 2003-02-11 International Business Machines Corporation Integrated video processing system having multiple video sources and implementing picture-in-picture with on-screen display graphics
US20010022889A1 (en) * 2000-03-15 2001-09-20 Masashi Ohta Video recording and playback apparatus and method
US20020126703A1 (en) * 2001-03-06 2002-09-12 Kovacevic Branko D. System for digitized audio stream synchronization and method thereof
US7548586B1 (en) * 2002-02-04 2009-06-16 Mimar Tibet Audio and video processing apparatus
US20040109504A1 (en) * 2002-12-04 2004-06-10 Seo Byeong Chan MPEG video decoding system
US20080247455A1 (en) * 2003-07-09 2008-10-09 Mediatek Inc. Video signal processing apparatus to generate both progressive and interlace video signals
US7411613B2 (en) * 2003-12-19 2008-08-12 Canon Kabushiki Kaisha Video signal processing apparatus
US20080239149A1 (en) * 2007-03-30 2008-10-02 Innocom Technology (Shenzhen) Co., Ltd. OSD system having colorful and dynamic OSD menu and method for controlling same
US20090043928A1 (en) * 2007-08-08 2009-02-12 Tony Lou Interface device and master device of a kvm switch system and a related method thereof
US20110179451A1 (en) * 2007-10-19 2011-07-21 British Sky Broadcasting Ltd. Television Display

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100238357A1 (en) * 2009-03-23 2010-09-23 Himax Media Solutions, Inc. Audio/video signal processor
EP2700035A4 (en) * 2011-04-18 2016-03-09 Supponor Oy Detection of graphics added to a video signal
US9373039B2 (en) 2011-04-18 2016-06-21 Supponor Oy Detection of graphics added to a video signal
US20130194397A1 (en) * 2012-01-27 2013-08-01 Samsung Electronics Co., Ltd. Display apparatus, apparatus for upgrading display apparatus, display system and data processing method of display system
US20220385983A1 (en) * 2012-07-11 2022-12-01 Google Llc Adaptive content control and display for internet media
US11662887B2 (en) * 2012-07-11 2023-05-30 Google Llc Adaptive content control and display for internet media
US20230297215A1 (en) * 2012-07-11 2023-09-21 Google Llc Adaptive content control and display for internet media
CN103853515A (en) * 2012-12-05 2014-06-11 宏碁股份有限公司 Electronic device and processing method for displayed data thereof
CN113840170A (en) * 2020-06-23 2021-12-24 武汉斗鱼网络科技有限公司 Live wheat-connecting method and device
US12141418B2 (en) * 2023-05-25 2024-11-12 Google Llc Adaptive content control and display for internet media

Also Published As

Publication number Publication date
TW201021548A (en) 2010-06-01
US9137458B2 (en) 2015-09-15
CN101742167B (en) 2013-07-10
CN101742167A (en) 2010-06-16
US20130265489A1 (en) 2013-10-10
TWI380682B (en) 2012-12-21

Similar Documents

Publication Publication Date Title
US9137458B2 (en) Video processing circuit and related method for merging video output streams with graphical stream for transmission
EP2197209A1 (en) Transmission device, image data transmission method, reception device, and image display method in reception device
KR101743776B1 (en) Display apparatus, method thereof and method for transmitting multimedia
WO2007102413A1 (en) Transmitting device, receiving device and transmitting/receiving device
JP2014515202A (en) Transforming multimedia data streams for use by connected devices
EP1672922A2 (en) Electronic device and method of controlling same
US20100020245A1 (en) Image displaying apparatus and image processing apparatus
US8769638B2 (en) Digital content authentication system, image display apparatus applied to the same, and digital content authentication controlling method of the same
US8040433B2 (en) Video output apparatus, control method thereof, and video device
CN106454153A (en) Touch terminal and display method thereof
US20090141197A1 (en) Liquid crystal display apparatus and method thereof for preventing transient noise
EP1944764A2 (en) Apparatus for receiving digital contents and method thereof
US6750918B2 (en) Method and system for using single OSD pixmap across multiple video raster sizes by using multiple headers
US9509921B2 (en) Video processing circuit and related method for merging video output streams with data stream for transmission
US20070083905A1 (en) Media player, control method thereof, and media play system having the same
US20140204994A1 (en) Auxiliary data encoding in video data
JP4502031B2 (en) Video display device
US20040174466A1 (en) Apparatus and method for outputting video data
US20080281990A1 (en) Expansion device adapted for use with a portable electronic device
JP2009044400A (en) Image display device
US20080174693A1 (en) Method and Apparatus for Video Format Conversion
EP1869876B1 (en) High-definition and single-definition digital television decoder
JP2009225306A (en) Video display apparatus
US20120062792A1 (en) Video processing device, display device and video processing method
US7663646B2 (en) Device, system and method for realizing on screen display

Legal Events

Date Code Title Description
AS Assignment

Owner name: MEDIATEK INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHIH, YANG-HUNG;LIN, HUNG-DER;PO, TANG-HUNG;AND OTHERS;REEL/FRAME:021879/0064

Effective date: 20081119

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION