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US20100018047A1 - Surface mount package - Google Patents

Surface mount package Download PDF

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Publication number
US20100018047A1
US20100018047A1 US12/566,744 US56674409A US2010018047A1 US 20100018047 A1 US20100018047 A1 US 20100018047A1 US 56674409 A US56674409 A US 56674409A US 2010018047 A1 US2010018047 A1 US 2010018047A1
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United States
Prior art keywords
surface mount
layer
metal
mount package
package
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US12/566,744
Inventor
William Palmteer
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Individual
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Individual
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Priority to US12/566,744 priority Critical patent/US20100018047A1/en
Publication of US20100018047A1 publication Critical patent/US20100018047A1/en
Assigned to RBS BUSINESS CAPITAL, A DIVISION OF RBS ASSET FINANCE, INC., AS AGENT reassignment RBS BUSINESS CAPITAL, A DIVISION OF RBS ASSET FINANCE, INC., AS AGENT SECURITY AGREEMENT Assignors: M/A-COM TECHNOLOGY SOLUTIONS HOLDINGS, INC., MIMIX BROADBAND, INC.
Assigned to M/A-COM TECHNOLOGY SOLUTIONS HOLDINGS, INC., MIMIX BROADBAND, INC. reassignment M/A-COM TECHNOLOGY SOLUTIONS HOLDINGS, INC. RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 25444/920 Assignors: RBS BUSINESS CAPITAL, A DIVISION OF RBS ASSET FINANCE, INC., AS ADMINISTRATIVE AGENT
Assigned to M/A-COM TECHNOLOGY SOLUTIONS HOLDINGS, INC. reassignment M/A-COM TECHNOLOGY SOLUTIONS HOLDINGS, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A.
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Definitions

  • This invention relates generally to surface mount packages, and more particularly, to surface mount packages for two terminal devices such as diodes.
  • Integrated Circuit (IC) mounting methods using surface mounting allow mounting of packages on both sides of, for example, a printed wiring board, thereby resulting in higher density mounting and reduced wire board size as compared to through-hole mounting.
  • IC Integrated Circuit
  • These surface mount packages also are becoming increasingly smaller and thinner to further provide this higher density mounting.
  • Surface mount packages include different isolated paths for electrical current flow, for example, to an anode and cathode within the packages.
  • Plastic is often used to form the surface mount package and may be used to isolate the current flow.
  • These surface mount packages are commonly referred to as plastic packages.
  • Separate metal connection pads may be used to provide electrical connection to the anode and cathode.
  • vias, other conduits or sidewall metallization may be included to provide electrical and/or thermal continuity between top metal connection pads and backside metal connection pads of the surface mount package.
  • These surface mount packages may be used to mount thereon different types of two terminal devices, such as, for example, diodes, and more particularly, light emitting diodes (LEDs).
  • LEDs light emitting diodes
  • operation of some of these two terminal devices generates high levels of heat.
  • Plastic packages may not provide acceptable levels of thermal dissipation for some of these devices and for certain applications. For example, certain high power devices may require thermal dissipation at levels higher than can be provided using these plastic packages. Further, because plastic has a relatively high thermal resistance, the efficiency of devices mounted within these packages may be reduced.
  • plastic packages it is difficult, if not impossible, to seal the plastic packages for certain applications, for example, to hermetically seal the plastic packages. This is because at the higher temperatures needed to hermitically seal the package (e.g., 300-400 degrees Celsius solder temperature), the plastic packages can melt.
  • plastic packages may not be suitable for certain applications and further may not provide acceptable operating characteristics.
  • a surface mount package includes a first metal layer and a second metal layer configured to be electrically connected to the first metal layer.
  • the surface mount package further includes a ceramic layer between the first and second metal layers. The ceramic layer has an opening therethrough.
  • a surface mount package includes a first lead frame and a second lead frame configured to be electrically connected to the first lead frame.
  • the surface mount package further includes a ceramic layer between the first and second lead frames. The ceramic layer is configured to electrically isolate a positive side and a negative side of the lead frames.
  • a method for manufacturing a surface mount package includes providing a first metal layer and providing a second metal layer electrically connected to the first metal layer.
  • the method further includes providing a ceramic layer between the first and second metal layers.
  • the ceramic layer has an opening therethrough and is configured to electrically isolate a positive side from a negative side of the surface mount package.
  • FIGS. 1A and 1B are elevation views of various embodiments illustrating surface mounting of surface mount devices.
  • FIG. 2 is a cross-sectional elevation view of a surface mount package constructed in accordance with an exemplary embodiment of the invention.
  • FIG. 3 is a top plan view of the surface mount package of FIG. 2 .
  • FIG. 4 is a cross-sectional elevation view of a surface mount package constructed in accordance with another exemplary embodiment of the invention.
  • FIG. 5 is a top plan view of the surface mount package of FIG. 4 .
  • FIG. 6 is a flowchart illustrating a process for manufacturing a surface mount package in accordance with an exemplary embodiment of the invention.
  • FIGS. 7A-7C are top plan views of arrays of surface mount packages constructed in accordance with exemplary embodiments of the invention.
  • FIG. 1A is a side elevation view of a surface mount arrangement wherein a surface mount device 32 (e.g., a diode) within a surface mount package 33 is mounted, for example, to a printed wiring board 38 . More particularly, the surface mount device 32 is mounted to mounting portions, for example, solder paste portions 34 on a top surface 36 of the printed wiring board 38 . Further, and as shown in FIG. 1B , surface mount devices 32 may be mounted to both the top surface 36 and a bottom surface 40 of the printed wiring board 38 .
  • a surface mount device 32 e.g., a diode
  • the first layer 44 includes a gap, groove or channel 50 formed (e.g., etched) thereon to electrically isolate an input side or positive side 52 and an output side or negative side 54 of the surface mount package 30 .
  • the input side 52 includes a plurality of anodes 56 formed as part of the first layer 44 and the output side 54 includes a plurality of cathodes 58 formed as part of the first layer 44 .
  • the first layer 44 is formed of a metal such as copper, Kovar, or other metal alloy (e.g., nickel), or a combination thereof.
  • the first layer 44 is formed as an etched lead frame constructed of any suitable electrically conducting material.
  • the second layer 46 is formed of a ceramic material, for example, alumina, calcia, beryllium oxide, aluminum nitride, silicon nitride, or other suitable ceramic material.
  • the second layer 46 is provided on top of the first layer 44 , using any known and suitable process, for example, using a brazing process.
  • the second layer 46 includes an opening 60 extending therethrough (e.g., a cutout portion).
  • the opening 60 is configured in a circular shape and provides access therethrough to the first layer 44 .
  • a plurality of vias 62 are provided through the second layer 46 , which in one embodiment, are metal filled vias 62 configured to provide electrical connection and connectivity between the first layer 44 and the third layer 48 .
  • the vias 62 provide for connecting the surface mount device 32 to the anodes 56 of the first layer 44 . Additional or fewer vias 62 may be provided.
  • a metal portion 64 extending generally perpendicularly from the first layer 44 may be provided (e.g., formed thereon) for mounting the surface mount device 32 thereto and for raising the surface mount device 32 above the second layer 46 . However, as should be appreciated, the metal portion 64 may be removed with the surface mount device 32 mounted directly to the first layer 44 .
  • a top and bottom surface of the second layer 46 may be metallized, using any known process, for example, refractory metallization, to provide electrical and thermal conductivity with the third and first layers 48 and 44 , respectively.
  • Various metals may be used for metallization, including, for example, silver.
  • the third layer 48 (e.g., a second metal layer) is also formed of a metal such as copper, Kovar, or other metal alloy (e.g., nickel), or a combination thereof.
  • the third layer 48 is formed as an etched lead frame constructed of any suitable electrically conducting material and provided on top of the second layer 46 using any known and suitable process, for example, using a brazing process.
  • the third layer 48 also includes an opening 66 that may be configured to receive therein or therethrough the surface mount device 32 .
  • the third layer 48 may be configured to form a frame structure surrounding a surface mount device 32 mounted in a cavity therein. As shown in FIG. 3 , the surface mount device 32 is mounted approximately in the center of the cavity.
  • the frame structure may be configured having angled inner walls 68 that include a reflective surface for redirecting and focusing light emitted from a surface mount device 32 therein, and more particularly, a light emitting diode (LED). More particularly, the angled walls 68 may be formed from a reflective silicon (e.g., etched in a silicon wafer). In an exemplary embodiment, the angled walls 68 are etched at an angle of approximately 60 degrees.
  • a light emitting diode package having angled walls is described in co-pending and commonly owned U.S. Patent Application entitled “Light Emitting Diode Package” having Ser. No. 10/914,361. It should be noted that the first and second layers 44 and 46 may define a submount portion with a frame portion defined by the third layer 48 provided on top thereof.
  • the surface mount device 32 is connected to the input and output sides 52 and 54 (e.g., positive and negative sides) using, for example, wire bonds 70 as is known.
  • a wire bond 70 may be connected from a terminal (e.g., positive terminal) of the surface mount device 32 to a metal pad (not shown) formed on the second layer 46 for connection to the anodes 56 through the vias 62 .
  • the metal pads may be provided as part of the vias 62 .
  • Another wire bond 70 may be connected from another terminal (e.g., negative terminal) of the surface mount device 32 through the opening 60 of the second layer 46 to the negative side 54 of the first layer 44 .
  • openings 60 and 66 may be configured in different shapes.
  • a surface mount package 80 may be provided such that the opening 60 is configured in a circular shape and the opening 66 is configured in an oval shape.
  • a metal pad 82 may be provided and formed as part of the vias 62 as described in more detail herein.
  • the surface mount device 32 may be mounted off center within the opening 66 .
  • a first layer is formed, for example, a metal lead frame is formed (e.g., cut) from a piece of metal.
  • a pattern is then etched or cut into the first layer at 94 . This may include, for example, providing connection members, such as, anodes and cathodes to the lead frame and providing a gap, groove or channel between the anodes and cathodes to electrically isolate an input and output that may be provided by the anode and cathode, respectively.
  • a metal portion may be formed on top of the first layer for later mounting thereon of a surface mount device as described in more detail herein.
  • a second layer is formed, for example, a ceramic layer is formed. The second layer is metallized at 98 , and more particularly, a top and bottom surface of the second layer is metallized.
  • an opening is provide (e.g., cut) in the second layer and configured to receive therein a surface mount device or the metal portion of the first layer.
  • vias or conduits are provided (e.g., cut) in the second layer at 102 .
  • These vias may be metal filled to provide electrical and thermal connection through the second layer. Additionally, metal pads may be formed as part of and on top of the metal filled vias.
  • a third layer is formed, for example, another metal lead frame is formed (e.g., cut) from a piece of metal. A pattern is then etched or cut into the third layer, and more particularly, at 106 an opening is provided (e.g., cut) therein for receiving a surface mount device.
  • the opening may be formed having reflective angled walls as described herein.
  • the three layers are connected, for example, by brazing with silver at 400 degrees Celsius or higher.
  • the layers may be bonded together, for example, using a polymer or adhesive (e.g., BCB).
  • the three layers thereby form a surface mount package that may be used to mount a surface mount device therein, for example, a surface mount diode, such as an LED or Zener diode.
  • the surface mount device may be connected to the surface mount package using wire bonds as is known.
  • the surface mount package may then be connected or mounted, for example, to a printed wiring board.
  • process 90 may be modified, for example, the steps described may be performed in a different order as desired or needed.
  • the first two layers may be connected before forming the third layer.
  • the methods of forming and cutting the layers may be provided using any known process as desired or needed.
  • a plurality of surface mount packages 30 may be formed as an array 110 as shown in FIGS. 7A-7C having different configurations.
  • the surface mount packages 30 may be aligned in series or parallel as shown and as desired or needed.
  • a surface mount package for a surface mount device e.g., surface mount LED
  • the surface mount package generally includes a ceramic layer between two metal layers, without the use of plastic.
  • the surface mount package allows use in a wider range of applications.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

A surface mount package is provided that includes a first metal layer and a second metal layer configured to be electrically connected to the first metal layer. The surface mount package further includes a ceramic layer between the first and second metal layers. The ceramic layer has an opening therethrough.

Description

  • This is a continuation of U.S. Ser. No. 11/136,249, filed May 24, 2005, which is incorporated by reference.
    • BACKGROUND OF THE INVENTION
  • This invention relates generally to surface mount packages, and more particularly, to surface mount packages for two terminal devices such as diodes.
  • Surface mount components or devices, and in particular, the use of surface mount packages allow smaller footprint designs with improved functionality and increased mounting densities. For example, Integrated Circuit (IC) mounting methods using surface mounting allow mounting of packages on both sides of, for example, a printed wiring board, thereby resulting in higher density mounting and reduced wire board size as compared to through-hole mounting. These surface mount packages also are becoming increasingly smaller and thinner to further provide this higher density mounting.
  • Surface mount packages include different isolated paths for electrical current flow, for example, to an anode and cathode within the packages. Plastic is often used to form the surface mount package and may be used to isolate the current flow. These surface mount packages are commonly referred to as plastic packages. Separate metal connection pads may be used to provide electrical connection to the anode and cathode. Further, vias, other conduits or sidewall metallization may be included to provide electrical and/or thermal continuity between top metal connection pads and backside metal connection pads of the surface mount package.
  • These surface mount packages may be used to mount thereon different types of two terminal devices, such as, for example, diodes, and more particularly, light emitting diodes (LEDs). However, operation of some of these two terminal devices generates high levels of heat. Plastic packages may not provide acceptable levels of thermal dissipation for some of these devices and for certain applications. For example, certain high power devices may require thermal dissipation at levels higher than can be provided using these plastic packages. Further, because plastic has a relatively high thermal resistance, the efficiency of devices mounted within these packages may be reduced.
  • Additionally, it is difficult, if not impossible, to seal the plastic packages for certain applications, for example, to hermetically seal the plastic packages. This is because at the higher temperatures needed to hermitically seal the package (e.g., 300-400 degrees Celsius solder temperature), the plastic packages can melt.
  • Thus, these plastic packages may not be suitable for certain applications and further may not provide acceptable operating characteristics.
    • BRIEF DESCRIPTION OF THE INVENTION
  • According to an exemplary embodiment, a surface mount package is provided that includes a first metal layer and a second metal layer configured to be electrically connected to the first metal layer. The surface mount package further includes a ceramic layer between the first and second metal layers. The ceramic layer has an opening therethrough.
  • According to another exemplary embodiment, a surface mount package is provided that includes a first lead frame and a second lead frame configured to be electrically connected to the first lead frame. The surface mount package further includes a ceramic layer between the first and second lead frames. The ceramic layer is configured to electrically isolate a positive side and a negative side of the lead frames.
  • According to yet another exemplary embodiment, a method for manufacturing a surface mount package is provided. The method includes providing a first metal layer and providing a second metal layer electrically connected to the first metal layer. The method further includes providing a ceramic layer between the first and second metal layers. The ceramic layer has an opening therethrough and is configured to electrically isolate a positive side from a negative side of the surface mount package.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A and 1B are elevation views of various embodiments illustrating surface mounting of surface mount devices.
  • FIG. 2 is a cross-sectional elevation view of a surface mount package constructed in accordance with an exemplary embodiment of the invention.
  • FIG. 3 is a top plan view of the surface mount package of FIG. 2.
  • FIG. 4 is a cross-sectional elevation view of a surface mount package constructed in accordance with another exemplary embodiment of the invention.
  • FIG. 5 is a top plan view of the surface mount package of FIG. 4.
  • FIG. 6 is a flowchart illustrating a process for manufacturing a surface mount package in accordance with an exemplary embodiment of the invention.
  • FIGS. 7A-7C are top plan views of arrays of surface mount packages constructed in accordance with exemplary embodiments of the invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1A is a side elevation view of a surface mount arrangement wherein a surface mount device 32 (e.g., a diode) within a surface mount package 33 is mounted, for example, to a printed wiring board 38. More particularly, the surface mount device 32 is mounted to mounting portions, for example, solder paste portions 34 on a top surface 36 of the printed wiring board 38. Further, and as shown in FIG. 1B, surface mount devices 32 may be mounted to both the top surface 36 and a bottom surface 40 of the printed wiring board 38.
  • Various embodiments of the present invention provide a surface mount package. In an exemplary embodiment, as shown in FIGS. 2 and 3, a surface mount package 30 generally includes a plurality of layers forming the surface mount package 30 and for mounting a surface mount device 32 thereto. Specifically, the surface mount package includes a first layer 44 (e.g., a first metal layer), which in this embodiment is a metal lead frame, a second layer 46, which in this embodiment is a ceramic layer, and a third layer 48, which in this embodiment is another metal lead frame. More particularly, the first layer 44, includes a gap, groove or channel 50 formed (e.g., etched) thereon to electrically isolate an input side or positive side 52 and an output side or negative side 54 of the surface mount package 30. Specifically, and as shown in FIG. 3, the input side 52 includes a plurality of anodes 56 formed as part of the first layer 44 and the output side 54 includes a plurality of cathodes 58 formed as part of the first layer 44.
  • In an exemplary embodiment, the first layer 44 is formed of a metal such as copper, Kovar, or other metal alloy (e.g., nickel), or a combination thereof. In general, the first layer 44 is formed as an etched lead frame constructed of any suitable electrically conducting material. In the exemplary embodiment, the second layer 46 is formed of a ceramic material, for example, alumina, calcia, beryllium oxide, aluminum nitride, silicon nitride, or other suitable ceramic material. The second layer 46 is provided on top of the first layer 44, using any known and suitable process, for example, using a brazing process. The second layer 46 includes an opening 60 extending therethrough (e.g., a cutout portion). In this exemplary embodiment, the opening 60 is configured in a circular shape and provides access therethrough to the first layer 44. Additionally a plurality of vias 62 (e.g., two vias) are provided through the second layer 46, which in one embodiment, are metal filled vias 62 configured to provide electrical connection and connectivity between the first layer 44 and the third layer 48. For example, the vias 62 provide for connecting the surface mount device 32 to the anodes 56 of the first layer 44. Additional or fewer vias 62 may be provided. Additionally, a metal portion 64 extending generally perpendicularly from the first layer 44 may be provided (e.g., formed thereon) for mounting the surface mount device 32 thereto and for raising the surface mount device 32 above the second layer 46. However, as should be appreciated, the metal portion 64 may be removed with the surface mount device 32 mounted directly to the first layer 44.
  • A top and bottom surface of the second layer 46 may be metallized, using any known process, for example, refractory metallization, to provide electrical and thermal conductivity with the third and first layers 48 and 44, respectively. Various metals may be used for metallization, including, for example, silver.
  • In this exemplary embodiment, the third layer 48 (e.g., a second metal layer) is also formed of a metal such as copper, Kovar, or other metal alloy (e.g., nickel), or a combination thereof. In general, the third layer 48 is formed as an etched lead frame constructed of any suitable electrically conducting material and provided on top of the second layer 46 using any known and suitable process, for example, using a brazing process. The third layer 48 also includes an opening 66 that may be configured to receive therein or therethrough the surface mount device 32. For example, the third layer 48 may be configured to form a frame structure surrounding a surface mount device 32 mounted in a cavity therein. As shown in FIG. 3, the surface mount device 32 is mounted approximately in the center of the cavity.
  • The frame structure may be configured having angled inner walls 68 that include a reflective surface for redirecting and focusing light emitted from a surface mount device 32 therein, and more particularly, a light emitting diode (LED). More particularly, the angled walls 68 may be formed from a reflective silicon (e.g., etched in a silicon wafer). In an exemplary embodiment, the angled walls 68 are etched at an angle of approximately 60 degrees. An example of a light emitting diode package having angled walls is described in co-pending and commonly owned U.S. Patent Application entitled “Light Emitting Diode Package” having Ser. No. 10/914,361. It should be noted that the first and second layers 44 and 46 may define a submount portion with a frame portion defined by the third layer 48 provided on top thereof.
  • The surface mount device 32 is connected to the input and output sides 52 and 54 (e.g., positive and negative sides) using, for example, wire bonds 70 as is known. Specifically, a wire bond 70 may be connected from a terminal (e.g., positive terminal) of the surface mount device 32 to a metal pad (not shown) formed on the second layer 46 for connection to the anodes 56 through the vias 62. For example, the metal pads may be provided as part of the vias 62. Another wire bond 70 may be connected from another terminal (e.g., negative terminal) of the surface mount device 32 through the opening 60 of the second layer 46 to the negative side 54 of the first layer 44.
  • It should be noted that the openings 60 and 66 may be configured in different shapes. For example, as shown in FIGS. 4 and 5, a surface mount package 80 may be provided such that the opening 60 is configured in a circular shape and the opening 66 is configured in an oval shape. A metal pad 82 may be provided and formed as part of the vias 62 as described in more detail herein. Thus, the surface mount device 32 may be mounted off center within the opening 66.
  • An exemplary process 90 for manufacturing a surface mount package 30 is shown in FIG. 6. Specifically, at 92, a first layer is formed, for example, a metal lead frame is formed (e.g., cut) from a piece of metal. A pattern is then etched or cut into the first layer at 94. This may include, for example, providing connection members, such as, anodes and cathodes to the lead frame and providing a gap, groove or channel between the anodes and cathodes to electrically isolate an input and output that may be provided by the anode and cathode, respectively. Additionally, a metal portion may be formed on top of the first layer for later mounting thereon of a surface mount device as described in more detail herein. Thereafter, at 96, a second layer is formed, for example, a ceramic layer is formed. The second layer is metallized at 98, and more particularly, a top and bottom surface of the second layer is metallized.
  • At 100, an opening is provide (e.g., cut) in the second layer and configured to receive therein a surface mount device or the metal portion of the first layer. Thereafter, vias or conduits are provided (e.g., cut) in the second layer at 102. These vias may be metal filled to provide electrical and thermal connection through the second layer. Additionally, metal pads may be formed as part of and on top of the metal filled vias. At 104, a third layer is formed, for example, another metal lead frame is formed (e.g., cut) from a piece of metal. A pattern is then etched or cut into the third layer, and more particularly, at 106 an opening is provided (e.g., cut) therein for receiving a surface mount device. The opening may be formed having reflective angled walls as described herein.
  • At 108, the three layers are connected, for example, by brazing with silver at 400 degrees Celsius or higher. Alternatively, the layers may be bonded together, for example, using a polymer or adhesive (e.g., BCB). The three layers thereby form a surface mount package that may be used to mount a surface mount device therein, for example, a surface mount diode, such as an LED or Zener diode. The surface mount device may be connected to the surface mount package using wire bonds as is known. The surface mount package may then be connected or mounted, for example, to a printed wiring board.
  • It should be noted that the process 90 may be modified, for example, the steps described may be performed in a different order as desired or needed. For example, the first two layers may be connected before forming the third layer. Additionally, the methods of forming and cutting the layers may be provided using any known process as desired or needed.
  • It should be noted that a plurality of surface mount packages 30 may be formed as an array 110 as shown in FIGS. 7A-7C having different configurations. The surface mount packages 30 may be aligned in series or parallel as shown and as desired or needed.
  • Thus, a surface mount package for a surface mount device (e.g., surface mount LED) is provided. The surface mount package generally includes a ceramic layer between two metal layers, without the use of plastic. The surface mount package allows use in a wider range of applications.
  • While the invention has been described in terms of various specific embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the claims.

Claims (3)

1. A method for manufacturing a surface mount package, the method comprising:
providing a first metal layer;
providing a second metal layer electrically connected to the first metal layer; and
providing a ceramic layer between the first and second metal layers, the ceramic layer having an opening therethrough and configured to electrically isolate a positive side from a negative side of the surface mount package.
2. The method according to claim 1, further comprising:
forming a gap within the first metal layer to electrically isolate the positive side from the negative side.
3. The method according to claim 1, further comprising:
providing an opening in both the second metal layer and ceramic layer configured to receive a surface mount device for mounting to the surface mount package.
US12/566,744 2005-05-24 2009-09-25 Surface mount package Abandoned US20100018047A1 (en)

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008034415A (en) * 2006-07-26 2008-02-14 Pioneer Electronic Corp Printed board, and circuit board
DE102008051928A1 (en) * 2008-10-16 2010-04-22 Osram Opto Semiconductors Gmbh Electrical connection conductor for a semiconductor component, semiconductor component and method for producing an electrical connection conductor
DE102008053489A1 (en) 2008-10-28 2010-04-29 Osram Opto Semiconductors Gmbh Carrier body for a semiconductor device, semiconductor device and method for producing a carrier body
US20120061698A1 (en) 2010-09-10 2012-03-15 Toscano Lenora M Method for Treating Metal Surfaces
CN103427005B (en) * 2012-05-23 2016-05-18 台达电子工业股份有限公司 Luminescent diode component and preparation method thereof and light source module

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5698866A (en) * 1994-09-19 1997-12-16 Pdt Systems, Inc. Uniform illuminator for phototherapy
US5838093A (en) * 1996-02-23 1998-11-17 Fujitsu Limited Piezoelectric element package in which a piezoelectric element on a chip carrier is reliably shielded by using a cap
US6310395B1 (en) * 1994-07-12 2001-10-30 Mitsubishi Denki Kabushiki Kaisha Electronic component with anodically bonded contact
US20010038140A1 (en) * 2000-04-06 2001-11-08 Karker Jeffrey A. High rigidity, multi-layered semiconductor package and method of making the same
US20020175621A1 (en) * 2001-05-24 2002-11-28 Samsung Electro-Mechanics Co., Ltd. Light emitting diode, light emitting device using the same, and fabrication processes therefor
US6627987B1 (en) * 2001-06-13 2003-09-30 Amkor Technology, Inc. Ceramic semiconductor package and method for fabricating the package
US7055987B2 (en) * 2001-09-13 2006-06-06 Lucea Ag LED-luminous panel and carrier plate
US20070076381A1 (en) * 2005-08-18 2007-04-05 Industrial Technology Research Institute Flexible circuit board with heat sink
US7227750B2 (en) * 2004-02-13 2007-06-05 Shanghai Sansi Technology Co. Ltd. Heat dissipating pin structure for mitigation of LED temperature rise
US7241030B2 (en) * 2004-07-30 2007-07-10 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Illumination apparatus and method

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4737236A (en) * 1986-09-08 1988-04-12 M/A-Com, Inc. Method of making microwave integrated circuits
US5268310A (en) * 1992-11-25 1993-12-07 M/A-Com, Inc. Method for making a mesa type PIN diode
US5369041A (en) * 1993-07-14 1994-11-29 Texas Instruments Incorporated Method for forming a silicon controlled rectifier
US5696466A (en) * 1995-12-08 1997-12-09 The Whitaker Corporation Heterolithic microwave integrated impedance matching circuitry and method of manufacture
US6114716A (en) * 1996-03-22 2000-09-05 The Whitaker Corporation Heterolithic microwave integrated circuits
US5877037A (en) * 1996-07-22 1999-03-02 The Whitaker Corporation Process for reducing bond resistance in semiconductor devices and circuits
US6014064A (en) * 1996-07-28 2000-01-11 The Whitaker Corporation Heterolithic voltage controlled oscillator
EP0921577A4 (en) * 1997-01-31 2007-10-31 Matsushita Electric Ind Co Ltd Light emitting element, semiconductor light emitting device, and method for manufacturing them
US6150197A (en) * 1997-04-25 2000-11-21 The Whitaker Corp. Method of fabricating heterolithic microwave integrated circuits
US5976941A (en) * 1997-06-06 1999-11-02 The Whitaker Corporation Ultrahigh vacuum deposition of silicon (Si-Ge) on HMIC substrates
US5841184A (en) * 1997-09-19 1998-11-24 The Whitaker Corporation Integrated emitter drain bypass capacitor for microwave/RF power device applications
US6191048B1 (en) * 1997-12-31 2001-02-20 The Whitaker Corporation Process for manufacturing composite glass/Si substrates for microwave integrated circuit fabrication
US6379785B1 (en) * 1997-12-31 2002-04-30 Tyco Electronic Corp Glass-coated substrates for high frequency applications
US5914501A (en) * 1998-08-27 1999-06-22 Hewlett-Packard Company Light emitting diode assembly having integrated electrostatic discharge protection
JP4125848B2 (en) * 1999-12-17 2008-07-30 ローム株式会社 Chip type light emitting device with case
US6486499B1 (en) * 1999-12-22 2002-11-26 Lumileds Lighting U.S., Llc III-nitride light-emitting device with increased light generating capability
JP3686569B2 (en) * 2000-03-02 2005-08-24 シャープ株式会社 Semiconductor light emitting device and display device using the same
US20030085416A1 (en) * 2001-11-08 2003-05-08 Tyco Electronics Corporation Monolithically integrated pin diode and schottky diode circuit and method of fabricating same
US6642550B1 (en) * 2002-08-26 2003-11-04 California Micro Devices Silicon sub-mount capable of single wire bonding and of providing ESD protection for light emitting diode devices
US20040184270A1 (en) * 2003-03-17 2004-09-23 Halter Michael A. LED light module with micro-reflector cavities
US6876008B2 (en) * 2003-07-31 2005-04-05 Lumileds Lighting U.S., Llc Mount for semiconductor light emitting device
US20050269695A1 (en) * 2004-06-07 2005-12-08 Brogle James J Surface-mount chip-scale package
US7402842B2 (en) * 2004-08-09 2008-07-22 M/A-Com, Inc. Light emitting diode package

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6310395B1 (en) * 1994-07-12 2001-10-30 Mitsubishi Denki Kabushiki Kaisha Electronic component with anodically bonded contact
US5698866A (en) * 1994-09-19 1997-12-16 Pdt Systems, Inc. Uniform illuminator for phototherapy
US5838093A (en) * 1996-02-23 1998-11-17 Fujitsu Limited Piezoelectric element package in which a piezoelectric element on a chip carrier is reliably shielded by using a cap
US20010038140A1 (en) * 2000-04-06 2001-11-08 Karker Jeffrey A. High rigidity, multi-layered semiconductor package and method of making the same
US20020175621A1 (en) * 2001-05-24 2002-11-28 Samsung Electro-Mechanics Co., Ltd. Light emitting diode, light emitting device using the same, and fabrication processes therefor
US6627987B1 (en) * 2001-06-13 2003-09-30 Amkor Technology, Inc. Ceramic semiconductor package and method for fabricating the package
US7055987B2 (en) * 2001-09-13 2006-06-06 Lucea Ag LED-luminous panel and carrier plate
US7227750B2 (en) * 2004-02-13 2007-06-05 Shanghai Sansi Technology Co. Ltd. Heat dissipating pin structure for mitigation of LED temperature rise
US7241030B2 (en) * 2004-07-30 2007-07-10 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Illumination apparatus and method
US20070076381A1 (en) * 2005-08-18 2007-04-05 Industrial Technology Research Institute Flexible circuit board with heat sink

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