US20070258073A1

US20070258073A1 - Enhanced lithographic resolution through double exposure

Info

Publication number: US20070258073A1
Application number: US11/822,995
Authority: US
Inventors: Jozef Finders; Donis Flagello; Steven Hansen
Original assignee: ASML Netherlands BV
Current assignee: ASML Netherlands BV
Priority date: 2004-01-28
Filing date: 2007-07-11
Publication date: 2007-11-08
Also published as: JP2005223321A; US20050162627A1; US7256873B2

Abstract

A system and method for enhancing the image resolution in a lithographic system, is presented herein. The invention comprises decomposing a reticle pattern into at least two constituent sub-patterns that are capable of being optically resolved by the lithographic system, coating a substrate with a pre-specified photoresist layer, and exposing a first of the at least two constituent sub-patterns by directing a projection beam through the first sub-pattern such that the lithographic system produces a first sub-pattern image onto the pre-specified photoresist layer of the substrate. The invention further comprises processing the exposed substrate, exposing a second of the at least two constituent sub-patterns by directing the projection beam through the second sub-pattern such that the lithographic system produces a second sub-pattern image onto the pre-specified photoresist layer of the substrate, and then combining the first and second sub-pattern images to produce a desired pattern on the substrate.

Description

The present application is a divisional application of U.S. patent application Ser. No. 10/765,218, filed Jan. 28, 2004, the entire contents of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention generally relates to photolithography and associated methods and apparatus for exposing semiconductor substrates.
2. Description of the Related Art
Lithographic exposure apparatuses can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, a patterning device may generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of photo-activated resist (i.e., photoresist) material. In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time.
The term “patterning device” as will be employed herein should be broadly interpreted to refer to a device that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate. The term “light valve” may also be used in this context. Generally, the pattern will correspond to a particular functional layer in a device being created in the target portion, such as an integrated circuit or other device (see below). Examples of such patterning devices include:

- (a) a mask: the concept of a mask or reticle is well known in lithography, and it includes reticle types such as binary, alternating phase-shift, and attenuated phase-shift, as well as various hybrid reticle types. Placement of such a reticle in the radiation beam causes selective transmission (in the case of a transmissive mask) or reflection (in the case of a reflective mask) of the radiation impinging on the reticle, according to the pattern on the reticle. In the case of a reticle, the support structure will generally be a reticle table, which ensures that the reticle can be held at a desired position in the incoming radiation beam, and that it can be moved relative to the beam if so desired;
- (b) a programmable mirror array: an example of such a device is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident light as diffracted light, whereas unaddressed areas reflect incident light as undiffracted light. Using an appropriate filter, the undiffracted light can be filtered out of the reflected beam, leaving only the diffracted light behind; in this manner, the beam becomes patterned according to the addressing pattern of the matrix-addressable surface. The required matrix addressing can be performed using suitable electronic means. More information on such mirror arrays can be gleaned, for example, from U.S. Pat. Nos. 5,296,891 and 5,523,193, which are incorporated herein by reference. In the case of a programmable mirror array, the support structure may be embodied as a frame or table, for example, which may be fixed or movable as required; and
- (c) a programmable LCD array: an example of such a construction is given in U.S. Pat. No. 5,229,872, which is incorporated herein by reference. As above, the support structure in this case may be embodied as a frame or table, for example, which may be fixed or movable as required.
  For purposes of simplicity, the rest of this text may, at certain locations, specifically direct itself to examples involving a reticle and reticle table; however, the general principles discussed in such instances should be seen in the broader context of the patterning devices as set forth above. Also, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection system, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”.

In current apparatuses, employing patterning by a reticle on a reticle table, a distinction can be made between two different types of machine. In one type of lithographic exposure apparatus, each target portion is irradiated by exposing the entire reticle pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the reticle pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Because, in general, the projection system will have a magnification factor M (generally<1),the speed V at which the substrate table is scanned will be a factor M times that at which the reticle table is scanned. More information with regard to lithographic devices as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
It is to be noted that the lithographic apparatus may also be of a type having two or more substrate tables (and/or two or more reticle tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
It will be appreciated that the wafer substrates Ws may be subjected to a variety of processes before lithographic apparatus exposes the reticle RE circuit pattern onto the wafer substrate W. For example, the wafer substrates Ws may be treated or coated with a layer of photo-activated resist (i.e. photoresist) material before exposure. Moreover, prior to exposure, the substrates Ws may also be subjected to cleaning, etching, ion implantation (e.g., doping), metallization, oxidation, chemo-mechanical polishing, priming, soft bake processes, and measurement processes.
The wafer substrates Ws may also be subjected to a host of post-exposure processes, such as, for example, post exposure bake (PEB), development, hard bake, etching, ion implantation (e.g., doping), metallization, oxidation, chemo-mechanical polishing, cleaning, and measurement processes. And, if several layers for each wafer substrate W is required, which is usually the case, the entire procedure, or variants thereof, will have to be repeated for each new layer.
The continual demand for smaller semiconductor devices, having smaller patterns and features on the wafer substrate, is pushing the limits on the optical resolution that can be achieved by lithographic exposure apparatus. Generally, the smallest size of repeatable feature (e.g., “half-pitch”) of a pattern exposed on wafer substrate W that can be optically resolved by lithographic exposure apparatus, depends on attributes of the projection lens PL and projection beam PB. In particular, the optical resolution for half-pitch feature size may be derived by using the simplified form of the Rayleigh resolution equation:
k ₁ =P _0.5 ·NA/λ≧0.25 (1)
where: p_0.5represents the repeatable feature size (e.g., “half-pitch”) in nm;

- NA represents the numerical aperture of projection lens PL;
- λ represents the wavelength of projection beam PB; and
- k₁represents the optical resolution limit for half-pitch feature size.

As indicated above, the theoretical optical resolution half-pitch lower limit k₁for 2-beam imaging, is 0.25. In an attempt to circumvent the k₁=0.25 barrier, considerable efforts have been directed to develop expensive technologies that are capable of employing shorter wavelengths and/or higher numerical apertures, thus allowing production of smaller features while not violating the k1≧0.25 constraint.

SUMMARY OF THE INVENTION

Systems, apparatuses and methods consistent with the principles of the present invention, as embodied and broadly described herein, provide for the enhancement of image resolution in a lithographic system. One embodiment of the present invention comprises decomposing a reticle pattern into at least two constituent sub-patterns that are capable of being optically resolved by the lithographic system, coating a substrate with a pre-specified photoresist layer, and exposing a first of the at least two constituent sub-patterns by directing a projection beam through the first sub-pattern such that the lithographic system produces a first sub-pattern image onto the pre-specified photoresist layer of the substrate. The invention further comprises processing the exposed substrate, exposing a second of the at least two constituent sub-patterns by directing the projection beam through the second sub-pattern such that the lithographic system produces a second sub-pattern image onto the pre-specified photoresist layer of the substrate, and then combining the first and second sub-pattern images to produce a desired pattern on the substrate.
Although specific reference may be made in this text to the use of the apparatus according to the invention in the manufacture of IC's, it should be explicitly understood that such an apparatus has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which:
FIG. 1 is a schematic illustration of a lithographic system in accordance with the present invention;
FIG. 2A is a functional flow diagram depicting an embodiment of the present invention;
FIG. 2B is a schematic illustration of a target reticle pattern and decomposed sub-patterns, in accordance with the present invention;
FIGS. 3A-3C schematically illustrate photoresist interactions during various lithographic processes, in accordance with an embodiment of the present invention; and
FIG. 3D charts energy information vs. baking interval, in accordance with the present invention.
In the figures, corresponding reference symbols indicate corresponding parts.

DETAILED DESCRIPTION

Lithographic Projection Apparatus
FIG. 1 schematically depicts a lithographic apparatus 100 according to a particular embodiment of the invention. Lithographic apparatus 100 comprises a radiation source LA and radiation system IL for providing projection beam PB, a first object table (e.g. reticle table) RT provided with a reticle holder for holding a reticle RE, and a projection system PL (e.g., lens) for imaging an irradiated portion of the reticle RE onto a target portion C (e.g. comprising one or more dies) of the substrate W. The combination of the reticle RE, reticle table RT, and reticle-related components are commonly referred to as the reticle stage RS.
As depicted, lithographic apparatus 100 is of a transmissive type (i.e. has a transmissive mask). However, in general, it may also be of a reflective type (with a reflective mask) and, alternatively, apparatus 100 may employ another kind of patterning device, such as a programmable mirror array of a type as indicated above
The projection beam PB may encompass different types of electromagnetic radiation including, but not limited to, ultraviolet radiation (UV) and extreme ultra-violet radiation (EUV), as well as particle beams, such as ion beams or electron beams.
Lithographic apparatus 100 further comprises a second object table (e.g., wafer substrate table) WT provided with a substrate holder for holding a wafer substrate W (e.g. a resist-coated silicon wafer). The combination of the wafer substrate W, wafer table WT, and wafer-related components are commonly referred to as the wafer substrate stage WS.
Source LA produces a beam of radiation, which is fed into illumination system (e.g., illuminator) IL, either directly or after having traversed conditioning mechanism, such as a beam expander EX, for example. Illuminator IL may comprise adjusting mechanism AM for setting the outer and/or inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in the beam. In addition, it will generally comprise various other components, such as an integrator IN and a condenser CO. In this way, the beam PB impinging on the reticle RE has a desired cross-sectional uniformity and intensity distribution.
Projection beam PB subsequently intercepts the reticle RE, which is held on a reticle table RT. The reticle table RT and/or the reticle stage RS may contain an actuating mechanism for adjusting the position of the reticle table RT, including height, tilt, rotational, and level positions. Having traversed the reticle RE, the beam PB passes through the lens PL, which focuses the beam PB onto a target portion C of the wafer substrate W. With the aid of the second positioning mechanism (and interferometric measuring mechanism IF), the substrate table WT can be moved accurately (e.g. so as to position different target portions C in the path of the beam PB). Similarly, the first positioning mechanism can be used to accurately position the reticle RE with respect to the path of the beam PB (e.g. after mechanical retrieval of the reticle RE from a reticle library, or during a scan).
In general, movement of the object tables RT, WT will be realized with the aid of a long-stroke module and a short-stroke module, which are not explicitly depicted in FIG. 1. However, in the case of a wafer stepper (as opposed to a step-and-scan apparatus), the reticle table RT may just be connected to a short stroke actuator, or may be fixed.
Lithographic apparatus 100 may operate in different modes:

- (a) step mode: reticle table RT is kept essentially stationary, and an entire reticle image is projected in one go (i.e. a single “flash”) onto a target portion C. The substrate table WT is then shifted in the x and/or y directions so that a different target portion C can be irradiated by the beam PB;
- (b) scan mode: essentially the same scenario applies, except that a given target portion C is not exposed in a single “flash”. Instead, reticle table RT is movable in a given direction (the so-called “scan direction”, e.g. the y direction) with a speed ν, so that projection beam PB is caused to scan over a reticle image. Concurrently, substrate table WT is simultaneously moved in the same or opposite direction at a speed V=Mν, in which M is the magnification of the lens PL (typically, M=¼ or ⅕). In this manner, a relatively large target portion C can be exposed, without having to compromise on resolution; and
- other mode: the mask table MT is kept essentially stationary holding a programmable patterning structure, and the substrate table WT is moved or scanned while a pattern imparted to the projection beam is projected onto a target portion C. In this mode, generally a pulsed radiation source is employed and the programmable patterning structure is updated as required after each movement of the substrate table WT or in between successive radiation pulses during a scan. This mode of operation can be readily applied to maskless lithography that utilizes programmable patterning structure, such as a programmable mirror array of a type as referred to above.

Embodiments

As noted above, their exists a constant need to achieve finer optical resolutions and circumventing the theoretical half-pitch lower limit k₁of 0.25 would provide an important advantage. Without this possibility, to achieve resolutions below this limit, efforts must concentrate on the development of expensive technologies that employ shorter wavelengths and/or higher numerical apertures.
As described in greater detail below, however, the present invention achieves resolutions lower than the half-pitch lower limit k₁of 0.25 by implementing a combination of multiple exposure techniques and reduced memory photoresist reaction processes. In particular, the disclosed invention takes advantage of the fact that appropriate photoresist processes can lock-in high contrast latent images while dissipating unwanted remnants of the optical exposure, and with multiple exposures yield half-pitch feature sizes smaller than what would otherwise be feasible under conventional lithographic processes.
The functional flow diagram of FIG. 2A depicts the general inventive concept of enhanced optical resolution process 200, constructed and operative in accordance with a particular embodiment of the present invention. As indicated in FIG. 2A, process 200 commences with procedure task P202, which involves the decomposition of target pattern T. Target pattern T contains a half-pitch feature size P_0.5smaller than what can be accommodated by lithographic apparatus 100. In other words, as depicted in FIG. 2B, the half-pitch feature size p_0.5of target pattern T corresponds to optical resolutions that are too small (e.g., k₁<0.25). As such, process 200 exploits the configuration of the features of target pattern T to split or decompose the features into at least two constituent sub-patterns T₁, T₂. As illustrated in FIG. 2B, each constituent sub-pattern T₁, T₂is arranged in a manner that can be optically resolved by lithographic apparatus 100 (i.e., k₁>0.25 for both T₁, T₂) and can be subsequently combined, interleaved, or otherwise superimposed to render the desired target pattern T.
Returning to FIG. 2A, process 200 progresses to procedure task P203 to select the photoresist to be applied to the wafer substrate W. In one embodiment, the photoresist selected enables the creation of a high contrast latent image while exhibiting reduced memory reaction characteristics. A reduced memory photoresist reaction process refers to a process in which the effects of an initial exposure on the photoresist are, to a certain extent, dissipated.
For example, a photoresist capable of providing high contrast latent images while having reduced reaction memory properties comprises a photo-acid generator PAG as well as a base B compound in a blocked matrix configuration, as illustrated in FIG. 3A. In this configuration, after exposure, photo-acid generator PAG is converted into a photo-acid PA+, of which some is neutralized by the base B compound, as depicted in FIG. 3B.
During the baking process, a reaction is catalyzed between the photo-acid PA+ and the polymer so that, after baking, the polymer is deblocked, rendering it soluble in typical developer solutions, and the photo-acid PA+ is largely dissipated, as illustrated in FIG. 3C. An example showing that photo-induced polymer deblocking reaction ceases, i.e. loses memory of the initial exposure, is shown in FIG. 3D. Here, after approximately 40 seconds of baking time, the chemical reactions occurring between the photo-acid PA+ and the polymer are reduced such that the extent of polymer deblocking does not increase with longer baking times. Thus, for this case, after a 40 sec. baking interval, the photo-acid PA+ virtually dissipates to provide a relatively high contrast and stable latent image on a photoresist that has little memory of any preceding exposures.
These dissipation characteristics will vary depending on the photoresist processing conditions, specifically bake time and temperature, and on the photoresist's chemical composition. It will be appreciated that baking time and temperature, as well as the composition of the photoresist, may be optimized to yield better and/or more consistent results.
In other embodiments, photoresist materials having non-linear responses, such as thermal resist material or equivalents, may be used to achieve these properties.
Upon selecting the photoresist, process 200 advances to procedure block P204, where wafer substrate W is directed to a pre-processing station or module configured to apply the selected photoresist. Wafer substrate W is then coated with the selected photoresist.
After coating, process 200 advances to procedure block P206, where wafer substrate W is directed to lithographic apparatus 100 for exposing the first sub-pattern T₁onto substrate W. After this first exposure, process 200 advances to procedure block P208, where substrate W directed to a baking station (e.g., PEB), where substrate W is baked for a predetermined interval of time (e.g., 60 sec.). As noted above, exposing and baking the substrate W “locks in” the features of the first sub-pattern T₁on the photoresist to provide a relatively high contrast and stable latent image.
Upon baking, process 200 progresses to procedure block P210, where wafer substrate W is directed back to lithographic apparatus 100, where the substrate W is shifted or offset by a predetermined distance ΔD. Predetermined distance ΔD corresponds to the shift necessary to adequately image the features of the second sub-pattern T₂on the photoresist to obtain the target image T. In other words, the offset of distance ΔD is determined so that when the second sub-pattern T₂is imaged on the photoresist, the features of the second sub-pattern T₂are properly aligned with the features of the already-imaged first sub-pattern T₁. In this manner, the superposition of the second sub-pattern T₂on the photoresist having the already-imaged first sub-pattern T₁, yields the original desired target pattern T.
After offsetting wafer substrate W by predetermined distance ΔD, processes 200 moves to procedure block P212, where wafer substrate W is directed to lithographic apparatus 100 for exposing the second sub-pattern T₂onto substrate W. After this second exposure, process 200 advances to procedure block P214, where substrate W directed to a baking station (e.g., PEB), where substrate W is baked for a predetermined interval of time to lock in the features of the second sub-pattern T₂on the photoresist. The substrate W is subsequently directed to a development station and other post-exposure processes, as indicated in procedure block P216, where a developer solution is applied to the substrate W to remove the unexposed photoresist material and prepare the substrate W for further processing, such as, for example, hard baking, etching, doping, metallization, and polishing.
In an alternative embodiment, indicated by the dashed lines of FIG. 2A, after procedure task P208, which directs the baking of the wafer substrate W having sub-pattern T₁imaged on the photoresist, process 200 progresses to procedure block P210A, where wafer substrate W is directed a development station that applies a developing solution to substrate W to remove the exposed photoresist material associated with the exposure of the first sub-pattern T₁. Then, in procedure task P212A, the substrate W is directed back to lithographic apparatus 100, where the substrate W is shifted or offset by a predetermined distance ΔD. As noted above, predetermined distance ΔD corresponds to the shift necessary to adequately image the features of the second sub-pattern T₂on the photoresist in order to superimpose the second sub-pattern T₂features in between the features of the already-imaged first sub-pattern T₁so as to render the original desired target pattern T.
After offsetting wafer substrate W by predetermined distance ΔD, process 200 moves to procedure block P214A, where wafer substrate W is directed to lithographic apparatus 100 for exposing the second sub-pattern T₂onto substrate W. After this second exposure, process 200 advances to procedure block P216A, where substrate W directed to a baking station (e.g., PEB), where substrate W is baked for a predetermined interval of time to lock in the features of the second sub-pattern T₂on the photoresist.
The substrate W is subsequently directed, once again, to a development station and other post-exposure processes, as indicated in procedure block P218A, where a developer solution is applied to the substrate W to remove the exposed photoresist material associated with the exposure of the second sub-pattern T₂and to prepare the substrate W for further processing.
In this manner, the disclosed invention is capable of exploiting the fact that patterns can be decomposed into two or more patterns with greater minimum half-pitch, multiple exposure techniques, and photoresist materials having reduced reaction memory to provide high contrast latent images having half-pitch feature sizes P_0.5smaller than what would otherwise be feasible under conventional lithographic processes.
The preceding detailed description refers to the accompanying drawings that illustrate exemplary embodiments consistent with the present invention. Other embodiments are possible and modifications may be made to the embodiments without departing from the spirit and scope of the invention. For example, the embodiments described above may, instead, be implemented in different embodiments of software, firmware, and hardware in the entities illustrated in the figures.
As such, the operation and behavior of the present invention has been described with the understanding that modifications and variations of the embodiments are possible, given the level of detail present herein. Thus, the above detailed description is not meant or intended to limit the invention—rather the scope of the invention is defined by the appended claims.

Claims

1. A method of enhancing the image resolution in a lithographic system, comprising:

decomposing a pattern into at least two constituent sub-patterns;

coating a substrate with a pre-specified photoresist layer, said pre-specified photoresist layer having reduced memory reaction characteristics;

exposing a first of said at least two constituent sub-patterns by directing a projection beam onto said first sub-pattern such that said lithographic system produces a first sub-pattern image onto said pre-specified photoresist layer of said substrate;

processing said exposed substrate;

exposing a second of said at least two constituent sub-patterns by directing said projection beam onto said second sub-pattern such that said lithographic system produces a second sub-pattern image onto said pre-specified photoresist layer of said substrate,

wherein said exposing results in a combination of said first and second sub-pattern images to produce a desired pattern on said substrate.

2. The method of claim 1, wherein said lithographic system is capable of optically resolving pattern features that correspond to a half-pitch lower limit k₁greater than 0.25 and said desired pattern includes features that correspond to a half-pitch lower limit k₁, less than or equal to 0.25.

3. The method of claim 1, wherein said processing includes,

baking said substrate having said first sub-pattern image on said photoresist layer, and

shifting said substrate, in said lithographic system, by a certain distance, in order to interleave said second sub-pattern image with said first sub-pattern image.

4. The method of claim 3, further including applying a developer solution to said substrate.

5. The method of claim 3, wherein said processing is optimized by employing specific bake times and temperatures such that said desired pattern includes features that correspond to a half-pitch lower limit k₁less than or equal to 0.25.

6. The method of claim 1, wherein said pre-specified photoresist layer further comprises a polymer resin compound, a photo-acid generator component, and a base component.

7. The method of claim 3, wherein said processing further includes,

applying a developer solution to said substrate, and

shifting said substrate, in said lithographic system, by a certain distance, in order to combine said second sub-pattern image with said first sub-pattern image.

8. The method of claim 7, further including baking said substrate having said second sub-pattern image and a developed first sub-pattern image on said photoresist layer.

9. The method of claim 8, wherein said processing is optimized by employing specific bake times and temperatures such that said desired pattern includes features that correspond to a half-pitch lower limit k₁less than or equal to 0.25.

10. The method of claim 9, wherein said pre-specified photoresist layer further comprises a polymer resin compound, a photo-acid generator component, and a base component.

11. The method of claim 3, further comprising shifting said substrate before exposing the second of said at least two constituent sub-patterns, in said lithographic system, by a certain distance, in order to interleave said second sub-pattern image with said first sub-pattern image.

12. An enhanced image resolution lithographic system, comprising:

a coating station configured to apply a photoresist layer onto a substrate, said photoresist layer configured to exhibit reduced memory reaction characteristics;

an exposure apparatus to expose a pattern onto said substrate; and

a processing station configured to process a substrate exposed by said exposure apparatus,

wherein said pattern is decomposed into at least two constituent sub-patterns that can be optically resolved by said exposure apparatus,

wherein a first of said at least two constituent sub-patterns is exposed onto said substrate by said exposure apparatus to produce a first sub-pattern image onto said photoresist layer of said substrate and said exposed substrate is processed by said processing station, and

wherein a second of said at least two constituent sub-patterns is exposed onto said substrate by said exposure apparatus to produce a second sub-pattern image onto said photoresist layer of said substrate and said first and second sub-pattern images are combined to produce a desired pattern.

13. The system of claim 12, wherein said exposure apparatus is capable of optically resolving pattern features that correspond to a half-pitch lower limit k₁greater than 0.25 and said desired pattern includes features that correspond to a half-pitch lower limit k₁less than or equal to 0.25.

14. The system of claim 12, wherein said processing station includes a baking station configured to bake said substrate having said first sub-pattern image on said photoresist layer.

15. The system of claim 14, configured to shift said substrate by a certain distance, in order to combine said second sub-pattern image with said first sub-pattern image.

16. The system of claim 14, configured to apply a developer solution to said substrate.

17. The system of claim 14, configured to optimize attributes of a baking of said substrate by employing specific bake times and temperatures such that said desired pattern includes features that correspond to a half-pitch lower limit k₁less than or equal to 0.25.

18. The system of claim 12, wherein said photoresist layer further comprises a polymer resin compound, a photo-acid generator component, and a base component.

19. The system of claim 12, wherein said processing station further includes:

a baking station configured to bake said substrate having said first sub-pattern image on said photoresist layer, and

a developer station to apply developer solution to said substrate.

20. The system of claim 19, configured to shift said substrate by a certain distance, in order to combine said second sub-pattern image with said first sub-pattern image.

21. The system of claim 20, further configured to bake said substrate having said second sub-pattern image and a developed first sub-pattern image on said photoresist layer.

22. The system of claim 21, configured to optimize attributes of a baking of said substrate by employing specific bake times and temperatures such that said desired pattern includes features that correspond to a half-pitch lower limit k₁less than or equal to 0.25.

23. The system of claim 22, wherein said photoresist layer further comprises a polymer resin compound, a photo-acid generator component, and a base component.