Nothing Special   »   [go: up one dir, main page]

US20060040497A1 - Material for contact etch layer to enhance device performance - Google Patents

Material for contact etch layer to enhance device performance Download PDF

Info

Publication number
US20060040497A1
US20060040497A1 US11/253,622 US25362205A US2006040497A1 US 20060040497 A1 US20060040497 A1 US 20060040497A1 US 25362205 A US25362205 A US 25362205A US 2006040497 A1 US2006040497 A1 US 2006040497A1
Authority
US
United States
Prior art keywords
film
stress
btbas
nitride
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/253,622
Inventor
Ashima Chakravarti
Shreesh Narasimha
Victor Chan
Judson Holt
Satya Chakravarti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/253,622 priority Critical patent/US20060040497A1/en
Publication of US20060040497A1 publication Critical patent/US20060040497A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C23C16/345—Silicon nitride
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane

Definitions

  • the present invention generally relates to integrated circuit manufacture, and more particularly to thin films and their production and their uses in conferring advantages upon the semiconductor devices being manufactured, especially in rapid thermal chemical vapor deposition (RTCVD) processes.
  • RTCVD rapid thermal chemical vapor deposition
  • various films have been produced for use in circuit manufacture (such as making transistors), in a variety of types of chemical vapor deposition (CVD) processes.
  • CVD chemical vapor deposition
  • Examples of the various CVD processes are low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), rapid thermal chemical vapor deposition (RTCVD), cyclic deposition (CLD), atomic layer deposition (ALD), and mixed deposition (MLD) (i.e., a mixture of CLD and ALD); etc.
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • HDPCVD high density plasma chemical vapor deposition
  • RTCVD rapid thermal chemical vapor deposition
  • CLD cyclic deposition
  • ALD atomic layer deposition
  • MLD mixed deposition
  • the respective deposition processes differ significantly from each other as to their conditions (temperature, pressure
  • U.S. Pat. No. 5,874,368 discloses formation of silicon nitrides from bis-tertiary butyl amino silane (BTBAS), in an LPCVD furnace, with pressure in a range of 20 mTorr to 2 Torr and a temperature range of 500-800° C. Also see Laxman et al., “A low-temperature solution for silicon nitride deposition,” Solid State Technology, April 2000, 79, disclosing LPCVD at 550-600° C.
  • BBAS bis-tertiary butyl amino silane
  • U.S. Pat. No. 6,046,494 (Apr. 4, 2000) discloses forming an insulating layer in a semiconductor device at a relatively low temperature and without plasma for lower negative bias temperature instability and reduced dopant segregation. Methods are described for how to make a silicon nitride liner in a LPCVD furnace. For making the nitride layer, a chlorinated silane gas is used.
  • U.S. Pat. No. 6,268,299 discloses a low temperature process for depositing barrier nitrides using SiH 4 , dichlorosilane (DCS), BTBAS, HCD and mixtures of these gases in an LPCVD process.
  • the flow ratio of NH 3 to the precursors was varied to give different Si:N ratios.
  • Japanese Patent 20030S 1452 discloses BTBAS nitride deposition by an LPCVD furnace. Film thickness accuracy is said to be improved by optimizing the cleaning process.
  • Another film produced using an LPCVD furnace is that of JP 2001230248A (Nov. 26, 2002), disclosing BTBAS nitride deposition using an LPCVD furnace.
  • LPCVD is but one known class of CVD processes.
  • Other manufacturing processes include PECVD and HDPCVD processes.
  • CLD CLD
  • ALD atomic layer deposition
  • MLD M-dielectric layer deposition
  • RTCVD RTCVD
  • Some films have been produced in RTCVD processes.
  • U.S. Pat. No. 6,153,261 (Nov. 28, 2000) discloses deposition of silicon nitride and oxide using BTBAS in an RTCVD process. See also U.S. Pat. App. 2001/0000476 A1 (Apr. 26, 2001).
  • U.S. Pat. No. 6,455,389 discloses an RTCVD process in which is formed a space layer that is a silicon nitride. Silane or dichloride silane is reacted with ammonia to form silicon nitride.
  • Huang et al. describe an RTCVD process generally as having the temperature of the chamber is about 650 to 700° C. and the pressure of the chamber is about 200 to 600 torr, with the proceeding time of the RTCVD deposition process being about 2 to 4 minutes.
  • Nitride films are used in many different applications. However, the question of satisfying a particular application is multi-variate and may be relatively complicated. Turning, for example, to semiconductor devices, many different properties are important for advantageous functioning of a particular device. There are many competing considerations for manufacturing a particular device. A variety of different manufacturing techniques have been suggested, of which the following are only some examples.
  • U.S. Pat. App. 2001/0034129 A1 discloses an etching process for layers with high carbon concentration.
  • the deposition uses TEOS, BTBAS, CCl 4 , CO 2 , etc. Spacers maybe formed by CVD using BTBAS and NH 3 .
  • U.S. Pat. App. 2002/0111039 discloses certain silicon oxynitride spacers with low dielectric constant formed by BTBAS and nitrogen containing gases, with stoichiometry and other properties controlled to give a varied wet etch rate. Carbon incorporation is taught, to improve dry etch rate resistance.
  • U.S. Pat. App. 2002/0127763 (Sep. 12, 2002) teaches formation of an L-shaped spacer by in-situ oxide-nitride-oxide deposition using BTBAS and O 2 and NH 3 by LPCVD. There is provided a low-cost alternative L-shaped spacer, said to be better for gap-fill for a subsequent dielectric film.
  • a gate stack It may be desired during manufacture to protect a gate stack from corrosives, such as reactive ion etching (RIE), wet etch, etc., as in US App. 2003/0068855 A1 (Apr. 10, 2003), disclosing deposition of a nucleation (seed) layer of nitride deposited on a gate stack, followed by a nitride layer deposited on the seed layer by BTBAS. The carbon of the BTBAS nitride is used to protect the gate stack from corrosives.
  • RIE reactive ion etching
  • U.S. Pat. No. 6,586,814 discloses use of BTBAS nitride for STI formation, using the etch resistance property of BTBAS nitride to help erosion of STI fill.
  • U.S. Pat. App. 2003/0127697 A1 discloses that, to generate compression in the channel of a PFET, the active region of a plurality of transistors is divided for each gate electrode and a thin STI is formed between adjacent gate electrodes.
  • U.S. Pat. App. 2002/0063292 A1 discloses certain wafer orientation to generate local stress in the channel, and generally mentions a high-tensile nitride dielectric, but without specifically disclosing what measured value is meant by high-tensile or what specific nitride is an example of a high-tensile nitride.
  • U.S. Pat. App. 2002/0179908 A1 (Dec. 5, 2002) teaches various ways of introducing impurities, and controls internal stress of wiring in a thin film transistor (TFT) by introducing impurities and annealing.
  • nitride liner 1 such as a nitride film
  • a device 2 having a device active layer 21 .
  • nitride film Conventionly have been available for wafer fabrication, providing different types of stress.
  • Novellus plasma enhanced chemical vapor deposition (PECVD), Applied PECVD, and Applied Materials rapid thermal chemical vapor deposition (RTCVD) tools can provide Tensile Nitride films, and the stress is usually up to +10 G dynes/cm 2 , with some examples according to conventional products being: Novellus, +2.5 G dynes/cm 2 ; PECVD, +4.5 G dynes/cm 2 ; RTCVD SiH 4 , +9.8 G dynes/cm 2 .
  • nitride liner As another example of a nitride liner, see U.S. Pat. App. 2003/0040158 A1, in which are disclosed two separate liners with different stress to improve mobility. One liner is made by LPCVD and the other liner is made by PECVD.
  • nitride liners and other films have not necessarily provided all of the characteristics that may be desirable for field effect transistors (FETs) and other applications.
  • FETs field effect transistors
  • nitride films used as a nitride liner have not been able to provide as much stress as would be desirable while balancing other needed characteristics.
  • the present inventors have especially considered that local mechanical stress (compressive or tensile stress) enhances the channel mobility and drive current in a field effect transistor (FET).
  • FET field effect transistor
  • Tensile stress in the nFET and compressive stress in the pFET can enhance the carrier mobility individually.
  • the present invention has as an objective to provide a desirable stress for FET applications, such as a sufficiently high-stress (such as stress exceeding +10 G dynes/cm, 2 such as, in a preferred example, stress of about +14.5 G dynes/cm 2 ) for an etch stop liner.
  • the present invention also has an objective to provide a material that continues to exhibit the desired high-stress after repeated annealing.
  • a film e.g., an RTCVD nitride film
  • a starting material precursor used to make the film such as, e.g., a compound containing Si, C and N in any combination, preferably, BTBAS
  • a treating material with which is treated the starting material precursor such as a nitrogen-containing precursor, preferably, a material suitable for forming a nitride film, most preferably, NH 3
  • a ratio of the starting material precursor to the treating material CVD conditions under which the film is grown (such as, e.g., RTCVD conditions); and/or a thickness to which the film is grown.
  • RTCVD rapid thermal chemical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • the reaction is carried out with a carbon concentration of 3 to 15 atomic %.
  • the compound comprising Si, N and C preferably may be (R—NH) 4 ⁇ n SiX n (I) wherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen.
  • a most preferable compound comprising Si, N and C is bis-tertiary butyl amino silane (BTBAS).
  • the present invention provides a process of producing a nitride film, comprising: reacting, under RTCVD conditions, PECVD conditions or LPCVD conditions, at a temperature in a range of about 500 to 700° C., at a pressure in a range of about 50 to 500 T, (A) a compound comprising Si, N and C in any combination, with (B) a nitrogen containing precursor (such as, e.g., NH 3 .).
  • inventive processes and methods are as follows.
  • addition of at least one chemical compound such as, e.g., silane, disilane, hexachloro disilane and other silane-based compounds.
  • the reacting step may be conducted at a temperature n a range of about 500 to 700° C.
  • the reacting step may be conducted at a pressure in a range of about 50 to 500 T.
  • a silicon nitride film comprising a film with a high stress provision in an amount exceeding +10 G dynes/cm 2 , such as, for example, a film comprising a reaction product of bis-tertiary butyl amino silane (BTBAS) and NH 3 (such as, e.g., a reaction product having a chemical structure of Si x N y C z H w wherein x, y, z and w are each an integer or non-integer greater than zero); a film that is stress-providing in a range of about +14 to +18 G dynes/cm 2 ; etc.
  • BBAS bis-tertiary butyl amino silane
  • NH 3 such as, e.g., a reaction product having a chemical structure of Si x N y C z H w wherein x, y, z and w are each an integer or non-integer greater than zero
  • the invention in a further preferred embodiment provides a method of semiconductor wafer manufacture, comprising: covering at least part of a device active layer with a silicon nitride liner having a tensile stress exceeding +10 G dynes/cm 2 (preferably, tensile stress of at least +14.5 G dynes/cm 2 ), such as, e.g., preferably, a silicon nitride liner comprising a nitride film which is a reaction product of BTBAS and NH 3 .
  • all of the device active layer is covered with the silicon nitride liner.
  • the covering step may be, for example, during a RTCVD process or other CVD process.
  • the invention in yet another preferred embodiment provides a nitride liner formed by a RTCVD, PECVD, or LPCVD process.
  • a preferred example of such an inventive liner is one comprising a nitride film which is a reaction product of, for example, BTBAS and NH 3 .
  • Another preferred example of an inventive liner is a liner wherein the nitride film has a tensile stress exceeding +10 G dynes/cm 2 , such as, for example, a nitride liner wherein the nitride film has a tensile stress of at least +14.5 G dynes/cm 2 .
  • Another preferred example of an inventive liner is a nitride liner is an ammonia-treated BTBAS reaction product that maintains a relatively-high stress level after repeated annealing.
  • the present invention in another preferred embodiment provides a method of adjusting a stress level of a nitride film, comprising adjusting at least two selected from the group consisting of: (1) a selection of a starting material precursor (such as, for example, a starting material precursor that is a compound containing Si, C and N in any combination, such as, preferably, BTBAS) used to make the nitride film; (2) a selection of a nitrogen-containing precursor (such as, preferably, NH 3 ) with which is treated the starting material precursor; (3) a ratio of the starting material precursor to the nitrogen-containing precursor; (4) a set of CVD conditions (such as RTCVD conditions, etc.) under which the film is grown; and (5) a thickness to which the film is grown (such as, e.g., thickness in a range of about 50 to 1,000 angstroms, etc.).
  • a starting material precursor such as, for example, a starting material precursor that is a compound containing Si, C and N in any combination, such as
  • the CVD conditions are at a temperature in a range of about 500-700° C. at a pressure in a range of about 50 to 500 T for a time in a range of about 30 to 600 seconds.
  • the inventive stress level adjustment method provides for the stress level of a nitride film to be adjusted to a range of +10 G to +18 G dynes/cm 2 .
  • the nitride film is an ammonia-treated BTBAS film.
  • FIG. 1 is a conventional assembly including a nitride liner covering a device active layer.
  • FIG. 2 is a chart showing compressive and tensile stress, for films after nitride deposition, including conventional films and a film (BTBAS) according to the present invention.
  • FIG. 3 are graphs of Ioff versus Ion for nFETs, including a conventional nFET according to a PECVD method and an inventive nFET (BTBAS).
  • FIG. 4 are graphs of Ioff versus Ion for pFETs, including a conventional pFET according to a PECVD method and an inventive pFET (BTBAS).
  • FIG. 5 are Iodlin data, showing the relationship between PECVD (conventional) and BTBAS (inventive) data.
  • FIG. 6 is a graph for heater temperature 675° C., pressure 275 torr, BTBAS flow 1slm.
  • the diamond points show stress and the box points show rate.
  • the x-axis is for ammonia flow (sccm); the left y-axis shows stress; the right y-axis shows deposition rate.
  • FIG. 7 is the chemical structure for bis-tertiary butyl amino silane (BTBAS).
  • the present invention in a particularly preferred embodiment provides a method of adjusting a stress level of a film (such as, e.g., a nitride film), by manipulating two or more of the following:
  • a starting material precursor used to make the film such as, e.g., a compound containing Si, C and N in any combination, of which a preferred example is BTBAS);
  • a nitrogen-containing precursor with which is treated the starting material precursor (with a preferred example of a nitrogen-containing precursor being a material suitable for forming a nitride film, most preferably, NH 3 );
  • a set of CVD conditions under which the film is grown such as, e.g., RTCVD conditions, preferably, RTCVD conditions at a temperature in a range of about 500-700° C. at a pressure in a range of about 50-500 T for a time in a range of about 30-600 seconds; and/or
  • a thickness to which the film is grown (such as, e.g., a thickness in a range of about 50 to 1,000 Angstroms.
  • the starting material precursor used to make the film and the nitrogen-containing precursor are selected to form a nitride film, with a particularly preferred combination being a reaction of BTBAS precursor with NH 3 gas to form a nitride film.
  • a nitride film formed from ammonia-treated BTBAS may be manipulated to have a high stress level (e.g., a stress level exceeding +10 G dynes/cm 2 ) with a particular value for stress level within a range of about +10 G dynes/cm 2 to +18 G dynes/cm 2 being selectable as desired by manipulation of one or more of the remaining manipulation factors, i.e., the ratio of the starting material precursor to the nitrogen-containing precursor; the set of CVD conditions under which the film is grown; and/or the thickness to which the film is grown.
  • a high stress level e.g., a stress level exceeding +10 G dynes/cm 2
  • the remaining manipulation factors i.e., the ratio of the starting material precursor to the nitrogen-containing precursor
  • the set of CVD conditions under which the film is grown i.e., the ratio of the starting material precursor to the nitrogen-containing precursor
  • the set of CVD conditions under which the film is grown and/
  • FIG. 1 shows an exemplary wafer fabrication assembly 4 , in which heavy mechanical stress can be produced by a nitride liner 1 (which may be a conventional nitride liner or a nitride liner according to the present invention) covering the active layer 21 of the device 2 .
  • the present invention provides superior performance (such as greater and/or different type of stress) compared to that provided by conventional examples of nitride films that have been available for wafer fabrication (such as use as liner 1 in an assembly 4 ).
  • FIG. 1 is provided by way of illustration and the present invention should not be considered limited to an arrangement according to FIG. 1 .
  • the present invention advantageously provides stress that is greater and/or different than that provided by conventional tools (of which some examples are, e.g., Novellus PECVD, Applied PECVD, and Applied Materials RTCVD tools, which have provided Tensile Nitride films with stress usually up to about +10 G dynes/cm 2 for those conventional films, as shown in FIG. 2 ).
  • conventional tools of which some examples are, e.g., Novellus PECVD, Applied PECVD, and Applied Materials RTCVD tools, which have provided Tensile Nitride films with stress usually up to about +10 G dynes/cm 2 for those conventional films, as shown in FIG. 2 ).
  • the present invention advantageously provides a film with relatively high tensile stress (such as, for example, tensile stress in excess of +10 G dynes/cm, 2 such as, in a preferred example of about +14.5 G dynes/cm 2 ) than provided by the conventional nitride films. Also advantageously, unlike many conventional films, this stress provided by films according to the invention does not change significantly after subsequent anneals.
  • BTBAS bis-tertiary butyl amino silane
  • the compound comprising Si, N and C (such as, e.g., BTBAS) is reacted with a suitable film-forming reagent such as, e.g., NH 3 , preferably with NH 3 under conditions for nitride-film forming, most preferably with NH 3 under conditions for forming a nitride film of desired stress measurement (such as, e.g., stress exceeding +10 G dynes/cm 2 , preferably, stress in a range of about +14 to +18 G dynes/cm 2 ) and/or other characteristics (such as maintainability of a stress characteristic through repeated annealing).
  • a suitable film-forming reagent such as, e.g., NH 3 , preferably with NH 3 under conditions for nitride-film forming, most preferably with NH 3 under conditions for forming a nitride film of desired stress measurement (such as, e.g., stress exceeding +10 G dynes
  • the reaction according to the present invention in which the compound comprising Si, N and C (such as, e.g, a BTBAS precursor) is used as a starting material may be conducted, e.g., under RTCVD conditions (most preferably, in a RTCVD tool, such as, for example, an Applied Material Centura RTCVD tool which is commercially available); under PECVD conditions; under LPCVD conditions, etc.
  • RTCVD conditions most preferably, in a RTCVD tool, such as, for example, an Applied Material Centura RTCVD tool which is commercially available
  • PECVD conditions under PECVD conditions
  • under LPCVD conditions etc.
  • the invention provides high-stress-level films, such as, in a particularly preferred example, an RTCVD ammonia-treated BTBAS nitride film.
  • the stress level of a film may be manipulated by the film thickness, such as by thickening the film (through increased amounts of the C, Si and N containing starting material (such as BTBAS) and the treating material (such as NH 3 ) or by increasing the deposition time to increase the stress level.
  • the films (such as nitride films) of the present invention may be used, for example, as an etch stop (barrier) nitride liner such as liner 1 in FIG. 1 . It will be appreciated that FIG. 1 is exemplary and that a liner according to the present invention may be used in other configurations. Additionally, the films (such as nitride films) of the present invention may be used for a shallow trench isolation (STI) liner, a gate spacer, etc.
  • STI shallow trench isolation
  • the present invention provides films superior in certain ways (such as provision of high tensile stress and/or low variability in stress data) compared to conventional PECVD films.
  • conventionally many types of PECVD films have been used to produce some tensile stress, unfortunately most of those PECVD films cannot produce tensile stress as high as may be desired.
  • the present invention provides, in a particularly preferred embodiment, an RTCVD BTBAS Nitride film which desirably can provide higher tensile stress, such as, e.g., stress exceeding +10 G dynes/cm 2 , preferably, stress exceeding +10 G dynes/cm 2 , such as stress in a range of about +14 to +18 G dynes/cm 2 .
  • the invention provides a BTBAS Nitride film that has smaller variation in stress data than the PECVD films.
  • the stress obtained from a BTBAS nitride film according to the present invention is extremely repeatable, and also is not influenced easily by process parameters.
  • a BTBAS nitride film that withstands influence by process parameters is an advantage of the present invention.
  • films may be deposited in a thickness as desired, with a preferred range of film thickness being about 50 to 1,000 angstroms.
  • the present invention further provides for variability of the film thickness for giving a desired stress level.
  • a nitride film thickness can be varied to provide different stress levels as desired. In setting the nitride thickness, the application (such as use as an etch-stop liner) is considered.
  • the spacer nitrides should be carefully selected with regard to thickness and stress, taking into account that the improvement in stress given by films according to the invention compared to conventional films is due to the exertion of tensile stress at the corner of the gate. That is, because the improvement is due to the exertion of tensile stress at the corner of the gate, if the spacer is too thick, or has too high a stress, the effect of the inventive film (such as a BTBAS film) would be minimized. Accordingly, the spacer nitrides should be selected so as not to be too thick or to provide too high a stress for the particular application, when an inventive film (such as a BTBAS film) is used as an etch-stop liner.
  • an inventive film such as a BTBAS film
  • Inventive films have advantageous applications for tensile stress production, providing a spacer, and other applications known for RTCVD SiH 4 films or PECVD films for spacer formation.
  • the present invention provides spacers (such as BTBAS spacers) that give better conformity and loading effect than conventional nitride films.
  • a film (i.e., a nitride film) was deposited by reacting BTBAS and NH 3 in a single wafer reactor.
  • a process condition is selected which gives a carbon concentration of 3 to 15 atomic %.
  • FIGS. 3 and 4 show the electrical characteristics of the nFET and pFET.
  • BTBAS nitride film can provide higher nFET drive current compared with devices with PECVD Tensile Nit film (and PECVD Compressive Nit film). There is also no degradation on the pFET drive current, for the film according to the inventive example.
  • the nFET drive current improvement is dependent on the local strain, hence the device geometry and nitride thickness. In general, for a long width nFET device, BTBAS with 500 A in thickness can provide 8% nFET current improvement, with 750 A BTBAS giving extra 3% current improvement. There is also no degradation on the pFET drive current.
  • FIG. 5 Iodlin data suggests that the improvement of the nFET drive current is mainly due to better carrier mobility in the channel and the external resistance in the source and drain and under the spacer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Stress level of a nitride film is adjusted as a function of two or more of the following: identity of a starting material precursor used to make the nitride film; identity of a nitrogen-containing precursor with which is treated the starting material precursor; ratio of the starting material precursor to the nitrogen-containing precursor; a set of CVD conditions under which the film is grown; and/or a thickness to which the film is grown. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound containing silicon, nitrogen and carbon (such as bis-tertiary butyl amino silane (BTBAS)) with NH3 can provide advantageous properties, such as high stress and excellent performance in an etch-stop application. An ammonia-treated BTBAS film is particularly excellent in providing a high-stress property, and further having maintainability of that high-stress property over repeated annealing.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention generally relates to integrated circuit manufacture, and more particularly to thin films and their production and their uses in conferring advantages upon the semiconductor devices being manufactured, especially in rapid thermal chemical vapor deposition (RTCVD) processes.
  • 2. Background Description
  • Conventionally, various films have been produced for use in circuit manufacture (such as making transistors), in a variety of types of chemical vapor deposition (CVD) processes. Examples of the various CVD processes are low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), rapid thermal chemical vapor deposition (RTCVD), cyclic deposition (CLD), atomic layer deposition (ALD), and mixed deposition (MLD) (i.e., a mixture of CLD and ALD); etc. The respective deposition processes differ significantly from each other as to their conditions (temperature, pressure, flow, etc.), equipment, parameters (substrate, time, etc.) and other variables.
  • Across these different kinds of deposition processes, different film production methods and films have been disclosed.
  • As an example films produced in LPCVD processes, U.S. Pat. No. 5,874,368 (Feb. 23, 1999) discloses formation of silicon nitrides from bis-tertiary butyl amino silane (BTBAS), in an LPCVD furnace, with pressure in a range of 20 mTorr to 2 Torr and a temperature range of 500-800° C. Also see Laxman et al., “A low-temperature solution for silicon nitride deposition,” Solid State Technology, April 2000, 79, disclosing LPCVD at 550-600° C.
  • U.S. Pat. No. 6,046,494 (Apr. 4, 2000) discloses forming an insulating layer in a semiconductor device at a relatively low temperature and without plasma for lower negative bias temperature instability and reduced dopant segregation. Methods are described for how to make a silicon nitride liner in a LPCVD furnace. For making the nitride layer, a chlorinated silane gas is used.
  • Another deposition that takes place during LPCVD, in an LPCVD batch furnace, is that of U.S. Pat. No. 6,268,299 (Jul. 31, 2001) disclosing formation of silicon-rich silicon nitride films used for barrier application. The silicion nitride films are deposited using various silicon containing precursors, e.g., bis-tertiary butyl amino silane (BTBAS), HCD, SiH4, etc., and NH3. The silicon to nitrogen ratio is modulated by changing the flow ratio of the silicon-containing precursor and NH3.
  • U.S. Pat. No. 6,268,299 (Jul. 31, 2001) discloses a low temperature process for depositing barrier nitrides using SiH4, dichlorosilane (DCS), BTBAS, HCD and mixtures of these gases in an LPCVD process. The flow ratio of NH3 to the precursors was varied to give different Si:N ratios.
  • Japanese Patent 20030S 1452 (Feb. 21, 2003) discloses BTBAS nitride deposition by an LPCVD furnace. Film thickness accuracy is said to be improved by optimizing the cleaning process.
  • Another film produced using an LPCVD furnace is that of JP 2001230248A (Nov. 26, 2002), disclosing BTBAS nitride deposition using an LPCVD furnace.
  • LPCVD, of course, is but one known class of CVD processes. Other manufacturing processes include PECVD and HDPCVD processes.
  • As an example of films made during PECVD and HDPCVD processes, see, for example, U.S. Pat. App. 2002/0090835 A1 (Jul. 11, 2002), by some of the same inventors as the present invention, disclosing formation of nitride films by BTBAS and related compounds with plasma energy, to give carbon incorporation, with particular suitability for PECVD and HDPCVD processes.
  • Other deposition processes include CLD, ALD and MLD. As an example of films made by CLD, ALD and MLD processes, see, e.g., U.S. Pat. App. 2003/0059535 A1 (Mar. 27, 2003). Deposition by CLD, ALD and MLD is disclosed for silicon nitride and other materials, using a variety of precursors. The reactions are carried out in cold-wall reactors.
  • Another category of deposition is that of RTCVD. Some films have been produced in RTCVD processes. For example, U.S. Pat. No. 6,153,261 (Nov. 28, 2000) discloses deposition of silicon nitride and oxide using BTBAS in an RTCVD process. See also U.S. Pat. App. 2001/0000476 A1 (Apr. 26, 2001).
  • U.S. Pat. No. 6,455,389 (Sep. 24, 2002) discloses an RTCVD process in which is formed a space layer that is a silicon nitride. Silane or dichloride silane is reacted with ammonia to form silicon nitride. Huang et al. describe an RTCVD process generally as having the temperature of the chamber is about 650 to 700° C. and the pressure of the chamber is about 200 to 600 torr, with the proceeding time of the RTCVD deposition process being about 2 to 4 minutes.
  • Nitride films are used in many different applications. However, the question of satisfying a particular application is multi-variate and may be relatively complicated. Turning, for example, to semiconductor devices, many different properties are important for advantageous functioning of a particular device. There are many competing considerations for manufacturing a particular device. A variety of different manufacturing techniques have been suggested, of which the following are only some examples.
  • For example, on the one hand, high carbon incorporation may be desired. U.S. Pat. App. 2001/0034129 A1 (Oct. 25, 2001) discloses an etching process for layers with high carbon concentration. The deposition uses TEOS, BTBAS, CCl4, CO2, etc. Spacers maybe formed by CVD using BTBAS and NH3.
  • U.S. Pat. App. 2002/0111039 (Aug. 15, 2002) discloses certain silicon oxynitride spacers with low dielectric constant formed by BTBAS and nitrogen containing gases, with stoichiometry and other properties controlled to give a varied wet etch rate. Carbon incorporation is taught, to improve dry etch rate resistance.
  • U.S. Pat. App. 2002/0127763 (Sep. 12, 2002) teaches formation of an L-shaped spacer by in-situ oxide-nitride-oxide deposition using BTBAS and O2 and NH3 by LPCVD. There is provided a low-cost alternative L-shaped spacer, said to be better for gap-fill for a subsequent dielectric film.
  • It may be desired during manufacture to protect a gate stack from corrosives, such as reactive ion etching (RIE), wet etch, etc., as in US App. 2003/0068855 A1 (Apr. 10, 2003), disclosing deposition of a nucleation (seed) layer of nitride deposited on a gate stack, followed by a nitride layer deposited on the seed layer by BTBAS. The carbon of the BTBAS nitride is used to protect the gate stack from corrosives.
  • U.S. Pat. No. 6,586,814 discloses use of BTBAS nitride for STI formation, using the etch resistance property of BTBAS nitride to help erosion of STI fill.
  • U.S. Pat. App. 2003/0127697 A1 (Jul. 10, 2003) discloses that, to generate compression in the channel of a PFET, the active region of a plurality of transistors is divided for each gate electrode and a thin STI is formed between adjacent gate electrodes.
  • In the case of semiconductor transistors, another property which has received some discussion is that of stress. For example, U.S. Pat. App. 2002/0063292 A1, discloses certain wafer orientation to generate local stress in the channel, and generally mentions a high-tensile nitride dielectric, but without specifically disclosing what measured value is meant by high-tensile or what specific nitride is an example of a high-tensile nitride.
  • U.S. Pat. App. 2002/0179908 A1 (Dec. 5, 2002) teaches various ways of introducing impurities, and controls internal stress of wiring in a thin film transistor (TFT) by introducing impurities and annealing.
  • U.S. Pat. No. 6,573,172 (Jun. 3, 2003) discloses formation of PECVD nitride films with different stress levels, on PMOS and NMOS devices.
  • Of course, optimizing any one property (such as a stress-related property) for a semiconductor device still must be balanced with satisfying many other necessary properties and performance considerations.
  • Also by way of background, in circuit manufacture, there has been used an assembly such as that shown in FIG. 1, in which, during wafer fabrication, a nitride liner 1 (such as a nitride film) covers a device 2 having a device active layer 21. Different types of nitride film conventionally have been available for wafer fabrication, providing different types of stress. Novellus plasma enhanced chemical vapor deposition (PECVD), Applied PECVD, and Applied Materials rapid thermal chemical vapor deposition (RTCVD) tools can provide Tensile Nitride films, and the stress is usually up to +10 G dynes/cm2, with some examples according to conventional products being: Novellus, +2.5 G dynes/cm2; PECVD, +4.5 G dynes/cm2; RTCVD SiH4, +9.8 G dynes/cm2.
  • As another example of a nitride liner, see U.S. Pat. App. 2003/0040158 A1, in which are disclosed two separate liners with different stress to improve mobility. One liner is made by LPCVD and the other liner is made by PECVD.
  • However, the conventional films and methods for producing nitride liners and other films have not necessarily provided all of the characteristics that may be desirable for field effect transistors (FETs) and other applications. For example, conventionally, nitride films used as a nitride liner have not been able to provide as much stress as would be desirable while balancing other needed characteristics. Nor are there adequately simple, feasible production methodologies for making films and semiconductor devices (such as FETs) to have desired characteristics.
    • SUMMARY OF THE INVENTION
  • The present inventors have especially considered that local mechanical stress (compressive or tensile stress) enhances the channel mobility and drive current in a field effect transistor (FET). Tensile stress in the nFET and compressive stress in the pFET can enhance the carrier mobility individually. Thus, the present invention has as an objective to provide a desirable stress for FET applications, such as a sufficiently high-stress (such as stress exceeding +10 G dynes/cm,2 such as, in a preferred example, stress of about +14.5 G dynes/cm2) for an etch stop liner.
  • Moreover, the present invention also has an objective to provide a material that continues to exhibit the desired high-stress after repeated annealing.
  • The present inventors have determined that the stress provided by a film (e.g., an RTCVD nitride film) may be manipulated as a function of a combination of two or more of the following: a starting material precursor used to make the film (such as, e.g., a compound containing Si, C and N in any combination, preferably, BTBAS); a treating material with which is treated the starting material precursor (such as a nitrogen-containing precursor, preferably, a material suitable for forming a nitride film, most preferably, NH3); a ratio of the starting material precursor to the treating material; CVD conditions under which the film is grown (such as, e.g., RTCVD conditions); and/or a thickness to which the film is grown.
  • It is a further object of the present invention to provide a method of producing a high-stress nitride film, comprising: reacting a compound comprising Si, N and C in any combination (with such a compound preferably being a non-chlorine compound), with NH3, under rapid thermal chemical vapor deposition (RTCVD) conditions, plasma-enhanced chemical vapor deposition (PECVD) conditions or low pressure chemical vapor deposition (LPCVD) conditions, wherein from the reacting step is formed a high-stress film with a stress provision value exceeding +10 G dynes/cm2. Some optional details for the above-mentioned method are as follows. In a preferred embodiment of such an inventive method, the reaction is carried out with a carbon concentration of 3 to 15 atomic %. The compound comprising Si, N and C preferably may be
    (R—NH)4−nSiXn   (I)
    wherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen. A most preferable compound comprising Si, N and C is bis-tertiary butyl amino silane (BTBAS).
  • In another preferred embodiment, the present invention provides a process of producing a nitride film, comprising: reacting, under RTCVD conditions, PECVD conditions or LPCVD conditions, at a temperature in a range of about 500 to 700° C., at a pressure in a range of about 50 to 500 T, (A) a compound comprising Si, N and C in any combination, with (B) a nitrogen containing precursor (such as, e.g., NH3.).
  • Further preferred embodiments of such inventive processes and methods are as follows. There may be further included, during the reacting step, addition of at least one chemical compound, such as, e.g., silane, disilane, hexachloro disilane and other silane-based compounds. There may from the reacting step be formed a film having a stress-provision value in an amount exceeding +10 G dynes/cm2. The reacting step may be conducted at a temperature n a range of about 500 to 700° C. The reacting step may be conducted at a pressure in a range of about 50 to 500 T.
  • Another preferred embodiment of the invention provides a silicon nitride film, comprising a film with a high stress provision in an amount exceeding +10 G dynes/cm2, such as, for example, a film comprising a reaction product of bis-tertiary butyl amino silane (BTBAS) and NH3 (such as, e.g., a reaction product having a chemical structure of SixNyCzHw wherein x, y, z and w are each an integer or non-integer greater than zero); a film that is stress-providing in a range of about +14 to +18 G dynes/cm2; etc.
  • The invention in a further preferred embodiment provides a method of semiconductor wafer manufacture, comprising: covering at least part of a device active layer with a silicon nitride liner having a tensile stress exceeding +10 G dynes/cm2 (preferably, tensile stress of at least +14.5 G dynes/cm2), such as, e.g., preferably, a silicon nitride liner comprising a nitride film which is a reaction product of BTBAS and NH3. In one preferred embodiment of the inventive method of semiconductor manufacture, all of the device active layer is covered with the silicon nitride liner. The covering step may be, for example, during a RTCVD process or other CVD process.
  • The invention in yet another preferred embodiment provides a nitride liner formed by a RTCVD, PECVD, or LPCVD process. A preferred example of such an inventive liner is one comprising a nitride film which is a reaction product of, for example, BTBAS and NH3. Another preferred example of an inventive liner is a liner wherein the nitride film has a tensile stress exceeding +10 G dynes/cm2, such as, for example, a nitride liner wherein the nitride film has a tensile stress of at least +14.5 G dynes/cm2. Another preferred example of an inventive liner is a nitride liner is an ammonia-treated BTBAS reaction product that maintains a relatively-high stress level after repeated annealing.
  • It also should be appreciated that the present invention in another preferred embodiment provides a method of adjusting a stress level of a nitride film, comprising adjusting at least two selected from the group consisting of: (1) a selection of a starting material precursor (such as, for example, a starting material precursor that is a compound containing Si, C and N in any combination, such as, preferably, BTBAS) used to make the nitride film; (2) a selection of a nitrogen-containing precursor (such as, preferably, NH3) with which is treated the starting material precursor; (3) a ratio of the starting material precursor to the nitrogen-containing precursor; (4) a set of CVD conditions (such as RTCVD conditions, etc.) under which the film is grown; and (5) a thickness to which the film is grown (such as, e.g., thickness in a range of about 50 to 1,000 angstroms, etc.). In one preferred example, the CVD conditions are at a temperature in a range of about 500-700° C. at a pressure in a range of about 50 to 500 T for a time in a range of about 30 to 600 seconds. In a preferred embodiment, the inventive stress level adjustment method provides for the stress level of a nitride film to be adjusted to a range of +10 G to +18 G dynes/cm2. In another preferred example, the nitride film is an ammonia-treated BTBAS film.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of the preferred embodiments of the invention with reference to the drawings, in which:
  • FIG. 1 is a conventional assembly including a nitride liner covering a device active layer.
  • FIG. 2 is a chart showing compressive and tensile stress, for films after nitride deposition, including conventional films and a film (BTBAS) according to the present invention.
  • FIG. 3 are graphs of Ioff versus Ion for nFETs, including a conventional nFET according to a PECVD method and an inventive nFET (BTBAS).
  • FIG. 4 are graphs of Ioff versus Ion for pFETs, including a conventional pFET according to a PECVD method and an inventive pFET (BTBAS).
  • FIG. 5 are Iodlin data, showing the relationship between PECVD (conventional) and BTBAS (inventive) data.
  • FIG. 6 is a graph for heater temperature 675° C., pressure 275 torr, BTBAS flow 1slm. The diamond points show stress and the box points show rate. The x-axis is for ammonia flow (sccm); the left y-axis shows stress; the right y-axis shows deposition rate.
  • FIG. 7 is the chemical structure for bis-tertiary butyl amino silane (BTBAS).
    • DETAILED DESCRIPTION OF CERTAIN PREFERRED EMBODIMENTS OF THE INVENTION
  • The present invention in a particularly preferred embodiment provides a method of adjusting a stress level of a film (such as, e.g., a nitride film), by manipulating two or more of the following:
  • a starting material precursor used to make the film (such as, e.g., a compound containing Si, C and N in any combination, of which a preferred example is BTBAS);
  • a nitrogen-containing precursor with which is treated the starting material precursor (with a preferred example of a nitrogen-containing precursor being a material suitable for forming a nitride film, most preferably, NH3);
  • a ratio of the starting material precursor to the nitrogen-containing precursor;
  • a set of CVD conditions under which the film is grown (such as, e.g., RTCVD conditions, preferably, RTCVD conditions at a temperature in a range of about 500-700° C. at a pressure in a range of about 50-500 T for a time in a range of about 30-600 seconds; and/or
  • a thickness to which the film is grown (such as, e.g., a thickness in a range of about 50 to 1,000 Angstroms.
  • In a preferred example according to the present inventive method of adjusting a stress level of a film, the starting material precursor used to make the film and the nitrogen-containing precursor are selected to form a nitride film, with a particularly preferred combination being a reaction of BTBAS precursor with NH3 gas to form a nitride film. A nitride film formed from ammonia-treated BTBAS may be manipulated to have a high stress level (e.g., a stress level exceeding +10 G dynes/cm2) with a particular value for stress level within a range of about +10 G dynes/cm2 to +18 G dynes/cm2 being selectable as desired by manipulation of one or more of the remaining manipulation factors, i.e., the ratio of the starting material precursor to the nitrogen-containing precursor; the set of CVD conditions under which the film is grown; and/or the thickness to which the film is grown.
  • The example of a nitride film is further discussed with reference to FIG. 1, showing an exemplary wafer fabrication assembly 4, in which heavy mechanical stress can be produced by a nitride liner 1 (which may be a conventional nitride liner or a nitride liner according to the present invention) covering the active layer 21 of the device 2. The present invention provides superior performance (such as greater and/or different type of stress) compared to that provided by conventional examples of nitride films that have been available for wafer fabrication (such as use as liner 1 in an assembly 4). It will be appreciated that FIG. 1 is provided by way of illustration and the present invention should not be considered limited to an arrangement according to FIG. 1. In a wafer fabrication assembly (such as the assembly 4 of FIG. 1), the present invention advantageously provides stress that is greater and/or different than that provided by conventional tools (of which some examples are, e.g., Novellus PECVD, Applied PECVD, and Applied Materials RTCVD tools, which have provided Tensile Nitride films with stress usually up to about +10 G dynes/cm2 for those conventional films, as shown in FIG. 2).
  • The present invention advantageously provides a film with relatively high tensile stress (such as, for example, tensile stress in excess of +10 G dynes/cm,2 such as, in a preferred example of about +14.5 G dynes/cm2) than provided by the conventional nitride films. Also advantageously, unlike many conventional films, this stress provided by films according to the invention does not change significantly after subsequent anneals.
  • For producing an exemplary film according to the present invention, there may be used as a starting material a compound comprising Si, N and C in any combination, of which a preferred example is a bis-tertiary butyl amino silane (BTBAS) precursor. BTBAS is a commercially available reagent, and, advantageously, is a non-chlorine precursor.
  • In the present invention, the compound comprising Si, N and C (such as, e.g., BTBAS) is reacted with a suitable film-forming reagent such as, e.g., NH3, preferably with NH3 under conditions for nitride-film forming, most preferably with NH3 under conditions for forming a nitride film of desired stress measurement (such as, e.g., stress exceeding +10 G dynes/cm2, preferably, stress in a range of about +14 to +18 G dynes/cm2) and/or other characteristics (such as maintainability of a stress characteristic through repeated annealing).
  • The reaction according to the present invention in which the compound comprising Si, N and C (such as, e.g, a BTBAS precursor) is used as a starting material may be conducted, e.g., under RTCVD conditions (most preferably, in a RTCVD tool, such as, for example, an Applied Material Centura RTCVD tool which is commercially available); under PECVD conditions; under LPCVD conditions, etc.
  • The invention provides high-stress-level films, such as, in a particularly preferred example, an RTCVD ammonia-treated BTBAS nitride film. The stress level of a film may be manipulated by the film thickness, such as by thickening the film (through increased amounts of the C, Si and N containing starting material (such as BTBAS) and the treating material (such as NH3) or by increasing the deposition time to increase the stress level.
  • The films (such as nitride films) of the present invention may be used, for example, as an etch stop (barrier) nitride liner such as liner 1 in FIG. 1. It will be appreciated that FIG. 1 is exemplary and that a liner according to the present invention may be used in other configurations. Additionally, the films (such as nitride films) of the present invention may be used for a shallow trench isolation (STI) liner, a gate spacer, etc.
  • It will be appreciated that the present invention provides films superior in certain ways (such as provision of high tensile stress and/or low variability in stress data) compared to conventional PECVD films. Although conventionally many types of PECVD films have been used to produce some tensile stress, unfortunately most of those PECVD films cannot produce tensile stress as high as may be desired. The present invention provides, in a particularly preferred embodiment, an RTCVD BTBAS Nitride film which desirably can provide higher tensile stress, such as, e.g., stress exceeding +10 G dynes/cm2, preferably, stress exceeding +10 G dynes/cm2, such as stress in a range of about +14 to +18 G dynes/cm2.
  • In addition, also beneficially, the invention provides a BTBAS Nitride film that has smaller variation in stress data than the PECVD films. On the other hand, the stress obtained from a BTBAS nitride film according to the present invention is extremely repeatable, and also is not influenced easily by process parameters. A BTBAS nitride film that withstands influence by process parameters is an advantage of the present invention.
  • In the present invention, films may be deposited in a thickness as desired, with a preferred range of film thickness being about 50 to 1,000 angstroms. The present invention further provides for variability of the film thickness for giving a desired stress level. For example, a nitride film thickness can be varied to provide different stress levels as desired. In setting the nitride thickness, the application (such as use as an etch-stop liner) is considered.
  • For example, for successfully using an inventive film (such as a BTBAS film) as an etch-stop liner, the spacer nitrides should be carefully selected with regard to thickness and stress, taking into account that the improvement in stress given by films according to the invention compared to conventional films is due to the exertion of tensile stress at the corner of the gate. That is, because the improvement is due to the exertion of tensile stress at the corner of the gate, if the spacer is too thick, or has too high a stress, the effect of the inventive film (such as a BTBAS film) would be minimized. Accordingly, the spacer nitrides should be selected so as not to be too thick or to provide too high a stress for the particular application, when an inventive film (such as a BTBAS film) is used as an etch-stop liner.
  • Inventive films (such as BTBAS films) have advantageous applications for tensile stress production, providing a spacer, and other applications known for RTCVD SiH4 films or PECVD films for spacer formation. Advantageously, the present invention provides spacers (such as BTBAS spacers) that give better conformity and loading effect than conventional nitride films.
  • Some inventive examples are given below, without the invention being limited to such examples.
    • INVENTIVE EXAMPLE 1
  • A film (i.e., a nitride film) was deposited by reacting BTBAS and NH3 in a single wafer reactor. A process condition is selected which gives a carbon concentration of 3 to 15 atomic %.
  • Device data was obtained that shows the drive current improvement compared to conventional films. FIGS. 3 and 4 show the electrical characteristics of the nFET and pFET. BTBAS nitride film can provide higher nFET drive current compared with devices with PECVD Tensile Nit film (and PECVD Compressive Nit film). There is also no degradation on the pFET drive current, for the film according to the inventive example. The nFET drive current improvement is dependent on the local strain, hence the device geometry and nitride thickness. In general, for a long width nFET device, BTBAS with 500 A in thickness can provide 8% nFET current improvement, with 750 A BTBAS giving extra 3% current improvement. There is also no degradation on the pFET drive current.
  • The FIG. 5 Iodlin data suggests that the improvement of the nFET drive current is mainly due to better carrier mobility in the channel and the external resistance in the source and drain and under the spacer.
    • INVENTIVE EXAMPLE 2
  • In an RTCVD process, BTBAS and NH3 are reacted, under the following conditions:
    Carbon concentration: ˜6 to 10%
    Temperature 650° C.
    Pressure 140 torr
    Dilane, disilane, hexachloro disilane? None

    Films of thickness 500 or 750 angstroms are formed. Other film thicknesses may be formed.
  • While the invention has been described in terms of its preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.

Claims (11)

1-14. (canceled)
15. A silicon nitride film, comprising a film with a high stress provision in an amount exceeding +10 G dynes/cm2.
16. The silicon nitride film of claim 15, wherein the film comprises a reaction product of bis-tertiary butyl amino silane (BTBAS) and NH3.
17. The silicon nitride film of claim 15, wherein the reaction product has a chemical structure of SixNyCzHw wherein x, y, z and w are each an integer or non-integer greater than zero.
18. The silicon nitride film of claim 15, wherein the film is stress-providing in a range of about +14 to +18 G dynes/cm2.
19-23. (canceled)
24. A nitride liner formed by a rapid thermal chemical vapor deposition (RTCVD), plasma-enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD) process, said liner comprising:
a nitride film which is a reaction product of bis-tertiary butyl amino silane (BTBAS) and NH3.
25. The nitride liner of claim 24, wherein the nitride film has a tensile stress exceeding +10 G dynes/cm2.
26. The nitride liner of claim 25, wherein the nitride film has a tensile stress of at least +14.5 G dynes/cm2.
27. The nitride liner of claim 24, wherein the ammonia-treated BTBAS reaction product maintains a relatively-high stress level after repeated annealing.
28-37. (canceled)
US11/253,622 2004-04-30 2005-10-20 Material for contact etch layer to enhance device performance Abandoned US20060040497A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/253,622 US20060040497A1 (en) 2004-04-30 2005-10-20 Material for contact etch layer to enhance device performance

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/835,949 US7001844B2 (en) 2004-04-30 2004-04-30 Material for contact etch layer to enhance device performance
US11/253,622 US20060040497A1 (en) 2004-04-30 2005-10-20 Material for contact etch layer to enhance device performance

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/835,949 Division US7001844B2 (en) 2004-04-30 2004-04-30 Material for contact etch layer to enhance device performance

Publications (1)

Publication Number Publication Date
US20060040497A1 true US20060040497A1 (en) 2006-02-23

Family

ID=35187673

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/835,949 Expired - Fee Related US7001844B2 (en) 2004-04-30 2004-04-30 Material for contact etch layer to enhance device performance
US11/253,622 Abandoned US20060040497A1 (en) 2004-04-30 2005-10-20 Material for contact etch layer to enhance device performance

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/835,949 Expired - Fee Related US7001844B2 (en) 2004-04-30 2004-04-30 Material for contact etch layer to enhance device performance

Country Status (4)

Country Link
US (2) US7001844B2 (en)
JP (1) JP4906270B2 (en)
CN (1) CN100459065C (en)
TW (1) TWI378505B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050085054A1 (en) * 2003-10-15 2005-04-21 Chakravarti Ashima B. Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion
US20100270622A1 (en) * 2006-02-01 2010-10-28 Texas Instruments Incorporated Semiconductor Device Having a Strain Inducing Sidewall Spacer and a Method of Manufacture Therefor
US8982254B2 (en) 2011-10-06 2015-03-17 Canon Kabushiki Kaisha Solid-state image sensor and manufacturing method thereof, and camera

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050287747A1 (en) * 2004-06-29 2005-12-29 International Business Machines Corporation Doped nitride film, doped oxide film and other doped films
US20060045986A1 (en) * 2004-08-30 2006-03-02 Hochberg Arthur K Silicon nitride from aminosilane using PECVD
US7268399B2 (en) * 2004-08-31 2007-09-11 Texas Instruments Incorporated Enhanced PMOS via transverse stress
US20060099763A1 (en) * 2004-10-28 2006-05-11 Yi-Cheng Liu Method of manufacturing semiconductor mos transistor device
JP2006165335A (en) * 2004-12-08 2006-06-22 Toshiba Corp Semiconductor device
US20060172556A1 (en) * 2005-02-01 2006-08-03 Texas Instruments Incorporated Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor
US7265015B2 (en) * 2005-06-30 2007-09-04 Promos Technologies Inc. Use of chlorine to fabricate trench dielectric in integrated circuits
JP5092751B2 (en) * 2005-12-19 2012-12-05 富士通株式会社 Semiconductor device and method for manufacturing the same
US8017472B2 (en) * 2006-02-17 2011-09-13 Infineon Technologies Ag CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof
US7790540B2 (en) * 2006-08-25 2010-09-07 International Business Machines Corporation Structure and method to use low k stress liner to reduce parasitic capacitance
JP2008053553A (en) * 2006-08-25 2008-03-06 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
US20080096331A1 (en) * 2006-10-04 2008-04-24 Neng-Kuo Chen Method for fabricating high compressive stress film and strained-silicon transistors
CN101192533B (en) * 2006-11-28 2010-06-16 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and etch stop layer forming method
US20080293194A1 (en) * 2007-05-24 2008-11-27 Neng-Kuo Chen Method of making a P-type metal-oxide semiconductor transistor and method of making a complementary metal-oxide semiconductor transistor
JP5309619B2 (en) * 2008-03-07 2013-10-09 ソニー株式会社 Semiconductor device and manufacturing method thereof
US9390909B2 (en) 2013-11-07 2016-07-12 Novellus Systems, Inc. Soft landing nanolaminates for advanced patterning
US8637411B2 (en) 2010-04-15 2014-01-28 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9373500B2 (en) 2014-02-21 2016-06-21 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
US9997357B2 (en) 2010-04-15 2018-06-12 Lam Research Corporation Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
US20110256734A1 (en) 2010-04-15 2011-10-20 Hausmann Dennis M Silicon nitride films and methods
US8956983B2 (en) 2010-04-15 2015-02-17 Novellus Systems, Inc. Conformal doping via plasma activated atomic layer deposition and conformal film deposition
US9257274B2 (en) 2010-04-15 2016-02-09 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
US9892917B2 (en) 2010-04-15 2018-02-13 Lam Research Corporation Plasma assisted atomic layer deposition of multi-layer films for patterning applications
US9611544B2 (en) 2010-04-15 2017-04-04 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9076646B2 (en) 2010-04-15 2015-07-07 Lam Research Corporation Plasma enhanced atomic layer deposition with pulsed plasma exposure
US8524612B2 (en) 2010-09-23 2013-09-03 Novellus Systems, Inc. Plasma-activated deposition of conformal films
US9685320B2 (en) 2010-09-23 2017-06-20 Lam Research Corporation Methods for depositing silicon oxide
KR101789592B1 (en) 2010-11-08 2017-10-25 삼성전자주식회사 Method of manufacturing a semiconductor device
US8647993B2 (en) 2011-04-11 2014-02-11 Novellus Systems, Inc. Methods for UV-assisted conformal film deposition
US8592328B2 (en) 2012-01-20 2013-11-26 Novellus Systems, Inc. Method for depositing a chlorine-free conformal sin film
US8728955B2 (en) 2012-02-14 2014-05-20 Novellus Systems, Inc. Method of plasma activated deposition of a conformal film on a substrate surface
US9355839B2 (en) 2012-10-23 2016-05-31 Lam Research Corporation Sub-saturated atomic layer deposition and conformal film deposition
SG2013083241A (en) 2012-11-08 2014-06-27 Novellus Systems Inc Conformal film deposition for gapfill
SG2013083654A (en) 2012-11-08 2014-06-27 Novellus Systems Inc Methods for depositing films on sensitive substrates
US8796098B1 (en) * 2013-02-26 2014-08-05 Cypress Semiconductor Corporation Embedded SONOS based memory cells
CN103247649A (en) * 2013-05-07 2013-08-14 上海华力微电子有限公司 Method for reducing electrical mutual disturbance of image sensor
US9214334B2 (en) 2014-02-18 2015-12-15 Lam Research Corporation High growth rate process for conformal aluminum nitride
US9478438B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method and apparatus to deposit pure titanium thin film at low temperature using titanium tetraiodide precursor
US9478411B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US10566187B2 (en) 2015-03-20 2020-02-18 Lam Research Corporation Ultrathin atomic layer deposition film accuracy thickness control
US9502238B2 (en) 2015-04-03 2016-11-22 Lam Research Corporation Deposition of conformal films by atomic layer deposition and atomic layer etch
US10526701B2 (en) 2015-07-09 2020-01-07 Lam Research Corporation Multi-cycle ALD process for film uniformity and thickness profile modulation
US9773643B1 (en) 2016-06-30 2017-09-26 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US10062563B2 (en) 2016-07-01 2018-08-28 Lam Research Corporation Selective atomic layer deposition with post-dose treatment
US10037884B2 (en) 2016-08-31 2018-07-31 Lam Research Corporation Selective atomic layer deposition for gapfill using sacrificial underlayer
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
US10541309B2 (en) * 2017-12-25 2020-01-21 United Microelectronics Corp Semiconductor structure and method for fabricating the same
SG11202111962QA (en) 2019-05-01 2021-11-29 Lam Res Corp Modulated atomic layer deposition

Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4365264A (en) * 1978-07-31 1982-12-21 Hitachi, Ltd. Semiconductor device with high density low temperature deposited Siw Nx Hy Oz passivating layer
US5874368A (en) * 1997-10-02 1999-02-23 Air Products And Chemicals, Inc. Silicon nitride from bis(tertiarybutylamino)silane
US6046494A (en) * 1994-09-30 2000-04-04 Intel Corporation High tensile nitride layer
US6153261A (en) * 1999-05-28 2000-11-28 Applied Materials, Inc. Dielectric film deposition employing a bistertiarybutylaminesilane precursor
US6268299B1 (en) * 2000-09-25 2001-07-31 International Business Machines Corporation Variable stoichiometry silicon nitride barrier films for tunable etch selectivity and enhanced hyrogen permeability
US20010034129A1 (en) * 1998-10-19 2001-10-25 Moore John T. Capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors and DRAMs
US6391803B1 (en) * 2001-06-20 2002-05-21 Samsung Electronics Co., Ltd. Method of forming silicon containing thin films by atomic layer deposition utilizing trisdimethylaminosilane
US20020063292A1 (en) * 2000-11-29 2002-05-30 Mark Armstrong CMOS fabrication process utilizing special transistor orientation
US20020090835A1 (en) * 2001-01-08 2002-07-11 Chakravarti Ashima B. Methods and materials for depositing films on semiconductor substrates
US20020111039A1 (en) * 2000-02-22 2002-08-15 Moore John T. Method of forming low dielectric silicon oxynitride spacer films highly selective to etchants
US20020127763A1 (en) * 2000-12-28 2002-09-12 Mohamed Arafa Sidewall spacers and methods of making same
US6486083B1 (en) * 2000-02-15 2002-11-26 Kokusai Electric Co., Ltd. Semiconductor device manufacturing method and semiconductor manufacturing apparatus
US20020179908A1 (en) * 2001-04-27 2002-12-05 Semiconductor Energy Laboratory Co., Ltd., Semiconductor device and method of manufacturing the same
US20030040158A1 (en) * 2001-08-21 2003-02-27 Nec Corporation Semiconductor device and method of fabricating the same
US20030059535A1 (en) * 2001-09-25 2003-03-27 Lee Luo Cycling deposition of low temperature films in a cold wall single wafer process chamber
US20030068855A1 (en) * 2000-02-22 2003-04-10 Moore John T. Method for forming protective films and spacers
US6573172B1 (en) * 2002-09-16 2003-06-03 Advanced Micro Devices, Inc. Methods for improving carrier mobility of PMOS and NMOS devices
US6586814B1 (en) * 2000-12-11 2003-07-01 Lsi Logic Corporation Etch resistant shallow trench isolation in a semiconductor wafer
US20030127697A1 (en) * 2002-01-10 2003-07-10 Hiroyuki Ohta Semiconductor device
US6660664B1 (en) * 2000-03-31 2003-12-09 International Business Machines Corp. Structure and method for formation of a blocked silicide resistor
US6812073B2 (en) * 2002-12-10 2004-11-02 Texas Instrument Incorporated Source drain and extension dopant concentration
US20050080286A1 (en) * 2003-10-10 2005-04-14 Ziyun Wang Composition and method for low temperature chemical vapor deposition of silicon-containing films including silicon carbonitride and silicon oxycarbonitride films
US6890869B2 (en) * 2000-08-18 2005-05-10 Tokyo Electron Limited Low-dielectric silicon nitride film and method of forming the same, semiconductor device and fabrication process thereof
US20060121746A1 (en) * 1999-11-24 2006-06-08 Kokusai Electric Co., Ltd. Semiconductor device manufacturing method and semiconductor manufacturing apparatus

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3211301B2 (en) * 1991-11-07 2001-09-25 カシオ計算機株式会社 Silicon nitride film
US20020062065A1 (en) * 1993-02-22 2002-05-23 Daniel S. Christopher Endoscopic retraction system and method
JP2002083812A (en) * 1999-06-29 2002-03-22 Semiconductor Energy Lab Co Ltd Wiring material and semiconductor device with the wiring material and its manufacturing device
JP2002198368A (en) * 2000-12-26 2002-07-12 Nec Corp Method for fabricating semiconductor device
JP4897159B2 (en) 2001-08-03 2012-03-14 株式会社日立国際電気 Manufacturing method of semiconductor device
US20050109276A1 (en) * 2003-11-25 2005-05-26 Applied Materials, Inc. Thermal chemical vapor deposition of silicon nitride using BTBAS bis(tertiary-butylamino silane) in a single wafer chamber

Patent Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4365264A (en) * 1978-07-31 1982-12-21 Hitachi, Ltd. Semiconductor device with high density low temperature deposited Siw Nx Hy Oz passivating layer
US6046494A (en) * 1994-09-30 2000-04-04 Intel Corporation High tensile nitride layer
US5874368A (en) * 1997-10-02 1999-02-23 Air Products And Chemicals, Inc. Silicon nitride from bis(tertiarybutylamino)silane
US20010034129A1 (en) * 1998-10-19 2001-10-25 Moore John T. Capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors and DRAMs
US6153261A (en) * 1999-05-28 2000-11-28 Applied Materials, Inc. Dielectric film deposition employing a bistertiarybutylaminesilane precursor
US20010000476A1 (en) * 1999-05-28 2001-04-26 Applied Materials, Inc. Dielectric film deposition employing a bistertiarybutylaminesilane precursor
US20060121746A1 (en) * 1999-11-24 2006-06-08 Kokusai Electric Co., Ltd. Semiconductor device manufacturing method and semiconductor manufacturing apparatus
US6486083B1 (en) * 2000-02-15 2002-11-26 Kokusai Electric Co., Ltd. Semiconductor device manufacturing method and semiconductor manufacturing apparatus
US20020111039A1 (en) * 2000-02-22 2002-08-15 Moore John T. Method of forming low dielectric silicon oxynitride spacer films highly selective to etchants
US20030068855A1 (en) * 2000-02-22 2003-04-10 Moore John T. Method for forming protective films and spacers
US6660664B1 (en) * 2000-03-31 2003-12-09 International Business Machines Corp. Structure and method for formation of a blocked silicide resistor
US6890869B2 (en) * 2000-08-18 2005-05-10 Tokyo Electron Limited Low-dielectric silicon nitride film and method of forming the same, semiconductor device and fabrication process thereof
US6268299B1 (en) * 2000-09-25 2001-07-31 International Business Machines Corporation Variable stoichiometry silicon nitride barrier films for tunable etch selectivity and enhanced hyrogen permeability
US20020063292A1 (en) * 2000-11-29 2002-05-30 Mark Armstrong CMOS fabrication process utilizing special transistor orientation
US6586814B1 (en) * 2000-12-11 2003-07-01 Lsi Logic Corporation Etch resistant shallow trench isolation in a semiconductor wafer
US20020127763A1 (en) * 2000-12-28 2002-09-12 Mohamed Arafa Sidewall spacers and methods of making same
US6500772B2 (en) * 2001-01-08 2002-12-31 International Business Machines Corporation Methods and materials for depositing films on semiconductor substrates
US20020090835A1 (en) * 2001-01-08 2002-07-11 Chakravarti Ashima B. Methods and materials for depositing films on semiconductor substrates
US20020179908A1 (en) * 2001-04-27 2002-12-05 Semiconductor Energy Laboratory Co., Ltd., Semiconductor device and method of manufacturing the same
US6391803B1 (en) * 2001-06-20 2002-05-21 Samsung Electronics Co., Ltd. Method of forming silicon containing thin films by atomic layer deposition utilizing trisdimethylaminosilane
US20030040158A1 (en) * 2001-08-21 2003-02-27 Nec Corporation Semiconductor device and method of fabricating the same
US20030059535A1 (en) * 2001-09-25 2003-03-27 Lee Luo Cycling deposition of low temperature films in a cold wall single wafer process chamber
US20030127697A1 (en) * 2002-01-10 2003-07-10 Hiroyuki Ohta Semiconductor device
US6573172B1 (en) * 2002-09-16 2003-06-03 Advanced Micro Devices, Inc. Methods for improving carrier mobility of PMOS and NMOS devices
US6812073B2 (en) * 2002-12-10 2004-11-02 Texas Instrument Incorporated Source drain and extension dopant concentration
US20050080286A1 (en) * 2003-10-10 2005-04-14 Ziyun Wang Composition and method for low temperature chemical vapor deposition of silicon-containing films including silicon carbonitride and silicon oxycarbonitride films

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050085054A1 (en) * 2003-10-15 2005-04-21 Chakravarti Ashima B. Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion
US7119016B2 (en) * 2003-10-15 2006-10-10 International Business Machines Corporation Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion
US20100270622A1 (en) * 2006-02-01 2010-10-28 Texas Instruments Incorporated Semiconductor Device Having a Strain Inducing Sidewall Spacer and a Method of Manufacture Therefor
US8982254B2 (en) 2011-10-06 2015-03-17 Canon Kabushiki Kaisha Solid-state image sensor and manufacturing method thereof, and camera

Also Published As

Publication number Publication date
TWI378505B (en) 2012-12-01
JP4906270B2 (en) 2012-03-28
US20050245081A1 (en) 2005-11-03
US7001844B2 (en) 2006-02-21
JP2005317980A (en) 2005-11-10
TW200536019A (en) 2005-11-01
CN100459065C (en) 2009-02-04
CN1694230A (en) 2005-11-09

Similar Documents

Publication Publication Date Title
US7001844B2 (en) Material for contact etch layer to enhance device performance
US7365029B2 (en) Method for silicon nitride chemical vapor deposition
US7253123B2 (en) Method for producing gate stack sidewall spacers
JP5890386B2 (en) Low temperature deposition of silicon-containing films
US7488694B2 (en) Methods of forming silicon nitride layers using nitrogenous compositions
US20060237846A1 (en) Doped nitride film, doped oxide film and other doped films and deposition rate improvement for rtcvd processes
US8906455B2 (en) Low temperature deposition of silicon-containing films
US20070082507A1 (en) Method and apparatus for the low temperature deposition of doped silicon nitride films
US20140273530A1 (en) Post-Deposition Treatment Methods For Silicon Nitride
US20060013946A1 (en) Methods of forming a thin film structure, and a gate structure and a capacitor including the thin film structure
US7166516B2 (en) Method for fabricating a semiconductor device including the use of a compound containing silicon and nitrogen to form an insulation film of SiN or SiCN
US7119016B2 (en) Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion
US20070196991A1 (en) Semiconductor device having a strain inducing sidewall spacer and a method of manufacture therefor
EP1312697A1 (en) CVD of dielectric films
US6235654B1 (en) Process for forming PECVD nitride with a very low deposition rate
JP2008010881A (en) Method for manufacturing semiconductor device
JP2003264285A (en) Semiconductor device and its manufacturing method
US6429149B1 (en) Low temperature LPCVD PSG/BPSG process
US6759346B1 (en) Method of forming dielectric layers
KR20200073452A (en) A Method of Silicon Insulating Film Deposition at Low Temperature
CN1420533A (en) System and method for enhancing dielectric film

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION