Nothing Special   »   [go: up one dir, main page]

US20050221579A1 - Semiconductor device and method of fabricating the same - Google Patents

Semiconductor device and method of fabricating the same Download PDF

Info

Publication number
US20050221579A1
US20050221579A1 US11/085,112 US8511205A US2005221579A1 US 20050221579 A1 US20050221579 A1 US 20050221579A1 US 8511205 A US8511205 A US 8511205A US 2005221579 A1 US2005221579 A1 US 2005221579A1
Authority
US
United States
Prior art keywords
trench
semiconductor substrate
etching
angle
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/085,112
Inventor
Takanori Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MATSUMOTO, TAKANORI
Publication of US20050221579A1 publication Critical patent/US20050221579A1/en
Priority to US11/611,030 priority Critical patent/US7781293B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Definitions

  • the present invention relates to a semiconductor device provided with trenches having high and low aspect ratios respectively and a method of fabricating the same.
  • STI shallow trench isolation
  • a semiconductor substrate with an etching pattern is disposed in a vacuum process chamber of a processing apparatus.
  • a reactive gas is then introduced into the chamber and a discharge plasma is generated so that reactive ions and radicals progress etching, whereby a trench is formed.
  • a film of insulating material is formed on the trench, whereupon the STI structure is obtained.
  • An amount and/or energy of each of ion and radical is adjusted so that an etched film is formed into a desired geometry or so that a deposited film has a high trench fill capability and high fabricating and film-forming speeds are ensured.
  • JP-A-2000-43413 discloses an improvement in the trench fill capability of the insulating film in the trench.
  • a taper angle of STI or an inclination of sidewalls relative to the trench bottom be reduced, that is, the inclination of trench sidewalls be gentler.
  • this method has the following inconvenience. That is, a distance between devices needs to be set to be shorter as miniaturization of the device structure progresses. In this case, when the taper angle is reduced in consideration of the aforementioned respect, a distance between portions where sidewalls intersect the bottom becomes shorter. Accordingly, limitations of a lower limit value of the taper angle become strict according to an opening width of the trench such that the limitations are difficult to cope with.
  • the taper angle When the taper angle is reduced as described above, an insulation distance between the devices becomes short such that the breakdown voltage is reduced. This results in a reduction in the function of STI, that is, function of isolating elements adjacent to each other. Accordingly, in order that the aforementioned inconvenience may be prevented, the taper angle needs to be maintained at a large value.
  • the conditions under which the opening width of the trench gives advantage to the trench fill capability is contrary to those under which the taper angle gives advantage to the trench fill capability. Under these conditions, the trench fill capability is hard to maintain at the level of the previous design rules.
  • the trench filling step needs to be repeated several times, instead of forming the insulating film at a single step so that the trench is completely filled with the insulating film. In this case, however, the productivity cannot be improved even if the trench fill capability can be satisfied. Additionally, it is difficult to reduce the costs.
  • an object of the present invention is to provide a semiconductor device in which a desirable trench fill capability of the insulating film in the trench with high aspect ration can be maintained even if the miniaturization of the device progresses, and a method of fabricating the same.
  • the present invention provides a semiconductor device comprising a semiconductor substrate having a surface, a first trench with a high aspect ratio formed in the surface of the semiconductor substrate and having a bottom, two sidewalls and an open end, the first trench being formed so that at the bottom side thereof, an inclination of each sidewall relative to the bottom has a first angle approximate to a right angle and at the bottom side, the inclination of each sidewall relative to the bottom has a second angle smaller than the first angle, and a second trench having a lower aspect ratio than the first trench, the second trench having a bottom, two sidewalls and an open end and being formed so that an inclination of each sidewall relative to the bottom thereof is substantially uniform from the bottom side to the open end side and has a third angle which is approximate to the second angle.
  • the invention also provides a method of fabricating a semiconductor device, comprising patterning an etching mask material so that trenches with higher and lower aspect ratios formed in a surface of a semiconductor substrate so as to open at the surface, respectively and etching the semiconductor substrate with the patterned etching mask using an etching gas made by mixing a halogen gas, a fluorocarbon gas and oxygen so that the trenches with the higher and lower aspect ratios respectively are simultaneously formed.
  • FIG. 1 is a typical section of a semiconductor device of one embodiment in accordance with the present invention, showing the state of the device after execution of a trench forming process;
  • FIG. 2 is a typical plan view of the semiconductor device, showing a state where a gate electrode has been formed
  • FIG. 3 is a typical section of the semiconductor device, showing the configuration of the trench in detail
  • FIGS. 4A to 4 D are typical sectional views of the semiconductor device corresponding to stages in the fabrication process
  • FIGS. 5A to 5 C show configurations of trenches compared with one another with respect to the trench fill capability
  • FIG. 6 is a graph showing dimensions indicative of the trench fill capability in different types of trenches
  • FIG. 7 is a graph showing the dimension indicative of the trench fill capability in the case where the curvature radius of the upper part of trench is changed.
  • FIG. 8 is a graph showing the dimension indicative of the trench fill capability in the case where the taper angle of the upper part of trench is changed.
  • FIG. 1 the state of the semiconductor device after execution of a trench forming process is shown.
  • FIG. 2 shows a control gate electrode.
  • FIG. 1 is a sectional view taken along line 1 - 1 in FIG. 2 .
  • Chips composing the flash memory each include a memory cell region in which a number of memory cells are formed and a peripheral circuit region in which peripheral circuits for driving the memory cells are formed.
  • a silicon substrate 1 serving as a semiconductor substrate has trenches 2 a and 2 b for forming element isolation regions.
  • the trenches 2 a and 2 b have opening widths A 1 and A 2 respectively and the same depth D as each other.
  • the trench 2 a has a higher aspect ratio R 1 (D/A 1 ) so as to correspond to a memory cell region 3
  • the trench 2 b has a lower aspect ratio R 2 (D/A 2 ) so as to correspond to the peripheral circuit region 4 .
  • Transistors formed in the peripheral circuit region 4 include at least one having a higher break-down voltage. Accordingly, the width A 2 of the trench 2 b is set to be larger that the width A 1 of the trench 2 a .
  • the trench 2 b has a bottom which is formed so that residue 5 is deposited without being etched. The residue 5 can be suppressed when an etching gas ratio which is one of etching conditions is optimized.
  • Three active regions 6 a , 6 b and 6 c are separately formed in the memory cell region 3 , a boundary and peripheral circuit region 4 respectively.
  • a silicon oxide film 7 serving as a gate insulating film
  • a polycrystalline silicon film 8 serving as a gate electrode material
  • a silicon nitride film 9 serving as a stopper in a chemical-mechanical polishing process
  • a silicon oxide film 10 serving as an etching mask for the substrate 1 sequentially in the active regions 6 a to 6 c.
  • silicon oxide films are buried in the respective trenches 2 a and 2 b so that STI structure regions 11 a and 11 b are formed. Further, control gate electrodes 12 are formed so as to extend across the active regions 6 a and 6 c.
  • FIG. 3 shows a section of a boundary where the trenches 2 a and 2 b with higher and lower aspect ratios respectively are adjacent to each other or the active regions 6 a and 6 b .
  • the trench 2 a is formed so that a width B 1 at the bottom thereof is smaller or narrower than a width A 1 at the upper opening in the silicon substrate 1 .
  • a taper angle is defined as an angle made by line L extending from a bottom end P 1 to an opening end P 2 and line H parallel to the bottom.
  • symbol “ ⁇ ” designates a taper angle of the trench 2 a
  • a sidewall 13 a of the trench 2 a rises up at the bottom end P 1 with a steeper inclination ⁇ 1 nearer to a right angle than the taper angle ⁇ .
  • the inclination ⁇ 1 is made by a tangent line S 1 along the sidewall 13 a at the bottom end P 1 and parallel line H.
  • the inclination of the sidewall 13 a gradually becomes gentler as the sidewall 13 a goes upward and has, at the opening end P 2 , a smaller inclination ⁇ 2 than the taper angle ⁇ .
  • the inclination ⁇ 2 is made by a tangent line S 2 along the sidewall 13 a at the opening end P 2 and parallel line H.
  • the sidewall 13 a of the trench 2 a has a rounded shape near the opening end P 2 while satisfying the above-described conditions. Consequently, the trench 2 a is formed so that a degree of opening is increased from the bottom toward the opening or so that the inner section thereof is trumpet-shaped.
  • a sidewall 13 b of the trench 2 b is formed so as to have, from the bottom end P 3 to the opening end P 4 , an inclination ⁇ 3 which is substantially equal to the taper angle ⁇ . Furthermore, the trench 2 b is formed so that an inclination ⁇ 3 at the opening end P 4 is substantially equal to the inclination ⁇ 2 at the opening end P 2 of the trench 2 a .
  • the aforementioned inclinations ⁇ 1, ⁇ 2 and ⁇ 3 serve as first, second and third inclinations respectively.
  • the inclinations ⁇ 2 and ⁇ 3 need not be substantially equal to each other but the inclination ⁇ 3 needs to be smaller than inclination ⁇ 1.
  • the trench 2 a is formed so that the inclination of the sidewall thereof is gentle near the opening and steep near the bottom.
  • the trench 2 b is formed so that the inclination of the sidewall thereof is smaller than that near the bottom of the trench 2 a and is uniform. Consequently, the trench fill capability of the silicon oxide film filling the interior of the trench is improved.
  • the reason for this would be that a capacity of the trench 2 a with the higher aspect ratio is decreased as compared with the other trench 2 a such that the trench fill capability is improved, as will be understood from the results of comparison later.
  • the silicon oxide film for filling the trench can be made by a single process, and a film thickness need not be increased for improvement of the trench fill capability. Consequently, the productivity can be improved.
  • the fabrication process up to the structure of FIG. 1 will be described with reference to FIGS. 4A to 4 D.
  • the silicon oxide film 7 serves as a gate insulating film of the floating gate.
  • the polycrystalline silicon film 8 constitutes a part of the floating gate (another polycrystalline silicon film will be deposited in a post-process).
  • the silicon nitride film 9 serves as a stopper in the chemical-mechanical polishing (CMP) process.
  • CMP chemical-mechanical polishing
  • the silicon oxide film 10 serves as a mask material in etching the silicon substrate 1 .
  • a resist 14 is applied so as to correspond to the active regions 6 a to 6 c and then exposed to light so as to be patterned, as shown in FIG. 4B .
  • the silicon oxide film 10 is etched with the resist 14 serving as a mask, and then, the resist 14 is removed, as shown in FIG. 4C .
  • the silicon nitride film 9 , polycrystalline silicon film 8 and silicon oxide film 7 are etched with the silicon oxide film 10 serving as a mask.
  • the silicon substrate 1 is etched using an etching gas in a reactive vacuum container of a processing apparatus so that the trenches 2 a and 2 b are formed.
  • the etching gas contains a halogen gas to which a fluorocarbon gas and oxygen are added.
  • the halogen gas includes Cl 2 (chlorine gas) and HBr (hydrogen bromide gas).
  • the fluorocarbon gas includes CF 4 , CHF 3 , CH 2 F 2 , C 5 F 8 and C 4 F 6 .
  • the halogen gas is mainly used for the etching.
  • the etched silicon is oxidized using oxygen such that silicon oxide is produced as a reaction product, which is deposited on the surface of the silicon substrate 1 .
  • the fluorocarbon gas has a function of re-etching the reaction product deposited as the silicon oxide resulting in residue, thereby blowing away the reaction product.
  • the silicon oxidized by oxygen becomes difficult to advance into the bottom side in the trench with the higher aspect ratio, namely, the trench 2 a of the memory cell region 3 .
  • An amount of silicon oxide is reduced as the bottom of the trench 2 a is dug downward by etching. Accordingly, the inclination of the sidewall 13 a is increased.
  • the trench 2 b with lower aspect ratio has a larger opening width A 2 , the silicon oxide is capable of reaching the bottom.
  • the sidewall 13 b is formed to have a gentle inclination ⁇ 3.
  • an amount of reaction product can be controlled or an amount of deposited reaction product can be controlled, whereupon the conditions under which a desired geometry of the trench can be achieved.
  • the above-described etching manner can form both trenches 2 a and 2 b by one time of etching process.
  • Specific etching conditions are as follows: regarding the gas flow rate, the halogen gas is set to a flow rate of about 70%, oxygen is set to a flow rate of about 20% and fluorocarbon gas is set to a flow rate of about 10%.
  • An etching pressure is set to about 20 mT and an RF power is set to about 500 W.
  • FIG. 5A shows the silicon substrate 1 having the trench 2 a of the embodiment.
  • FIG. 5B shows a silicon substrate 16 having a straight-tapered trench 15 .
  • FIG. 5C shows a silicon substrate 18 having a bowing trench 17 .
  • a silicon oxide film 19 is formed on each of the trenches 2 a , 15 and 17 to be used to measure the trench fill capability.
  • FIG. 6 shows the trench fill capabilities of the trenches 2 a , 15 and 17 of the silicon substrates 1 , 16 and 18 respectively.
  • Dimension BT (nm) indicative of the trench fill capability refers to the difference between an interface of the silicon substrate 1 and the silicon oxide film 7 and the trench bottom, as shown in FIG. 5A .
  • the results show that the trench 2 a of the embodiment has a largest dimension BT of the three, whereas the bowing trench 17 has a smallest dimension BT.
  • the trench fill capability was measured regarding the silicon substrate 1 of the embodiment and the silicon substrate 16 with the straight-tapered trench 15 .
  • the silicon substrate 1 had the dimension BT of 143 nm whereas the silicon substrate 16 had the dimension BT of 91 nm.
  • the silicon substrate 1 formed with the trench 2 a is superior to the other substrates in the trench fill capability.
  • the trench fill capability was evaluated regarding the silicon substrate 1 formed with the trench 2 a in a case where the inclination ⁇ 2 of the trench opening side was changed.
  • a rounded portion of the silicon substrate 1 at the opening side was approximated to a part of a circle, instead of the inclination ⁇ 2.
  • a curvature radius r of the rounded portion served as a parameter.
  • FIG. 7 shows that the trench fill capability can be improved (an increase in the dimension BT) with increase in the curvature radius r defined as described above. This signifies that the trench fill capability can be improved as the inclination ⁇ 2 is reduced.
  • the dimension BT during the trench filling process can be adjusted by controlling the curvature radius r. Consequently, the number and time of fabrication steps can each be reduced to about two thirds in the conventional number and time, whereupon the number of fabrication steps can be reduced.
  • the trench fill capability of the trench 2 a was evaluated by the simulation using a computer.
  • the sidewall 16 a of the trench 2 a was divided into three stages, that is, upper, middle and lower parts in the direction of depth. Taper angles of the respective divided regions were changed and then combined together.
  • the trench fill capability was evaluated in the same manner. Consequently, a degree of influence upon the trench fill capability was shown as upper inclined portion>middle inclined portion>lower inclined portion. As obvious from the results as shown in FIG. 8 , the trench fill capability was found to be improved when the inclined angle is gentler or when the curvature radius is larger.
  • the trench fill capability can be improved when the opening side has a large curvature radius r or when the taper angle ⁇ is gentle, the element isolating function ensuring sufficient insulating performance can be provided while the trench filling capability can be ensured.
  • the sidewall 16 a of the trench 2 a was divided into three stages. However, the number of divided states is optional. In this case, too, the similar effect to the above-described one can be achieved.
  • An etching gas other than those exemplified above may be used when it belongs to the same type of gas.
  • the mixing ratio or the flow rate may be set to a suitable value so that the same object as described above is achieved.
  • the invention may be applied to any type of non-volatile memory other than the flash memory. Additionally, the invention may be applied to any semiconductor device employing the arrangement in which a plurality of trenches having different aspect ratios and the trench interior is filled with an insulating film.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A semiconductor device includes a semiconductor substrate and first and second trenches. The first trench with a high aspect ratio is formed in a surface of the semiconductor substrate and has a bottom, two sidewalls and an open end. The first trench is formed so that at the bottom side, an inclination of each sidewall relative to the bottom has a first angle approximate to a right angle and at the bottom side, the inclination of each sidewall relative to the bottom has a second angle smaller than the first angle. The second trench has a lower aspect ratio than the first trench. The second trench has a bottom, two sidewalls and an open end and is formed so that an inclination of each sidewall relative to the bottom is substantially uniform from the bottom side to the open end side and has a third angle which is approximate to the second angle.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims priority from Japanese patent application No. 2004-85051, filed Mar. 23, 2004, the content of which is incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device provided with trenches having high and low aspect ratios respectively and a method of fabricating the same.
  • 2. Description of the Related Art
  • Semiconductor devices employ a shallow trench isolation (STI) structure in order that elements may be isolated from each other. A trench is formed in a semiconductor substrate and filled with an insulating material such as silicon oxide (SiO2), whereby the element isolating STI structure is formed.
  • In forming a trench, a semiconductor substrate with an etching pattern is disposed in a vacuum process chamber of a processing apparatus. A reactive gas is then introduced into the chamber and a discharge plasma is generated so that reactive ions and radicals progress etching, whereby a trench is formed. A film of insulating material is formed on the trench, whereupon the STI structure is obtained. An amount and/or energy of each of ion and radical is adjusted so that an etched film is formed into a desired geometry or so that a deposited film has a high trench fill capability and high fabricating and film-forming speeds are ensured.
  • However, an aspect ratio of the STI region is increased as the size of a device structure is reduced. With this, the trench fill capability of an insulating film material tends to be reduced. As a result, the trench cannot completely be filled with the insulating film material, whereupon voids are formed in the trench. The voids further result in a new failure such as short circuit between the elements with an increasing frequency of occurrence. JP-A-2000-43413 discloses an improvement in the trench fill capability of the insulating film in the trench.
  • In order that the trench fill capability of the insulating film may be improved, it is suggested that a taper angle of STI or an inclination of sidewalls relative to the trench bottom be reduced, that is, the inclination of trench sidewalls be gentler. However, this method has the following inconvenience. That is, a distance between devices needs to be set to be shorter as miniaturization of the device structure progresses. In this case, when the taper angle is reduced in consideration of the aforementioned respect, a distance between portions where sidewalls intersect the bottom becomes shorter. Accordingly, limitations of a lower limit value of the taper angle become strict according to an opening width of the trench such that the limitations are difficult to cope with.
  • When the taper angle is reduced as described above, an insulation distance between the devices becomes short such that the breakdown voltage is reduced. This results in a reduction in the function of STI, that is, function of isolating elements adjacent to each other. Accordingly, in order that the aforementioned inconvenience may be prevented, the taper angle needs to be maintained at a large value. Thus, the conditions under which the opening width of the trench gives advantage to the trench fill capability is contrary to those under which the taper angle gives advantage to the trench fill capability. Under these conditions, the trench fill capability is hard to maintain at the level of the previous design rules.
  • In order that the trench fill capability of insulating film may be improved, for example, the trench filling step needs to be repeated several times, instead of forming the insulating film at a single step so that the trench is completely filled with the insulating film. In this case, however, the productivity cannot be improved even if the trench fill capability can be satisfied. Additionally, it is difficult to reduce the costs.
    • BRIEF SUMMARY OF THE INVENTION
  • Therefore, an object of the present invention is to provide a semiconductor device in which a desirable trench fill capability of the insulating film in the trench with high aspect ration can be maintained even if the miniaturization of the device progresses, and a method of fabricating the same.
  • The present invention provides a semiconductor device comprising a semiconductor substrate having a surface, a first trench with a high aspect ratio formed in the surface of the semiconductor substrate and having a bottom, two sidewalls and an open end, the first trench being formed so that at the bottom side thereof, an inclination of each sidewall relative to the bottom has a first angle approximate to a right angle and at the bottom side, the inclination of each sidewall relative to the bottom has a second angle smaller than the first angle, and a second trench having a lower aspect ratio than the first trench, the second trench having a bottom, two sidewalls and an open end and being formed so that an inclination of each sidewall relative to the bottom thereof is substantially uniform from the bottom side to the open end side and has a third angle which is approximate to the second angle.
  • The invention also provides a method of fabricating a semiconductor device, comprising patterning an etching mask material so that trenches with higher and lower aspect ratios formed in a surface of a semiconductor substrate so as to open at the surface, respectively and etching the semiconductor substrate with the patterned etching mask using an etching gas made by mixing a halogen gas, a fluorocarbon gas and oxygen so that the trenches with the higher and lower aspect ratios respectively are simultaneously formed.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other objects, features and advantages of the present invention will become clear upon reviewing the following description of the embodiment with reference to the accompanying drawings, in which:
  • FIG. 1 is a typical section of a semiconductor device of one embodiment in accordance with the present invention, showing the state of the device after execution of a trench forming process;
  • FIG. 2 is a typical plan view of the semiconductor device, showing a state where a gate electrode has been formed;
  • FIG. 3 is a typical section of the semiconductor device, showing the configuration of the trench in detail;
  • FIGS. 4A to 4D are typical sectional views of the semiconductor device corresponding to stages in the fabrication process;
  • FIGS. 5A to 5C show configurations of trenches compared with one another with respect to the trench fill capability;
  • FIG. 6 is a graph showing dimensions indicative of the trench fill capability in different types of trenches;
  • FIG. 7 is a graph showing the dimension indicative of the trench fill capability in the case where the curvature radius of the upper part of trench is changed; and
  • FIG. 8 is a graph showing the dimension indicative of the trench fill capability in the case where the taper angle of the upper part of trench is changed.
    • DETAILED DESCRIPTION OF THE INVENTION
  • One embodiment of the present invention will be described with reference to the accompanying drawings. The invention is applied to a flash memory which is one type of non-volatile memory. Referring to FIG. 1, the state of the semiconductor device after execution of a trench forming process is shown. FIG. 2 shows a control gate electrode. FIG. 1 is a sectional view taken along line 1-1 in FIG. 2. Chips composing the flash memory each include a memory cell region in which a number of memory cells are formed and a peripheral circuit region in which peripheral circuits for driving the memory cells are formed.
  • A silicon substrate 1 serving as a semiconductor substrate has trenches 2 a and 2 b for forming element isolation regions. The trenches 2 a and 2 b have opening widths A1 and A2 respectively and the same depth D as each other. The trench 2 a has a higher aspect ratio R1 (D/A1) so as to correspond to a memory cell region 3, whereas the trench 2 b has a lower aspect ratio R2 (D/A2) so as to correspond to the peripheral circuit region 4.
  • Transistors formed in the peripheral circuit region 4 include at least one having a higher break-down voltage. Accordingly, the width A2 of the trench 2 b is set to be larger that the width A1 of the trench 2 a. The trench 2 b has a bottom which is formed so that residue 5 is deposited without being etched. The residue 5 can be suppressed when an etching gas ratio which is one of etching conditions is optimized.
  • Three active regions 6 a, 6 b and 6 c are separately formed in the memory cell region 3, a boundary and peripheral circuit region 4 respectively. On the upper surface of the substrate 1 are deposited a silicon oxide film 7 serving as a gate insulating film, a polycrystalline silicon film 8 serving as a gate electrode material, a silicon nitride film 9 serving as a stopper in a chemical-mechanical polishing process and a silicon oxide film 10 serving as an etching mask for the substrate 1 sequentially in the active regions 6 a to 6 c.
  • In the structure as shown in FIG. 2, silicon oxide films are buried in the respective trenches 2 a and 2 b so that STI structure regions 11 a and 11 b are formed. Further, control gate electrodes 12 are formed so as to extend across the active regions 6 a and 6 c.
  • In order that geometries of trenches 2 a and 2 b may be compared with each other, FIG. 3 shows a section of a boundary where the trenches 2 a and 2 b with higher and lower aspect ratios respectively are adjacent to each other or the active regions 6 a and 6 b. In the figure, the trench 2 a is formed so that a width B1 at the bottom thereof is smaller or narrower than a width A1 at the upper opening in the silicon substrate 1.
  • Referring now to FIG. 3, a taper angle is defined as an angle made by line L extending from a bottom end P1 to an opening end P2 and line H parallel to the bottom. On one hand, when symbol “α” designates a taper angle of the trench 2 a, a sidewall 13 a of the trench 2 a rises up at the bottom end P1 with a steeper inclination θ1 nearer to a right angle than the taper angle α. The inclination θ1 is made by a tangent line S1 along the sidewall 13 a at the bottom end P1 and parallel line H. The inclination of the sidewall 13 a gradually becomes gentler as the sidewall 13 a goes upward and has, at the opening end P2, a smaller inclination θ2 than the taper angle α. The inclination θ2 is made by a tangent line S2 along the sidewall 13 a at the opening end P2 and parallel line H.
  • The sidewall 13 a of the trench 2 a has a rounded shape near the opening end P2 while satisfying the above-described conditions. Consequently, the trench 2 a is formed so that a degree of opening is increased from the bottom toward the opening or so that the inner section thereof is trumpet-shaped.
  • On the other hand, when symbol “β” designates a taper angle of the trench 2 b, a sidewall 13 b of the trench 2 b is formed so as to have, from the bottom end P3 to the opening end P4, an inclination θ3 which is substantially equal to the taper angle β. Furthermore, the trench 2 b is formed so that an inclination θ3 at the opening end P4 is substantially equal to the inclination θ2 at the opening end P2 of the trench 2 a. The aforementioned inclinations θ1, θ2 and θ3 serve as first, second and third inclinations respectively. The taper angles α and β are shown by the following equations (1) and (2) on the basis of the aforementioned dimensions:
    Taper angle α=arctan (2D/(A1−B1))  (1)
    Taper angle β=arctan (2D/(A2−B2))  (2)
  • The inclinations θ2 and θ3 need not be substantially equal to each other but the inclination θ3 needs to be smaller than inclination θ1.
  • As described above, the trench 2 a is formed so that the inclination of the sidewall thereof is gentle near the opening and steep near the bottom. The trench 2 b is formed so that the inclination of the sidewall thereof is smaller than that near the bottom of the trench 2 a and is uniform. Consequently, the trench fill capability of the silicon oxide film filling the interior of the trench is improved. The reason for this would be that a capacity of the trench 2 a with the higher aspect ratio is decreased as compared with the other trench 2 a such that the trench fill capability is improved, as will be understood from the results of comparison later. Further, the silicon oxide film for filling the trench can be made by a single process, and a film thickness need not be increased for improvement of the trench fill capability. Consequently, the productivity can be improved.
  • The fabrication process up to the structure of FIG. 1 will be described with reference to FIGS. 4A to 4D. Firstly, on the silicon substrate 1 are sequentially formed the silicon oxide film 7, polycrystalline silicon film 8, silicon nitride film 9 and silicon oxide film (boro-silicate glass (BSG) film) 10. The silicon oxide film 7 serves as a gate insulating film of the floating gate. The polycrystalline silicon film 8 constitutes a part of the floating gate (another polycrystalline silicon film will be deposited in a post-process). The silicon nitride film 9 serves as a stopper in the chemical-mechanical polishing (CMP) process. The silicon oxide film 10 serves as a mask material in etching the silicon substrate 1.
  • Subsequently, a resist 14 is applied so as to correspond to the active regions 6 a to 6 c and then exposed to light so as to be patterned, as shown in FIG. 4B. Thereafter, the silicon oxide film 10 is etched with the resist 14 serving as a mask, and then, the resist 14 is removed, as shown in FIG. 4C. The silicon nitride film 9, polycrystalline silicon film 8 and silicon oxide film 7 are etched with the silicon oxide film 10 serving as a mask. Subsequently, as shown in FIG. 4D, the silicon substrate 1 is etched using an etching gas in a reactive vacuum container of a processing apparatus so that the trenches 2 a and 2 b are formed. The etching gas contains a halogen gas to which a fluorocarbon gas and oxygen are added. The halogen gas includes Cl2 (chlorine gas) and HBr (hydrogen bromide gas). The fluorocarbon gas includes CF4, CHF3, CH2F2, C5F8 and C4F6. The halogen gas is mainly used for the etching. The etched silicon is oxidized using oxygen such that silicon oxide is produced as a reaction product, which is deposited on the surface of the silicon substrate 1. The fluorocarbon gas has a function of re-etching the reaction product deposited as the silicon oxide resulting in residue, thereby blowing away the reaction product.
  • On one hand, the silicon oxidized by oxygen becomes difficult to advance into the bottom side in the trench with the higher aspect ratio, namely, the trench 2 a of the memory cell region 3. An amount of silicon oxide is reduced as the bottom of the trench 2 a is dug downward by etching. Accordingly, the inclination of the sidewall 13 a is increased. On the other hand, since the trench 2 b with lower aspect ratio has a larger opening width A2, the silicon oxide is capable of reaching the bottom. As a result, the sidewall 13 b is formed to have a gentle inclination θ3.
  • Thus, when the mixing ratio of the aforementioned gas is suitably set, an amount of reaction product can be controlled or an amount of deposited reaction product can be controlled, whereupon the conditions under which a desired geometry of the trench can be achieved. Further, the above-described etching manner can form both trenches 2 a and 2 b by one time of etching process. Specific etching conditions are as follows: regarding the gas flow rate, the halogen gas is set to a flow rate of about 70%, oxygen is set to a flow rate of about 20% and fluorocarbon gas is set to a flow rate of about 10%. An etching pressure is set to about 20 mT and an RF power is set to about 500 W.
  • The trench fill capability of the silicon oxide film serving as an insulating film was examined regarding the trenches 2 a and 2 b of the embodiment and trenches formed for the comparison purpose and having geometries other than those of the trenches 2 a and 2 b. FIG. 5A shows the silicon substrate 1 having the trench 2 a of the embodiment. FIG. 5B shows a silicon substrate 16 having a straight-tapered trench 15. FIG. 5C shows a silicon substrate 18 having a bowing trench 17. A silicon oxide film 19 is formed on each of the trenches 2 a, 15 and 17 to be used to measure the trench fill capability.
  • FIG. 6 shows the trench fill capabilities of the trenches 2 a, 15 and 17 of the silicon substrates 1, 16 and 18 respectively. Dimension BT (nm) indicative of the trench fill capability refers to the difference between an interface of the silicon substrate 1 and the silicon oxide film 7 and the trench bottom, as shown in FIG. 5A. The results show that the trench 2 a of the embodiment has a largest dimension BT of the three, whereas the bowing trench 17 has a smallest dimension BT.
  • Furthermore, in a case where the taper angles α of the trenches 2 a and 15 were set to the same, the trench fill capability was measured regarding the silicon substrate 1 of the embodiment and the silicon substrate 16 with the straight-tapered trench 15. Although the taper angles α were the same, the silicon substrate 1 had the dimension BT of 143 nm whereas the silicon substrate 16 had the dimension BT of 91 nm. As a result, the silicon substrate 1 formed with the trench 2 a is superior to the other substrates in the trench fill capability.
  • In a state where the STIs 11 a are formed, a distance between elements via the bottom of the trench 2 a is uniform between the active regions adjacent to each other. Consequently, it can be understood that the trench fill capability is improved while the insulating characteristic is maintained.
  • The trench fill capability was evaluated regarding the silicon substrate 1 formed with the trench 2 a in a case where the inclination θ2 of the trench opening side was changed. In this case, a rounded portion of the silicon substrate 1 at the opening side was approximated to a part of a circle, instead of the inclination θ2. A curvature radius r of the rounded portion served as a parameter. A value serving as the curvature radius r obtained at a portion about 20 nm deep from the upper surface of the silicon substrate 1. FIG. 7 shows that the trench fill capability can be improved (an increase in the dimension BT) with increase in the curvature radius r defined as described above. This signifies that the trench fill capability can be improved as the inclination θ2 is reduced. Accordingly, it can be understood that the dimension BT during the trench filling process can be adjusted by controlling the curvature radius r. Consequently, the number and time of fabrication steps can each be reduced to about two thirds in the conventional number and time, whereupon the number of fabrication steps can be reduced.
  • The trench fill capability of the trench 2 a was evaluated by the simulation using a computer. In the simulation, the sidewall 16 a of the trench 2 a was divided into three stages, that is, upper, middle and lower parts in the direction of depth. Taper angles of the respective divided regions were changed and then combined together. The trench fill capability was evaluated in the same manner. Consequently, a degree of influence upon the trench fill capability was shown as upper inclined portion>middle inclined portion>lower inclined portion. As obvious from the results as shown in FIG. 8, the trench fill capability was found to be improved when the inclined angle is gentler or when the curvature radius is larger.
  • Summarizing the foregoing results, the trench fill capability can be improved when the opening side has a large curvature radius r or when the taper angle α is gentle, the element isolating function ensuring sufficient insulating performance can be provided while the trench filling capability can be ensured. In this evaluation, the sidewall 16 a of the trench 2 a was divided into three stages. However, the number of divided states is optional. In this case, too, the similar effect to the above-described one can be achieved.
  • Several modified forms will be described. An etching gas other than those exemplified above may be used when it belongs to the same type of gas. Furthermore, the mixing ratio or the flow rate may be set to a suitable value so that the same object as described above is achieved.
  • The invention may be applied to any type of non-volatile memory other than the flash memory. Additionally, the invention may be applied to any semiconductor device employing the arrangement in which a plurality of trenches having different aspect ratios and the trench interior is filled with an insulating film.
  • The foregoing description and drawings are merely illustrative of the principles of the present invention and are not to be construed in a limiting sense. Various changes and modifications will become apparent to those of ordinary skill in the art. All such changes and modifications are seen to fall within the scope of the invention as defined by the appended claims.

Claims (6)

1. A semiconductor device comprising:
a semiconductor substrate having a surface;
a first trench having a higher aspect ratio and formed in the surface of the semiconductor substrate, first trench having a bottom, two sidewalls and an open end, the first trench being formed so that at the bottom side thereof, an inclination of each sidewall relative to the bottom has a first angle approximate to a right angle and at the bottom side, the inclination of each sidewall relative to the bottom has a second angle smaller than the first angle; and
a second trench having a lower aspect ratio than the first trench, the second trench having a bottom, two sidewalls and an open end and being formed so that an inclination of each sidewall relative to the bottom thereof is substantially uniform from the bottom side to the open end side and has a third angle which is approximate to the second angle.
2. The semiconductor device according to claim 1, wherein the first trench is formed as an element isolation region for a region where a memory cell is adapted to be formed, and the second trench is formed as an element isolation region for a region where a peripheral circuit is adapted to be formed.
3. The semiconductor device according to claim 2, wherein the semiconductor substrate is formed with a gate insulating film and a gate electrode.
4. A method of fabricating a semiconductor device, comprising:
patterning an etching mask material so that trenches having higher and lower aspect ratios and formed in a surface of a semiconductor substrate so as to be open at the surface, respectively; and
etching the semiconductor substrate with the patterned etching mask using an etching gas made by mixing a halogen gas, a fluorocarbon gas and oxygen so that the trenches are simultaneously formed.
5. The method according to claim 4, further comprising, prior to the etching step, depositing a gate insulating film and a gate electrode material on the semiconductor substrate.
6. A method of fabricating a semiconductor device, comprising:
forming a gate insulating film on a semiconductor substrate;
forming a polycrystalline silicon film;
forming a silicon nitride film;
forming a silicon oxide film;
etching the silicon oxide film, silicon nitride film, polycrystalline silicon film and gate insulating film all formed on the semiconductor substrate into a pattern corresponding to a first trench with a higher aspect ratio and a second trench with a lower aspect ratio, with a mask serving as a resist;
etching the semiconductor substrate using an etching gas made by mixing a halogen gas, a fluorocarbon gas and oxygen with the patterned silicon oxide film serving as a mask until a predetermined depth is reached, thereby forming a trench; and
filling the trench with an insulating film.
US11/085,112 2004-03-23 2005-03-22 Semiconductor device and method of fabricating the same Abandoned US20050221579A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/611,030 US7781293B2 (en) 2004-03-23 2006-12-14 Semiconductor device and method of fabricating the same including trenches of different aspect ratios

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004085051A JP4564272B2 (en) 2004-03-23 2004-03-23 Semiconductor device and manufacturing method thereof
JP2004-085051 2004-03-23

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/611,030 Division US7781293B2 (en) 2004-03-23 2006-12-14 Semiconductor device and method of fabricating the same including trenches of different aspect ratios

Publications (1)

Publication Number Publication Date
US20050221579A1 true US20050221579A1 (en) 2005-10-06

Family

ID=35046651

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/085,112 Abandoned US20050221579A1 (en) 2004-03-23 2005-03-22 Semiconductor device and method of fabricating the same
US11/611,030 Active 2026-07-19 US7781293B2 (en) 2004-03-23 2006-12-14 Semiconductor device and method of fabricating the same including trenches of different aspect ratios

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/611,030 Active 2026-07-19 US7781293B2 (en) 2004-03-23 2006-12-14 Semiconductor device and method of fabricating the same including trenches of different aspect ratios

Country Status (4)

Country Link
US (2) US20050221579A1 (en)
JP (1) JP4564272B2 (en)
KR (1) KR100707899B1 (en)
CN (1) CN100377332C (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100707899B1 (en) 2004-03-23 2007-04-16 가부시끼가이샤 도시바 Semiconductor device and manufacturing method thereof
US20070145639A1 (en) * 2005-10-18 2007-06-28 Canon Kabushiki Kaisha Imprint method, imprint apparatus, and process for producing chip
US20080044981A1 (en) * 2006-07-07 2008-02-21 Samsung Electronics Co., Ltd. Trench Isolation Methods, Methods of Forming Gate Structures Using the Trench Isolation Methods and Methods of Fabricating Non-Volatile Memory Devices Using the Trench Isolation Methods
US20080064195A1 (en) * 2006-08-29 2008-03-13 Young-Ju Kim Method for Manufacturing Gate of Non Volatile Memory Device
US20080153304A1 (en) * 2006-12-20 2008-06-26 Elpida Memory, Inc. Method of producing a semiconductor device
US20080197378A1 (en) * 2007-02-20 2008-08-21 Hua-Shuang Kong Group III Nitride Diodes on Low Index Carrier Substrates
US20090052250A1 (en) * 2007-08-21 2009-02-26 Koichi Kawashima Semiconductor memory device and its manufacturing method
US20110039413A1 (en) * 2009-08-12 2011-02-17 International Business Machines Corporation Method for forming trenches having different widths and the same depth
US20120034757A1 (en) * 2010-08-05 2012-02-09 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices having various isolation regions
US20150137309A1 (en) * 2006-03-01 2015-05-21 Infineon Technologies Ag Methods of Fabricating Isolation Regions of Semiconductor Devices and Structures Thereof
EP2741331A3 (en) * 2012-12-06 2017-10-25 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Method for producing a component with a suspended structure and a transistor integrated on a single substrate
US10600799B2 (en) 2016-01-07 2020-03-24 Renesas Electronics Corporation Memory device and low breakdown voltage transistor
US20200234586A1 (en) * 2015-10-16 2020-07-23 Ford Global Technologies, Llc System and method for pseudo navigation assistance in a vehicle

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100913004B1 (en) * 2006-09-06 2009-08-20 주식회사 하이닉스반도체 Method of forming trench in semiconductor device
JP2010272758A (en) * 2009-05-22 2010-12-02 Hitachi High-Technologies Corp Plasma etching method for etching object
WO2013177576A1 (en) * 2012-05-25 2013-11-28 The Regents Of The University Of California Method for fabrication of high aspect ratio trenches and formation of nanoscale features therefrom
CN104217985A (en) * 2013-05-31 2014-12-17 中芯国际集成电路制造(上海)有限公司 Semiconductor device and fabrication method of shallow trench
CN105470201A (en) * 2014-06-18 2016-04-06 上海华力微电子有限公司 Flash memory device process for simultaneously improving shallow trench isolation (STI) filling holes and floating gate polycrystalline silicon (FG Poly) filling holes
CN105336696A (en) * 2014-06-18 2016-02-17 上海华力微电子有限公司 Method for improving STI and FG poly filling hole process window simultaneously
US10896803B2 (en) 2016-08-19 2021-01-19 The Regents Of The University Of California Ion beam mill etch depth monitoring with nanometer-scale resolution
US10593678B1 (en) 2018-08-24 2020-03-17 Micron Technology, Inc. Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related semiconductor devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242788B1 (en) * 1997-08-01 2001-06-05 Nippon Steel Corporation Semiconductor device and a method of manufacturing the same
US20030013270A1 (en) * 2001-07-13 2003-01-16 Infineon Technologies North America Corp. High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern
US6521538B2 (en) * 2000-02-28 2003-02-18 Denso Corporation Method of forming a trench with a rounded bottom in a semiconductor device
US6914616B2 (en) * 2000-10-31 2005-07-05 Seiko Epson Corporation Image reproduction display apparatus utilizing a controller with selection mask conversion module

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03196624A (en) * 1989-12-26 1991-08-28 Sony Corp Dry etching
JP3229058B2 (en) 1993-02-05 2001-11-12 株式会社リコー Method of manufacturing semiconductor device having filling groove isolation region
JP3309620B2 (en) * 1995-01-27 2002-07-29 富士電機株式会社 Manufacturing method of parts by dry etching
KR0176153B1 (en) * 1995-05-30 1999-04-15 김광호 An isolation layer of a semiconductor device
KR100192178B1 (en) * 1996-01-11 1999-06-15 김영환 Isolation method of semiconductor device
KR19980030859U (en) * 1996-11-29 1998-08-17 진호선 Men's shorts
JPH09289313A (en) * 1996-04-19 1997-11-04 Sony Corp Threshold voltage setting method for semiconductor device
JPH11307627A (en) * 1997-08-01 1999-11-05 Nippon Steel Corp Semiconductor device and manufacture thereof
US6303460B1 (en) * 2000-02-07 2001-10-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
KR19990055775A (en) * 1997-12-27 1999-07-15 김영환 Device isolation method of semiconductor device using trench
US6060370A (en) * 1998-06-16 2000-05-09 Lsi Logic Corporation Method for shallow trench isolations with chemical-mechanical polishing
US6159801A (en) * 1999-04-26 2000-12-12 Taiwan Semiconductor Manufacturing Company Method to increase coupling ratio of source to floating gate in split-gate flash
JP4666700B2 (en) * 1999-08-30 2011-04-06 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
KR100555490B1 (en) * 1999-10-15 2006-03-03 삼성전자주식회사 Method for forming trench isolation in semiconductor device
JP3485081B2 (en) * 1999-10-28 2004-01-13 株式会社デンソー Semiconductor substrate manufacturing method
US6303447B1 (en) * 2000-02-11 2001-10-16 Chartered Semiconductor Manufacturing Ltd. Method for forming an extended metal gate using a damascene process
JP2002043413A (en) 2000-07-25 2002-02-08 Toshiba Corp Semiconductor device and its manufacturing method
JP2003060024A (en) * 2001-08-13 2003-02-28 Mitsubishi Electric Corp Semiconductor device and method for manufacturing the same
JP4129189B2 (en) * 2002-02-07 2008-08-06 東京エレクトロン株式会社 Etching method
US7018929B2 (en) * 2002-07-02 2006-03-28 Taiwan Semiconductor Manufacturing Co., Ltd Method for reducing a low volatility byproduct from a wafer surface following an etching process
KR100466196B1 (en) * 2002-07-18 2005-01-13 주식회사 하이닉스반도체 Method for manufacturing flash memory
KR100443126B1 (en) * 2002-08-19 2004-08-04 삼성전자주식회사 trench structure and method of forming thereof
JP2004087843A (en) * 2002-08-27 2004-03-18 Toshiba Corp Semiconductor device
JP2004095886A (en) * 2002-08-30 2004-03-25 Fujitsu Ltd Semiconductor device and its manufacturing method
KR100481558B1 (en) * 2002-09-09 2005-04-08 동부아남반도체 주식회사 Method for forming a shallow trench isolation using of air gap
US6576558B1 (en) * 2002-10-02 2003-06-10 Taiwan Semiconductor Manufacturing Company High aspect ratio shallow trench using silicon implanted oxide
US7482178B2 (en) * 2003-08-06 2009-01-27 Applied Materials, Inc. Chamber stability monitoring using an integrated metrology tool
JP4564272B2 (en) 2004-03-23 2010-10-20 株式会社東芝 Semiconductor device and manufacturing method thereof
US20080166854A1 (en) * 2005-09-09 2008-07-10 Dong-Suk Shin Semiconductor devices including trench isolation structures and methods of forming the same
KR100772704B1 (en) * 2005-09-29 2007-11-02 주식회사 하이닉스반도체 Method for manufacturing of semiconductor deive with taper type trench

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242788B1 (en) * 1997-08-01 2001-06-05 Nippon Steel Corporation Semiconductor device and a method of manufacturing the same
US6350655B2 (en) * 1997-08-01 2002-02-26 Nippon Steel Corporation Semiconductor device and a method of manufacturing the same
US6521538B2 (en) * 2000-02-28 2003-02-18 Denso Corporation Method of forming a trench with a rounded bottom in a semiconductor device
US6914616B2 (en) * 2000-10-31 2005-07-05 Seiko Epson Corporation Image reproduction display apparatus utilizing a controller with selection mask conversion module
US20030013270A1 (en) * 2001-07-13 2003-01-16 Infineon Technologies North America Corp. High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100707899B1 (en) 2004-03-23 2007-04-16 가부시끼가이샤 도시바 Semiconductor device and manufacturing method thereof
US20070145639A1 (en) * 2005-10-18 2007-06-28 Canon Kabushiki Kaisha Imprint method, imprint apparatus, and process for producing chip
US7828984B2 (en) * 2005-10-18 2010-11-09 Canon Kabushiki Kaisha Imprint method, imprint apparatus, and process for producing chip
US9507256B2 (en) 2005-10-18 2016-11-29 Canon Kabushiki Kaisha Imprint method, imprint apparatus, and process for producing chip
US20150137309A1 (en) * 2006-03-01 2015-05-21 Infineon Technologies Ag Methods of Fabricating Isolation Regions of Semiconductor Devices and Structures Thereof
US9653543B2 (en) * 2006-03-01 2017-05-16 Infineon Technologies Ag Methods of fabricating isolation regions of semiconductor devices and structures thereof
US20080044981A1 (en) * 2006-07-07 2008-02-21 Samsung Electronics Co., Ltd. Trench Isolation Methods, Methods of Forming Gate Structures Using the Trench Isolation Methods and Methods of Fabricating Non-Volatile Memory Devices Using the Trench Isolation Methods
US20080064195A1 (en) * 2006-08-29 2008-03-13 Young-Ju Kim Method for Manufacturing Gate of Non Volatile Memory Device
US20080153304A1 (en) * 2006-12-20 2008-06-26 Elpida Memory, Inc. Method of producing a semiconductor device
US20080197378A1 (en) * 2007-02-20 2008-08-21 Hua-Shuang Kong Group III Nitride Diodes on Low Index Carrier Substrates
US20110084277A1 (en) * 2007-08-21 2011-04-14 Panasonic Corporation Semiconductor memory device and its manufacturing method
US20090052250A1 (en) * 2007-08-21 2009-02-26 Koichi Kawashima Semiconductor memory device and its manufacturing method
US8138093B2 (en) * 2009-08-12 2012-03-20 International Business Machines Corporation Method for forming trenches having different widths and the same depth
US20110039413A1 (en) * 2009-08-12 2011-02-17 International Business Machines Corporation Method for forming trenches having different widths and the same depth
US20120034757A1 (en) * 2010-08-05 2012-02-09 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices having various isolation regions
US8530329B2 (en) * 2010-08-05 2013-09-10 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices having various isolation regions
EP2741331A3 (en) * 2012-12-06 2017-10-25 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Method for producing a component with a suspended structure and a transistor integrated on a single substrate
US20200234586A1 (en) * 2015-10-16 2020-07-23 Ford Global Technologies, Llc System and method for pseudo navigation assistance in a vehicle
US10818176B2 (en) * 2015-10-16 2020-10-27 Ford Global Technologies, Llc System and method for pseudo navigation assistance in a vehicle
US10600799B2 (en) 2016-01-07 2020-03-24 Renesas Electronics Corporation Memory device and low breakdown voltage transistor
US11393838B2 (en) 2016-01-07 2022-07-19 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
CN1674248A (en) 2005-09-28
US20070082458A1 (en) 2007-04-12
JP4564272B2 (en) 2010-10-20
KR20060044527A (en) 2006-05-16
KR100707899B1 (en) 2007-04-16
CN100377332C (en) 2008-03-26
JP2005276930A (en) 2005-10-06
US7781293B2 (en) 2010-08-24

Similar Documents

Publication Publication Date Title
US7781293B2 (en) Semiconductor device and method of fabricating the same including trenches of different aspect ratios
US7241665B2 (en) Shallow trench isolation
US6995095B2 (en) Methods of simultaneously fabricating isolation structures having varying dimensions
US7772670B2 (en) Method of simultaneously fabricating isolation structures having rounded and unrounded corners
US6656793B2 (en) Method of forming a self-aligned floating gate in flash memory cell
US7754610B2 (en) Process for etching tungsten silicide overlying polysilicon particularly in a flash memory
US7442606B2 (en) Method of manufacturing a semiconductor device
KR100341480B1 (en) Method for self-aligned shallow trench isolation
KR20050112262A (en) Method for manufacturing of semiconductor device
US8048739B2 (en) Method of manufacturing flash memory device
US11984352B2 (en) Formation method of semiconductor structure
US7566924B2 (en) Semiconductor device with gate spacer of positive slope and fabrication method thereof
KR20040008521A (en) Method for manufacturing flash memory
JP4039504B2 (en) Manufacturing method of semiconductor device
CN210837653U (en) Semiconductor structure and memory
KR100538882B1 (en) Method of manufacturing a semiconductor device
KR100986899B1 (en) Method of manufacturing a semiconductor device
CN112908840A (en) Semiconductor structure, forming method thereof and memory
KR100763102B1 (en) Method for fabrication of semiconductor device
KR100652311B1 (en) Method for manufacturing isolation film of semiconductor device
CN107665856B (en) Method for forming contact hole and plasma etching method
KR20020075008A (en) Trench isolation structure and method of forming the same
CN115116852A (en) MOSFET device and manufacturing method thereof
KR20000004548A (en) Method for forming contact of semiconductor device
CN111799269A (en) Flash memory and manufacturing method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MATSUMOTO, TAKANORI;REEL/FRAME:016709/0773

Effective date: 20050405

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION