US20050189630A1 - Bonding arrangement and method for LTCC circuitry - Google Patents
Bonding arrangement and method for LTCC circuitry Download PDFInfo
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- US20050189630A1 US20050189630A1 US10/786,125 US78612504A US2005189630A1 US 20050189630 A1 US20050189630 A1 US 20050189630A1 US 78612504 A US78612504 A US 78612504A US 2005189630 A1 US2005189630 A1 US 2005189630A1
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- 239000004020 conductor Substances 0.000 claims abstract description 63
- 239000000919 ceramic Substances 0.000 claims abstract description 28
- 239000000654 additive Substances 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 238000010304 firing Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 78
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- 239000010931 gold Substances 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 238000001465 metallisation Methods 0.000 claims description 11
- 229910010293 ceramic material Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
- H05K3/247—Finish coating of conductors by using conductive pastes, inks or powders
- H05K3/248—Finish coating of conductors by using conductive pastes, inks or powders fired compositions for inorganic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/035—Paste overlayer, i.e. conductive paste or solder paste over conductive layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/049—Wire bonding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49016—Antenna or wave energy "plumbing" making
- Y10T29/49018—Antenna or wave energy "plumbing" making with other electrical component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
- Y10T29/49075—Electromagnet, transformer or inductor including permanent magnet or core
- Y10T29/49078—Laminated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Definitions
- the invention in general relates to the field of LTCC (low temperature cofired ceramic) circuitry.
- LTCC low temperature cofired ceramic
- An LTCC circuit is comprised of a plurality of ceramic layers with passive and/or active components and stacked together to form a module, with each ceramic layer containing thick film printed circuitry metallization, generally gold or silver.
- the ceramic layers include conductive vias for making electrical contact between layers and the ceramic layers are cofired at a temperature high enough to sinter the layers, yet low enough so as prevent flowing or melting of the metallization. The result of the firing is to form a rigid monolithic structure.
- LTCC circuits have high packing density, can be customized to meet desired applications, are cost effective, reliable and can be controlled with respect to dielectric values.
- the LTCC allows for integration of digital and RF, stripline and microstrip circuits in a single light weight 3-D package. Such LTCC circuits are used for high frequency applications in both military as well as commercial devices.
- wire or ribbon leads are bonded to conductors on the surface of the structure for connection to the other circuitry.
- a problem often arises however in that the bonded leads may form a poor contact with, or pull loose from, the conductors. This is due to the fact that the conductors contain one or more additives to promote conductor adhesion to the ceramic base layer and it is these additives which degrade the bonding of the leads.
- An LTCC structure in accordance with the present invention consists of a plurality of stacked layers of ceramic material including metallization in predetermined patterns on and through the layers.
- the stacked layers include a plurality of exposed electrical conductors to which leads are to be bonded.
- the conductors are of a metal which includes one or more additives to promote adhesion to the ceramic layer on which the conductors are deposited.
- a bonding metal layer is deposited on top of the conductors at predetermined locations and is of the same metal as the conductors, however devoid of the one or more additives. The leads are then bonded to the bonding metal layer for improved bonding performance.
- the bonding metal layer may be deposited and may be cofired with the stack of ceramic layers. Alternatively, the stack may be cofired and the bonding metal layer subsequently deposited and thereafter be fired in a second firing of the stack.
- FIG. 1A is an exploded view of an LTCC structure.
- FIG. 1B illustrates the structure of FIG. 1A in a fired modular form.
- FIG. 2 is a cross-sectional view through conductors of the structure of FIG. 1 , illustrating an embodiment of the present invention.
- FIG. 3 is a view of an active device on an intermediate layer of the LTCC structure.
- an LTCC structure 10 which is comprised of a plurality of ceramic layers 12 to 17 , each having a pattern of metallization. It is to be noted that structure 10 does not represent an actual circuit but is presented to show typical components which may be placed on the individual ceramic layers. Further, in the description to follow, the metallization will be described using gold, by way of example.
- Bottom layer 12 includes a ground plane 20 having voids 21 where a ground plane is not desired.
- Layer 13 has metallization areas 24 for the mounting of active devices (not shown), and connected to passive devices such as capacitors 26 by means of conductors 27 .
- metallization areas 24 Surrounding metallization areas 24 are vias 28 which are vertical apertures in the layer, filled with a specially formulated conductive material for making electrical contact with components on different layers.
- Layer 14 includes an opening, or cavity, 30 to accommodate any active devices on metallization areas 24 on the previous layer, and includes a plurality of conductor pads 32 to which leads from those active devices will be connected.
- layer 14 also illustrates conductors 36 , some of which include passive devices in the form of resistors 38 .
- the next two layers 15 and 16 both include vias 28 and respective cavities 42 and 44 , providing access to the active devices.
- the top, or surface layer 17 includes cavity 46 and vias 28 to which are connected various conductors 50 .
- Some conductors 50 include resistors 52 in their path while other conductors 50 include metallization areas 54 for placement of active devices.
- layer 17 illustrates a plurality of conductor pads 56 , connected to components on a previous layer or layers and to which will be connected leads for connection to other circuitry in a system. Similarly, various conductors 50 will also be used for this purpose.
- sections of green (unfired) ceramic tape of an appropriate size for processing are cut from a larger roll. Vias are formed, such as by a punching process and filled with the conductive material.
- the conductors including the conductor pads are applied in desired patterns by a process using patterned screens to which are applied gold paste.
- the gold paste includes one or more additives to promote adhesion.
- additives commonly used include copper, bismuth and glass, by way of example, depending upon the formulation of the ceramic material. Any cavities are then formed in appropriate layers, which are then stacked and fired at a temperature of around 850° C. to sinter the gold paste and ceramic layers to form the solid unitary module 60 shown in FIG. 1B .
- leads are bonded to cavity and surface conductors so that the module 60 may be connected to other circuitry of a system.
- These leads which may be wires or ribbons, for example, are bonded to the conductors by a process which includes both heat and ultrasonic vibration.
- a problem arises however, in that, at times, the leads are poorly bonded and eventually come loose, or do not initially bond at all. This may be attributed to the additives which are included in the conductor paste to promote adhesion to the ceramic layer. It is these additives which prevent optimal bonding.
- this bonding layer may be applied to the conductors in a limited bonding area, prior to firing and then be cofired along with the stack of ceramic layers.
- the bonding layer may be applied to the conductors in a limited bonding area and may be post fired after the initial firing of the stack of ceramic layers. Any such bonding layer to be applied to conductors on intermediate ceramic layers (such as conductor pads 32 on layer 14 in FIG. 1A ) would have to use the cofired option.
- FIG. 2 illustrates a portion of ceramic layer 17 , together with a typical gold conductor 50 and gold conductor pad 56 , both containing additives for better adhesion to the ceramic under layer 17 .
- a bonding layer 70 is affixed to a limited bonding area 72 on top of conductor 50 such as by the same screening process for depositing the conductor.
- Bonding layer 70 is of pure gold devoid of any of the additives contained in conductor 50 and receives wire or ribbon lead 74 , attached by the conventional process of heat and vibration, or thermosonic, bonding. The absence of the additives ensures for a positive and strong bond, coupled with good electrical contact to the conductor 50 .
- bonding layer 76 also of pure gold devoid of any additives, is affixed to a limited bonding area 78 on conductor pad 56 to ensure for a strong bond with lead 89 .
- FIG. 3 illustrates the application of the present invention to an intermediate ceramic layer.
- An active device 84 affixed to metallization area 24 on ceramic layer 13 and extends through cavity 30 .
- Respective bonding layers 86 have been applied to conductor pads 32 and have been cofired with the stack of ceramic layers.
- Leads 88 of active device 84 are securely bonded to the pure gold bonding layers 86 by thermosonic bonding.
- the present invention provided improved bondability that were from 10% to 20% stronger than conventional techniques. Further, in some instances of prior art bonding, the leads would not even bond to the conductors, leading to a “no stick” situation. The present invention may reduce such no sticks by as much as 50%.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
An LTCC (low temperature cofired ceramic) structure which has conductors to which leads are to be bonded for connection to external circuitry. The conductors include additives to promote adhesion to the ceramic layer. The presence of these additives degrade bonding performance. For better bondability of the leads, a pure conductor metal layer, devoid of the additives is placed on the conductors in areas where leads are to be bonded. This pure conductor metal layer may be cofired with the stack of ceramic layers or may be post fired after stack firing.
Description
- This invention was made with Government support under Contract F33657-97-LTCC-0030 awarded by the Department of Defense. The Government has certain rights in the invention.
- 1. Field of the Invention
- The invention in general relates to the field of LTCC (low temperature cofired ceramic) circuitry.
- 2. Description of Related Art
- An LTCC circuit is comprised of a plurality of ceramic layers with passive and/or active components and stacked together to form a module, with each ceramic layer containing thick film printed circuitry metallization, generally gold or silver. The ceramic layers include conductive vias for making electrical contact between layers and the ceramic layers are cofired at a temperature high enough to sinter the layers, yet low enough so as prevent flowing or melting of the metallization. The result of the firing is to form a rigid monolithic structure.
- LTCC circuits have high packing density, can be customized to meet desired applications, are cost effective, reliable and can be controlled with respect to dielectric values. The LTCC allows for integration of digital and RF, stripline and microstrip circuits in a single light weight 3-D package. Such LTCC circuits are used for high frequency applications in both military as well as commercial devices.
- In order to electrically connect the LTCC structure to other circuitry, wire or ribbon leads are bonded to conductors on the surface of the structure for connection to the other circuitry. A problem often arises however in that the bonded leads may form a poor contact with, or pull loose from, the conductors. This is due to the fact that the conductors contain one or more additives to promote conductor adhesion to the ceramic base layer and it is these additives which degrade the bonding of the leads.
- It is therefore a primary object of the present invention to provide a LTCC structure with much improved lead bondability.
- An LTCC structure in accordance with the present invention consists of a plurality of stacked layers of ceramic material including metallization in predetermined patterns on and through the layers. The stacked layers include a plurality of exposed electrical conductors to which leads are to be bonded. The conductors are of a metal which includes one or more additives to promote adhesion to the ceramic layer on which the conductors are deposited. A bonding metal layer is deposited on top of the conductors at predetermined locations and is of the same metal as the conductors, however devoid of the one or more additives. The leads are then bonded to the bonding metal layer for improved bonding performance.
- The bonding metal layer may be deposited and may be cofired with the stack of ceramic layers. Alternatively, the stack may be cofired and the bonding metal layer subsequently deposited and thereafter be fired in a second firing of the stack.
- Further scope of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood, however, that the detailed description and specific example, while disclosing the preferred embodiment of the invention, is provided by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art, from the detailed description.
- The present invention will become more fully understood from the detailed description provided hereinafter and the accompanying drawings, which are not necessarily to scale, and are given by way of illustration only, and wherein:
-
FIG. 1A is an exploded view of an LTCC structure. -
FIG. 1B illustrates the structure ofFIG. 1A in a fired modular form. -
FIG. 2 is a cross-sectional view through conductors of the structure ofFIG. 1 , illustrating an embodiment of the present invention. -
FIG. 3 is a view of an active device on an intermediate layer of the LTCC structure. - Referring now to
FIG. 1 , there is illustrated anLTCC structure 10 which is comprised of a plurality of ceramic layers 12 to 17, each having a pattern of metallization. It is to be noted thatstructure 10 does not represent an actual circuit but is presented to show typical components which may be placed on the individual ceramic layers. Further, in the description to follow, the metallization will be described using gold, by way of example. - Bottom layer 12 includes a ground plane 20 having voids 21 where a ground plane is not desired.
Layer 13 hasmetallization areas 24 for the mounting of active devices (not shown), and connected to passive devices such ascapacitors 26 by means of conductors 27. Surroundingmetallization areas 24 arevias 28 which are vertical apertures in the layer, filled with a specially formulated conductive material for making electrical contact with components on different layers. -
Layer 14 includes an opening, or cavity, 30 to accommodate any active devices onmetallization areas 24 on the previous layer, and includes a plurality ofconductor pads 32 to which leads from those active devices will be connected. In addition tovias 28,layer 14 also illustratesconductors 36, some of which include passive devices in the form of resistors 38. The next two layers 15 and 16 both includevias 28 andrespective cavities - The top, or
surface layer 17 includescavity 46 andvias 28 to which are connectedvarious conductors 50. Someconductors 50 includeresistors 52 in their path whileother conductors 50 include metallization areas 54 for placement of active devices. Further,layer 17 illustrates a plurality ofconductor pads 56, connected to components on a previous layer or layers and to which will be connected leads for connection to other circuitry in a system. Similarly,various conductors 50 will also be used for this purpose. - In the manufacture of the
LTCC structure 10, sections of green (unfired) ceramic tape of an appropriate size for processing are cut from a larger roll. Vias are formed, such as by a punching process and filled with the conductive material. The conductors including the conductor pads are applied in desired patterns by a process using patterned screens to which are applied gold paste. - In order that the gold paste conductor pattern is suitably affixed to the ceramic tape layer, the gold paste includes one or more additives to promote adhesion. Such additives commonly used include copper, bismuth and glass, by way of example, depending upon the formulation of the ceramic material. Any cavities are then formed in appropriate layers, which are then stacked and fired at a temperature of around 850° C. to sinter the gold paste and ceramic layers to form the solid unitary module 60 shown in
FIG. 1B . - After firing, leads are bonded to cavity and surface conductors so that the module 60 may be connected to other circuitry of a system. These leads, which may be wires or ribbons, for example, are bonded to the conductors by a process which includes both heat and ultrasonic vibration. A problem arises however, in that, at times, the leads are poorly bonded and eventually come loose, or do not initially bond at all. This may be attributed to the additives which are included in the conductor paste to promote adhesion to the ceramic layer. It is these additives which prevent optimal bonding.
- The present invention obviates this problem by adding a bonding layer of the same metal as the conductor, only in a pure state devoid of any of the additives contained in the conductor. In one embodiment, this bonding layer may be applied to the conductors in a limited bonding area, prior to firing and then be cofired along with the stack of ceramic layers. In a second embodiment the bonding layer may be applied to the conductors in a limited bonding area and may be post fired after the initial firing of the stack of ceramic layers. Any such bonding layer to be applied to conductors on intermediate ceramic layers (such as
conductor pads 32 onlayer 14 inFIG. 1A ) would have to use the cofired option. -
FIG. 2 illustrates a portion ofceramic layer 17, together with atypical gold conductor 50 andgold conductor pad 56, both containing additives for better adhesion to the ceramic underlayer 17. In accordance with the present invention, abonding layer 70 is affixed to a limited bonding area 72 on top ofconductor 50 such as by the same screening process for depositing the conductor.Bonding layer 70 is of pure gold devoid of any of the additives contained inconductor 50 and receives wire or ribbon lead 74, attached by the conventional process of heat and vibration, or thermosonic, bonding. The absence of the additives ensures for a positive and strong bond, coupled with good electrical contact to theconductor 50. - In a similar fashion,
bonding layer 76, also of pure gold devoid of any additives, is affixed to alimited bonding area 78 onconductor pad 56 to ensure for a strong bond with lead 89. -
FIG. 3 illustrates the application of the present invention to an intermediate ceramic layer. Anactive device 84 affixed tometallization area 24 onceramic layer 13 and extends throughcavity 30. Respective bonding layers 86 have been applied toconductor pads 32 and have been cofired with the stack of ceramic layers. Leads 88 ofactive device 84 are securely bonded to the pure gold bonding layers 86 by thermosonic bonding. - In actual tests of LTCC lead bonds, the present invention provided improved bondability that were from 10% to 20% stronger than conventional techniques. Further, in some instances of prior art bonding, the leads would not even bond to the conductors, leading to a “no stick” situation. The present invention may reduce such no sticks by as much as 50%.
- The foregoing detailed description merely illustrates the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are thus within its spirit and scope.
Claims (7)
1. An LTCC structure comprising:
a plurality of stacked layers of ceramic material including metallization in predetermined patterns on and through said layers;
said stacked layers including a plurality of exposed electrical conductors to which leads are to be bonded;
said conductors being of a metal which includes one or more additives to promote adhesion to said ceramic layer on which said conductors are deposited;
a bonding metal layer on top of said conductors at predetermined locations and being of said same metal as said conductors, however devoid of said one or more additives;
said leads being bonded to said bonding metal layer.
2. Apparatus according to claim 1 wherein:
said bonding metal layer is deposited on a limited area of a said conductor only where said lead is to be bonded.
3. Apparatus according to claim 1 wherein:
said conductors are of a gold paste with said additives;
said bonding metal layer is of a pure gold paste devoid of said additives.
4. Apparatus according to claim 1 wherein:
predetermined ones of said layers include respective cavities;
predetermined ones of said conductors being located on at least one said layer below the top layer of said stacked layers;
said predetermined ones of said conductors being accessible through said cavities for bonding of said leads.
5. A method of making an LTCC structure, comprising the steps of:
providing a plurality of ceramic layers to be stacked together to form a module;
applying to said layers, prior to said stacking, conductor patterns of a metal containing one or more additives to promote adhesion of said conductor patterns to said layers;
applying to areas of exposed conductors to which leads will be bonded said same metal, however devoid of said additives, to form a bonding layer at said areas;
stacking and firing said layers to form said module;
bonding said leads to said bonding layers on said exposed conductors.
6. A method according to claim 5 which includes:
providing predetermined ones of said layers with cavities such that some of said exposed conductors are on a layer other than a surface layer, and are accessible through said cavities for lead bonding.
7. A method of making an LTCC structure, comprising the steps of:
providing a plurality of ceramic layers to be stacked together to form a module;
applying to said layers, prior to said stacking, conductor patterns of a metal containing one or more additives to promote adhesion of said conductor patterns to said layers;
stacking and firing said layers to form said module;
applying to areas of conductors, on a surface layer, to which leads will be bonded, said same metal, however devoid of said additives, to form a bonding layer at said areas;
firing said stack a second time;
bonding said leads to said bonding layers.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/786,125 US20050189630A1 (en) | 2004-02-26 | 2004-02-26 | Bonding arrangement and method for LTCC circuitry |
PCT/US2005/005655 WO2005101493A2 (en) | 2004-02-26 | 2005-02-23 | Improved bonding arrangement and method for ltcc circuitry |
US11/450,417 US7820490B2 (en) | 2004-02-26 | 2006-06-12 | Method for LTCC circuitry |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/786,125 US20050189630A1 (en) | 2004-02-26 | 2004-02-26 | Bonding arrangement and method for LTCC circuitry |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/450,417 Division US7820490B2 (en) | 2004-02-26 | 2006-06-12 | Method for LTCC circuitry |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050189630A1 true US20050189630A1 (en) | 2005-09-01 |
Family
ID=34886674
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/786,125 Abandoned US20050189630A1 (en) | 2004-02-26 | 2004-02-26 | Bonding arrangement and method for LTCC circuitry |
US11/450,417 Active 2026-06-06 US7820490B2 (en) | 2004-02-26 | 2006-06-12 | Method for LTCC circuitry |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/450,417 Active 2026-06-06 US7820490B2 (en) | 2004-02-26 | 2006-06-12 | Method for LTCC circuitry |
Country Status (2)
Country | Link |
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US (2) | US20050189630A1 (en) |
WO (1) | WO2005101493A2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8698006B2 (en) * | 2009-06-04 | 2014-04-15 | Morgan Advanced Ceramics, Inc. | Co-fired metal and ceramic composite feedthrough assemblies for use at least in implantable medical devices and methods for making the same |
WO2015048808A1 (en) * | 2013-09-30 | 2015-04-02 | Wolf Joseph Ambrose | Silver thick film paste hermetically sealed by surface thin film multilayer |
CN104540318A (en) * | 2014-12-22 | 2015-04-22 | 泰州市博泰电子有限公司 | High-frequency LTCC multilayer circuit module internally provided with passive assemblies |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6419980B1 (en) * | 1999-05-17 | 2002-07-16 | Siemens Aktiengesellschaft | Process for producing an automatic-machine-bondable ceramic circuit carrier, and automatic-machine-bondable ceramic circuit carrier |
US6528875B1 (en) * | 2001-04-20 | 2003-03-04 | Amkor Technology, Inc. | Vacuum sealed package for semiconductor chip |
US6698084B2 (en) * | 2000-09-07 | 2004-03-02 | Tdk Corporation | Method for manufacturing radio frequency module components with surface acoustic wave element |
-
2004
- 2004-02-26 US US10/786,125 patent/US20050189630A1/en not_active Abandoned
-
2005
- 2005-02-23 WO PCT/US2005/005655 patent/WO2005101493A2/en active Application Filing
-
2006
- 2006-06-12 US US11/450,417 patent/US7820490B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6419980B1 (en) * | 1999-05-17 | 2002-07-16 | Siemens Aktiengesellschaft | Process for producing an automatic-machine-bondable ceramic circuit carrier, and automatic-machine-bondable ceramic circuit carrier |
US6698084B2 (en) * | 2000-09-07 | 2004-03-02 | Tdk Corporation | Method for manufacturing radio frequency module components with surface acoustic wave element |
US6528875B1 (en) * | 2001-04-20 | 2003-03-04 | Amkor Technology, Inc. | Vacuum sealed package for semiconductor chip |
Also Published As
Publication number | Publication date |
---|---|
WO2005101493A2 (en) | 2005-10-27 |
WO2005101493A3 (en) | 2006-08-03 |
US20060236533A1 (en) | 2006-10-26 |
US7820490B2 (en) | 2010-10-26 |
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