US20030054730A1

US20030054730A1 - Systems for reducing photo-assisted corrosion in wafers during cleaning processes

Info

Publication number: US20030054730A1
Application number: US10/234,413
Authority: US
Inventors: Helmuth Treichel; Julia Svirchevski; Mike Ravkin
Original assignee: Lam Research Corp
Current assignee: Lam Research Corp
Priority date: 1999-09-29
Filing date: 2002-09-03
Publication date: 2003-03-20
Also published as: JP2003510836A; DE60016773T8; DE60016773D1; KR100752965B1; EP1218927B1; KR20020030290A; TW508627B; DE60016773T2; WO2001024232A1; EP1218927A1; US20020061718A1

Abstract

A cover to be disposed over a substrate processing apparatus is provided. The cover includes a material capable of being tuned between an opaque state and a transparent state. Being tuned closer to the opaque state limits an amount of light capable of passing through the tunable cover and into the substrate processing apparatus during substrate processing. Being tuned closer to the transparent state allows viewing into the substrate processing apparatus without removing the cover.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from U.S. patent application Ser. No. 09/408,001, filed on Sep. 29, 1999, and entitled “METHOD AND APPARATUS FOR REDUCING PHOTO-ASSISTED CORROSION IN WAFERS DURING CLEANING PROCESSES.” This Patent Application is herein incorporated by reference.[0001]

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor wafer cleaning and, more particularly, to techniques for reducing photo-corrosion on wafers used to fabricate semiconductor devices.

2. Description of the Related Art

In the semiconductor chip fabrication process, it is well-known that there is a need to clean the surface of the wafer after a chemical mechanical polishing (CMP) process. A copper (Cu) CMP process leaves many types of contaminants such as particles and metallic ions on the wafer surface. Cleaning is therefore necessary to avoid the degradation of the electrical characteristics of the dielectrics.

For purposes of discussion only, FIG. 1 shows a simplified wafer cleaning system having a

brush box

100. After a copper CMP process, the wafer is sometimes put through HF containing cleaning process in the wafer cleaning system. The wafer enters the brush box 100 where the wafer may be inserted between a top brush 104 a and a bottom brush 104 b. The wafer is typically rotated by the brushes 104 and a set of rollers (not shown), thereby enabling the brushes 104 to adequately clean the top and bottom surfaces of the wafer. The cleaning process can be viewed through the brush box cover 102, which is typically a clear plastic material.

FIG. 2A shows a partial cross-sectional view of an

exemplary semiconductor chip

201 after the top layer has undergone a copper CMP process. Using standard impurity implantation, photolithography, and etching techniques, P-type transistors and N-type transistors are fabricated into the P-type silicon substrate 200. As shown, each transistor has a gate, source, and drain, which are fabricated into appropriate wells. The pattern of alternating P-type transistors and N-type transistors creates a complementary metal oxide semiconductor (CMOS) device.

A

first oxide layer

202 is fabricated over the transistors and substrate 200. Conventional photolithography, etching, and deposition techniques are used to create tungsten plugs 210 and copper lines 212. The tungsten plugs 210 provide electrical connections between the copper lines 212 and the active features on the transistors. A second oxide layer 204 may be fabricated over the first oxide layer 202 and copper lines 212. Conventional photolithography, etching, and deposition techniques are used to create copper vias 220 and copper lines 214 in the second oxide layer 204. The copper vias 220 provide electrical connections between the copper lines 214 in the second layer and the copper lines 212 or the tungsten plugs 210 in the first layer.

The wafer then typically undergoes a copper CMP process to planarize the surface of the wafer, leaving a level surface as shown in FIG. 2A. After the copper CMP process, the wafer is cleaned in the wafer cleaning system, as discussed above with reference to FIG. 1.

FIG. 2B shows the partial cross-sectional view of the conventional semiconductor wafer of FIG. 2A after the wafer has undergone a cleaning in the wafer cleaning system of FIG. 1. As shown, the

copper lines

214 on the top layer have been subjected to photo-corrosion during the cleaning process. The photo-corrosion is believed to be partially caused by light photons that pass through the clear plastic cover 102 of the brush box 100 and reaches the P/N junctions, which can act as solar cells. The light photons are projected ton the clear plastic cover 102 by way of normal cleanroom lighting. Unfortunately, this amount of normal light, which is generally needed to view the cleaning process (i.e., view whether the brushes are properly cleaning the wafers), causes a catastrophic corrosion effect.

In this cross-sectional example, the copper lines, copper vias, or tungsten plugs are electrically connected to different parts of the P/N junction. The cleaning solution used to clean the wafer surface, which is typically an electrolite, closes the electrical circuit as electrons e ⁻ and holes h⁺ are transferred across the P/N junctions. The electron/hole pairs photo-generated in the junction are separated by the electrical field. The introduced carriers induce a potential difference between the two sides of the junction. This potential difference increases with light intensity. Accordingly, at the electrode connected to the P-side of the junction, the copper is corroded: Cu→Cu²⁺+2e⁻. The produced soluble ionic species can diffuse to the other electrode, where the reduction can occur: Cu²⁺+2e⁻→Cu. Note that the general corrosion formula for any metal is M→Mⁿ⁺+ne⁻, and the general reduction formula for any metal is Mⁿ⁺+ne⁻→M.

Unfortunately, this type of photo-corrosion displaces the copper lines and destroys the intended physical topography of the copper features, as shown in FIG. 2B. At some locations on the wafer surface over the P-type transistors, the photo-corrosion effect may cause corroded

copper lines

224 or completely dissolved copper lines 226. In other words, the photo-corrosion may completely corrode the copper line such that the line no longer exists. On the other hand, over the N-type transistors, the photo-corrosion effect may cause copper deposit 222 to be formed. This distorted topography, including the corrosion of the copper lines, will cause device defects that render the entire chip inoperable. One defective device means the entire chip must be discarded, thus, decreasing yield and drastically increasing the cost of the fabrication process. This effect, however, will generally occur over the entire wafer, thus destroying all of the chips on the wafer. This, of course, increases the cost of fabrication.

Various attempts have been made to reduce the corrosion phenomenon. One attempt involves adding corrosion inhibitors in chemical cleaning solutions used to clean wafer surfaces. Examples of corrosion inhibitors include complexing agents or passivating agents. This method of altering the chemical cleaning solution, however, has not proven to be adequately effective. For more information on photo-corrosion effects, reference can be made to an article by A. Beverina et al., “Photo-Corrosion Effects During Cu Interconnection Cleanings,” to be published in the 196 ^th ECS Meeting, Honolulu, Hi. (October 1999). This article is hereby incorporated by reference.

In view of the foregoing, there is a need for a cleaning process that avoids the problems of the prior art by implementing improved techniques for reducing the photo-corrosion effect on wafers during cleaning.

SUMMARY OF THE INVENTION

Broadly speaking, the present invention fills these needs by providing methods and systems for substantially eliminating the photo-corrosion effect in semiconductor wafers during cleaning operations. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.

In one embodiment, a cover to be disposed over a substrate processing apparatus is provided. The cover includes a material capable of being tuned between an opaque state and a transparent state. Being tuned closer to the opaque state limits an amount of light capable of passing through the tunable cover and into the substrate processing apparatus during substrate processing. Being tuned closer to the transparent state allows viewing into the substrate processing apparatus without removing the cover.

In another embodiment, a cover to be disposed over a substrate processing apparatus is provided. The cover includes a multi-layer composite material capable of being tuned between the opaque state and the transparent state. The multi-layer composite material includes a first transparent layer, a transparency tunable layer over the first transparent layer, a first set of electrical connections attached to the transparency tunable layer at a first portion, a second set of electrical connections attached to the transparency tunable layer at a second portion, and a second transparent layer over the transparency tunable layer. Being tuned closer to the opaque state limits an amount of light capable of passing through the tunable cover and into the substrate processing apparatus during substrate processing. Being tuned closer to the transparent state allows viewing into the substrate processing apparatus without removing the cover.

In yet another embodiment, an integrated substrate processing tool is provided. The integrated substrate processing tool includes a system control unit, a substrate cleaning apparatus coupled to the system control unit, a cover disposed over the substrate cleaning apparatus, and a substrate polishing apparatus coupled to the system control unit. The cover is defined from a material capable of being tuned between an opaque state and a transparent state. Being tuned closer to the opaque state limits an amount of light capable of passing through the tunable cover and into the substrate cleaning apparatus during substrate processing. Being tuned closer to the transparent state allows viewing into the substrate cleaning apparatus without removing the cover. The cover is coupled to the system control unit for interfacing with tuning control circuitry that communicates commands for moving the cover between the opaque state and the transparent state. The substrate polishing apparatus is integrated with the substrate cleaning apparatus, wherein the substrate is transferred between each apparatus for processing.

In still another embodiment, a method for making a composite material is disclosed. A first transparent layer is formed. A transparency tunable layer is formed over the first transparent layer. Electrical connections are defined between a first portion and a second portion of the transparency tunable layer. And a second transparent layer is formed over the transparency tunable layer.

In yet another embodiment, a semiconductor wafer cleaning system is disclosed. The system comprises a cover having a first portion and a second portion, the cover being a multi-layer composite material. The cover includes a first transparent layer, a transparency tunable layer over the first transparent layer, a first set of electrical connections attached to the transparency tunable layer at the first portion, a second set of electrical connections attached to the transparency tunable layer at the second portion, and a second transparent layer over the transparency tunable layer.

In still another embodiment, a transparency tunable cover is disclosed. The cover has a first side and a second side and comprises a first transparent layer extending between the first side and the second side, a transparency tunable layer coated over the first transparent layer, a first set of electrical connections conductively integrated to the coated transparency tunable layer at the first side, a second set of electrical connections conductively integrated to the coated transparency tunable layer at the second side, and a second transparent layer coated over the transparency tunable layer and extending between the first side and the second side.

Advantageously, the present invention addresses the problem of photoassisted corrosion by providing a cover for a wafer cleaning system that preferably can be tuned from being substantially transparent to being opaque. When the cover is opaque, the cleaning process can be run in the substantial absence of light, thereby nearly eliminating the damaging effects of light energy on the wafer surface. In addition to stand-alone cleaning systems, the cover can also be integrated into a post-chemical mechanical polishing (post-CMP) cleaning system in order to minimize photo-assisted corrosion. Photo-assisted corrosion can also be minimized by integrating such a cover to an integrated CMP tool. Integrated CMP tools are those that implement both a cleaning module and a CMP module. Typically, these modules are joined or connected by way of special wafer handling equipment.

Thus, a wafer being cleaned preferably will not be effected by photo-corrosion that displaces copper lines and that destroys the intended topography of the copper features. As a result, device defects that render the entire chip inoperable will be substantially reduced. Fewer chips will have to be discarded, yield will preferably increase, and the cost of running the fabrication process will not unduly increase.

Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, in which like reference numerals designate like structural elements. [0025]
FIG. 1 shows a wafer cleaning system having a brush box. [0026]
FIG. 2A shows a cross-sectional view of a conventional semiconductor chip after the top layer has undergone a copper CMP process. [0027]
FIG. 2B shows a cross-sectional view of the conventional semiconductor chip of FIG. 2A after the wafer has undergone a cleaning in the wafer cleaning system of FIG. 1. [0028]
FIG. 3A shows a top view of a wafer cleaning system, in accordance with one embodiment of the present invention. [0029]
FIG. 3B shows a side view of a wafer cleaning system, in accordance with one embodiment of the present invention. [0030]
FIG. 3C shows a side view of a wafer cleaning system, in accordance with one embodiment of the present invention. [0031]
FIG. 4A shows a side view of a composite material used for the cover on a wafer cleaning system, in accordance with one embodiment of the present invention. [0032]
FIG. 4B shows a top view of a composite material used for the cover on a wafer cleaning system, in accordance with one embodiment of the present invention. [0033]
FIG. 5 shows a high-level schematic diagram of preferred system components for the tunable transparency cover, in accordance with one embodiment of the present invention. [0034]
FIG. 6A shows a flow chart of a method for forming a composite material, in accordance with one embodiment of the present invention. [0035]
FIG. 6B shows a flow chart of a method for forming a transparency tunable cover for a wafer cleaning system, in accordance with one embodiment of the present invention. [0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An invention for methods and systems for reducing photo-assisted copper corrosion during a wafer cleaning process are disclosed. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be understood, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention. [0037]
FIGS. 3A, 3B, and [0038] 3C show a top view and side views, respectively, of a wafer cleaning system, in accordance with one embodiment of the present invention. The wafer cleaning system 300 typically includes an input station 302 where a plurality of wafers may be inserted for cleaning through the system after the wafers have undergone CMP operations. Once the wafers are inserted into the input station 302, a wafer may be taken from the input station 302 and moved into the brush box 304, which contains a first brush box 304 a and a second brush box 304 b. Inside the brush box, various cleaning operations may be applied to the wafer.
After brushes have been applied to the wafer in the [0039] brush boxes 304, the wafer is moved into a spin, rinse, and dry (SRD) station 306. In the SRD station 306, deionized (DI) water is sprayed onto the surface of the wafer while the wafer is spun at a speed of between about 100 and 400 revolutions per minute, and then is spun to dry. After the wafer has been placed through the SRD station 306, an unload handler 308 takes the wafer and moves it into an output station 310. The cleaning system 300 is programmed and controlled from system electronics 312.
The transparency level of the cover of the [0040] wafer cleaning system 300 is preferably tunable from being substantially transparent to being opaque, as shown in FIG. 3C. The “cover” is the portion of the wafer cleaning system that houses the wafer cleaning operations. The term “substantially transparent” means substantially all of the light that is directed toward the outer surface of the cover passes through the cover. The term “opaque” means about none of the light that is directed toward the outer surface of the cover passes through the cover. The “outer surface of the cover” refers to the surface of the cover that is not facing the wafer cleaning operations. The term “light” refers to light that is within the ultra-violet (UV) and visible spectrum. Depending on the material used to construct the cover, a change in transparency may be accompanied by a corresponding change in color, as further discussed below with reference to FIG. 4A.
When the cover is substantially transparent, a user can view the cleaning process. However, as discussed in greater detail above, light energy may assist in corroding copper lines when cleaning is performed after a copper CMP process. Accordingly, the present invention provides a cover for the cleaning system that preferably can be tuned to be opaque when cleaning operations are being performed and substantially transparent when the cleaning is not being performed. In certain cases, it may be desired to run a cleaning operation when the cover is substantially opaque, but the inner cleaning operations can still be viewed. This will allow an operator to determine whether the brushes are operating properly, and the like. [0041]
FIGS. 4A and 4B show a side view and a top view, respectively, of a [0042] composite material 400 used for the cover on a wafer cleaning system, in accordance with one embodiment of the present invention. The composite material 400 preferably includes a first transparent layer 404 a, a second transparency layer 404 b, and a transparency tunable layer 406 coated between the transparency layers 404. The transparency layers 404 are preferably a clear acrylic material. Although, other known plastics and/or glass can also be used.
The [0043] transparency tunable layer 406 is preferably a photochromic or electrochromic material, such as tungsten oxide (WO₃, WO_x). Alternative materials can include, for example, NB₂O₅, V₂O₇, TiO₂, ZnO, Cr₂O₃, MnO₂, CoO, NiO₂. Any one of these materials can also be implemented depending on the specific application. For purposes of this exemplary discussion, reference will be made to tungsten oxide. To create the composite material, the transparency tunable layer 406 is preferably sputtered onto the first transparency layer 404 a (or the second transparency layer 404 b). Another technique is a spin-on technique, where the transparency tunable layer 404 a is, for example, formed by a “sol-gel” process. The second transparency layer 404 b is formed atop the transparency tunable layer 406.
Sets of [0044] electrical connections 402 a and 402 b are conductively integrated to portions of the transparency tunable layer 406. When a bias voltage V⁺ is applied across the transparency tunable layer 406 between the portions, an electrical circuit defined by the electrical connections 402 and the transparency tunable layer 406 is closed. As shown in a preferred embodiment in FIG. 4, a first portion is on a first side of the transparency tunable layer 406, and a second portion is on a second side of the transparency tunable layer 406.
As the desired voltage application V[0045] ⁺ is increased, a current I that runs across the transparency tunable layer 406 proportionately increases. This increase in current causes electrons e⁻ to flow and excite the atoms in the photochromic or electrochromic material. This excitation of atoms causes a change in transparency level, which may be accompanied by a change in color. Tungsten oxide, for example, is a light yellowish color in a lesser excited state, thereby making the tunable layer 406 substantially transparent. Tungsten oxide is a dark blue color in a more excited state, thereby making the tunable layer 406 opaque. In sum, a low voltage V⁺ causes the cover to be substantially transparent, while a high voltage V⁺ causes the cover to be opaque.
Generally, the voltage V[0046] ⁺ preferably ranges from between about 0.5 volts and about 3 volts, more preferably between about 1 volt and about 1.5 volts, and most preferably about 1.25 volts. Where tungsten oxide (WO₃) is used, the voltage V⁺ preferably ranges from between about 0.5 volts and about 5 volts, and most preferably about 3 volts.
The dimensions of the [0047] composite material 400 are preferably defined by at least two parameters, the cover thickness b and the tunable layer thickness a. The cover thickness b is preferably about 1 cm. The tunable layer thickness a is preferably between about 0.5 μm and about 10 μm, and most preferably about 3 μm.
FIG. 5 shows a high-level schematic diagram of preferred system components for the tunable transparency cover, in accordance with one embodiment of the present invention. A [0048] voltage controller 502 has electrodes (not shown) coupled to the electrical connections 402 and, thereby, establishes a bias voltage V⁺ across the transparency tunable layer 406. Tuning control circuitry 504 that receives input from a control unit 506 provides the appropriate state for the voltage controller 502. The control unit 506 provides a user with operation control 512 and emergency control 514. When the user is using the operation control 512, the tuning control circuitry 504 provides a state of regular operation 510 to the voltage controller 502. Operation control 512 allows the user to tune the voltage low or high, depending on the transparency level that is required.
When the user is using the [0049] emergency control 514, the tuning control circuitry 504 preferably provides a voltage shut-off to the voltage controller 502. When the voltage is shut-off, the composite material 400 is preferably in about its most transparent state. The emergency control 514 may be desired for cases when the cleaning system experiences a problem, e.g., a broken wafer, and the user needs to ascertain the problem immediately. In other cases, the emergency control 514 will be advantageous when the power unexpectedly shuts off and the operator needs to view the inside of the cleaner to determine the current state of a cleaning session.
FIG. 6A shows a flow chart of a method for forming a [0050] composite material 400, in accordance with one embodiment of the present invention. The method starts in operation 702 where a first transparent layer is formed. The method then proceeds to operation 704 where a transparency tunable layer is formed over the first transparent layer. The transparency tunable layer preferably has characteristics such as those discussed with reference to FIGS. 4A and 4B. Next, the method moves to operation 706 where electrical connections are defined between a first portion and a second portion of the transparency tunable layer. The method then moves to operation 708 where a second transparent layer is formed over the transparency tunable layer.
FIG. 6B shows a flow chart of a method for forming a transparency tunable cover for a wafer cleaning system, in accordance with one embodiment of the present invention. The method starts in [0051] operation 802 where a first transparent layer is formed for a semiconductor cleaning station cover. The method then proceeds to operation 804 where a transparency tunable layer is formed over the first transparent layer.
The cover preferably has electrodes at appropriate ends to enable circuitry to couple thereto and enable a current flow, as discussed with reference to FIG. 4B. The current flow through the cover will therefore enable the cover to change in transparency. When the cleaning system is operational, and the cleaning is being performed after a copper CMP, the photo-assisted corrosion will be advantageously prevented. This is a substantial advance in cleaning technology, in that conventional cleaning systems all use one-state clear covers that allow light to freely pass therethrough. A cleaning system using this tunable cover can now program the state of transparency to be substantially dark when the cleaning is in progress and light when no cleaning operation is being performed. Of course, the level of transparency can vary anywhere in between each extreme, depending on the users needs and the type of cleaning being performed. [0052]
Next, the method moves to [0053] operation 806 where electrical connections are defined between a first portion and a second portion of the transparency tunable layer. The method then moves to operation 808 where a second transparent layer is formed over the transparency tunable layer.
While this invention has been described in terms of several preferred embodiments, it will be appreciated that those skilled in the art upon reading the preceding specifications and studying the drawings will realize various alterations, additions, permutations and equivalents thereof. For example, although specific reference is made to brush boxes, any other brush scrubbing apparatus can benefit from the method teachings of the present invention. Additionally, the cleaning embodiments can be applied to any size wafer, such as, 200 mm, 300 mm, and larger, as well as other sizes and shapes. It is therefore intended that the present invention includes all such alterations, additions, permutations, and equivalents that fall within the true spirit and scope of the invention.[0054]

Claims

What is claimed is:

1. A cover configured to be disposed over a substrate processing apparatus, the cover comprising:

a material capable of being tuned between an opaque state and a transparent state, wherein being tuned closer to the opaque state limits an amount of light capable of passing through the tunable cover and into the substrate processing apparatus during substrate processing, and the cover being tuned closer to the transparent state allows viewing into the substrate processing apparatus without removing the cover.

2. A cover as recited in claim 1, wherein the material is a multi-layer composite material that includes,

a first transparent layer;

a transparency tunable layer over the first transparent layer;

a first set of electrical connections attached to the transparency tunable layer at a first portion;

a second set of electrical connections attached to the transparency tunable layer at a second portion; and

a second transparent layer over the transparency tunable layer.

3. A cover as recited in claim 2, wherein the first transparent layer and the second transparent layer are acrylic.

4. A cover as recited in claim 2, wherein the transparency tunable layer is configured to be one of a photochromic and electrochromic material.

5. A cover as recited in claim 2, wherein the transparency tunable layer is tungsten oxide.

6. A cover configured to be disposed over a substrate processing apparatus, the cover comprising:

a multi-layer composite material capable of being tuned between an opaque state and a transparent state, the multi-layer composite material including,

a first transparent layer;

a transparency tunable layer over the first transparent layer;

a second transparent layer over the transparency tunable layer,

wherein being tuned closer to the opaque state limits an amount of light capable of passing through the tunable cover and into the substrate processing apparatus during substrate processing, and the cover being tuned closer to the transparent state allows viewing into the substrate processing apparatus without removing the cover.

7. A cover as recited in claim in claim 6, wherein the substrate processing apparatus is an integrated chemical mechanical polishing (CMP) apparatus.

8. A cover as recited in claim in claim 7, wherein the integrated CMP apparatus includes a cleaning module and a CMP module.

9. A cover as recited in claim in claim 6, wherein the substrate processing apparatus is a post-CMP cleaning system.

10. A cover as recited in claim 6, wherein the transparency tunable layer is configured to be one of a photochromic and electrochromic material.

11. A cover as recited in claim 6, wherein the transparency tunable layer is made from a material selected from the group consisting of WO₃, WO_x, NB₂O₅, V₂O₇, TiO₂, ZnO, Cr₂O₃, MnO₂, CoO, and NiO₂.

12. An integrated substrate processing tool, comprising:

a system control unit;

a substrate cleaning apparatus being coupled to the system control unit;

a cover configured to be disposed over the substrate cleaning apparatus, the cover being defined from a material capable of being tuned between an opaque state and a transparent state, wherein being tuned closer to the opaque state limits an amount of light capable of passing through the tunable cover and into the substrate cleaning apparatus during substrate processing, and the cover being tuned closer to the transparent state allows viewing into the substrate cleaning apparatus without removing the cover, the cover being coupled to the system control unit for interfacing with tuning control circuitry that communicates commands for moving the cover between the opaque state and the transparent state; and

a substrate polishing apparatus being coupled to the system control unit, the substrate polishing apparatus being integrated with the substrate cleaning apparatus, wherein the substrate is transferred between each apparatus for processing.

13. An integrated substrate processing tool as recited in claim 12, wherein the material is a multi-layer composite material that includes,

a first transparent layer;

a transparency tunable layer over the first transparent layer;

a second transparent layer over the transparency tunable layer.

14. An integrated substrate processing tool as recited in claim 13, wherein a first electrode connector of a voltage controller defined in the substrate cleaning apparatus is coupled to the first set of electrical connections and a second electrode connector of the voltage controller is coupled to the second set of electrical connections.

15. An integrated substrate processing tool as recited in claim 14, wherein the voltage controller coupled to the cover is integrated to the tuning control circuitry, the tuning control circuitry being configured to set a bias voltage to the transparency tunable layer so as to cause a change in a transparency level of the cover.

16. An integrated substrate processing tool as recited in claim 15, wherein an increase in the magnitude of the bias voltage decreases the transparency level of the cover.

17. An integrated substrate processing tool as recited in claim 15, wherein a decrease in the magnitude of the bias voltage increases the transparency level of the cover.

18. An integrated substrate processing tool as recited in claim 15, wherein when the magnitude of the bias voltage is about zero, the cover is substantially transparent.

19. An integrated substrate processing tool as recited in claim 13, wherein the first transparent layer and the second transparent layer are acrylic.

20. An integrated substrate processing tool as recited in claim 13, wherein the transparency tunable layer is configured to be one of a photochromic and electrochromic material.