US10109714B2 - Buried contact structures for a vertical field-effect transistor - Google Patents
Buried contact structures for a vertical field-effect transistor Download PDFInfo
- Publication number
- US10109714B2 US10109714B2 US15/694,109 US201715694109A US10109714B2 US 10109714 B2 US10109714 B2 US 10109714B2 US 201715694109 A US201715694109 A US 201715694109A US 10109714 B2 US10109714 B2 US 10109714B2
- Authority
- US
- United States
- Prior art keywords
- effect transistor
- section
- layer
- field
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 claims abstract description 111
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 127
- 125000006850 spacer group Chemical group 0.000 description 25
- 239000000463 material Substances 0.000 description 23
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000003672 processing method Methods 0.000 description 5
- 239000000470 constituent Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 230000000737 periodic effect Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000000615 nonconductor Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- -1 SiO2) Chemical compound 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Definitions
- the present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures including a vertical field-effect transistor, as well as methods of fabricating a structure including a vertical field-effect transistor.
- CMOS complementary metal-oxide-semiconductor
- Field-effect transistor structures can be broadly categorized based upon the orientation of the channel relative to a surface of a semiconductor substrate in conjunction with which they are formed.
- the channel is located in a semiconductor fin that projects vertically from the surface of the semiconductor substrate and that is surrounded by a gate electrode.
- a source/drain region is arranged at the bottom of the semiconductor fin, and another source/drain region is arranged at the top of the semiconductor fin.
- the gate electrode is arranged vertically between the source/drain regions. The direction of the gated current flow in the channel between the source/drain regions is generally perpendicular (i.e., vertical) to the substrate surface and parallel to the height of the fin.
- the bottom source/drain region protrudes laterally relative to the footprint of the gate electrode to provide an area for landing the middle-of-line contact that is vertically oriented.
- the contact and series resistance of the bottom source/drain region may be higher than desirable.
- the requirement for a middle-of-line contact hinders the scaling of invertors formed using vertical field-effect transistors.
- Improved structures including a vertical field-effect transistor and improved fabrication methods for a structure including a vertical field-effect transistor are needed.
- a structure includes a vertical field-effect transistor having a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin.
- the structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.
- a method includes forming a first semiconductor fin and a second semiconductor fin of a field-effect transistor on a section of a semiconductor layer with the first semiconductor fin and second semiconductor fin having a parallel arrangement.
- the method further includes forming a trench in the section of the semiconductor layer that is positioned between the first semiconductor fin and the second semiconductor fin.
- the method further includes forming a contact in the trench in the section of the semiconductor layer.
- a source/drain region of the field-effect transistor is located in the section of the semiconductor layer.
- the trench is arranged in the section of the semiconductor layer such that the contact is coupled with the source/drain region of the field-effect transistor.
- FIG. 1 is a top view of a structure at an initial fabrication stage of a processing method in accordance with embodiments of the invention and in which sections of a hardmask layer on top of the fins is omitted for clarity of description.
- FIG. 1A is a cross-sectional view taken generally along line 1 A- 1 A in FIG. 1 .
- FIG. 1B is a cross-sectional view taken generally along line 1 B- 1 B in FIG. 1 .
- FIG. 2 is a top view of the structure at a fabrication stage of the processing method subsequent to FIG. 1 and in which sections of a hardmask layer on top of the fins is omitted for clarity of description.
- FIG. 2A is a cross-sectional view taken generally along line 2 A- 2 A in FIG. 2 .
- FIG. 2B is a cross-sectional view taken generally along line 2 B- 2 B in FIG. 2 .
- FIG. 3 is a top view of the structure at a fabrication stage of the processing method subsequent to FIG. 2 and in which sections of a hardmask layer on top of the fins and sidewall spacers are omitted for clarity of description.
- FIG. 3A is a cross-sectional view taken generally along line 3 A- 3 A in FIG. 3 .
- FIG. 3B is a cross-sectional view taken generally along line 3 B- 3 B in FIG. 3 .
- FIG. 3C is a cross-sectional view taken generally along line 3 C- 3 C in FIG. 3 .
- FIG. 4 is a top view of the structure at a fabrication stage of the processing method subsequent to FIG. 3 and in which sections of a hardmask layer on top of the fins is omitted for clarity of description.
- FIG. 4A is a cross-sectional view taken generally along line 4 A- 4 A in FIG. 4 .
- FIG. 4B is a cross-sectional view taken generally along line 4 B- 4 B in FIG. 4 .
- FIGS. 5A and 5B are respective cross-sectional views at a fabrication stage of the processing method subsequent to FIGS. 4A and 4B .
- FIG. 5C is a cross-sectional view similar to FIG. 3C at the fabrication stage of FIGS. 5A and 5B .
- FIG. 6 is a cross-sectional view similar to FIG. 3C in accordance with alternative embodiments of the invention.
- FIG. 7 is a cross-sectional view similar to FIG. 3C in accordance with alternative embodiments of the invention.
- fins 10 may project vertically from a doped layer 14
- fins 12 may project vertically from a doped layer 16 .
- Each of the fins 12 may be aligned in a row with one of the fins 10
- each of the fins 10 and the fins 12 may be capped by a section of the hardmask layer 15 .
- the doped layers 14 , 16 may constitute portions of an epitaxial semiconductor layer 17 at the top surface of a substrate 18 .
- the substrate 18 beneath the doped layer 14 may be, for example, a bulk single-crystal silicon substrate.
- the fins 10 , 12 may be three-dimensional bodies comprised of a semiconductor material, such as intrinsic silicon, and may project in a vertical direction relative to a top surface of the substrate 18 .
- the fins 10 , 12 may be formed from an epitaxial layer of intrinsic semiconductor material that is grown on a top surface of the doped layer 14 and patterned using photolithography and etching processes, such as a sidewall imaging transfer (SIT) process or self-aligned double patterning (SADP).
- SIT sidewall imaging transfer
- SADP self-aligned double patterning
- Each of the fins 10 , 12 may be capped by a section of a hardmask layer 15 composed of, for example, silicon nitride (Si 3 N 4 ), that is introduced during fin patterning.
- the fins 10 may be used to form a vertical field-effect transistor in which the doped layer 14 serves as a bottom source/drain region.
- the fins 12 may be used to form a vertical field-effect transistor in which the doped layer 16 serves as a bottom source/drain region.
- source/drain region means a doped region of semiconductor material that can function as either a source or a drain of a vertical field-effect transistor.
- the fins 10 may be used to form an n-type vertical field-effect transistor, and the fins 12 may be used to form a p-type vertical field-effect transistor.
- the doped layer 14 may be composed of silicon and include a concentration of an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P) or arsenic (As)) that is effective to impart n-type electrical conductivity to the constituent semiconductor material.
- Group V of the Periodic Table e.g., phosphorus (P) or arsenic (As)
- the doped layer 16 may be composed of a silicon-germanium (SiGe) alloy and include a concentration of p-type dopant from Group III of the Periodic Table (e.g., boron (B)) in a concentration that is effective to impart p-type to the constituent semiconductor material. If composed of a silicon-germanium (SiGe) alloy, the doped layer 16 may be formed by, for example, a thermal condensation technique.
- trenches 20 are formed in the doped layer 14
- trenches 22 are formed in the doped layer 16
- a trench 24 is formed at a location positioned between the trenches 20 and the trenches 22 .
- Each of the trenches 20 is located between a pair of the fins 10 and may extend along a portion of the length of the fins 10 .
- the trenches 20 are recessed into the doped layer 14 to a given depth relative to a top surface 11 of the doped layer 14 and a top surface 13 of the doped layer 16 .
- Each of the trenches 22 is located between a pair of the fins 12 and may extend along a portion of the length of the fins 12 .
- the trenches 22 are recessed into the doped layer 16 to a given depth relative to a top surface 13 of the doped layer 16 .
- the fins 10 and trenches 20 are located on one side of trench 24
- fins 12 and trenches 22 are located on the opposite side of trench 24 .
- the trench 24 is located between fins 10 and fins 12 .
- Trenches 20 and trenches 22 intersect with the trench 24 to form a continuous recessed volume.
- the trench 24 is recessed into both of the doped layers 14 , 16 to a given depth relative to the top surfaces 11 , 13 . In an embodiment, the depths of the trenches 20 , 22 , 24 may be equal.
- the trenches 20 , 22 , 24 maybe formed by a self-aligned etching process.
- the top surfaces 11 , 13 may be slightly recessed by the self-aligned etching process by a lesser extent than at the location of the trenches 20 between the adjacent fins 10 , trenches 22 between adjacent fins 12 , and trench 24 between the fins 10 and the fins 12 .
- the self-aligned etching process may rely on loading or another effect that causes deeper etching over smaller-size areas located between adjacent pairs of the fins 10 , 12 .
- the self-aligned etching process may be performed in conjunction with the etching process forming the fins 10 , 12 in a seamless manner, rather than performed as a separate etching process as in the representative embodiment.
- an additional trench 20 may be formed in the doped layer 14 adjacent to each of the fins 10 that are at the opposite edges of the set of fins 10
- an additional trench 22 may be formed in the doped layer 16 adjacent to each of the fins 12 that are at the opposite edges of the set of fins 12 .
- the added trenches 20 , 22 are intersected by extensions of trench 24 .
- the added trenches 20 which are located adjacent to only a single fin 10 , may be narrower in width than the trenches 20 that are located between adjacent pairs of fins 10 .
- the added trenches 22 which are located adjacent to only a single fin 12 , may be narrower in width than the trenches 22 that are located between adjacent pairs of fins 12 .
- spacers 26 are formed along the sidewalls of the fins 10 , 12 .
- the spacers 26 may be composed of a dielectric material, such as silicon nitride (Si 3 N 4 ) deposited by CVD.
- a conformal layer of the dielectric material may be deposited and etched with an anisotropic etching process, such as reactive ion etching (RIE), that preferentially removes the dielectric material of conformal layer from horizontal surfaces and leaves the spacers 26 on vertical surfaces (e.g., the vertical sidewalls of the fins 10 , 12 ).
- RIE reactive ion etching
- the trenches 20 , 22 , 24 are respectively filled with contacts 28 , 30 , 32 .
- a conductor layer may be deposited and recessed with an etching process such that the remaining conductor is located in the trenches 20 , 22 , 24 to form the contacts 28 , 30 , 32 .
- the contacts 28 , 30 , 32 may be composed of a metal, such as titanium (Ti), titanium nitride (TiN), or tungsten (W), deposited by CVD.
- the contacts 28 are coupled with the bottom source/drain region provided by the doped layer 14 associated with fins 10 .
- the contacts 30 are coupled with the bottom source/drain region provided by the doped layer 16 associated with fins 12 .
- the contact 32 cross-couples the contacts 28 with the contacts 30 .
- the spacers 26 are located between the conductor layer and the fins 10 , 12 so as to prevent contact, and protect the fins 10 , 12 during the etching process that recesses the conductor layer.
- the doped layer 14 intersects with the doped layer 16 along a vertical interface 34 to define a p-n junction.
- the p-n junction defined by the vertical interface 34 is located vertically beneath the contact 32 .
- the contacts 28 , 30 , 32 provide a continuous conductive path that is in a contacting relationship with the doped layer 14 and in a contacting relationship with the doped layer 16 .
- a trench isolation region 36 is formed in the doped layers 14 , 16 .
- the trench isolation region 36 defines the size, geometrical shape, and outer boundary for the active device regions used to form the vertical field-effect transistors and extends about the outer perimeter of these active device regions.
- the trench isolation region 36 is located in trenches penetrating vertically to a shallow depth into the doped layers 14 , 16 .
- the trench isolation region 36 may be formed by a shallow trench isolation (STI) technique that relies on lithography and dry etching processes to define the trenches, deposits an electrical insulator to fill the trenches, and recesses the electrical insulator using, for example, an etch-back process.
- the trench isolation region 36 may be comprised of a dielectric material, such as silicon dioxide (e.g., SiO 2 ), deposited by CVD.
- the trench isolation region 36 does not extend into the space between the fins 10 and the fins 12 because this space is occupied by the contact 32 , as best shown in FIG. 3C . As such, the normal trench isolation that is formed between the fins 10 and the fins 12 can be eliminated.
- the doped layer 14 providing a bottom source/drain region for vertical field-effect transistors of one CMOS type and the doped layer 16 providing a bottom source/drain region for vertical field-effect transistors of the opposite CMOS type are touching and in contact, which provides an n-p junction.
- the sharing of the bottom source/drain regions afforded by the elimination of the conventional trench isolation region between fins 10 and fins 12 may permit a significant reduction in the footprint of a CMOS inverter by shrinking the dimensions of the device layout.
- a bottom spacer layer 38 is formed on the top surface 13 of the doped layer 14 , on the top surface of the doped layer 16 , and on the contacts 28 , 30 , 32 .
- the bottom spacer layer 38 may be composed of a dielectric material, such as silicon nitride (Si 3 N 4 ), that is deposited by a directional deposition technique, such as gas cluster ion beam (GCM) deposition.
- a dielectric material such as silicon nitride (Si 3 N 4 )
- GCM gas cluster ion beam
- the fins 10 , 12 penetrate vertically through the thickness of the bottom spacer layer 38 with only a fraction of their respective lengths overlapped by the bottom spacer layer 38 , while the contacts are buried in the doped layers 14 , 16 beneath the bottom spacer layer 38 .
- a gate electrode 40 is formed that surrounds respective vertical channel regions of the fins 10 and a gate electrode 42 is formed that surrounds respective vertical channel regions of the fins 12 .
- the gate electrodes 40 , 42 each include a gate electrode layer 44 and a gate dielectric layer 46 .
- the gate electrode layer 44 may be composed of one or more metals (e.g., titanium (Ti) and/or tungsten (W)) deposited by physical vapor deposition (PVD), CVD, etc.
- the gate dielectric layer 46 may be composed of an electrical insulator, such as a high-k dielectric material like hafnium oxide, deposited by CVD, ALD, etc.
- the gate electrodes 40 , 42 may be formed by conformally depositing the gate dielectric layer 46 , depositing the gate electrode layer 44 , and recessing these layers 44 , 46 with an etching process.
- a top spacer layer 48 is formed on the top surface of the gate electrode layer 44 .
- the top spacer layer 48 may be composed of a dielectric material, such as silicon nitride (Si 3 N 4 ), that is deposited by CVD and then planarized by chemical mechanical polishing (CMP).
- CMP chemical mechanical polishing
- the fins 10 , 12 may penetrate vertically through the thickness of the top spacer layer 48 and protrude above the top spacer layer 48 .
- the recessed top surface of the gate electrode layer 44 provides the vertical space needed to form the top spacer layer 48 .
- the layer stack that includes the bottom spacer layer 38 , gate electrode layer 44 , and top spacer layer 48 may be patterned by performing a masked etch, such as reactive ion etching (RIE) with an etch mask applied, using one or more etch chemistries.
- the gate electrode layer 44 is patterned to form the gate electrodes 40 , 42 .
- a patterned section of the bottom spacer layer 38 underlies each of the gate electrodes 40 , 42 and a patterned section of the top spacer layer 48 overlies each of the gate electrodes 40 , 42 .
- the gate electrodes 40 and 42 may be connected with each other, as in an inverter. Alternatively, the gate electrode 40 may be disconnected and isolated from gate electrode 42 after patterning.
- Top source/drain regions 50 of a vertical field-effect transistor 70 are formed that are respectively coupled with one end of the fins 10 .
- a vertical channel region is defined in a portion of the fins 10 overlapped by the gate electrode 40 vertically between the bottom source/drain region defined by the doped layer 14 and the top source/drain regions 50 .
- the semiconductor material constituting the top source/drain regions 50 is doped to have the same conductivity type as the doped layer 14 .
- the top source/drain regions 50 may be sections of an epitaxial layer of semiconductor material formed by an epitaxial growth process with in-situ doping, and may include a concentration of an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P) or arsenic (As)) effective to impart n-type electrical conductivity to the constituent semiconductor material.
- Group V of the Periodic Table e.g., phosphorus (P) or arsenic (As)
- the top source/drain regions 50 may be formed by a selective epitaxial growth (SEG) process in which semiconductor material nucleates for epitaxial growth on semiconductor surfaces such as the surfaces of the fins 10 , but does not nucleate for epitaxial growth from insulator surfaces (e.g., the top spacer layer 48 ).
- SEG selective epitaxial growth
- the top source/drain regions 50 may grow upwardly and laterally to overgrow areas on the top surface of the top spacer layer 48 locally near the respective fins 10 .
- the top source/drain regions 50 are positioned in alignment with the portions of the fins 10 revealed through the top spacer layer 48 .
- top source/drain regions 52 of a vertical field-effect transistor 72 are formed that are respectively coupled with one end of the fins 12 .
- a vertical channel region is defined in a portion of the fins 12 overlapped by the gate electrode 42 vertically between the bottom source/drain region defined by the doped layer 16 and the top source/drain regions 52 .
- the semiconductor material constituting the top source/drain regions 52 is doped to have the same conductivity type as the doped layer 16 .
- the top source/drain regions 52 may be sections of an epitaxial layer of semiconductor material formed by an epitaxial growth process with in-situ doping, and may include a concentration of a p-type dopant from Group III of the Periodic Table (e.g., boron (B)) effective to impart p-type electrical conductivity to the constituent semiconductor material.
- the top source/drain regions 52 may be composed of a silicon-germanium (SiGe) alloy and may be formed separately from the top source/drain regions 50 .
- the epitaxial growth process forming the top source/drain regions 52 is separate and distinct from the epitaxial growth process forming the top source/drain regions 50 .
- the top source/drain regions 50 may be masked with a protective layer during the growth of the top source/drain regions 52 .
- the top source/drain regions 52 may be formed by a selective epitaxial growth (SEG) process in which semiconductor material nucleates for epitaxial growth on semiconductor surfaces such as the surfaces of the fins 12 , but does not nucleate for epitaxial growth from insulator surfaces (e.g., the top spacer layer 48 ).
- SEG selective epitaxial growth
- the top source/drain regions 52 may grow upwardly and laterally to overgrow areas on the top surface of the top spacer layer 48 locally near the respective fins 12 .
- the top source/drain regions 52 are positioned in alignment with the portions of the fins 12 revealed through the top spacer layer 48 .
- MOL processing follows to define a local interconnect structure.
- An interlayer dielectric layer 54 is formed that covers the vertical field-effect transistors 70 , 72 .
- the interlayer dielectric layer 54 may be composed of a dielectric material, such as silicon dioxide (SiO 2 ), deposited by chemical vapor deposition (CVD) and planarized with, for example, CMP.
- a contact 56 is formed in the interlayer dielectric layer 54 that is coupled with the top source/drain regions 50 of the vertical field-effect transistor 70 .
- a contact 58 is formed in the interlayer dielectric layer 54 that is coupled with the top source/drain regions 52 of the vertical field-effect transistor 72 .
- a contact 60 is formed in the interlayer dielectric layer 54 that is coupled with the gate electrode 40 of the vertical field-effect transistor 70 .
- a contact 62 is formed in the interlayer dielectric layer 54 that is coupled with the gate electrode 40 of the vertical field-effect transistor 72 .
- a contact (not shown) is formed in the interlayer dielectric layer 54 that is coupled with the doped layer 16 of the vertical field-effect transistor 72 .
- the contacts 56 , 58 , 60 , 62 may be composed of a conductor, such as tungsten (W), and may be clad with a conductive liner (e.g., titanium nitride (TiN)).
- BEOL processing follows, which includes formation of dielectric layers, via plugs, and wiring for an interconnect structure coupled by the local interconnect structure with the vertical field-effect transistors 70 , 72 , as well as other similar contacts for additional device structures that replicate the vertical field-effect transistors 70 , 72 .
- the doped layers 14 , 16 representing the respective source/drain regions of the vertical field-effect transistors 70 , 72 are coupled together by the buried metal of the contacts 28 , 30 , 32 .
- the doped layer 14 has an ohmic contact with the contact 28
- the doped layer 16 has an ohmic contact with the contact 30 .
- the contacts 28 , 30 , 32 provide an electrical connection that eliminates the need for contacts and trench silicide that extend through the interlayer dielectric layer 54 to, for example, the doped layer 14 serving as the bottom source/drain region of the vertical field-effect transistor 70 .
- the buried metal structure represented by the contacts 28 , 30 , 32 may promote interconnection of the bottom source/drain regions of the vertical field-effect transistors 70 , 72 in an inverter with less wiring in the BEOL interconnect structure.
- the buried metal structure which is provided by the contacts 28 , 30 , 32 , may significantly reduce contact and series resistance so as to improve the performance of advanced devices.
- the elimination of trench isolation between the fins 10 and the fins 12 may promote the scaling of a MOSFET inverter formed using the vertical field-effect transistors 70 , 72 because a minimum space for the insertion of trench isolation is not needed in the device layout so as to shrink the size of a standard cell.
- the doped layers 14 , 16 may be located over a lightly-doped layer 80 formed in the substrate 18 .
- the lightly-doped layer 80 is separated vertically from a portion of the substrate 18 by a doped layer 82 .
- the semiconductor material of the substrate 18 may be doped to have a particular conductivity type.
- the doped layer 82 may be constituted by semiconductor material of the substrate 18 that has been doped to have the opposite conductivity type from the lightly-doped layer 80 and the substrate 18 .
- the doped layer 82 may be composed of n-type semiconductor material from an n-well, the lightly-doped layer 80 may be composed of p-type semiconductor material formed by ion implantation, and the substrate 18 may be composed of p-type semiconductor material.
- the doped layer 82 may be composed of n-type semiconductor material from a deep n-well, the lightly-doped layer 80 may be composed of p-type semiconductor material from a p-well, and the substrate 18 may be composed of p-type semiconductor material.
- the doped layer 14 may be formed in a well 90 constituted by semiconductor material of the substrate 18 that has been doped to have the opposite conductivity type from the doped layer 14 .
- the doped layer 16 may be formed in a well 92 constituted by semiconductor material of the substrate 18 that has been doped to have the opposite conductivity type from the doped layer 16 .
- the well 90 and the well 92 intersect along a vertical interface 94 to define a p-n junction, which is located vertically beneath the contact 32 .
- the doped layers 14 , 16 are separated from each and do not intersect because the vertical interface 94 and portions of the wells 90 , 92 are located in a space between the doped layer 14 and the doped layer 16 .
- the contacts 28 , 30 , 32 provide a continuous conductive path that is in a contacting relationship with the doped layer 14 and that is also in a contacting relationship with the doped layer 16 .
- the methods as described above are used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
- the end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
- references herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference.
- the terms “horizontal” and “lateral” as used herein are defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation.
- the terms “vertical” and “normal” as used herein refer to a direction perpendicular to the horizontal, as just defined. Terms such as “above” and “below” are used to indicate positioning of elements or structures relative to each other as opposed to relative elevation.
- a feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present.
- a feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent.
- a feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/694,109 US10109714B2 (en) | 2017-03-02 | 2017-09-01 | Buried contact structures for a vertical field-effect transistor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/447,639 US9831317B1 (en) | 2017-03-02 | 2017-03-02 | Buried contact structures for a vertical field-effect transistor |
US15/694,109 US10109714B2 (en) | 2017-03-02 | 2017-09-01 | Buried contact structures for a vertical field-effect transistor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/447,639 Division US9831317B1 (en) | 2017-03-02 | 2017-03-02 | Buried contact structures for a vertical field-effect transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
US20180254327A1 US20180254327A1 (en) | 2018-09-06 |
US10109714B2 true US10109714B2 (en) | 2018-10-23 |
Family
ID=60408932
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/447,639 Active US9831317B1 (en) | 2017-03-02 | 2017-03-02 | Buried contact structures for a vertical field-effect transistor |
US15/694,109 Active US10109714B2 (en) | 2017-03-02 | 2017-09-01 | Buried contact structures for a vertical field-effect transistor |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/447,639 Active US9831317B1 (en) | 2017-03-02 | 2017-03-02 | Buried contact structures for a vertical field-effect transistor |
Country Status (1)
Country | Link |
---|---|
US (2) | US9831317B1 (en) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9831317B1 (en) * | 2017-03-02 | 2017-11-28 | Globalfoundries Inc. | Buried contact structures for a vertical field-effect transistor |
US10727317B2 (en) | 2018-10-04 | 2020-07-28 | International Business Machines Corporation | Bottom contact formation for vertical transistor devices |
US10777469B2 (en) | 2018-10-11 | 2020-09-15 | International Business Machines Corporation | Self-aligned top spacers for vertical FETs with in situ solid state doping |
US10872818B2 (en) | 2018-10-26 | 2020-12-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Buried power rail and method forming same |
US10998238B2 (en) | 2018-10-31 | 2021-05-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuits with buried interconnect conductors |
US10833089B2 (en) | 2018-11-16 | 2020-11-10 | International Business Machines Corporation | Buried conductive layer supplying digital circuits |
US11171142B2 (en) | 2018-11-16 | 2021-11-09 | International Business Machines Corporation | Integrated circuit with vertical structures on nodes of a grid |
US11164879B2 (en) | 2018-11-16 | 2021-11-02 | International Business Machines Corporation | Microelectronic device with a memory element utilizing stacked vertical devices |
US10804266B2 (en) | 2018-11-16 | 2020-10-13 | International Business Machines Corporation | Microelectronic device utilizing stacked vertical devices |
US11152307B2 (en) * | 2018-12-18 | 2021-10-19 | International Business Machines Corporation | Buried local interconnect |
US11164795B2 (en) * | 2020-03-24 | 2021-11-02 | Globalfoundries U.S. Inc. | Transistors with source/drain regions having sections of epitaxial semiconductor material |
US11316029B2 (en) | 2020-04-15 | 2022-04-26 | International Business Machines Corporation | Sacrificial fin for contact self-alignment |
US11515427B2 (en) * | 2020-06-15 | 2022-11-29 | International Business Machines Corporation | Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance |
US11817497B2 (en) | 2021-08-25 | 2023-11-14 | International Business Machines Corporation | Vertical field effect transistor inverter with single fin device |
CN117038689B (en) * | 2023-08-18 | 2024-10-15 | 武汉新芯集成电路股份有限公司 | CMOS image sensor with vertical channel region and method of forming the same |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4786960A (en) * | 1984-08-07 | 1988-11-22 | Commissariat A L'energie Atomique | CMOS integrated circuit and process for producing an electric isolation zones in said integrated circuit |
US5627393A (en) | 1994-12-07 | 1997-05-06 | United Microelectronics Corporation | Vertical channel device having buried source |
US6891225B2 (en) | 2000-09-08 | 2005-05-10 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device |
US7230286B2 (en) | 2005-05-23 | 2007-06-12 | International Business Machines Corporation | Vertical FET with nanowire channels and a silicided bottom contact |
US20120238061A1 (en) | 2010-08-31 | 2012-09-20 | Micron Technology, Inc. | Methods Of Forming Transistors, And Methods Of Forming Memory Arrays |
US9356022B2 (en) * | 2013-02-25 | 2016-05-31 | Alpha And Omega Semiconductor Incorporated | Semiconductor device with termination structure for power MOSFET applications |
US9831317B1 (en) * | 2017-03-02 | 2017-11-28 | Globalfoundries Inc. | Buried contact structures for a vertical field-effect transistor |
US9876087B2 (en) * | 2013-08-07 | 2018-01-23 | Unisantis Electronics Singapore Pte. Ltd. | Surround gate transistor device and contact structure for same |
-
2017
- 2017-03-02 US US15/447,639 patent/US9831317B1/en active Active
- 2017-09-01 US US15/694,109 patent/US10109714B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4786960A (en) * | 1984-08-07 | 1988-11-22 | Commissariat A L'energie Atomique | CMOS integrated circuit and process for producing an electric isolation zones in said integrated circuit |
US5627393A (en) | 1994-12-07 | 1997-05-06 | United Microelectronics Corporation | Vertical channel device having buried source |
US6891225B2 (en) | 2000-09-08 | 2005-05-10 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device |
US7230286B2 (en) | 2005-05-23 | 2007-06-12 | International Business Machines Corporation | Vertical FET with nanowire channels and a silicided bottom contact |
US20120238061A1 (en) | 2010-08-31 | 2012-09-20 | Micron Technology, Inc. | Methods Of Forming Transistors, And Methods Of Forming Memory Arrays |
US9356022B2 (en) * | 2013-02-25 | 2016-05-31 | Alpha And Omega Semiconductor Incorporated | Semiconductor device with termination structure for power MOSFET applications |
US9876087B2 (en) * | 2013-08-07 | 2018-01-23 | Unisantis Electronics Singapore Pte. Ltd. | Surround gate transistor device and contact structure for same |
US9831317B1 (en) * | 2017-03-02 | 2017-11-28 | Globalfoundries Inc. | Buried contact structures for a vertical field-effect transistor |
Also Published As
Publication number | Publication date |
---|---|
US20180254327A1 (en) | 2018-09-06 |
US9831317B1 (en) | 2017-11-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10109714B2 (en) | Buried contact structures for a vertical field-effect transistor | |
US11935835B2 (en) | Methods of manufacturing semiconductor devices | |
US9847391B1 (en) | Stacked nanosheet field-effect transistor with diode isolation | |
US11721581B2 (en) | Semiconductor devices including contact plugs | |
US10283408B2 (en) | Middle of the line (MOL) contacts with two-dimensional self-alignment | |
US11955475B2 (en) | Resistor with doped regions and semiconductor devices having the same | |
US10236363B2 (en) | Vertical field-effect transistors with controlled dimensions | |
US7902026B2 (en) | Method of fabricating semiconductor device having vertical channel transistor | |
US11776857B2 (en) | Semiconductor device | |
US10163900B2 (en) | Integration of vertical field-effect transistors and saddle fin-type field effect transistors | |
KR102496973B1 (en) | Semiconductor devices and methods of manufacturing the same | |
KR102723823B1 (en) | Semiconductor devices | |
US9911738B1 (en) | Vertical-transport field-effect transistors with a damascene gate strap | |
US10050125B1 (en) | Vertical-transport field-effect transistors with an etched-through source/drain cavity | |
KR20210072477A (en) | Resistor with doped regions | |
US10916470B2 (en) | Modified dielectric fill between the contacts of field-effect transistors | |
US10276391B1 (en) | Self-aligned gate caps with an inverted profile | |
US20220165887A1 (en) | Semiconductor device | |
US10867912B2 (en) | Dummy fill scheme for use with passive devices | |
KR20230062467A (en) | Semiconductor structure and manufacturing method thereof | |
KR20200140976A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZANG, HUI;LEE, TEK PO RINUS;SIGNING DATES FROM 20170228 TO 20170301;REEL/FRAME:043472/0780 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001 Effective date: 20201022 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |