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TWM628743U - 溝渠式功率半導體裝置 - Google Patents

溝渠式功率半導體裝置 Download PDF

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TWM628743U
TWM628743U TW111201932U TW111201932U TWM628743U TW M628743 U TWM628743 U TW M628743U TW 111201932 U TW111201932 U TW 111201932U TW 111201932 U TW111201932 U TW 111201932U TW M628743 U TWM628743 U TW M628743U
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trench
epitaxial layer
active element
power semiconductor
semiconductor device
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TW111201932U
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劉莒光
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杰力科技股份有限公司
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Priority to TW111201932U priority Critical patent/TWM628743U/zh
Priority to US17/704,022 priority patent/US20230268405A1/en
Priority to CN202220686841.2U priority patent/CN217158188U/zh
Publication of TWM628743U publication Critical patent/TWM628743U/zh

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Abstract

一種溝渠式功率半導體裝置，包括基板、磊晶層、汲極電極、第一主動元件、第二主動元件以及數個隔離溝渠結構。磊晶層設置於基板的一面，汲極電極設置於基板的另一面。第一主動元件設置於磊晶層的第一部分中，並具有第一源極電極與第一閘極電極。第二主動元件設置於磊晶層的第二部分中，並具有第二源極電極與第二閘極電極。隔離溝渠結構設置於磊晶層的所述第一部分與所述第二部分之間，以電性隔離第一主動元件與第二主動元件。

Description

溝渠式功率半導體裝置
本新型創作是有關於一種功率半導體技術，且特別是有關於一種溝渠式功率半導體裝置。
功率半導體元件一般用於開關模式電源或其他高速電源開關的裝置中。為了更高的元件密度，功率半導體元件多採取垂直結構的設計，其利用晶片背面作為汲極，而於晶片正面製作源極以及閘極。
傳統的功率半導體元件會根據應用電壓範圍的不同，製作在不同的晶片上，再利用晶圓級封裝進行電路連接，以避免漏電或產生其他電性問題。
然而，分開製作在不同晶片的方式既浪費時間也會增加製造成本。目前雖然也有利用厚氧化層等結構來進行元件電性隔離，但是仍需要額外的步驟來形成厚氧化層。
本新型創作提供一種溝渠式功率半導體裝置，能改善同一基板上的兩個主動元件之間的電性隔絕能力，以且不需要額外長時間的熱氧化處理或額外的光罩製程。
本新型創作的溝渠式功率半導體裝置，包括基板、磊晶層、汲極電極、第一主動元件、第二主動元件以及數個隔離溝渠結構。基板具有相對的第一表面與第二表面。磊晶層設置於基板的所述第一表面。汲極電極設置於基板的所述第二表面。第一主動元件設置於磊晶層的第一部分中，具有第一源極電極與第一閘極電極。第二主動元件設置於磊晶層的第二部分中，具有第二源極電極與第二閘極電極。數個隔離溝渠結構設置於磊晶層的所述第一部分與所述第二部分之間，以電性隔離第一主動元件與第二主動元件。
在本新型創作的一實施例中，上述隔離溝渠結構的數目為3以上。
在本新型創作的一實施例中，上述第一主動元件與上述第二主動元件之間的跨壓值與隔離溝渠結構的數目正相關。
在本新型創作的一實施例中，每個所述隔離溝渠結構包括浮動電位的多晶矽結構與絕緣層。所述多晶矽結構是從磊晶層的表面延伸至磊晶層內，而絕緣層介於多晶矽結構與磊晶層之間。
在本新型創作的一實施例中，上述第一主動元件包括具有第一導電型的所述磊晶層、具有第二導電型的第一井區、數個第一溝渠式閘極結構、上述第一閘極電極、具有第一導電型的第一源極區以及上述第一源極電極。第一井區位於所述磊晶層內。第一溝渠式閘極結構設置於所述磊晶層內並從磊晶層的表面延伸至第一井區下方。第一閘極電極設置於磊晶層上方並電性連接所述第一溝渠式閘極結構。第一源極區位於所述磊晶層的表面，第一源極電極則設置於磊晶層上方並電性連接所述第一源極區。
在本新型創作的一實施例中，上述溝渠式功率半導體裝置還可包括具有第二導電型的數個第一重摻雜區，形成在第一源極電極下方的第一井區內，且第一源極電極電性連接第一重摻雜區。
在本新型創作的一實施例中，上述第一閘極電極包圍上述第一源極電極。
在本新型創作的一實施例中，上述第二主動元件包括具有第一導電型的所述磊晶層、具有第二導電型的第二井區、數個第二溝渠式閘極結構、上述第二閘極電極、具有第一導電型的第二源極區以及上述第二源極電極。第二井區位於所述磊晶層內。第二溝渠式閘極結構設置於所述磊晶層內並從磊晶層的表面延伸至第二井區下方。第二閘極電極設置於所述磊晶層上方並電性連接所述第二溝渠式閘極結構。第二源極區位於所述磊晶層的表面，而第二源極電極設置於磊晶層上方並電性連接所述第二源極區。
在本新型創作的一實施例中，上述溝渠式功率半導體裝置還可包括具有第二導電型的數個第二重摻雜區，形成在第二源極電極下方的第二井區內，且第二源極電極電性連接第二重摻雜區。
在本新型創作的一實施例中，上述第二閘極電極包圍上述第二源極電極。
在本新型創作的一實施例中，上述基板為具有第一導電型的半導體基板。
在本新型創作的一實施例中，上述第一導電型為N型，上述第二導電型為P型。
在本新型創作的一實施例中，上述第一導電型為P型，上述第二導電型為N型。
在本新型創作的一實施例中，上述第一主動元件與上述第二主動元件具有相同的面積。
在本新型創作的一實施例中，上述第一主動元件的面積小於上述第二主動元件的面積。
在本新型創作的一實施例中，上述第一主動元件與上述第二主動元件為不對稱的結構。
在本新型創作的一實施例中，上述第一主動元件與上述第二主動元件為鏡像對稱的結構。
基於上述，本新型創作利用設置於磊晶層的第一與第二部分之間的數個隔離溝渠結構來電性隔離第一主動元件與第二主動元件，且隔離溝渠結構與主動元件的溝渠式閘極結構基本一樣，所以不需要額外長時間的熱氧化處理或額外的光罩製程，即可實現在同一基板上設置兩個主動元件的目的。
為讓本新型創作的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下內容提供許多不同的實施方式或實施例，用於實施本新型創作的不同特徵。而且，這些實施例僅為示範例，並不用來限制本新型創作的範圍與應用。再者，為了清楚起見，各區域或結構元件的相對尺寸（如長度、厚度、間距等）及相對位置可能縮小或放大。另外，在各圖式中使用相似或相同的元件符號表示相似或相同元件或特徵。
圖1是依照本新型創作的一實施例的一種溝渠式功率半導體裝置的剖面示意圖。
請參照圖1，本實施例的溝渠式功率半導體裝置包括基板100、磊晶層102、汲極電極104、第一主動元件106、第二主動元件108以及數個隔離溝渠結構110。基板100具有相對的第一表面100a與第二表面100b。磊晶層102設置於基板100的第一表面100a。汲極電極104設置於基板100的第二表面100b。第一主動元件106設置於磊晶層102的第一部分I中，具有第一源極電極S1與第一閘極電極G1。第二主動元件108設置於磊晶層102的第二部分II中，具有第二源極電極S2與第二閘極電極G2。數個隔離溝渠結構110設置於磊晶層102的第一部分I與第二部分II之間，以電性隔離第一主動元件106與第二主動元件108。
在本實施例中，第一主動元件106以及第二主動元件108可共用汲極（汲極電極104），亦即圖1是一個單晶粒（die）且切割道（cutting line）CL就在第一主動元件106與第二主動元件108的外側，因此本實施例的溝渠式功率半導體裝置的電路圖例如圖2所示。
在圖2中，溝渠式功率半導體裝置可以有以下四種操作模式： 第一種模式是輸入電壓Vin是第一主動元件106的第一源極S1的電壓（Vin=V(S1)）、輸出電壓Vout是第二主動元件108的第二源極S2的電壓（Vout=V(S2)）、第一主動元件106的第一閘極G1的電壓V(G1)和第二主動元件108的第二閘極G2的電壓V(G2)都是低電壓。第一源極S1與第二源極S2的電位可以互調。 第二種模式是Vin=V(S1)、Vout=V(S2)、V(G1)是高電壓、V(G2)是低電壓。第一源極S1與第二源極S2的電位可以互調。 第三種模式是Vin=V(S1)、Vout=V(S2)、V(G1)是低電壓、V(G2)是高電壓。第一源極S1與第二源極S2的電位可以互調。 第四種模式是Vin=V(S1)、Vout=V(S2)、V(G1)和V(G2)都是高電壓。第一源極S1與第二源極S2的電位可以互調。
請再度參照圖1，隔離溝渠結構110的數目為4，但本新型創作並不限於此。第一主動元件106與第二主動元件108之間的跨壓值（cross voltage）與隔離溝渠結構的數目正相關。舉例來說，第一主動元件106與第二主動元件108之間的跨壓值是30V，隔離溝渠結構的數目是3的話；若是第一主動元件106與第二主動元件108之間的跨壓值高於30V，則隔離溝渠結構的數目可變更為4，依此類推。
在本實施例中，每個隔離溝渠結構110包括浮動電位的多晶矽結構112與絕緣層114。所述多晶矽結構112是從磊晶層102的表面102a延伸至磊晶層102內，而絕緣層114介於多晶矽結構112與磊晶層102之間。
在本實施例中，第一主動元件106包括具有第一導電型的磊晶層102、具有第二導電型的第一井區W1、數個第一溝渠式閘極結構116、第一閘極電極G1、具有第一導電型的第一源極區118以及第一源極電極S1。在本實施例中，基板100為具有第一導電型的半導體基板，且第一導電型為N型，第二導電型為P型。然而，本新型創作並不限於此；在另一實施例中，第一導電型為P型，第二導電型為N型。第一井區W1位於磊晶層102內。第一溝渠式閘極結構116設置於磊晶層102內並從磊晶層102的表面102a延伸至第一井區W1下方。第一閘極電極G1設置於磊晶層102上方並電性連接第一溝渠式閘極結構116，且第一閘極電極G1可通過設置在介電層ILD的導電插塞P1電性連接第一溝渠式閘極結構116。第一源極區118位於磊晶層102的表面102a，第一源極電極S1則設置於磊晶層102上方並電性連接第一源極區118，且第一源極電極S1可通過設置在介電層ILD的另一導電插塞P1電性連接第一源極區118。
在本實施例中，溝渠式功率半導體裝置還可包括具有第二導電型的數個第一重摻雜區120，形成在第一源極電極S1下方的第一井區W1內，以增加與第一井區W1的歐姆接觸。第一源極電極S1電性連接第一重摻雜區120，且第一源極電極S1可通過設置在介電層ILD的導電插塞P1電性連接第一重摻雜區120。
在本實施例中，第二主動元件108包括具有第一導電型的磊晶層102、具有第二導電型的第二井區W2、數個第二溝渠式閘極結構122、第二閘極電極G2、具有第一導電型的第二源極區124以及第二源極電極S2。第二井區W2位於磊晶層102內。第二溝渠式閘極結構122設置於磊晶層102內並從磊晶層102的表面102a延伸至第二井區W2下方。第二閘極電極G2設置於磊晶層102上方並電性連接第二溝渠式閘極結構122，且第二閘極電極G2可通過設置在介電層ILD的導電插塞P2電性連接第二溝渠式閘極結構122。第二源極區124位於磊晶層102的表面102a，而第二源極電極S2設置於磊晶層102上方並電性連接第二源極區124，且第二源極電極S2可通過設置在介電層ILD的另一導電插塞P2電性連接第二源極區124。
在本實施例中，溝渠式功率半導體裝置還可包括具有第二導電型的數個第二重摻雜區126，形成在第二源極電極S2下方的第二井區W2內，以增加與第二井區W2的歐姆接觸。第二源極電極S2電性連接第二重摻雜區126，且第二源極電極S2可通過設置在介電層ILD的導電插塞P2電性連接第二重摻雜區126。
除了圖1所示的第一主動元件106以及第二主動元件108，本新型創作的主動元件也可採用結構上有不同設計的元件，例如省略圖1中的部分構件的主動元件，或者在圖1中增加結構層或是摻雜區的主動元件，並不侷限於本實施例中的內容。
在一實施例中，隔離溝渠結構110的深度可與第一溝渠式閘極結構116的深度一樣。在另一實施例中，隔離溝渠結構110的深度可與第二溝渠式閘極結構122的深度一樣。在又一實施例中，第一溝渠式閘極結構116的深度可與第二溝渠式閘極結構122的深度一樣。當第一溝渠式閘極結構116、第二溝渠式閘極結構122以及隔離溝渠結構110的深度都一樣，則三者可利用同一製程形成。
在圖1中，第一井區W1與第二井區W2相鄰，且隔離溝渠結構110分別位在部分第一井區W1與部分第二井區W2內，且一部分隔離溝渠結構110從磊晶層102的表面102a延伸至第一井區W1下方，另一部分隔離溝渠結構110從磊晶層102的表面102a延伸至第二井區W2下方。然而，本新型創作並不限於此；在另一實施例中，第一井區W1與第二井區W2並不相鄰，且隔離溝渠結構110並未設置在第一井區W1與第二井區W2中，而是設置在第一井區W1與第二井區W2之間的磊晶層102內。
圖1顯示的是溝渠式功率半導體裝置的剖面，而其上視圖可以有以下幾種範例。
圖3A是上述實施例的一例的上視示意圖。在圖3A中，第一主動元件106與第二主動元件108具有相同的面積，本新型創作的隔離溝渠結構(未示出)則是圍繞在第一主動元件106與第二主動元件108之間。在圖3A中，第一主動元件106與第二主動元件108為鏡像對稱的結構，第一閘極電極G1包圍第一源極電極S1，且第二閘極電極G2包圍第二源極電極S2。
圖3B是上述實施例的另一例的上視示意圖。在圖3B中，第一主動元件106與第二主動元件108具有相同的面積，本新型創作的隔離溝渠結構(未示出)則是圍繞在第一主動元件106與第二主動元件108之間。在圖3B中，第一主動元件106與第二主動元件108為鏡像對稱的結構，第一閘極電極G1包圍第一源極電極S1，且第二閘極電極G2包圍第二源極電極S2。
圖3C是上述實施例的再一例的上視示意圖。在圖3C中，第一主動元件106的面積小於第二主動元件108的面積，本新型創作的隔離溝渠結構(未示出)則是圍繞在第一主動元件106與第二主動元件108之間。在圖3C中，第一主動元件106與第二主動元件108為不對稱的結構，第一閘極電極G1包圍第一源極電極S1，且第二閘極電極G2包圍第二源極電極S2。
綜上所述，本新型創作的溝渠式功率半導體裝置是在同一基板上設置兩個主動元件，並利用設置在兩個主動元件之間的數個隔離溝渠結構來進行電性隔離，且隔離溝渠結構與主動元件的溝渠式閘極結構基本一樣，所以不需要額外長時間的熱氧化處理或額外的光罩製程。而且，本新型創作還可以根據兩個主動元件之間的跨壓，預先設定隔離溝渠結構的數目。
雖然本新型創作已以實施例揭露如上，然其並非用以限定本新型創作，任何所屬技術領域中具有通常知識者，在不脫離本新型創作的精神和範圍內，當可作些許的更動與潤飾，故本新型創作的保護範圍當視後附的申請專利範圍所界定者為準。
100: 100a:第一表面 100b:第二表面 102:磊晶層 102a:表面 104:汲極電極 106:第一主動元件 108:第二主動元件 110:隔離溝渠結構 112:多晶矽結構 114:絕緣層 116:第一溝渠式閘極結構 118:第一源極區 120:第一重摻雜區 122:第二溝渠式閘極結構 124:第二源極區 126:第二重摻雜區 CL:切割道 G1:第一閘極電極 G2:第二閘極電極 ILD:介電層 P1、P2:導電插塞 S1:第一源極電極 S2:第二源極電極 W1:第一井區 W2:第二井區 I:第一部分 II:第二部分
圖1是依照本新型創作的一實施例的一種溝渠式功率半導體裝置的剖面示意圖。 圖2是上述實施例的溝渠式功率半導體裝置的電路圖。 圖3A是上述實施例的一例的上視示意圖。 圖3B是上述實施例的另一例的上視示意圖。 圖3C是上述實施例的再一例的上視示意圖。
100:基板
100a:第一表面
100b:第二表面
102:磊晶層
102a:表面
104:汲極電極
106:第一主動元件
108:第二主動元件
110:隔離溝渠結構
112:多晶矽結構
114:絕緣層
116:第一溝渠式閘極結構
118:第一源極區
120:第一重摻雜區
122:第二溝渠式閘極結構
124:第二源極區
126:第二重摻雜區
CL:切割道
G1:第一閘極電極
G2:第二閘極電極
ILD:介電層
P1、P2:導電插塞
S1:第一源極電極
S2:第二源極電極
W1:第一井區
W2:第二井區
I:第一部分
II:第二部分

Claims (17)

  1. 一種溝渠式功率半導體裝置，包括： 基板，具有相對的第一表面與第二表面； 磊晶層，設置於所述基板的所述第一表面； 汲極電極，設置於所述基板的所述第二表面； 第一主動元件，設置於所述磊晶層的第一部分中，具有第一源極電極與第一閘極電極； 第二主動元件，設置於所述磊晶層的第二部分中，具有第二源極電極與第二閘極電極；以及 數個隔離溝渠結構，設置於所述磊晶層的所述第一部分與所述第二部分之間，以電性隔離所述第一主動元件與所述第二主動元件。
  2. 如請求項1所述的溝渠式功率半導體裝置，其中所述數個隔離溝渠結構的數目為3以上。
  3. 如請求項1所述的溝渠式功率半導體裝置，其中所述第一主動元件與所述第二主動元件之間的跨壓值與所述數個隔離溝渠結構的數目正相關。
  4. 如請求項1所述的溝渠式功率半導體裝置，其中每個所述隔離溝渠結構包括： 浮動電位的多晶矽結構，從所述磊晶層的表面延伸至所述磊晶層內；以及 絕緣層，介於所述多晶矽結構與所述磊晶層之間。
  5. 如請求項1所述的溝渠式功率半導體裝置，其中所述第一主動元件包括： 具有第一導電型的所述磊晶層； 具有第二導電型的第一井區，位於所述磊晶層內； 數個第一溝渠式閘極結構，設置於所述磊晶層內並從所述磊晶層的表面延伸至所述第一井區下方； 所述第一閘極電極，設置於所述磊晶層上方並電性連接所述第一溝渠式閘極結構； 具有所述第一導電型的第一源極區，位於所述磊晶層的所述表面；以及 所述第一源極電極，設置於所述磊晶層上方並電性連接所述第一源極區。
  6. 如請求項5所述的溝渠式功率半導體裝置，更包括具有所述第二導電型的數個第一重摻雜區，形成在所述第一源極電極下方的所述第一井區內，且所述第一源極電極電性連接所述數個第一重摻雜區。
  7. 如請求項5所述的溝渠式功率半導體裝置，其中所述第一閘極電極包圍所述第一源極電極。
  8. 如請求項1所述的溝渠式功率半導體裝置，其中所述第二主動元件包括： 具有第一導電型的所述磊晶層； 具有第二導電型的第二井區，位於所述磊晶層內； 數個第二溝渠式閘極結構，設置於所述磊晶層內並從所述磊晶層的表面延伸至所述第二井區下方； 所述第二閘極電極，設置於所述磊晶層上方並電性連接所述第二溝渠式閘極結構； 具有所述第一導電型的第二源極區，位於所述磊晶層的所述表面；以及 所述第二源極電極，設置於所述磊晶層上方並電性連接所述第二源極區。
  9. 如請求項8所述的溝渠式功率半導體裝置，更包括具有所述第二導電型的數個第二重摻雜區，形成在所述第二源極電極下方的所述第二井區內，且所述第二源極電極電性連接所述數個第二重摻雜區。
  10. 如請求項8所述的溝渠式功率半導體裝置，其中所述第二閘極電極包圍所述第二源極電極。
  11. 如請求項5~10中任一項所述的溝渠式功率半導體裝置，其中所述基板為具有所述第一導電型的半導體基板。
  12. 如請求項11所述的溝渠式功率半導體裝置，其中所述第一導電型為N型，所述第二導電型為P型。
  13. 如請求項11所述的溝渠式功率半導體裝置，其中所述第一導電型為P型，所述第二導電型為N型。
  14. 如請求項1所述的溝渠式功率半導體裝置，其中所述第一主動元件與所述第二主動元件具有相同的面積。
  15. 如請求項1所述的溝渠式功率半導體裝置，其中所述第一主動元件的面積小於所述第二主動元件的面積。
  16. 如請求項1所述的溝渠式功率半導體裝置，其中所述第一主動元件與所述第二主動元件為不對稱的結構。
  17. 如請求項1所述的溝渠式功率半導體裝置，其中所述第一主動元件與所述第二主動元件為鏡像對稱的結構。
TW111201932U 2022-02-24 2022-02-24 溝渠式功率半導體裝置 TWM628743U (zh)

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CN202220686841.2U CN217158188U (zh) 2022-02-24 2022-03-28 沟槽式功率半导体装置

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US7781826B2 (en) * 2006-11-16 2010-08-24 Alpha & Omega Semiconductor, Ltd. Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
US8569780B2 (en) * 2011-09-27 2013-10-29 Force Mos Technology Co., Ltd. Semiconductor power device with embedded diodes and resistors using reduced mask processes

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