TWM606602U - High-power integrated circuit chip packaging device - Google Patents

Abstract

This creation provides a high-power integrated circuit chip packaging device. The high-power integrated circuit chip packaging device includes a high-power integrated circuit chip, a lead frame, and a package body. The lead frame includes a slide table and at least ten pins; the slide table has a recessed and sunken flat surface relative to the plane where the at least ten pins are located, and is used to carry high-power integrated circuit chips and sink the slide table At least a part of the portion is exposed to the outside of the package body; at least four adjacent pins among the at least ten pins are connected together and widened to form a widened pin, and the widened pin is relative to the carrier Connect to form a heat dissipation channel between the high-power integrated circuit chip and the external environment. Compared with similar structures, the integrated circuit chip packaging device according to this creative embodiment has better heat dissipation performance and lower manufacturing cost, so it can be used for the design, packaging, large-scale manufacturing and application of high-power integrated circuit chips .

Description

High-power integrated circuit chip packaging device

This creation relates to the field of semiconductors, and more specifically to a high-power integrated circuit chip packaging device.

The manufacturing process of the integrated circuit chip mainly includes the following stages: the design phase of the integrated circuit chip, the production phase of the integrated circuit chip, the packaging phase of the integrated circuit chip, and the testing phase of the integrated circuit chip. After the integrated circuit chip is manufactured, there are usually multiple bonding pads on the integrated circuit chip. In the packaging stage of the integrated circuit chip, the bonding pads on the integrated circuit chip and the corresponding lead frame are usually electrically connected to each other. The integrated circuit chip is usually connected to the lead frame by wire bonding or ball bonding, so that the bonding pads of the integrated circuit chip are electrically connected to the contacts of the lead frame, thereby realizing the packaging structure of the integrated circuit chip Internal electrical connections.

With the increasing use of power integrated circuit chips, how to achieve high-power integrated circuit chips with high heat dissipation performance has become a common concern in the semiconductor industry.

This creation provides a novel high-power integrated circuit chip packaging device and a lead frame used in the packaging device.

According to an embodiment of the present creation, an integrated circuit chip packaging device is provided, which includes a high-power integrated circuit chip, a lead frame, and a package. Wherein, the lead frame includes a slide table and at least ten pins; the slide table has a concave and sunken plane relative to the plane where the at least ten pins are located, and is used to carry high-power integrated circuit chips, and At least a part of the sinking portion is exposed to the outside of the package body; and at least four adjacent pins among the at least ten pins are connected together and widened to form a widened pin, and the widened pin Connected with the slide table to form a heat dissipation channel between the high-power integrated circuit chip and the external environment.

In one embodiment, the spacing between some or all adjacent pins among the at least ten pins is greater than 1.0 mm.

In one embodiment, the area of the sunken portion of the slide table exposed on the surface of the package accounts for more than 30% of the surface area of the same side of the package.

In one embodiment, the high-power integrated circuit chip packaging device is a SMD structure or a dual in-line structure.

In one embodiment, the high-power integrated circuit chip is a switching power supply chip.

According to the embodiment of the present creation, a lead frame is also provided, which includes a stage and at least ten pins. Wherein, the slide table has a concave and sunken plane with respect to the plane where the at least ten pins are located, and is used to carry the high-power integrated circuit chip; and at least four adjacent pins among the at least ten pins are connected to Together, they are widened to form widened pins, and the widened pins are connected with the stage to form a heat dissipation channel between the high-power integrated circuit chip and the external environment.

Compared with similar structures, the integrated circuit chip packaging device according to this creative embodiment has better heat dissipation performance and lower manufacturing cost, so it can be used for the design, packaging, large-scale manufacturing and application of high-power integrated circuit chips .

1(VDD), 2(PRT), 3(FB), 4(GND), 5(CS), 6(DRAIN), 7(DRAIN), 8(DRAIN), 9(DRAIN), 10(HV): Pin

2A: Lead frame

2A-1, 4-3: Slide table

4-1: High-power integrated circuit chip

4-2: Control IC chip

a1: X-direction side length of exposed stage

b1: Length of side in Y direction of exposed stage

L1: Wide spacing between high voltage (or high and low voltage) pins

This creation can be better understood from the following description of the specific implementation of this creation in combination with the diagrams, in which:

Figure 1A shows a top view of a high-power integrated circuit chip packaging device according to an embodiment of the present invention;

FIG. 1B shows a cross-sectional view of the high-power integrated circuit chip packaging device shown in FIG. 1A along A-A;

2A shows a top view of the lead frame in the high-power integrated circuit chip packaging device according to the present creative embodiment;

Fig. 2B shows a cross-sectional view of the lead frame shown in Fig. 2A along B-B;

3A shows a top view of a high-power integrated circuit chip packaging device according to another embodiment of the present invention;

3B shows a cross-sectional view of the high-power integrated circuit chip packaging device shown in FIG. 3A along C-C;

FIG. 4 shows a top view of the internal packaging structure of the high-power integrated circuit chip packaging device according to this creative embodiment;

Fig. 5 shows a schematic diagram of pins of an exemplary switching power supply chip packaging device according to the present creative embodiment.

FIG. 6 shows a schematic circuit connection diagram of a flyback power converter applying the exemplary switching power supply chip packaging device shown in FIG. 5.

The features and exemplary embodiments of various aspects of the present creation will be described in detail below. In the following detailed description, many specific details are proposed in order to provide a comprehensive understanding of this creation. However, it is obvious to those skilled in the art that this creation can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present creation by showing an example of the present creation. This creation is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement and improvement of elements, components and algorithms without departing from the spirit of this creation. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessary obscurity of the creation.

With the increasing use of power integrated circuit chips, how to achieve high-power integrated circuit chips with high heat dissipation performance has become a common concern in the semiconductor industry. In view of this problem, this creation provides a novel high-power integrated circuit chip packaging device.

The following describes in detail the high-power integrated circuit chip packaging device according to this creative embodiment and the lead frame applied to the packaging device in conjunction with the drawings.

Fig. 1A shows a top view of a high-power integrated circuit chip packaging device according to an embodiment of the present invention. Fig. 1B shows a cross-sectional view along A-A of the high-power integrated circuit chip packaging device shown in Fig. 1A. The high-power integrated circuit chip packaging device can be applied to the lead frame shown in FIGS. 2A and 2B. The high-power integrated circuit chip packaging device is, for example, a SMD structure, which may include a high-power integrated circuit chip, a lead frame, and a package body, wherein the lead frame includes pins 1, pins 2, ..., pins 10. A total of 10 pins, and a carrier for carrying high-power integrated circuit chips Film table. As shown in Fig. 1A, pin 6, pin 7, pin 8, and pin 9 are connected together and widened to form a whole widened pin.

As can be seen in conjunction with FIGS. 1A and 1B, the slide table has a flat surface that is concave and sunk relative to the plane where the pins 1 to 10 are located. The recessed and sinking plane is inside the package and is used to carry the high-power integrated circuit chip, and at least a part of the sinking portion of the carrier table (for example, the concave and sinking plane of the carrier The opposite surface) may be exposed to the outside of the package body of the high-power integrated circuit chip packaging device to form a heat dissipation channel between the high-power integrated circuit chip and the external environment. In addition, the widened pin formed by connecting pin 6, pin 7, pin 8, and pin 9 can be connected to the stage to further expand the heat dissipation channel between the high-power integrated circuit chip and the external environment. The surface mount structure can not only be applied to the traditional reflow soldering process of Printed Circuit Board Assembly (PCBA) factories, but also to the wave soldering process that is traditionally used for plug-in structure. Similar assembly processing factories use assembly patches to greatly reduce assembly costs.

Note that although FIGS. 1A and 1B do not show the integrated circuit chip itself included in the integrated circuit chip packaging device and the package for packaging the integrated circuit chip and the lead frame, those skilled in the art should understand that the integrated circuit chip The circuit chip packaging device necessarily includes at least one integrated circuit chip and a package body.

The structure of the lead frame used in the high-power integrated circuit chip packaging device according to the present creative embodiment will be described in more detail below with reference to FIGS. 2A and 2B. As shown in Fig. 2A, the lead frame 2A includes pins 1, pins 2,..., and 10 pins, a total of 10 pins, and a stage 2A-1; a stage 2A-1 and pins 6, Pin 7, pin 8, and pin 9 are connected together; pin 6, pin 7, pin 8, and pin 9 are also connected together and widened to form a whole widened pin.

Fig. 2B shows a cross-sectional view of the lead frame shown in Fig. 2A along B-B. It can be seen from Figures 2A and 2B that the stage 2A-1 has a concave and sinking plane with respect to the plane where the pins 1 to 10 are located, and is connected to pins 6, 7, 8, and 8. 9 is connected together, but not connected to other pins.

When the lead frame 2A is applied to the high-power integrated circuit chip packaging device, the carrier 2A-1 is connected to the pins 6, 7, 8, and 9, so it is carried on the chip. The heat dissipation channel between the high-power integrated circuit chip on the platform 2A-1 and the external environment includes four pins. Furthermore, since the pins 6, 7, 8, and 9 themselves are connected together and are widened, the high-power integrated circuit chip carried on the stage 2A-1 is further enlarged. The cooling channel of the environment.

In addition, when the lead frame 2A is applied to a high-power integrated circuit chip packaging device, it can be further enlarged by exposing at least a part of the sinking portion of the stage 2A-1 to the outside of the integrated circuit chip packaging device. The heat dissipation channel between the high-power integrated circuit chip and the external environment carried on the stage 2A-1. In order to expose the sinking portion of the stage 2A-1 to the outside of the integrated circuit chip packaging device, the thickness of the integrated circuit chip packaging device may be reduced.

In some embodiments, the spacing between some or all adjacent pins of the lead frame 2A can be adjusted to a larger spacing. For example, the spacing (ie L1 shown in Figure 1A) can be designed to be greater than 1.0mm (for example, in the range of 1.0-3.6mm) to prevent certain application conditions, especially adjacent pins in humid environments (especially The ignition problem between the high-voltage and low-voltage pins, thereby ensuring the reliability and safety of the integrated circuit chip packaging device using the lead frame 2A. In addition, in some embodiments, the size of the stage 2A-1 can be made larger, for example, its area occupies 10%-90% of the total area of the package body of the integrated circuit chip packaging device, thereby carrying more Large-size and high-power integrated circuit chips can also have a larger heat dissipation area exposed to the outside of the integrated circuit chip packaging device. For example, the area of the sunken portion of the stage 2A-1 exposed on the surface of the package (ie the product of a1*b1 shown in FIG. 1A) can account for more than 30% of the surface area of the same side of the package.

Fig. 3A shows a top view of an integrated circuit chip packaging device according to another embodiment of the present invention. Fig. 3B shows a cross-sectional view along C-C of the integrated circuit chip packaging device shown in Fig. 3A. The integrated circuit chip packaging device shown in Figures 3A and 3B is a dual-in-line structure. This structure can be easily applied to the plug-in assembly of a single-sided PCBA design. The design and process requirements and restrictions on the assembly factory are small, and the production And the manufacturing process is simple. Other aspects are similar to the integrated circuit chip packaging device described in conjunction with FIGS. 1A and 1B, and will not be repeated here.

Fig. 4 shows a top view of the internal packaging structure of the high-power integrated circuit chip packaging device according to this creative embodiment. As shown in Figure 4, the stage 4-3 is implemented to have a larger size (which can be enlarged according to actual needs) to carry a larger high-power integrated circuit chip 4-1. The high-power integrated circuit chip The smaller control IC chip 4-2 can be pasted on the 4-1; the stage 4-3 is connected with pins 6, 7, 8, and 9 to make the high-power product The heat dissipation channel between the bulk circuit chip 4-1 and the external environment includes four pins; pin 6, pin 7, pin 8, and pin 9 are connected together, which further expands the high-power integrated circuit chip 4-1 Heat dissipation channel with the external environment.

As described above, the high-power integrated circuit chip packaging device according to the present creative embodiment is suitable for packaging power-type integrated circuit chips with higher power. For example, the high-power integrated circuit chip may be a switching power supply chip. Fig. 5 shows a schematic diagram of pins of an exemplary switching power supply chip packaging device according to the present creative embodiment.

As shown in Figure 5, the switching power supply chip packaging device has 10 pins, of which pin 1, pin 2, pin 3, pin 4, pin 5, and pin 10 are six independent pins, and Pin 6, pin 7, pin 8, and pin 9 are connected together to form a whole widened pin.

FIG. 6 shows a schematic circuit connection diagram of a flyback power converter applying the exemplary switching power supply chip packaging device shown in FIG. 5. As shown in Figure 5 and Figure 6, Pin 1 is set as the VDD pin, which is the primary power supply pin; Pin 2 is set as the PRT pin, which is the over-temperature sensing and protection pin; Pin 3 is set It is the FB pin, which is the loop compensation pin; pin 4 is set as the GND pin, which is the chip ground pin; pin 5 is set as the CS pin, which is the power and power MOS field effect transistor current sensing lead Pin; Pin 10 is set as the HV pin, which is the high-voltage start pin; and the overall widened pin formed by pin 6, pin 7, pin 8 and pin 9 is set as DRAIN pin, namely Connect the pin of the power power MOS field effect transistor drain in the switching power supply chip.

The above description uses the switching power supply chip as an example to describe the pin setting of the integrated circuit chip packaging device according to this creative embodiment. However, it should be understood that the integrated circuit chip packaging device according to this creative embodiment can be used for packaging various high-power integrated circuit chips.

In addition, although the ten-pin package structure is taken as an example to describe the pin arrangement of the integrated circuit chip packaging device according to this creative embodiment, it should be understood that the integrated circuit chip packaging device according to this creative embodiment It is not limited to only including ten pins, but more pins may be included.

Furthermore, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the above description, many specific details are provided to give a sufficient understanding of the embodiments of the present creation. However, those skilled in the art will realize that the technical solution of this creation can be practiced without one or more of the specific details, or other methods, components, materials, etc. can be used. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the main technical ideas of this creation.

Those skilled in the art should understand that the above-mentioned embodiments are all exemplary rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Those skilled in the art should be able to understand and implement other modified embodiments of the disclosed embodiments on the basis of studying the drawings, specifications, and the scope of patent applications. The presence of certain technical features in different subordinate claims does not mean that these technical features cannot be combined to achieve beneficial effects.

1(VDD), 2(PRT), 3(FB), 4(GND), 5(CS), 6(DRAIN), 7(DRAIN), 8(DRAIN), 9(DRAIN), 10(HV): Pin

a1: X-direction side length of exposed stage

b1: Length of side in Y direction of exposed stage

L1: Wide spacing between high voltage (or high and low voltage) pins

Claims (9)

A high-power integrated circuit chip packaging device includes a high-power integrated circuit chip, a lead frame, and a package body, wherein: The lead frame includes a stage and at least ten pins; The slide table has a recessed and sunk plane with respect to the plane where the at least ten pins are located, and is used to carry the high-power integrated circuit chip, and at least a part of the sink portion of the slide table is exposed On the outside of the package; and At least four adjacent pins among the at least ten pins are connected together and widened to form a widened pin, and the widened pin is connected to the stage to form the The heat dissipation channel between the high-power integrated circuit chip and the external environment. The high-power integrated circuit chip packaging device according to claim 1, wherein the distance between some or all adjacent pins among the at least ten pins is greater than 1.0 mm. The high-power integrated circuit chip packaging device according to claim 1, wherein the area of the sunken portion of the stage that is exposed on the surface of the package occupies more than 30% of the surface area on the same side of the package . The high-power integrated circuit chip packaging device according to claim 1, wherein the high-power integrated circuit chip packaging device is configured as a chip structure. The high-power integrated circuit chip packaging device according to claim 1, wherein the high-power integrated circuit chip packaging device is configured as a dual in-line structure. The high-power integrated circuit chip packaging device according to claim 1, wherein the high-power integrated circuit chip is a switching power supply chip. A lead frame includes a stage and at least ten pins, wherein: The slide table has a flat surface that is recessed and sunk relative to the flat surface where the at least ten pins are located, and is used to carry high-power integrated circuit chips; and At least four adjacent pins among the at least ten pins are connected together and widened to form a widened pin, and the widened pin is connected to the stage to form the The heat dissipation channel between the high-power integrated circuit chip and the external environment. The lead frame according to claim 6, wherein the spacing between some or all of the adjacent pins among the at least ten pins is greater than 1.0 mm. The lead frame according to claim 6, wherein the high-power integrated circuit chip is a switching power supply chip.

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