TWM606415U - Control system of accessing data for memory storage - Google Patents

Abstract

A control system of accessing data and method thereof for memory storage are provided. The control system includes a memory storage interface, a host system interface, and a control device. When a memory storage operates in a first communication protocol, the memory storage interface electrically connects to the host system interface via a second selector, a bridge device, and a first selector. When a memory storage operates in a second communication protocol, the memory storage interface electrically connects to the host system interface via the second selector, and the memory storage interface electrically connects to the host system interface via the first selector. When a memory storage operates in a third communication protocol, the memory storage interface electrically connects to the host system interface via a first selector, a second selector, a third selector, and a bridge device.

Description

Read and write control system of memory storage device

This creation is related to an electronic device and method, in particular to a read-write control system and method of a memory storage device.

With the rapid development of information technology, the application of electronic products has become increasingly popular, such as handheld electronic devices such as notebook computers, mobile phones, and tablet computers. The characteristics of these electronic devices are that they can be carried and used anytime and anywhere, and in order to enable a large amount of data transmission between various electronic devices, it is usually the memory storage device that is plugged into the memory access device to make the above The electronic product can read and write data of the memory storage device to expand the memory storage capacity of the electronic product.

However, as the data access speed of the memory storage device becomes faster and faster, it is impossible to access the memory storage device of the newer version specification with the control method of the older version specification, so that the memory storage device of the newer specification cannot be Used in memory access devices of older version specifications, that is, memory storage devices of newer specifications cannot support access of memory access devices of older specifications, resulting in memory storage devices and memory access devices The problem of compatibility between the control chips and reduce the flexibility of the memory storage device. In view of this, there is still a need to develop a new type of electronic device and method to improve the above problems.

One of the purposes of this creation is to provide a read-write control system and method, through the control module of the control device, the first selector, and the third selector, so that the host system can use the first interface, the second interface, and the third interface. It can support different communication protocols to read and write the data of the memory storage device, solve the compatibility problem between the memory storage device and the read-write control system, and increase the flexibility of the memory storage device while reducing the read-write control system Production costs.

To achieve the above objective, the first embodiment of the present invention provides a read-write control system for a host system to read and write data of a memory storage device. The read-write control system includes: a memory storage device interface, Used to connect the memory storage device; a host system interface electrically connected to the memory storage device interface, and the host system connects to the host system interface; and a control device including a control module and a first selector , The control module is electrically connected to the memory storage device interface, the host system interface and the first selector, the first selector is electrically connected to the host system interface, the control module includes: a bridge device, electrical The host system interface, the memory storage device interface and the first selector; and a second selector electrically connected to the host system interface, the memory storage device interface, and the bridge device; wherein, the control The device further includes a third selector electrically connected to the memory storage device interface, the bridge device, and the first selector; wherein, when the memory storage device operates under a first communication protocol, The memory storage device interface is electrically connected to the host system interface through the second selector, the bridge device, and the first selector; wherein, when the memory storage device operates under a second communication protocol, the The memory storage device interface is electrically connected to the host system interface through the second selector, and the memory storage device interface is also electrically connected to the host system interface through the third selector and the first selector; Wherein, when the memory storage device operates under a third communication protocol, the memory storage device interface is electrically connected to the host system interface via the second selector and the bridge device, and the memory storage device interface is also The third selector, the bridge device and the first selector are electrically connected to the host system interface.

In one embodiment, the control device detects that the memory storage device is electrically connected to the memory storage device interface, and connects to the memory storage device by the first communication protocol by default, and activates by the first communication protocol The memory storage device.

In one embodiment, the bridge device includes: a first interface electrically connected to the host system interface and the first selector; and a second interface electrically connected to the memory storage device interface and the first interface And the second selector; a third interface electrically connected to the first interface, the second interface and the third selector; wherein, when the memory storage device operates under the first communication protocol, the memory The volume storage device interface is electrically connected to the host system interface via the second selector, the second interface, and the first interface, and via the first selector of the control device, wherein the memory storage device interface , The transmission path between the second interface, the first interface and the host system interface is defined as a first transmission path, the memory storage device interface, the second selector, the second interface, the first interface, The transmission path between the first selector and the host system interface is defined as a second transmission path, so that the host system communicates with the memory storage device interface through the first transmission path and communicates with the memory storage device through the second transmission path. The first communication protocol reads and writes the data of the memory storage device; wherein, when the memory storage device operates with the second communication protocol, the memory storage device interface is used to interface with the host system through the second selector And the memory storage device interface is electrically connected to the host system interface through the third selector and the first selector of the control device, wherein the memory storage device interface and the second selector And the transmission path between the host system interface is defined as a third transmission path, and the transmission path between the memory storage device interface, the first selector, the third selector, and the host system interface is defined as a fourth transmission Path, so that the host system communicates with the memory storage device interface through the third transmission path, and reads and writes the data of the memory storage device through the fourth transmission path using the second communication protocol; wherein, when the memory When the volume storage device operates under the third communication protocol, the memory storage device interface is electrically connected to the host system interface through the second selector, the third interface, and the first interface, and the memory storage The device interface is electrically connected to the host system interface through the third selector, the third interface, the first interface, and the first selector of the control device, wherein the memory storage device interface, the second The selector, the third interface, the first interface, and the host system interface are defined as a fifth transmission path, the memory storage device interface, the third selector, the third interface, the first interface, and the first selection The device and the host system interface are defined as a sixth transmission path, so that the host system communicates with the memory storage device interface through the fifth transmission path, and reads and writes the memory through the sixth transmission path using the third communication protocol The data of the body storage device.

In one embodiment, the host system interface includes a first sub-interface and a second sub-interface, the first selector includes a first transmitting and receiving end and a second transmitting and receiving end, and the third selector includes a The third transmitting and receiving end and the fourth transmitting and receiving end. When the memory storage device operates under the first communication protocol, the host system generates a first trigger signal through the first interface of the bridge device to trigger the first The first transmitting and receiving end of the selector allows the memory storage device interface to be electrically connected to the second sub-interface of the host system interface through the bridge device and the first transmitting and receiving end, and the memory storage device interface is also The first sub-interface of the host system interface is electrically connected through the second selector and the first interface and the second interface of the bridge device.

In one embodiment, when the memory storage device operates under the second communication protocol, the second interface triggers the second selector with a second trigger signal to allow the memory storage device interface to pass through the second The selector is electrically connected to the first sub-interface of the host system interface, and the host system generates a third trigger signal through the third interface to trigger the fourth transmitting and receiving end of the third selector, and the host system through the The first interface generates the first trigger signal to trigger the second transmitting and receiving end of the first selector, so that the memory storage device interface is electrically connected to the host through the fourth transmitting and receiving end and the second transmitting and receiving end The second sub-interface of the system interface.

In one embodiment, when the memory storage device operates under the third communication protocol, the second interface triggers the second selector with a second trigger signal to allow the memory storage device interface to pass through the second The selector, the third interface, and the first interface are electrically connected to the first sub-interface of the host system interface, and the host system generates the first trigger signal through the first interface to trigger the first selector of the first selector A transmitting and receiving end, the host system generates a third trigger signal through the third interface to trigger the third selector, so that the memory storage device interface is electrically transparent to the third transmitting and receiving end and the first transmitting and receiving end The second sub-interface of the host system interface is connected.

In one embodiment, when the memory storage device operates under the second communication protocol, the host system interface disconnects the first transmission and reception end of the first selector.

In one embodiment, the host system communicates with the memory storage device through the host system interface, the first transmitting and receiving end of the first selector, and the second selector to determine whether the memory storage device supports The protocol version of the host system, the protocol version includes PCIe1.0, PCIe2.0 and PCIe3.0 protocol versions.

In one embodiment, when the host system confirms through the host system interface that the first communication protocol of the memory storage device supports the PCIe1.0 protocol version or the PCIe2.0 protocol version of the host system, the host system uses the The host system interface and the first transmitting and receiving end of the first selector read and write the data of the memory storage device, when the host system confirms through the host system interface that the second communication protocol of the memory storage device supports the The PCIe3.0 protocol version of the host system, the host system reads and writes to the memory storage device through the host system interface and the second transmitting and receiving end of the first selector and the fourth transmitting and receiving end of the third selector When the host system confirms through the host system interface that the third communication protocol of the memory storage device supports the PCIe1.0 protocol version or the PCIe2.0 protocol version of the host system, the host system passes the host system The interface and the first transmitting and receiving end of the first selector, the first interface, the third interface and the third transmitting and receiving end of the third selector read and write the data of the memory storage device.

In one embodiment, when the memory storage device supports the operation of the second communication protocol, a non-volatile memory shortcut (NVMe) protocol driver of the host system passes through the host system interface and the first selector The second transmitting and receiving end accesses the data of the memory storage device.

In one embodiment, the first communication protocol and the third communication protocol of the memory storage device are defined as a secure digital (SD) mode, and the second communication protocol of the memory storage device is defined as a fast secure digital (SD Express) mode. )mode.

In one embodiment, the data transfer rate of the first communication protocol and the third communication protocol of the memory storage device is less than the data transfer rate of the second communication protocol, and the data transfer rate of the first communication protocol is less than the data transfer rate of the first communication protocol. 3. The data transfer rate of the communication protocol.

The second embodiment of the present invention provides a read-write control system for a host system to read and write data in a memory storage device. The read-write control system includes: a first transmission path connected to a memory storage Between the device interface, a bridge device, and a host system interface, the memory storage device interface is used to connect the memory storage device; a second transmission path is connected to the memory storage device interface and a second selector , The bridge device, a first selector, and the host system interface; a third transmission path connected between the memory storage device interface, the second selector, and the host system interface; and a fourth A transmission path is connected between the memory storage device interface, a third selector, the first selector, and the host system interface; a fifth transmission path is connected to the memory storage device interface and the second selection A sixth transmission path connected between the memory storage device interface, the third selector, the bridge device, the first selector, and the host system interface ; Wherein, when the memory storage device operates with the first communication protocol, the host system communicates with the memory storage device interface through the host system interface through the first transmission path and communicates with the memory storage device interface through the second transmission path The first communication protocol reads and writes the data of the memory storage device; wherein, when the memory storage device operates under the second communication protocol, the host system communicates with the memory through the third transmission path through the host system interface The volume storage device interface communicates and reads and writes the data of the memory storage device using the second communication protocol through the fourth transmission path; wherein, when the memory storage device operates under the third communication protocol, the host system The host system interface communicates with the memory storage device interface through the fifth transmission path, and reads and writes the data of the memory storage device through the sixth transmission path using the third communication protocol.

In one embodiment, the host system interface includes a first sub-interface and a second sub-interface, the bridge device includes a first interface, a second interface, and a third interface, and the first selector includes a first Transmitting and receiving end and a second transmitting and receiving end. The third selector includes a third transmitting and receiving end and a fourth transmitting and receiving end. When the memory storage device operates under the first communication protocol, the host system The first interface generates a first trigger signal to trigger the first transmitting and receiving end of the first selector, so that the memory storage device interface is electrically connected to the host system interface through the bridge device and the first transmitting and receiving end The second sub-interface and the memory storage device interface are also electrically connected to the first sub-interface of the host system interface through the second selector and the first interface and the second interface of the bridge device.

In one embodiment, when the memory storage device operates under the second communication protocol, the second interface triggers the second selector with a second trigger signal to allow the memory storage device interface to pass through the second The selector is electrically connected to the first sub-interface of the host system interface, and the host system generates a third trigger signal through the third interface to trigger the fourth transmitting and receiving end of the third selector, and the host system interface is The first interface generates the first trigger signal to trigger the second transmitting and receiving end of the first selector, so that the memory storage device interface is electrically connected to the fourth transmitting and receiving end and the second transmitting and receiving end The second sub-interface of the host system interface.

In one embodiment, when the memory storage device operates under the third communication protocol, the second interface triggers the second selector with a second trigger signal to allow the memory storage device interface to pass through the second The selector, the third interface, and the first interface are electrically connected to the first sub-interface of the host system interface, and the host system generates the first trigger signal through the first interface to trigger the first selector of the first selector A transmitting and receiving end, the host system generates a third trigger signal through the third interface to trigger the third selector, so that the memory storage device interface is electrically transparent to the third transmitting and receiving end and the first transmitting and receiving end The second sub-interface of the host system interface is connected. In one embodiment, the third interface is electrically connected to the first interface through the second interface.

In one embodiment, when the memory storage device operates under the second communication protocol, the host system interface disconnects the first transmission and reception end of the first selector, and when the memory storage device uses the first When the communication protocol or the third communication protocol is operating, the host system interface disconnects the second transmitting and receiving end of the first selector.

The third embodiment of the present invention provides a read-write control method for a read-write control system for a host system to read and write a memory storage device through the read-write control system. The read-write control system includes a memory A bulk storage device interface, a host system interface, and a control device. The control device includes a control module, a first selector, and a third selector. The control module includes a bridge device and a second selector. The bridge device includes a first interface, a second interface, and a third interface. The host system interface includes a first sub-interface and a second sub-interface. The first selector includes a first transmitting and receiving end and a third interface. The second transmitting and receiving end, the third selector includes a third transmitting and receiving end and a fourth transmitting and receiving end, the read-write control method includes the following steps:

The host system generates a first trigger signal through the bridge device to trigger the first transmitting and receiving end of the first selector, and the host system uses the host system interface, the first transmitting and receiving end of the first selector, and the The control module is electrically connected to the memory storage device interface;

Detecting that the memory storage device is connected to the memory storage device interface, and connects with the memory storage device using a first communication protocol;

Determine whether the memory storage device supports the operation of a second communication protocol;

When it is determined that the memory storage device supports the second communication protocol operation, the memory storage device interface is electrically connected to the host system interface via the second selector, and the memory storage device interface is also selected via the third selection The first selector and the first selector are electrically connected to the host system interface, and the host system communicates with the second transmitting and receiving end of the first selector of the control device through the host system interface, using the second communication protocol Read and write the data of the memory storage device;

When it is determined that the memory storage device does not support the operation of the second communication protocol, it is determined whether the memory storage device supports the operation of a third communication protocol;

When it is determined that the memory storage device supports the operation of the third communication protocol, the memory storage device interface is electrically connected to the host system interface via the second selector and the bridge device, and the memory storage device interface is also The third selector, the bridge device, and the first selector are electrically connected to the host system interface, so that the host system communicates with the first transmission of the first selector of the control device through the host system interface. The receiving end uses the third communication protocol to read and write the data of the memory storage device;

When it is determined that the memory storage device does not support the operation of the third communication protocol, the memory storage device operates under the first communication protocol, and the memory storage device interfaces through the second selector, the bridge device, and the first communication protocol. A selector is electrically connected with the host system interface, so that the host system reads and writes the data of the memory storage device through the host system interface using the first communication protocol.

In one embodiment, after the step of detecting that the memory storage device is connected to the interface of the memory storage device, it further includes the second interface generating a second trigger signal to trigger the second selector.

In one embodiment, after detecting that the memory storage device is connected to the memory storage device interface, the host system activates the memory storage device through the host system interface and the bridge device using the first communication protocol When it is determined that the memory storage device supports the operation of the second communication protocol, the memory storage device is activated by the second communication protocol, and when it is determined that the memory storage device supports the operation of the third communication protocol, the third communication protocol is used. The communication protocol activates the memory storage device.

In one embodiment, when the memory storage device operates under the second communication protocol, the second interface triggers the second selector with a second trigger signal to allow the memory storage device interface to pass through the second The selector is electrically connected to the first sub-interface of the host system interface.

In one embodiment, when the memory storage device operates under the second communication protocol, the third interface of the bridge device generates a third trigger signal to trigger the fourth transmitting and receiving end of the third selector, the The first interface of the bridge device generates a first trigger signal to trigger the second transmitting and receiving end of the first selector, so that the memory storage device interface can pass through the fourth transmitting and receiving end and the second transmitting and receiving end The second sub-interface of the host system interface is electrically connected.

In one embodiment, when the memory storage device operates under the third communication protocol, the second interface of the bridge device triggers the second selector with a second trigger signal so that the memory storage device interface The first sub-interface of the host system interface is electrically connected to the first interface through the third interface. In one embodiment, the third interface is electrically connected to the first interface through the second interface.

In one embodiment, when the memory storage device operates under the third communication protocol, the third interface of the bridge device generates a third trigger signal to trigger the third transmitting and receiving end of the third selector, the The first interface of the bridge device generates a first trigger signal to trigger the first transmitting and receiving end of the first selector, so that the memory storage device interface can pass through the third transmitting and receiving end, the bridge device, and the first The transmitting and receiving end is electrically connected to the second sub-interface of the host system interface.

In one embodiment, when the memory storage device operates under the first communication protocol, the second interface of the bridge device triggers the second selector with a second trigger signal, so that the memory storage device interface The first sub-interface of the host system interface is electrically connected to the first interface through the second interface.

In one embodiment, when the memory storage device operates under the first communication protocol, the first interface of the bridge device generates a first trigger signal to trigger the first transmitting and receiving end of the first selector to The memory storage device interface is electrically connected to the second sub-interface of the host system interface through the second selector, the bridge device and the first transmitting and receiving end.

In one embodiment, when the memory storage device operates under the second communication protocol, the host system interface disconnects the first transmission and reception end of the first selector.

In one embodiment, the host system communicates with the memory storage device through the host system interface, the first transmitting and receiving end of the first selector, and the second selector to determine whether the memory storage device supports The protocol version of the host system, the protocol version includes PCIe1.0, PCIe2.0 and PCIe3.0 protocol versions.

In one embodiment, when it is confirmed that the first communication protocol of the memory storage device supports the PCIe1.0 protocol version or the PCIe2.0 protocol version of the host system interface, the host system communicates with the first protocol through the host system interface. The first transmitting and receiving end of the selector reads and writes the data of the memory storage device, and when it is confirmed that the second communication protocol of the memory storage device supports the PCIe3.0 protocol version of the host system, the host system uses the host The system interface and the second transmitting and receiving end of the first selector and the fourth transmitting and receiving end of the third selector read and write the data of the memory storage device, when the host system confirms the data through the host system interface The third communication protocol of the memory storage device supports the PCIe1.0 protocol version or the PCIe2.0 protocol version of the host system, and the host system communicates with the first transmitting and receiving end of the first selector through the host system interface, The first interface, the third interface, and the third transmitting and receiving end of the third selector read and write the data of the memory storage device.

In one embodiment, the first communication protocol and the third communication protocol of the memory storage device are defined as a secure digital (SD) mode, and the second communication protocol of the memory storage device is defined as a fast secure digital (SD Express) mode. )mode.

In one embodiment, the data transfer rate of the first communication protocol and the third communication protocol of the memory storage device is less than the data transfer rate of the second communication protocol, and the data transfer rate of the first communication protocol is less than the data transfer rate of the first communication protocol. 3. The data transfer rate of the communication protocol.

In one embodiment, when the memory storage device supports the operation of the second communication protocol, a non-volatile memory shortcut (NVMe) protocol driver of the host system passes through the host system interface and the first selector The second transmitting and receiving end accesses the data of the memory storage device.

The reading and writing control system and method of this creation, through the control module of the control device, the first selector and the third selector, enable the host system to support different interfaces through the first interface, the second interface and the third interface The communication protocol reads and writes the data of the memory storage device, solves the compatibility problem between the memory storage device and the read-write control system, and improves the flexibility of the memory storage device while reducing the production cost of the read-write control system.

Please refer to the drawings, where the same component symbols represent the same components or similar components. The principle of this creation is illustrated by implementing it in a suitable computing environment. The following description is based on the illustrated specific embodiments of the present creation, which should not be regarded as limiting other specific embodiments of the present creation not detailed here.

Refer to Figure 1, which is a block diagram of the read-write control system according to this creative embodiment. The read-write control system is used for a host system 103 to read and write data of a memory storage device 100. The read-write control system includes a memory storage device interface 101, a host system interface 102, and a control device 104. The memory storage device 100 may be a memory card (Memory Card), embedded memory (Embedded Multi Media Card, eMMC), solid state disk (Solid State Disk, SSD), or other types of storage devices. There is no restriction on the type of the memory storage device 100.

As shown in FIG. 1, the memory storage device interface 101 is used to connect the memory storage device 100. The host system interface 102 is electrically connected to the memory storage device interface 101, and the host system 103 is connected to the host system interface 102. The control device 104 is connected between the memory storage device interface 101 and the host system interface 102. The control device 104 includes a control module 106, a first selector 108, and a third selector 115. The control module 106 is electrically connected to the memory storage device interface 101, the host system interface 102, and the first selector 108 And a third selector 115, the first selector 108 is electrically connected to the memory storage device interface 101 and the host system interface 102, and the third selector 115 is electrically connected to the memory storage device interface 101 and the first The selector 108. The control module 106 includes a bridge device 109 and a second selector 114, and the bridge device 109 is electrically connected to the host system interface 102, the memory storage device interface 101, the first selector 108 and the third selector 115 , The second selector 114 is electrically connected to the host system interface 102, the memory storage device interface 101 and the bridge device 109.

Wherein, when the memory storage device 100 operates under the first communication protocol, the memory storage device interface 101 communicates with the host system interface 102 via the second selector 114, the bridge device 109, and the first selector 108 Electrical connection. When the memory storage device 100 operates under the second communication protocol, the memory storage device interface 101 is electrically connected to the host system interface 102 via the second selector 114, and the memory storage device interface 101 also passes through the The third selector 115 and the first selector 101 are electrically connected to the host system interface 102. When the memory storage device 100 operates under a third communication protocol, the memory storage device interface 101 is electrically connected to the host system interface 102 via the second selector 114 and the bridge device 109, and the memory storage device The device interface 101 is also electrically connected to the host system interface 102 via the third selector 115, the bridge device 109, and the first selector 108. In addition, in this embodiment, the bridge device 109 includes a first interface 110, a second interface 112, and a third interface 113. The first interface 110 is electrically connected to the host system interface 102 and the first selector 108, and the second interface 112 is electrically connected to the memory storage device interface 101, the first interface 110 and the second selector 114. The third interface 113 is electrically connected to the first interface 110, the second interface 112 and the third selector 115. In an embodiment, the bridge device 109 can generate a first trigger signal TS1, a second trigger signal TS2, and a third trigger signal TS3.

Figure 2 is a block diagram of the read-write control system according to the first embodiment of the creation. Please continue to refer to Figure 2. In one embodiment, the host system 103 can detect through the control device 104 that the memory storage device interface 101 is electrically connected to the host system interface 102, and uses the first communication protocol to communicate with The memory storage device 100 is connected to initialize or start (Initialization process) the memory storage device 100 using the first communication protocol. The initialization is, for example, that the host system interface 102 provides power required for operation of the memory storage device 100, and the host system interface 102 transmits operation and access commands to the memory storage device 100 through the memory storage device interface 101 to establish a two-way communication between the host system interface 102 and the memory storage device 100. Among them, in Figure 2, the solid line components and the transmission direction represent, for example, the transmission path under the state of the first communication protocol. In contrast, the dashed element and the transmission direction, for example, indicate a transmission path that is disabled in the state of the first communication protocol, but is not limited thereto.

Furthermore, when the memory storage device 100 operates under the first communication protocol, the memory storage device interface 101 can pass through the second selector 114, the second interface 110, and the first interface 112, and through The first selector 108 of the control device 104 is electrically connected to the host system interface 102. In this embodiment, the transmission path between the memory storage device interface 101, the second interface 112, the first interface 110, and the host system interface 102 is defined as the first transmission path P1. The aforementioned transmission path between the memory storage device interface 101, the second selector 114, the second interface 112, the first interface 110, the first selector 108, and the host system interface 102 is defined as the first 2. Transmission path P2. Therefore, in this embodiment, the host system interface 102 can communicate with the memory storage device interface 101 through the first transmission path P1 and read and write to the memory storage device using the first communication protocol through the second transmission path P2. 100 of the information. In detail, in this embodiment, the host system interface 102 detects that the memory storage device interface 101 is electrically connected to the host system interface 102 through the first transmission path P1. The host system interface 102 can initialize the memory storage device 100 with the first communication protocol via the first transmission path P1. In a preferred embodiment, in the process of detecting the connection of the memory storage device 100, the host system 103 uses the host system interface 102 and the first interface 110 and the second interface 112 of the bridge device 109, for example. , Initialize or start the memory storage device 100 with the first communication protocol. Wherein, the first communication protocol is, for example, a secure digital (SD) mode.

Figure 3 is a block diagram of the read-write control system according to the second embodiment of the invention. Among them, in Figure 3, the solid line components and the transmission direction represent, for example, the transmission path performed in the state of the second communication protocol. In contrast, the dashed element and the transmission direction, for example, indicate a transmission path that is disabled in the state of the second communication protocol, but is not limited to this. Please continue to refer to FIG. 3. In one embodiment, when the memory storage device 100 operates with the second communication protocol, the memory storage device interface 101 communicates with the host system interface 102 through the second selector 114 And the memory storage device interface 101 is electrically connected to the host system interface 102 via the third selector 115 and the first selector 108 of the control device 104, wherein the memory storage device interface 101, The transmission path between the second selector 114 and the host system interface 102 is defined as a third transmission path P3, the memory storage device interface 101, the third selector 115, the first selector 108, and the host system interface 102 The intermediate transmission path is defined as the fourth transmission path P4, so that the host system interface 102 communicates with the memory storage device interface 101 through the third transmission path P3 and reads with the second communication protocol through the fourth transmission path P4 Write the data of the memory storage device 100. Wherein, after determining that the memory storage device 100 supports the operation of the second communication protocol, in this embodiment, for example, the memory storage device 100 is initialized or started (Initialization process) using the second communication protocol to perform subsequent operations. Communication or read and write operations. Wherein, the second communication protocol is, for example, a fast and secure digital (SD Express) mode.

Figure 4 is a block diagram of the read-write control system according to the third embodiment of this creation. . Please continue to refer to Fig. 4, the read-write control system of this embodiment is similar to the read-write control system of the embodiment in Fig. 3. Furthermore, compared with the read-write control system of the embodiment in FIG. 3, the read-write control system of this embodiment further has a transmission and reception channel 116, and the memory storage device interface 101 can be directly connected through the transmission and reception channel 116 The host system interface 102. In this way, when the memory storage device 100 supports the operation of the second communication protocol, a non-volatile memory shortcut (NVMe) protocol driver of the host system 103 can pass through the host system interface 102, the transmission and reception The channel 116 and the memory storage device interface 101 access the data of the memory storage device 100. Wherein, in this embodiment, the quick and secure digital mode is a secure digital protocol version, for example, it supports a secure digital (SD) 7.0 protocol version and SD 8.0 or later updated protocol versions. The read-write control system of this embodiment can be configured on a circuit board, for example, and the transmission and reception channel 116 is, for example, a data transmission and reception circuit on the circuit board.

Figure 5 is a block diagram of the read-write control system in the fourth embodiment according to the invention. Please continue to refer to FIG. 5. In this embodiment, when the memory storage device 100 operates under the third communication protocol, the memory storage device interface 101 passes through the second selector 114, the third interface 113, and The first interface 110 is electrically connected to the host system interface 102, and the memory storage device interface 101 passes through the third selector 115 of the control device 104, the third interface 113, the first interface 110, and The first selector 108 is electrically connected to the host system interface 102, wherein the memory storage device interface 101, the second selector 114, the third interface 113, the first interface 110 and the host system interface 102 define Is a fifth transmission path P5, the memory storage device interface 101, the third selector 115, the third interface 113, the first interface 110, the first selector 108, and the host system interface 102 are defined as a The sixth transmission path P6 enables the host system 103 to communicate with the memory storage device interface 101 through the fifth transmission path P5 and to read and write the memory storage device 100 through the sixth transmission path P6 using the third communication protocol Of the information. In one embodiment, the third interface 113 is electrically connected to the first interface 110 through the second interface 112.

Please refer to Fig. 1. In one embodiment, the memory interface 101 is, for example, a secure digital memory storage protocol, such as SD-UHS I, SD-UHS II, SD-UHS III, SD 7.0 And agreement versions such as SD 8.0, but not limited to this. In one embodiment, the first communication protocol of the memory storage device 100 is defined as a secure digital (SD) mode, such as SD-UHS I, SD-UHS II, and SD-UHS III protocol versions. The second communication protocol of the memory storage device 100 is defined as a fast and secure digital (SD Express) mode. The secure digital mode is the protocol version before the fast secure digital mode, and the fast secure digital mode is the secure digital (SD) 7.0 and SD 8.0 protocol versions, for example, it supports the secure digital (SD) 7.0 protocol version and SD 8.0 or The updated version of the agreement. In one embodiment, the data transfer rate of the first communication protocol and the third communication protocol of the memory storage device 100 is less than the data transfer rate of the second communication protocol, and the data transfer rate of the first communication protocol is less than the The data transfer rate of the third communication protocol. The host system interface 102 is, for example, a peripheral component interconnect express (PCIe) root complex component, which is used to connect the processor and memory to a PCIe switching architecture composed of one or more switching devices. In notebook computers, mobile phones, tablet computers, or other electronic devices connected to the processor and memory. The control device 104 is, for example, a control chip or a control circuit of a memory access device, but is not limited thereto.

In addition, in an embodiment, the host system interface 102 may include a first sub-interface 102a and a second sub-interface 102b. The first selector 108 includes a first transmitting and receiving terminal TR1 and a second transmitting and receiving terminal TR2. The three selector 115 includes a third transmitting and receiving terminal TR3 and a fourth transmitting and receiving terminal TR4. For example, the first sub-interface 102a includes a PCI Express Reset (PERST#) signal, a clock request operation signal (clock request, CLKREQ#), and a reference clock differential pair signal (reference clock, REFCLK+) signal. , REFCLK-), where the shortcut peripheral component interconnection reset (PERST#) signal is used to manage the reset operation of the second sub-interface 102b; the clock request operation signal (clock request, CLKREQ#) is used to request the reference clock operation; The reference clock differential pair signal (reference clock, REFCLK+, REFCLK-) is used to provide the reference clock. The first sub-interface 102a is electrically connected to the first interface 110 of the bridge device 109 and the second selector 114 for transmitting the above-mentioned 4 signals, including PERST#, CLKREQ#, REFCLK+, and REFCLK- 4 signals. The second sub-interface 102b is used to perform data transmission/receive (transmit/receive, TX/RX) between the interface device 102 and the memory storage device interface 101. The second sub-interface 102b supports PCIe1.0, PCIe2.0 and PCIe3.0 protocol versions. For example, the transmission bandwidth of PCIe1.0 is 2.5GHz, the transmission bandwidth of PCIe2.0 is 5.0GHz, and the transmission bandwidth of PCIe3.0 is 8.0GHz. The first transmitting and receiving terminal TR1 is, for example, a low-speed transmitting and receiving terminal, and the second transmitting and receiving terminal TR2 is, for example, a high-speed transmitting and receiving terminal, but not limited to this, such as the first transmitting and receiving terminal TR1 and the second transmitting and receiving terminal TR2. Have different transmission bandwidths.

Please refer to Fig. 1 and Fig. 2 at the same time. In one embodiment, when the memory storage device 100 operates with the first communication protocol, the host system interface 102 is generated through the first interface of the bridge device 109 The first trigger signal TS1 triggers the first transmitting and receiving terminal TR1 of the first selector 108, so that the memory storage device interface 101 is electrically connected to the host system interface through the bridge device 109 and the first transmitting and receiving terminal TR1 The second sub-interface 102b of 102, the memory storage device interface 101 is also electrically connected to the host system interface 102 through the second selector 114 and the first interface 110 and the second interface 112 of the bridge device 109 The first sub-interface 102a. The first transmitting and receiving terminal TR1 is, for example, a low-speed transmitting and receiving terminal, but not limited to this. For example, the first transmitting and receiving terminal TR1 and the second transmitting and receiving terminal TR2 have different transmission bandwidths.

Please refer to FIG. 1 and FIG. 3 at the same time. In one embodiment, when the memory storage device 100 operates under the second communication protocol, the second interface 112 of the bridge device 109 is triggered by the second trigger signal TS2 The second selector 114 allows the memory storage device interface 101 to be electrically connected to the first sub-interface 102a of the host system interface 102 through the second selector 114, and the host system 103 through the third interface 113 A third trigger signal TS3 is generated to trigger the fourth transmitting and receiving terminal TR4 of the third selector 115, and the host system generates a first trigger signal TS1 through the first interface 102 to trigger the second transmission of the first selector 108 The receiving terminal TR2 allows the memory storage device interface 101 to be electrically connected to the second sub-interface 102b of the host system interface 102 through the fourth transmitting and receiving terminal TR4 and the second transmitting and receiving terminal TR2. In one embodiment, when the memory storage device 100 operates under the second communication protocol, the host system interface 102 disconnects the first transmitting and receiving terminal TR1 of the first selector 108.

Please refer to FIGS. 1 and 5 at the same time. In one embodiment, when the memory storage device 100 operates under the third communication protocol, the second interface 112 uses a second trigger signal TS2 to trigger the second Selector 114 to allow the memory storage device interface 101 to be electrically connected to the first sub-interface 102a of the host system interface 102 through the second selector 114, the third interface 113, and the first interface 110, and the The host system 103 generates the first trigger signal TS1 through the first interface 110 to trigger the first transmitting and receiving terminal TR1 of the first selector 108, and the host system 103 generates a third trigger signal TS3 through the third interface 113 to trigger The third selector 115 allows the memory storage device interface 101 to be electrically connected to the second sub-interface 102b of the host system interface 102 through the third transmitting and receiving terminal TR3 and the first transmitting and receiving terminal TR1. In one embodiment, the third interface 113 is electrically connected to the first interface 110 through the second interface 112, for example.

As shown in FIGS. 1 to 5, the host system 103 scans the memory through the first transmission and reception terminal TR1 of the first selector 108 and the second selector 114 via the host system interface 102, for example. The storage device 100 determines whether the memory storage device 100 supports the protocol version of the host system interface 102, and the protocol version includes PCIe1.0, PCIe2.0, and PCIe3.0 protocol versions. When it is confirmed that the first communication protocol of the memory storage device 100 supports the PCIe1.0 protocol version or the PCIe2.0 protocol version of the host system interface 102, the host system 103, for example, through the host system interface 102 through the first The first transmitting and receiving terminal TR1 of the selector 114 reads and writes the data of the memory storage device 100. When it is confirmed that the second communication protocol of the memory storage device 100 supports the PCIe3.0 protocol version of the host system interface 102, the host system 103, for example, passes through the host system interface 102 to pass the second selector of the first selector 108 The transmitting and receiving terminal TR2 and the fourth transmitting and receiving terminal TR4 of the third selector 115 read and write the data of the memory storage device 100. When the host system 103 confirms through the host system interface 102 that the third communication protocol of the memory storage device 100 supports the PCIe1.0 protocol version or the PCIe2.0 protocol version of the host system, the host system 103 uses the host system The interface 102 and the first transmitting and receiving terminal TR1 of the first selector 108, the first interface 110, the third interface 113, and the third transmitting and receiving terminal TR3 of the third selector 115 read and write the memory storage The data of the device 100.

As shown in Figure 1, in one embodiment, the second interface 112 of the bridge device 109 includes a control interface 112a and a transmission interface 112b. The control interface 112a is connected to the memory storage device interface 101, and the transmission interface 112b The second selector 114 is connected. The control interface 112a includes signals such as secure digital command (SD CMD) and secure digital clock (SD CLK) for establishing a communication link between the second interface 112 and the memory storage device interface 101 . The transmitting and receiving interface 112b includes secure digital data (SD DAT), such as SD DAT 0~3, which includes 4 bits for transmitting and receiving data between the second interface 112 and the memory storage device interface 101 data. The control interface 112a and the receiving interface 112b of the second interface 112 are respectively used to convert the communication and data transmission format between the first sub-interface 102a and the second sub-interface 102b of the host system interface 102 and the first communication protocol . In one embodiment, the second selector 114 is, for example, a multiplexer, but is not limited thereto, for example, a selector formed by combining circuit elements or logic elements. In one embodiment, the second interface 112 is, for example, the main controller of the SD-UHS I.

In one embodiment, the third interface 113 of the bridge device 109 includes a reference clock and data signals, such as a secure digital reference clock (SD UHS-II RCLK) and a secure digital clock data signal (SD DAT0~1), It corresponds to the 4 bit channels of SD DAT 0~3 secure digital data. In an embodiment, the third selector 115 is, for example, a multiplexer, but is not limited thereto, for example, a selector formed by combining circuit elements or logic elements. In one embodiment, the third interface 113 is, for example, the main controller of SD-UHS II.

As shown in Figures 1 to 5, in one embodiment, the read-write control system is used to control the reading and writing of data in a memory storage device 100. The read-write control system includes a first transmission path P1, a second The second transmission path P2, the third transmission path P3, the fourth transmission path P4, the fifth transmission path P5, and the sixth transmission path P6. The first transmission path P1 is connected between a memory storage device interface 101, a bridge device 109 and a host system interface 102, wherein the memory storage device interface 101 is used to connect the memory storage device 100. The second transmission path P2 is connected between the memory storage device interface 101, a second selector 114, the bridge device 109, a first selector 108, and the host system interface 102. The third transmission path P3 is connected between the memory storage device interface 101, the second selector 114 and the host system interface 102. The fourth transmission path P4 is connected between the memory storage device interface 101, the third selector 115, the first selector 108, and the host system interface 102. The fifth transmission path P5 is connected between the memory storage device interface 101, the second selector 114, the bridge device 109 and the host system interface 102. The sixth transmission path P6 is connected between the memory storage device interface 101, the third selector 115, the bridge device 106, the first selector 108 and the host system interface 102. Wherein, when the memory storage device 100 operates under the first communication protocol, the host system 103 communicates with the memory storage device interface 101 through the first transmission path P1 and communicates with the first transmission path P2 through the second transmission path P2. A communication protocol reads and writes the data of the memory storage device 100. Wherein, when the memory storage device 100 operates under the second communication protocol, the host system 103 communicates with the memory storage device interface 101 through the third transmission path P3 and communicates with the first transmission path P4 through the fourth transmission path P4. Two communication protocols read and write the data of the memory storage device 100. When the memory storage device 100 operates under the third communication protocol, the host system 103 communicates with the memory storage device interface 101 through the host system interface 102 through the fifth transmission path P5 and through the sixth transmission path P6 uses the third communication protocol to read and write the data of the memory storage device 100.

According to the above, the read-write control system of this creation uses the control module 106, the first selector 108, and the third selector 115 of the control device 104 to enable the host system 103 to pass through the first interface 110, the second interface 112, and the second interface. The three interfaces 113 can support different communication protocols to read and write data of the memory storage device 100, solve the compatibility problem between the memory storage device 100 and the read-write control system, and improve the flexibility of the memory storage device 100 , While reducing the production cost of the read-write control system.

Please refer to Fig. 1 and Fig. 6 again. Fig. 6 is a flow chart of the method of reading and writing control according to the first embodiment of the creation. The read-write control method is used in a read-write control system for the host system 103 to read and write the memory storage device 100 through the read-write control system. The read-write control system includes a memory storage device interface 101, a host system interface 102, and a control device 104. The control device 104 includes a control module 106, a first selector 108 and a third selector 115, The control module 106 includes a first interface 110, a second interface 112, and a second selector 114. The host system interface 102 includes a first sub-interface 102a and a second sub-interface 102b. The first selector 108 It includes a first transmitting and receiving terminal TR1 and a second transmitting and receiving terminal TR2. The third selector 115 includes a third transmitting and receiving terminal TR3 and a fourth transmitting and receiving terminal TR4. The read-write control method includes the following steps:

In step S200, the host system 103 generates the first trigger signal TS1 through the bridge device 109 to trigger the first transmitting and receiving terminal TR1 of the first selector 108, and the host system 103 uses the host system interface 102, the first selection The first transmitting and receiving terminal TR1 of the device 108 and the control module 106 are electrically connected to the memory storage device interface 101.

In step S202, it is detected that the memory storage device 100 is connected to the host system interface 102 and the control device 104. In one embodiment, the host system 103 is connected to the memory storage device 100 in advance through a first communication protocol, for example.

In step S204, it is determined whether the memory storage device 100 supports the operation of a second communication protocol.

In step S206, when it is determined that the memory storage device 100 supports the second communication protocol operation, the memory storage device interface 101 is electrically connected to the host system interface 102 through the second selector 114, and the memory The storage device interface 101 is also electrically connected to the host system interface 102 via the third selector 115 and the first selector 108, and the host system 103 passes through the host system interface 102 and the first selection of the control device 104 The second transmitting and receiving terminal TR2 of the device 108 uses the second communication protocol to read and write the data of the memory storage device 100.

In step S208, when it is determined that the memory storage device does not support the operation of the second communication protocol, it is determined whether the memory storage device supports the operation of a third communication protocol.

In step S210, when it is determined that the memory storage device 100 supports the operation of the third communication protocol, the memory storage device interface 101 communicates with the host system interface 102 via the second selector 114 and the bridge device 109. The memory storage device interface 101 is also electrically connected to the host system interface 102 through the third selector 115, the bridge device 109, and the first selector 108, so that the host system 103 can pass through the host system The interface 102 and the first transmitting/receiving terminal TR1 of the first selector 108 of the control device 104 read and write the data of the memory storage device 100 by the third communication protocol.

In step S212, when it is determined that the memory storage device 100 does not support the operation of the third communication protocol, the memory storage device 100 operates according to the first communication protocol, and the memory storage device interface 101 undergoes the second selection The device 114, the bridge device 109, and the first selector 108 are electrically connected to the host system interface 102, so that the host system 103 can read and write to the memory storage device 100 through the host system interface 102 using the first communication protocol Of the information.

Please refer to Figure 1 and Figures 7-8 again. Figures 7-8 show the flow chart of the read-write control method according to the second embodiment of this creation, which is used in a read-write control system. The read-write control system includes A memory storage device interface 101, a host system interface 102, and a control device 104. The control device 104 includes a control module 106, a first selector 108, and a third selector 115. The control module 106 includes A bridge device 109 and a second selector 114. The bridge device 109 includes a first interface 110, a second interface 112, and a third interface 113. The host system interface 102 includes a first sub-interface 102a and a second interface. Two sub-interfaces 102b, the first selector 108 includes a first transmitting/receiving terminal TR1 and a second transmitting/receiving terminal TR2, the read-write control method includes the following steps:

In step S300, the host system 103 triggers the first transmitting and receiving terminal TR1 of the first selector 108 through the host system interface 102 with the first trigger signal TS1, and the host system interface 102 passes through the second selector 108 of the first selector 108. A transmitting and receiving terminal TR1 and the control module 106 are electrically connected to the memory storage device interface 101.

In step S302, it is detected that the memory storage device 100 is electrically connected to the memory storage device interface 101. In this embodiment, for example, the first communication protocol is used to connect with the memory storage device 100. In a preferred embodiment, the control device 104 detects that the memory storage device 100 is electrically connected to the memory storage device interface 101. The control device 104 can send detection messages to the host system 103, for example. Any action that detects that the memory storage device 100 is electrically connected to the memory storage device interface 101 is within the spirit and scope of the present disclosure, and there is no limitation here.

In step S304, the second interface 112 generates a second trigger signal TS2 to trigger the second selector 114.

In step S306, the memory storage device 100 is initialized or started (Initialization process) using the first communication protocol. In one embodiment, the host system 103 can initialize or activate the memory storage device 100 through the first interface 110 and the second interface 112 of the bridge device 109 of the control module 106, for example. In other embodiments, the control module 106 may also use the first communication protocol to initialize or activate the memory storage device 100 through the first interface 110, the second interface 112, and the third interface 113 of the bridge device 109 . Any actions of initializing or starting the memory storage device 100 using the first communication protocol are within the spirit and scope of the disclosure, and no limitation is made herein.

In step S308, it is determined whether the memory storage device 100 supports the operation of the second communication protocol. In one embodiment, the host system 103 can determine whether the memory storage device 100 supports the second communication protocol through the first transmitting and receiving end TR1 of the first selector 108 via the host system interface 102 Operation. In other embodiments, for example, the control module 106 can determine whether the memory storage device 100 supports the operation of the second communication protocol. Any technology for determining whether the memory storage device 100 supports the operation of the second communication protocol falls within the spirit and scope of this disclosure, and this article does not make any restrictions here. It is worth mentioning that when it is determined that the memory storage device 100 supports the operation of the second communication protocol, for example, the memory storage device is initialized or activated (Initialization process) by the second communication protocol. After it is determined that the memory storage device 100 supports the operation of the third communication protocol, for example, the memory storage device 100 is initialized or activated (Initialization process) with the third communication protocol.

In step S310, when it is determined that the memory storage device 100 supports the second communication protocol operation, the second interface 112 triggers the second selector 114 with the second trigger signal TS2, so that the memory storage device interface 101 is electrically connected to the first sub-interface 102a of the host system interface 102 through the second selector 114. In one embodiment, the first sub-interface 102a supports a PCIe3.0 protocol version, for example.

In step S312, when the memory storage device 100 operates under the second communication protocol, the third interface 113 of the bridge device 109 generates a third trigger signal TS3 to trigger the fourth transmission of the third selector 115 The receiving terminal TR4, the first interface 110 of the bridge device 109 generates a first trigger signal TR1 to trigger the second transmitting and receiving terminal TR2 of the first selector 108, so that the memory storage device interface 101 can pass through the fourth The transmitting/receiving terminal TR4 and the second transmitting/receiving terminal TR2 are electrically connected to the second sub-interface 102b of the host system interface 102. In one embodiment, the second sub-interface 102b supports PCIe3.0 protocol version, for example.

In step S314, when the memory storage device 100 operates under the second communication protocol, the host system interface 102 disconnects the first transmission and reception terminal TR1 of the first selector 108, and the first transmission and reception terminal TR1 For example, it supports PCIe1.0 and PCIe2.0 protocol versions.

In step S316, when the memory storage device 100 supports the operation of the second communication protocol, in one embodiment, a non-volatile memory shortcut (NVMe) protocol driver of the host system 103 passes through the host system The interface 102 and the second transmitting and receiving terminal TR2 of the first selector 108 access the data of the memory storage device 100 in SD Express mode.

In step S318, when it is determined that the memory storage device 100 does not support the operation of the second communication protocol, it is determined whether the memory storage device 100 supports the operation of a third communication protocol. In one embodiment, the third communication protocol is, for example, the protocol version of SD-UHS II.

In step S320, when the memory storage device 100 operates under the third communication protocol, the second interface 112 of the bridge device 109 triggers the second selector 114 with a second trigger signal TS2, so that the memory The bulk storage device interface 101 is electrically connected to the first sub-interface 102a of the host system interface 102 through the third interface 113 and the first interface 110.

In step S322, when the memory storage device 100 operates under the third communication protocol, the third interface 112 of the bridge device 109 generates a third trigger signal TS3 to trigger the third transmission of the third selector 115 The receiving terminal TR3, the first interface 110 of the bridge device 109 generates a first trigger signal TR1 to trigger the first transmitting and receiving terminal TR1 of the first selector 108, so that the memory storage device interface 101 can pass through the first The transmitting and receiving terminal TR1 is electrically connected to the second sub-interface 102b of the host system interface 102.

In step S324, the driver of the host system 103 connects the third transmission and reception terminal TR3 of the third selector 115, the third interface 113, and the first transmission and reception of the first selector 108 through the host system interface 102. The terminal TR2 accesses the data of the memory storage device 100, that is, the SD-UHS II mode.

In step S326, when it is determined that the memory storage device 100 does not support the operation of the third communication protocol, the memory storage device 100 operates according to the first communication protocol. When the memory storage device 100 operates under the first communication protocol, the second interface 112 of the bridge device 109 triggers the second selector 114 with a second trigger signal TS2, so that the memory storage device interface 101 The first sub-interface 102 a of the host system interface 102 is electrically connected to the first interface 110 through the second interface 112.

In step S328, when the memory storage device 100 operates under the first communication protocol, the first interface 110 of the bridge device 109 generates a first trigger signal TS1 to trigger the first transmission of the first selector 108 The receiving terminal TR1 allows the memory storage device interface 101 to be electrically connected to the second sub-interface 102b of the host system interface 102 through the first transmitting and receiving terminal TR1.

In step S330, the driver of the host system 103 connects the second selector 114, the second interface 112, and the first receiver TR2 of the first selector 108 through the host system interface 102 to access the memory storage The data of the device 100 is in the SD-UHS I mode.

After step S308, if it is determined that the memory storage device 100 does not support the operation of the second communication protocol, step S318 is performed. That is, in step S318, it is determined whether the memory storage device 100 supports the operation of a third communication protocol. If the host system 103 confirms through the host system interface 102 that the third communication protocol of the memory storage device 100 supports the PCIe1.0 protocol version or the PCIe2.0 protocol version of the host system interface 102, the host system interface 102 passes The first transmitting and receiving terminal TR1 of the first selector 108 reads and writes the data of the memory storage device 100.

To sum up, the read-write control system and method of this creation, through the control module of the control device, the first selector and the third selector, make the host system through the first interface, the second interface and the third interface, It can support different communication protocols to read and write the data of the memory storage device, solve the compatibility problem between the memory storage device and the read-write control system, and increase the flexibility of the memory storage device while reducing the read-write control system Production costs.

In a preferred embodiment, the above-mentioned read-write control system and method can switch various access interfaces of the secure digital card by configuring a driver on the same PCIe port, but it is not limited to this.

Although this creation has been disclosed above in the preferred embodiment, it is not used to limit this creation. Those with ordinary knowledge in the technical field to which this creation belongs can make various changes and changes without departing from the spirit and scope of this creation. Retouching, therefore, the protection scope of this creation shall be subject to the scope of the attached patent application.

100: Memory storage device 101: Memory storage device interface 102: Host system interface 102a: The first sub-interface 102b: The second sub-interface 103: host system 104: control device 106: control module 108: First selector 109: Bridge device 110: First interface 112: Second interface 112a: Control interface 112b: Transmission and receiving interface 113: Third Interface 114: second selector 115: third selector 116: Transmission Channel TS1: the first trigger signal TS2: second trigger signal TS3: third trigger signal TR1: First pass and receive end TR2: Second pass and receive end TR3: Third pass and receive end TR4: The fourth pass DAT 0~3: data P1: The first transmission path P2: second transmission path P3: Third transmission path P4: Fourth transmission path P5: fifth transmission path P6: sixth transmission path SD DAT 0~3: Secure digital data SD CMD: Secure Digital Instructions SD CLK: Secure digital clock TX/RX: data transmission/reception PERST#: Quick peripheral component interconnection reset signal CLKREQ#: Clock request operation signal REFCLK+, REFCLK-: reference clock differential pair signal S200, S202, S204, S206, S208, S210, S212, S300, S302, S304, S306, S308, S310, S312, S314, S316, S318, S320, S322, S324, S326, S328, S330: steps

In order to more clearly explain the technical solutions in the creative embodiments, the following will briefly introduce the drawings needed in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the creative. For those with ordinary knowledge in the technical field to which this creation belongs, other drawings can also be obtained from these drawings. Figure 1 is a block diagram of the read-write control system according to this creative embodiment. Figure 2 is a block diagram of the read-write control system according to the first embodiment of the creation. Figure 3 is a block diagram of the read-write control system according to the second embodiment of the invention. Figure 4 is a block diagram of the read-write control system according to the third embodiment of this creation. Figure 5 is a block diagram of the read-write control system in the fourth embodiment according to the invention. Figure 6 is a flowchart showing the method of reading and writing control in the first embodiment of the creation. Figures 7-8 show the flow chart of the method for reading and writing in the second embodiment of the creation.

100: Memory storage device

101: Memory storage device interface

102: Host system interface

102a: The first sub-interface

102b: The second sub-interface

103: host system

104: control device

106: control module

108: First selector

109: Bridge device

110: First interface

112: Second interface

112a: Control interface

112b: Transmission and receiving interface

113: Third Interface

114: second selector

115: third selector

TS1: the first trigger signal

TS2: second trigger signal

TS3: third trigger signal

TR1: First pass and receive end

TR2: Second pass and receive end

TR3: Third pass and receive end

TR4: The fourth pass

DAT 0~3: data

P1: The first transmission path

P2: second transmission path

P3: Third transmission path

P4: Fourth transmission path

P5: fifth transmission path

P6: sixth transmission path

SD DAT 0~3: Secure digital data

SD CMD: Secure Digital Instructions

SD CLK: Secure digital clock

TX/RX: data transmission/reception

PERST#: Quick peripheral component interconnection reset signal

CLKREQ#: Clock request operation signal

REFCLK+, REFCLK-: reference clock differential pair signal

Claims (9)

A read-write control system for a host system to read and write data of a memory storage device, the read-write control system includes: A memory storage device interface for connecting the memory storage device; A host system interface electrically connected to the memory storage device interface, and the host system is connected to the host system interface; and A control device includes a control module and a first selector. The control module is electrically connected to the memory storage device interface, the host system interface and the first selector, and the first selector is electrically connected to the The host system interface, the control module includes: A bridge device electrically connected to the host system interface, the memory storage device interface and the first selector; and A second selector electrically connected to the host system interface, the memory storage device interface and the bridge device; Wherein, the control device further includes a third selector electrically connected to the memory storage device interface, the bridge device and the first selector; Wherein, when the memory storage device operates under a first communication protocol, the memory storage device interface is electrically connected to the host system interface via the second selector, the bridge device, and the first selector; Wherein, when the memory storage device operates with a second communication protocol, the memory storage device interface is electrically connected to the host system interface via the second selector, and the memory storage device interface is also connected via the third The selector and the first selector are electrically connected to the host system interface; Wherein, when the memory storage device operates under a third communication protocol, the memory storage device interface is electrically connected to the host system interface via the second selector and the bridge device, and the memory storage device interface is also The third selector, the bridge device and the first selector are electrically connected to the host system interface. Such as the read-write control system described in item 1 of the scope of patent application, wherein the control device detects that the memory storage device is electrically connected to the memory storage device interface, and presets the first communication protocol and the memory storage The device is connected, and the memory storage device is activated with the first communication protocol. The read-write control system described in item 1 of the scope of patent application, wherein the bridge device includes: A first interface electrically connected to the host system interface and the first selector; A second interface electrically connected to the memory storage device interface, the first interface and the second selector; and A third interface electrically connected to the first interface, the second interface and the third selector; Wherein, when the memory storage device operates under the first communication protocol, the memory storage device interface passes through the second selector, the second interface, and the first interface, and passes through the first selection of the control device The device is electrically connected to the host system interface, wherein the transmission path between the memory storage device interface, the second interface, the first interface and the host system interface is defined as a first transmission path, and the memory storage The transmission path between the device interface, the second selector, the second interface, the first interface, the first selector, and the host system interface is defined as a second transmission path through which the host system transmits The path communicates with the memory storage device interface and reads and writes the data of the memory storage device using the first communication protocol through the second transmission path; Wherein, when the memory storage device operates under the second communication protocol, the memory storage device interface is electrically connected to the host system interface via the second selector, and the memory storage device interface is via the control device The third selector and the first selector are electrically connected to the host system interface, wherein the transmission path between the memory storage device interface, the second selector and the host system interface is defined as a third Transmission path, the transmission path between the memory storage device interface, the third selector, the first selector and the host system interface is defined as a fourth transmission path, so that the host system can communicate with each other through the third transmission path The memory storage device interface communicates and reads and writes the data of the memory storage device through the fourth transmission path using the second communication protocol; Wherein, when the memory storage device operates under the third communication protocol, the memory storage device interface is electrically connected to the host system interface through the second selector, the third interface and the first interface, And the memory storage device interface is electrically connected to the host system interface through the third selector, the third interface, the first interface, and the first selector of the control device, wherein the memory storage device The interface, the second selector, the third interface, the first interface, and the host system interface are defined as a fifth transmission path, the memory storage device interface, the third selector, the third interface, and the first interface , The first selector and the host system interface are defined as a sixth transmission path, so that the host system communicates with the memory storage device interface through the fifth transmission path and uses the third communication through the sixth transmission path The protocol reads and writes the data in the memory storage device. As described in item 3 of the scope of patent application, the host system interface includes a first sub-interface and a second sub-interface, and the first selector includes a first transmitting and receiving terminal and a second transmitting terminal. The receiving end, the third selector includes a third transmitting and receiving end and a fourth transmitting and receiving end; Wherein, when the memory storage device operates under the first communication protocol, the host system generates a first trigger signal through the first interface of the bridge device to trigger the first transmitting and receiving end of the first selector to The memory storage device interface is electrically connected to the second sub-interface of the host system interface through the bridge device and the first transmitting and receiving end, and the memory storage device interface is also through the second selector and the bridge device The first interface and the second interface are electrically connected to the first sub-interface of the host system interface; Wherein, when the memory storage device operates under the second communication protocol, the second interface triggers the second selector with a second trigger signal so that the memory storage device interface is electrically connected through the second selector The first sub-interface is connected to the host system interface, and the host system generates a third trigger signal through the third interface to trigger the fourth transmitting and receiving end of the third selector, and the host system generates through the first interface The first trigger signal triggers the second transmitting and receiving end of the first selector, so that the memory storage device interface is electrically connected to the host system interface through the fourth transmitting and receiving end and the second transmitting and receiving end A second sub-interface, and when the memory storage device operates with the second communication protocol, the host system interface disconnects the first transmitting and receiving end of the first selector; Wherein, when the memory storage device operates under the third communication protocol, the second interface triggers the second selector with a second trigger signal, so that the memory storage device interface passes through the second selector, the The third interface and the first interface are electrically connected to the first sub-interface of the host system interface, and the host system generates the first trigger signal through the first interface to trigger the first transmitting and receiving end of the first selector The host system generates a third trigger signal through the third interface to trigger the third selector, so that the memory storage device interface is electrically connected to the host system through the third transmitting and receiving end and the first transmitting and receiving end The second sub-interface of the interface. The read-write control system described in item 4 of the scope of patent application, wherein the host system communicates with the memory storage device through the host system interface, the first transmitting and receiving end of the first selector, and the second selector To determine whether the memory storage device supports the protocol version of the host system, and the protocol version includes PCIe1.0, PCIe2.0 and PCIe3.0 protocol versions; Wherein, when the host system confirms through the host system interface that the first communication protocol of the memory storage device supports the PCIe 1.0 protocol version or the PCIe 2.0 protocol version of the host system, the host system communicates with the host system through the host system interface The first transmitting and receiving end of the first selector reads and writes the data of the memory storage device; Wherein, when the host system confirms through the host system interface that the second communication protocol of the memory storage device supports the PCIe3.0 protocol version of the host system, the host system communicates with the first selector of the host system through the host system interface. The second transmitting and receiving end and the fourth transmitting and receiving end of the third selector read and write the data of the memory storage device; Wherein, when the host system confirms through the host system interface that the third communication protocol of the memory storage device supports the PCIe 1.0 protocol version or the PCIe 2.0 protocol version of the host system, the host system communicates with the host system through the host system interface The first transmitting and receiving end of the first selector, the first interface, the third interface, and the third transmitting and receiving end of the third selector read and write the data of the memory storage device. Such as the read-write control system described in item 4 of the scope of patent application, wherein when the memory storage device supports the operation of the second communication protocol, a non-volatile memory shortcut (NVMe) protocol driver of the host system passes The host system interface and the second transmitting and receiving end of the first selector access the data of the memory storage device; Wherein, when the second communication protocol of the memory storage device is defined as the SD Express 7.0 or 8.0 mode, the non-volatile memory shortcut (NVMe) protocol driver of the host system passes through the host system interface A transmission and reception channel between the interface with the memory storage device accesses the data of the memory storage device. For the read-write control system described in item 1 of the scope of patent application, the first communication protocol and the third communication protocol of the memory storage device are defined as a secure digital (SD) mode, and the second The communication protocol is defined as a fast and secure digital (SD Express) mode, in which the data transfer rate of the first communication protocol and the third communication protocol of the memory storage device is less than the data transfer rate of the second communication protocol, and the first communication The data transmission rate of the protocol is lower than the data transmission rate of the third communication protocol. A read-write control system for a host system to read and write data of a memory storage device, the read-write control system includes: A first transmission path connected between a memory storage device interface, a bridge device and a host system interface, wherein the memory storage device interface is used to connect the memory storage device; A second transmission path connected between the memory storage device interface, a second selector, the bridge device, a first selector, and the host system interface; A third transmission path connected between the memory storage device interface, the second selector and the host system interface; A fourth transmission path connected between the memory storage device interface, a third selector, the first selector and the host system interface; A fifth transmission path connected between the memory storage device interface, the second selector, the bridge device, and the host system interface; and A sixth transmission path connected between the memory storage device interface, the third selector, the bridge device, the first selector, and the host system interface; Wherein, when the memory storage device operates under the first communication protocol, the host system communicates with the memory storage device interface through the host system interface through the first transmission path and communicates with the memory storage device interface through the second transmission path. A communication protocol to read and write the data of the memory storage device; Wherein, when the memory storage device operates with the second communication protocol, the host system communicates with the memory storage device interface via the host system interface through the third transmission path and communicates with the memory storage device interface through the fourth transmission path. 2. The communication protocol reads and writes the data of the memory storage device; Wherein, when the memory storage device operates under the third communication protocol, the host system communicates with the memory storage device interface via the host system interface through the fifth transmission path and communicates with the memory storage device interface through the sixth transmission path. Three communication protocols read and write the data of the memory storage device. The read-write control system described in claim 8, wherein the host system interface includes a first sub-interface and a second sub-interface, and the bridge device includes a first interface, a second interface, and a third interface , The first selector includes a first transmitting and receiving end and a second transmitting and receiving end, and the third selector includes a third transmitting and receiving end and a fourth transmitting and receiving end; Wherein, when the memory storage device operates under the first communication protocol, the host system generates a first trigger signal through the first interface to trigger the first transmitting and receiving end of the first selector, so that the memory The storage device interface is electrically connected to the second sub-interface of the host system interface through the bridge device and the first transmitting/receiving terminal, and the memory storage device interface is also through the second selector and the first interface of the bridge device The first sub-interface of the host system interface is electrically connected to the second interface; Wherein, when the memory storage device operates under the second communication protocol, the second interface triggers the second selector with a second trigger signal so that the memory storage device interface is electrically connected through the second selector The first sub-interface of the host system interface is connected, and the host system generates a third trigger signal through the third interface to trigger the fourth transmitting and receiving end of the third selector. The host system interface uses the first interface The first trigger signal is generated to trigger the second transmitting and receiving end of the first selector, so that the memory storage device interface is electrically connected to the host system interface through the fourth transmitting and receiving end and the second transmitting and receiving end The second sub-interface; Wherein, when the memory storage device operates under the third communication protocol, the second interface triggers the second selector with a second trigger signal, so that the memory storage device interface passes through the second selector, the The third interface and the first interface are electrically connected to the first sub-interface of the host system interface, and the host system generates the first trigger signal through the first interface to trigger the first transmitting and receiving end of the first selector The host system generates a third trigger signal through the third interface to trigger the third selector, so that the memory storage device interface is electrically connected to the host system through the third transmitting and receiving end and the first transmitting and receiving end The second sub-interface of the interface; Wherein, when the memory storage device operates under the second communication protocol, the host system interface disconnects the first transmitting and receiving end of the first selector, and when the memory storage device operates under the first communication protocol or When the third communication protocol is operating, the host system interface disconnects the second transmitting and receiving end of the first selector.

Images