TWI835126B - Liquid crystal display panel - Google Patents

Abstract

A liquid crystal display (LCD) panel includes a first substrate, a pixel circuit array, a plurality of pixel electrodes, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The pixel circuit array including a plurality of data lines defines a plurality of sub-pixel areas on the first substrate. Two adjacent data lines are distributed in each of the sub-pixel areas. The pixel electrodes are located in the sub-pixel area respectively and electrically connected to the pixel circuit array. In each of the sub-pixel areas, the pixel electrodes and two adjacent data lines overlap. During the display of an image on the LCD panel, the voltages of the two adjacent data lines in each sub-pixel area are different from each other.

Description

LCD panel

The present invention relates to a display, and in particular to a liquid crystal display panel (LCD Panel).

Today, LCD panels have been widely used in many displays, such as computer screens, televisions, and mobile phone screens. Although LCD panels have been widely used, some internal circuits of LCD panels, such as data lines, can interfere with the rotation of liquid crystal molecules and affect the gray scale of pixels, thereby reducing image quality.

At least one embodiment of the present invention provides a liquid crystal display panel to help reduce or avoid interference of data lines on the rotation of liquid crystal molecules, thereby maintaining or improving image quality.

A liquid crystal display panel provided by at least one embodiment of the present invention includes a first substrate, a pixel circuit array, a plurality of pixel electrodes, a second substrate and a liquid crystal layer. The pixel circuit array is disposed on the first substrate and includes a plurality of parallel data lines. The pixel circuit array defines a plurality of sub-pixel areas arranged in an array on the first substrate. A part of each data line is located in one of the sub-pixel areas, and two adjacent data lines are distributed in each sub-pixel area. These pixel electrodes are arranged on the pixel circuit array and are respectively located in the sub-pixel areas, wherein these pixel electrodes are electrically connected to the pixel circuit array. In each sub-pixel area, the pixel electrode overlaps with two adjacent data lines. During the period when the liquid crystal display panel displays an image, the voltages of the two adjacent data lines distributed in each sub-pixel area are different from each other. The liquid crystal layer is disposed between the first substrate and the second substrate.

In at least one embodiment of the present invention, each pixel electrode includes a connecting shaft, a plurality of first ribs and two second ribs. The connecting shaft extends along the first direction. These first ribs and these second ribs are connected to the connecting axis, and these second ribs are connected to the connecting axis and overlap with two adjacent data lines in one of the sub-pixel areas, wherein these first ribs and these second ribs Extending outward from opposite sides of the connecting shaft along the second direction and the opposite direction of the second direction, the slit is formed between adjacent two of the first ribs and the second ribs.

In at least one embodiment of the present invention, at least one first rib is located between the second ribs in the same sub-pixel area.

In at least one embodiment of the present invention, in the same sub-pixel area, the second ribs are located between two of the first ribs.

In at least one embodiment of the present invention, the width of each second rib is greater than the width of each first rib.

In at least one embodiment of the present invention, each pixel electrode further includes two third ribs. The third ribs are connected to the connecting shaft and extend outward from opposite sides of the connecting shaft along the second direction and the opposite direction to the second direction, wherein slits are formed between the first ribs, the second ribs and the third ribs. Three ribs are adjacent to each other.

In at least one embodiment of the present invention, the width of each second rib is greater than the width of each third rib and the width of each first rib.

In at least one embodiment of the present invention, the width of each first rib, the width of each second rib, and the width of each third rib are each greater than the width of the slit.

In at least one embodiment of the present invention, in the overlapping second ribs and data lines, the second ribs protrude from two opposite long sides of the data lines.

In at least one embodiment of the present invention, in the overlapping second ribs and data lines, the distance between the long side of the second rib and the long side of the adjacent data line is between 0.5 microns and 2 microns.

In at least one embodiment of the present invention, the liquid crystal display panel further includes a first linear polarizer and a second linear polarizer. The first linear polarizer is disposed on the first substrate and has a first polarization direction. The second linear polarizer is disposed on the second substrate and has a second polarization direction, wherein the first polarization direction is substantially perpendicular to the second polarization direction, and the first direction is substantially perpendicular to the second direction. The angle between the first polarization direction and the first direction is between 40 degrees and 50 degrees, and the angle between the second polarization direction and the second direction is between 40 degrees and 50 degrees.

In at least one embodiment of the present invention, the pixel circuit array further includes a common electrode pattern. The common electrode pattern is disposed on the first substrate and has a plurality of openings corresponding to the pixel electrodes. During the period when the liquid crystal display panel displays an image, the voltage of the common electrode pattern distributed in one of the sub-pixel areas is different from the voltage of two adjacent data lines.

In at least one embodiment of the present invention, during the period when the liquid crystal display panel displays an image, in one of the sub-pixel areas, the voltage of the common electrode pattern is higher than the voltage of one of the data lines and lower than the voltage of the other data line. .

In at least one embodiment of the present invention, the common electrode pattern includes a plurality of common electrons. These common sub-electrodes are arranged in an array and are respectively located in these sub-pixel areas. Each common sub-electrode includes two parallel electrode strips, and the electrode strips of each common sub-electrode are distributed in one of the sub-pixel areas. and located around one of the openings. Two adjacent data lines are distributed in one of the openings and are located between the electrode strips of the same common sub-electrode.

In at least one embodiment of the present invention, the liquid crystal display panel further includes a common electrode. The common electrode is disposed on the second substrate, the liquid crystal layer is sandwiched between the common electrode and the pixel circuit array, and the liquid crystal layer, the common electrode and the pixel circuit array are all located between the first substrate and the second substrate.

In at least one embodiment of the present invention, the liquid crystal layer is a vertical alignment liquid crystal.

Based on the above, since these pixel electrodes overlap with two adjacent data lines in each sub-pixel area, during the period when the liquid crystal display panel displays an image, even if the two adjacent data lines distributed in each sub-pixel area are The voltages are different from each other. The pixel electrodes can shield the electric field and weaken or eliminate the abnormal electric field caused by the data lines, which helps to reduce or avoid the interference of the data lines on the rotation of liquid crystal molecules, thereby maintaining or improving image quality.

In the following text, in order to clearly present the technical features of this case, the dimensions (such as length, width, thickness and depth) of the components (such as layers, films, substrates, regions, etc.) in the drawings will be exaggerated in varying proportions. . Therefore, the description and explanation of the embodiments below are not limited to the sizes and shapes of the components in the drawings, but should cover the size, shape, and deviations in both caused by actual manufacturing processes and/or tolerances. For example, flat surfaces shown in the drawings may have rough and/or non-linear features, while acute angles shown in the drawings may be rounded. Therefore, the components shown in the drawings of this case are mainly for illustration and are not intended to accurately depict the actual shapes of the components, nor are they intended to limit the patent scope of this case.

Secondly, the words "about", "approximately" or "substantially" appearing in the content of this case not only cover the clearly stated numerical values and numerical ranges, but also cover what can be understood by a person with ordinary knowledge in the technical field to which the invention belongs. The allowable deviation range, where the deviation range can be determined by the error generated during measurement, and this error is caused, for example, by limitations of the measurement system or process conditions. For example, two objects (such as the plane or traces of a substrate) are "substantially parallel" or "substantially perpendicular", where "substantially parallel" and "substantially perpendicular" respectively represent the parallelism and perpendicularity between the two objects. It can include non-parallelism and non-perpendicularity caused by the allowable deviation range.

In addition, "about" may mean within one or more standard deviations of the above numerical value, such as within ±30%, ±20%, ±10%, or ±5%. Words such as "approximately", "approximately" or "substantially" appearing in this text can be used to select acceptable deviation ranges or standard deviations based on optical properties, etching properties, mechanical properties or other properties, and are not solely based on one The standard deviation applies to all the above optical properties, etching properties, mechanical properties and other properties.

1A is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention. Referring to FIG. 1A , the liquid crystal display panel 100 has a plurality of sub-pixel areas SP1 , where the sub-pixel areas SP1 can be regularly arranged, for example, in an array. It should be noted that FIG. 1A is a partial top view of the liquid crystal display panel 100 , in which FIG. 1A depicts four sub-pixel regions SP1 arranged in a 2×2 array as an example. In actual situations, the liquid crystal display panel 100 may have more than four sub-pixel areas SP1, such as thousands or tens of thousands of sub-pixel areas SP1. Therefore, FIG. 1A is only for illustration and does not limit the features of the liquid crystal display panel 100. The number of sub-pixel areas SP1.

The liquid crystal display panel 100 includes a first substrate 111 and a pixel circuit array 120, where the pixel circuit array 120 is disposed on the first substrate 111. The first substrate 111 may be a transparent substrate, such as a glass plate, a sapphire substrate or a transparent plastic plate. The pixel circuit array 120 includes a plurality of parallel data lines 121d and a plurality of parallel scan lines 121s, wherein the scan lines 121s all extend along the first direction D1, and the data lines 121d all extend along the second direction D2.

In FIG. 1A, the first direction D1 may be a horizontal direction, and the second direction D2 may be a vertical direction, so the first direction D1 and the second direction D2 are substantially perpendicular to each other, and the scan line 121s may be along the horizontal direction. The data line 121d may extend along the vertical direction. Therefore, the scan lines 121s can intersect with the data lines 121d.

The liquid crystal display panel 100 further includes a plurality of pixel electrodes 130 , and the pixel circuit array 120 may further include a plurality of control elements 123 . The pixel electrodes 130 are disposed on the pixel circuit array 120 and are electrically connected to the pixel circuit array 120. The scanning lines 121s and the data lines 121d are electrically connected to the control elements 123, and the control elements 123 are electrically connected respectively. These pixel electrodes 130 are connected to control these pixel electrodes 130 .

The pixel electrode 130 may be a transparent conductive layer, which may be made of a metal oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrodes 130 are respectively located in the sub-pixel areas SP1, and a control element 123 and a pixel electrode 130 can be provided in each sub-pixel area SP1, as shown in FIG. 1A. Therefore, these pixel electrodes 130 may also be arranged regularly, for example, in an array. It should be emphasized that since FIG. 1A is a partial top view of the liquid crystal display panel 100 , FIG. 1A only shows a part of the pixel circuit array 120 . In other words, FIG. 1A does not limit the number of pixel electrodes 130, data lines 121d, scanning lines 121s and control elements 123.

These data lines 121d and these scan lines 121s are distributed in these sub-pixel areas SP1, so part of each data line 121d and part of each scan line 121s are located in one of the sub-pixel areas SP1. Taking FIG. 1A as an example, one scan line 121s and two adjacent data lines 121d may be distributed in each sub-pixel area SP1. In each sub-pixel area SP1, the pixel electrode 130 overlaps two adjacent data lines 121d, but the pixel electrode 130 may not overlap the scan line 121s, as shown in the embodiment of FIG. 1A. However, in other embodiments, at least one pixel electrode 130 may overlap with a portion of one of the scan lines 121s to form a storage capacitor (Cst on gate) structured on the scan line.

FIG. 1B is a partial top view of the liquid crystal display panel in FIG. 1A , wherein FIG. 1B depicts a partial top view of the liquid crystal display panel 100 in a single sub-pixel area SP1 , and the liquid crystal display panel 100 shown in FIG. 1B is located in FIG. 1A The upper half of the liquid crystal display panel 100 in . Referring to FIGS. 1A and 1B , the pixel circuit array 120 may further include a common electrode pattern 122 , wherein the common electrode pattern 122 is disposed on the first substrate 111 and has a plurality of openings 122 h corresponding to the pixel electrodes 130 . In other words, the pixel electrodes 130 are respectively located in the openings 122h. Each opening 122h is a closed opening, so these openings 122h are not connected to each other, and one opening 122h is provided in each sub-pixel area SP1.

The common electrode pattern 122 may be a patterned transparent conductive layer, and the pixel electrode 130 and the common electrode pattern 122 may be made of the same material, such as metal oxides such as indium tin oxide (ITO) or indium zinc oxide (IZO). . The common electrode pattern 122 may include a plurality of common sub-electrodes 122p, wherein the common sub-electrodes 122p are respectively located in the sub-pixel areas SP1, and one common sub-electrode 122p is provided in each sub-pixel area SP1.

Each common sub-electrode 122p includes two parallel electrode strips V22, and the electrode strips V22 of each common sub-electrode 122p are distributed in one of the sub-pixel regions SP1 and located around one of the openings 122h. These electrode strips V22 may extend along the second direction D2, so the extending direction of the electrode strips V22 may be the same as the extending direction of the data line 121d. Among the two adjacent common sub-electrodes 122p arranged along the first direction D1, the electrode strip V22 of one common sub-electrode 122p is connected to the electrode strip V22 of the other common sub-electrode 122p. In other words, two adjacent common sub-electrodes 122p arranged along the first direction D1 will be connected to each other.

Each common sub-electrode 122p may also include two connection bars H21 and H22, where both the connection bars H21 and H22 may extend along the first direction D1. The widths of connecting bars H21 and H22 may be different. Taking FIG. 1B as an example, the width of the connecting bar H22 can be greater than the width of the connecting bar H21, that is, the connecting bar H22 can be thicker than the connecting bar H21. In the same common sub-electrode 122p, the connection strips H21, H22 and the electrode strips V22 are connected to each other, so that the connection strips H21, H22 and the electrode strips V22 can surround an opening 122h. Therefore, each common sub-electrode 122p may have a closed opening 122h.

It can be seen from FIG. 1A and FIG. 1B that in the same sub-pixel area SP1, two adjacent data lines 121d are distributed in one of the openings 122h and are located between the electrode strips V22 of the same common sub-electrode 122p. . Secondly, these electrode strips V22, connecting strips H21 and scanning lines 121s are adjacent to the edge of the sub-pixel area SP1. In other words, the common sub-electrodes 122p and the scan lines 121s can determine the size and shape of the sub-pixel areas SP1, so that the pixel circuit array 120 can define the sub-pixel areas SP1 on the first substrate 111.

Each pixel electrode 130 includes a connecting shaft 139 and a plurality of ribs, where the widths of at least two ribs are unequal to each other. Taking FIG. 1B as an example, each pixel electrode 130 may include at least two first ribs 131, at least two second ribs 132, and at least two third ribs 133, wherein the width W2 of each second rib 132 is larger than that of each second rib 132. The width W3 of the third rib 133 is the same as the width W1 of each first rib 131 , and the width W3 of each third rib 133 may be greater than the width W1 of each first rib 131 . Therefore, the ribs of the pixel electrode 130 essentially have three different widths W1, W2, and W3, and the width W2 of the second rib 132 is the maximum width.

In this embodiment, the width W2 of the second rib 132 may be between 9 microns and 10 microns, the width W1 of the first rib 131 may be between 2.5 microns and 4 microns, and the width W3 of the third rib 133 Can be between 5 microns and 8 microns. It can be seen from this that the width W2 of the second rib 132 is the maximum width. In addition, when the width W3 of the third rib 133 is between 5 microns and 8 microns, obvious dark lines can be prevented from appearing in the image displayed by the liquid crystal display panel 100, thereby maintaining or improving image quality.

In each pixel electrode 130, the connecting axis 139 extends along the first direction D1, and the first ribs 131, the second ribs 132 and the third ribs 133 are connected to the connecting axis 139 and extend along the second direction D2. The direction opposite to the second direction D2 extends outward from opposite sides of the connecting shaft 139 . The first ribs 131 , the second ribs 132 and the third ribs 133 in the same pixel electrode 130 are juxtaposed and separated from each other, so among the first ribs 131 , the second ribs 132 and the third ribs 133 A slit S1 will be formed between the two adjacent ones.

In this embodiment, each of the widths W1, W2 and W3 is larger than the width WS1 of the slit S1. Alternatively, each of the widths W2 and W3 is greater than the width WS1 of the slit S1, but the width W1 of the first rib 131 is equal to the width WS1 of the slit S1. For example, the width WS1 of the slit S1 may be within 2.5 microns, such as between 2 microns and 2.5 microns. Alternatively, the width WS1 may be equal to 2 microns or 2.5 microns, and according to the aforementioned range of the width W1, the width W1 of the first rib 131 may also be equal to 2.5 microns.

In the same pixel electrode 130, the first ribs 131, the second ribs 132, the third ribs 133 and the connecting shaft 139 can be formed from the same layer of transparent conductive layer by lithography and etching, so that the first ribs 131 There is no identifiable boundary such as a seam at the connection between each of the second rib 132 and the third rib 133 and the connecting shaft 139 . Therefore, the first ribs 131 , the second ribs 132 , the third ribs 133 and the connecting shaft 139 in the same pixel electrode 130 may be integrally formed into one.

The third ribs 133 respectively overlap with the electrode strips V22 to form a storage capacitor (Cst on common) structured on a common line. In addition, in the same sub-pixel area SP1, the third ribs 133 are adjacent to the edge of the sub-pixel area SP1, so that all the first ribs 131 and all the second ribs 132 are located between the third ribs 133. As shown in Figure 1B.

In the same pixel electrode 130, at least one first rib 131 is located between the second ribs 132. Taking FIG. 1B as an example, four first ribs 131 are located between two second ribs 132 . However, in the same pixel electrode 130 in other embodiments, only one first rib 131 may be located between the second ribs 132 . Therefore, in the same sub-pixel area SP1, the number of first ribs 131 located between the second ribs 132 is not limited to that of FIG. 1A and FIG. 1B.

The two second ribs 132 overlap with the two adjacent data lines 121d in one of the sub-pixel regions SP1, where the two adjacent data lines 121d may be located between the electrode strips V22 of the same common sub-electrode 122p. Therefore, in the same sub-pixel area SP1, these data lines 121d can be located between the two third ribs 133. In particular, the electrode strip V22 will not overlap with any data line 121d to weaken or prevent the parasitic capacitance formed between the electrode strip V22 and the data line 121d, thereby avoiding grayscale distortion caused by insufficient charging of the liquid crystal capacitor. shortcomings.

Figure 1C is a partially enlarged schematic diagram of Figure 1B. Please refer to FIG. 1B and FIG. 1C. Among the overlapping second ribs 132 and the data line 121d, the second ribs 132 protrude from the two opposite long sides L12 of the data line 121d, so that the second ribs 132 completely cover the data. The portion of line 121d located within opening 122h. In addition, due to the influence of the mask shift (PEP Shift), the distance G12 between the long side 132s of the second rib 132 and the long side L12 of the adjacent data line 121d may be between 0.5 microns and 2 microns, such as 1.5 microns to ensure that the second rib 132 completely covers the portion of the data line 121d located within the opening 122h.

FIG. 1D is a schematic cross-sectional view drawn along line 1D-1D in FIG. 1B. Referring to FIG. 1B and FIG. 1D , the liquid crystal display panel 100 further includes a second substrate 112 , a common electrode 140 and a liquid crystal layer 150 , where the liquid crystal layer 150 is disposed between the first substrate 111 and the second substrate 112 . The common electrode 140 is disposed on the second substrate 112 . The liquid crystal layer 150 is sandwiched between the common electrode 140 and the pixel circuit array 120, and the liquid crystal layer 150, the common electrode 140 and the pixel circuit array 120 are all located between the first substrate 111 and the second substrate 112, as shown in Figure 1D Show.

Similar to the first substrate 111, the second substrate 112 can also be a transparent substrate, such as a glass plate, a sapphire substrate or a transparent plastic plate. Similar to the pixel electrode 130 and the common electrode pattern 122, the common electrode 140 can also be a transparent conductive layer, which can be made of the above-mentioned metal oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO). It should be noted that FIGS. 1A to 1C omit the second substrate 112 , the common electrode 140 and the liquid crystal layer 150 to present the wiring structure (layout) of both the pixel circuit array 120 and the pixel electrode 130 .

In the embodiments shown in FIGS. 1B and 1D , the control element 123 may be a transistor, and may be a thin film transistor (TFT) formed by stacking multiple film layers, where FIGS. 1A , 1B and The control element 123 shown in FIG. 1D can not only be a thin film transistor, but also a field-effect transistor (Field-Effect Transistor, FET).

Specifically, each control element 123 includes a gate 123g, a channel layer 123c, a source 123s and a drain 123d, and the pixel circuit array 120 may also include an insulating layer 124. The gate 123g and the insulating layer 124 are both formed on the first substrate 111. The insulating layer 124 completely covers the upper surface of the first substrate 111 and the gate 123g. The channel layer 123c is formed on the insulating layer 124 and is connected with the gate. Extremely 123g overlap.

The channel layer 123c may be a semiconductor layer, and its constituent material is, for example, silicon or Indium Gallium Zinc Oxide (IGZO). The insulating layer 124 is located between the gate electrode 123g and the channel layer 123c, and separates the gate electrode 123g and the channel layer 123c, so that the gate electrode 123g, the channel layer 123c and the portion sandwiched between the gate electrode 123g and the channel layer 123c Insulating layer 124 may form a capacitor.

The source electrode 123s and the drain electrode 123d are formed on the insulating layer 124 and the channel layer 123c, where both the source electrode 123s and the drain electrode 123d are electrically connected to the channel layer 123c. In addition, the pixel circuit array 120 may further include an insulating layer 126, where the insulating layer 126 is formed on the insulating layer 124 and covers the source electrode 123s, the drain electrode 123d and the channel layer 123c. The insulating layer 126 has a plurality of contact windows H11 , where the contact windows H11 are through holes formed in the insulating layer 126 .

The contact windows H11 are respectively located above the drain electrodes 123d, and the insulating layer 126 does not cover the portion of the drain electrodes 123d located at the bottom of the contact windows H11. The pixel electrode 130 is formed on the insulating layer 126 and extends from the upper surface of the insulating layer 126 into the contact window H11 so that the pixel electrode 130 is electrically connected to the drain electrode 123d located at the bottom of the contact window H11. In this way, the control element 123 is electrically connected to the pixel electrode 130 to control the pixel electrode 130 .

The gates 123g and the scan lines 121s can be formed by lithography and etching from one metal layer, and the sources 123s and the data lines 121d can be formed from another metal layer by lithography and etching. The gates 123g are electrically connected to the scan lines 121s, and the sources 123s are electrically connected to the data lines 121d. Therefore, these scan lines 121s can turn on and off these control elements 123, so that the pixel voltage can be input to the source 123s of the control element 123 through the data line 121d. When the control element 123 is turned on, the pixel voltage is transmitted from the source electrode 123s through the channel layer 123c to the drain electrode 123d. In this way, the pixel voltage transmitted by the data line 121d can be input to the pixel electrode 130 through the control element 123.

Please refer to FIG. 1A. It is particularly worth mentioning that in the liquid crystal display panel 100 shown in FIG. 1A, the same scan line 121s only connects the multiple control elements 123 in one of the sub-pixel regions SP1. Therefore, each scan line 121s can turn on and off a plurality of control elements 123 in one of the column-sub-pixel regions SP1, so that these data lines 121d can only input pixel voltages to a plurality of pixel electrodes 130 in one of the column-sub-pixel regions SP1.

Referring to FIG. 1B and FIG. 1D , the liquid crystal display panel 100 may also include a plurality of filter layers 171 (only one is shown in FIG. 1D ) and a black matrix 172 , wherein the black matrix 172 and these filter layers 171 are disposed on the second substrate. 112, and the common electrode 140 can cover the black matrix 172 and these filter layers 171. The shape of the black matrix 172 can be a mesh, and has a plurality of grids (not labeled), and the filter layers 171 are respectively arranged in the grids of the black matrix 172, so that the filter layers 171 can be arranged in an array. .

These filter layers 171 can filter light to produce multiple colors of light, such as blue light, green light and red light, so these filter layers 171 can be blue light, green light and red light filter layers. The filter layers 171 can be respectively aligned with the pixel electrodes 130 located in the sub-pixel area SP1, so that the light passing through the pixel electrodes 130 can be incident on the filter layers 171. Therefore, the filter layer 171, the black matrix 172, the second substrate 112 and the common electrode 140 can form a color filter substrate, and multiple colors of light, such as blue light, green light and red light, can be emitted from the filter layers 171 respectively.

It is particularly noted that the control element 123 shown in FIG. 1A, FIG. 1B and FIG. 1D is a bottom-gate thin film transistor (bottom-gate TFT) as an example. However, in other embodiments, the control element 123 may also be a top-gate thin film transistor (top-gate TFT). Therefore, the control element 123 shown in FIG. 1A , FIG. 1B and FIG. 1D is only for illustration and does not limit the type of the control element 123 .

The liquid crystal display panel 100 may further include a first linear polarizer 191 and a second linear polarizer 192, wherein the first linear polarizer 191 is disposed on the first substrate 111, and the second linear polarizer 192 is disposed on the second substrate 112. . 1D, the first substrate 111 is located between the first linear polarizing plate 191 and the pixel circuit array 120, and the second substrate 112 is located between the second linear polarizing plate 192 and the common electrode 140, where the first substrate 111 and the second substrate 112 may both be located between the first linear polarizing plate 191 and the second linear polarizing plate 192, as shown in FIG. 1D.

When the data line 121d inputs the pixel voltage to the pixel electrode 130, the pixel electrode 130 can rotate the liquid crystal molecules in the liquid crystal layer 150, so that the liquid crystal layer 150 can change the polarization state of the light. Therefore, by utilizing the liquid crystal layer 150 and combining the first linear polarizing plate 191 and the second linear polarizing plate 192, the pixel voltage input to the pixel electrode 130 can change the light transmittance of the sub-pixel area SP1, thereby changing the light transmittance through The intensity of the light behind the first linear polarizer 191, the liquid crystal layer 150 and the second linear polarizer 192. In this way, adjusting the pixel voltage can control the intensity of light incident on the filter layer 171 to generate different grayscale colored lights (such as blue light, green light, and red light), thereby generating an image.

In particular, the common electrode 140 disposed on the second substrate 112 faces the pixel electrodes 130 , and the liquid crystal layer 150 is located between the common electrode 140 and the pixel electrodes 130 . When a pixel voltage is input to the pixel electrode 130, an electric field will be generated between the common electrode 140 and the pixel electrode 130, and its direction will be substantially perpendicular to the first substrate 111. For example, the direction of the electric field will be substantially parallel to the third direction D3 in FIG. 1D , where the third direction D3 is substantially perpendicular to the upper surface of the first substrate 111 .

The above-mentioned electric field parallel to the third direction D3 can rotate the liquid crystal molecules in the liquid crystal layer 150 to change the light transmittance of the liquid crystal display panel 100 in each sub-pixel area SP1, and adjust the input of the data line 121d to the pixel electrode 130 The pixel voltage can change the intensity of the electric field, so that the gray scale value of the sub-pixel area SP1 can be controlled, thereby enabling the liquid crystal display panel 100 to display images. In addition, in this embodiment, the liquid crystal layer 150 may be a vertical alignment liquid crystal, but other embodiments may use other types of liquid crystal materials as the liquid crystal layer 150, and the liquid crystal layer 150 is not limited to only vertical alignment liquid crystal.

FIG. 1E is a schematic diagram of the polarization directions of the first linear polarizing plate and the second linear polarizing plate in FIG. 1D. Please refer to FIG. 1D and FIG. 1E. The liquid crystal display panel 100 in FIG. 1E is drawn along the top view direction. Therefore, the liquid crystal display panel 100 in FIG. 1A, FIG. 1B, FIG. 1C and FIG. 1E are all drawn along the same direction (i.e. Looking down direction) and drawing. Therefore, the first direction D1 in Figure 1E is the same as the first direction D1 in Figures 1A to 1C (both from left to right), and the second direction D2 in Figure 1E is the same as the first direction D2 in Figures 1A to 1C The second direction is D2 (both from top to bottom).

The first linear polarizer 191 has a first polarization direction D91, and the second linear polarizer 192 has a second polarization direction D92, wherein the first polarization direction D91 and the second polarization direction D92 are substantially perpendicular. Therefore, when the liquid crystal display panel 100 does not have the liquid crystal layer 150 , the light penetrating the first linear polarizer 191 and the first substrate 111 will be blocked by the second linear polarizer 192 . In the same way, the light passing through the second linear polarizer 192 and the second substrate 112 will also be blocked by the first linear polarizer 191 .

The first polarization direction D91 and the second polarization direction D92 are both different from the first direction D1 or the second direction D2, so the first polarization direction D91 and the second polarization direction D92 will each form an angle with the first direction D1 or the second direction D2. . Taking FIG. 1E as an example, an included angle A1 can be formed between the first polarization direction D91 and the first direction D1, which can be between 40 degrees and 50 degrees, wherein the included angle A1 is preferably 45 degrees. The second polarization direction D92 and the second direction D2 can form an included angle A2, which can be between 40 degrees and 50 degrees, wherein the included angle A2 is preferably 45 degrees.

Since the first direction D1 and the second direction D2 are substantially perpendicular, and the first polarization direction D91 and the second polarization direction D92 are substantially perpendicular, the included angle A1 and the included angle A2 may be substantially equal to each other. In addition, under the condition that the included angle A1 and the included angle A2 are both substantially 45 degrees, the included angle A1 can be substantially equal to the included angle between the first polarization direction D91 and the second direction D2, and the included angle A2 can be substantially equal to the second polarization direction. The angle between D92 and the first direction D1, where both the first polarization direction D91 and the second polarization direction D92 can be regarded as the angular bisector between the first direction D1 and the second direction D2, as shown in FIG. 1E.

Referring to FIGS. 1B and 1D , since the first rib 131 , the second rib 132 and the third rib 133 extend outward from opposite sides of the connecting shaft 139 along the second direction D2 and the opposite direction of the second direction D2 , Therefore, the pixel electrode 130 receiving the pixel voltage will generate different electric fields, so that the liquid crystal molecules in the liquid crystal layer 150 can tilt along the second direction D2 and the opposite direction of the second direction D2.

Taking FIG. 1B as an example, when the pixel voltage is input to the pixel electrode 130, a plurality of first ribs 131, second ribs 132 and third ribs 133 located on one side of the connecting axis 139 (for example, located on the connecting axis in FIG. 1B The liquid crystal molecules above the first rib 131, the second rib 132 and the third rib 133) on the upper side of the connecting axis 139 will pour along the second direction D2, while the other first ribs 131 and the second rib 132 on the other side of the connecting axis 139 The liquid crystal molecules above the third rib 133 (for example, the first rib 131 , the second rib 132 and the third rib 133 located below the connecting shaft 139 in FIG. 1B ) will tilt in the opposite direction of the second direction D2 .

In this way, each pixel electrode 130 can generate a dual domain, so that the image displayed on the liquid crystal display panel 100 is not easily changed significantly by the change of viewing angle, so that the image quality of the liquid crystal display panel 100 is not easily affected by the viewer's The viewing angle changes, thereby maintaining or improving the image quality of the liquid crystal display panel 100 .

Please refer to FIG. 1A, FIG. 1B and FIG. 1D. These data lines 121d can alternately input pixel voltages of the same polarity to the pixel electrodes 130, in which the liquid crystal display panel 100 can adopt column inversion or column inversion. The dot inversion mode (dot inversion) driver is used to display the image, but the frame inversion mode (frame inversion) is not used. Additionally, polarity may be equivalent to voltage.

In this embodiment, when the data lines 121d arranged in odd-numbered rows input relatively high pixel voltages to the plurality of pixel electrodes 130, the data lines 121d arranged in even-numbered rows input relatively low pixel voltages to other pixel electrodes 130. 130. On the contrary, when the data lines 121d arranged in odd-numbered rows input relatively low pixel voltages to multiple pixel electrodes 130, the data lines 121d arranged in even-numbered rows input relatively high pixel voltages to other pixel electrodes 130. The above-mentioned low and high pixel voltages are based on the common voltage (common voltage). The high pixel voltage is higher than the common voltage, while the low pixel voltage is lower than the common voltage. In addition, a high pixel voltage represents a positive polarity, while a low pixel voltage represents a negative polarity.

Therefore, during the period when the liquid crystal display panel 100 displays an image, the voltages of the two adjacent data lines 121d distributed in each sub-pixel area SP1 are different from each other, and the common electrode pattern 122 distributed in one of the sub-pixel areas SP1 The voltage (ie, the common voltage) will be different from the voltage of the two adjacent data lines 121d. For example, while the liquid crystal display panel 100 displays an image, in one of the sub-pixel regions SP1, the voltage of the common electrode pattern 122 will be higher than the voltage of one of the data lines 121d, but lower than the voltage of the other data line 121d.

When the liquid crystal display panel 100 displays an image, the voltages of the two adjacent data lines 121d distributed in each sub-pixel area SP1 are different from each other. Therefore, when the liquid crystal display panel 100 displays an image, the voltages of the two adjacent data lines 121d in each sub-pixel area SP1 are different. , the polarity of one of the data lines 121d will be the same as the polarity of the pixel electrode 130, but the polarity of the other data line 121d is different from the polarity of the pixel electrode 130. For example, in the same sub-pixel area SP1, the polarity of one data line 121d and the polarity of the pixel electrode 130 are both positive, but the polarity of the other data line 121d is negative.

If no conductor is provided between the common electrode 140 and each data line 121d on the second substrate 112 to shield the electric field, an abnormal electric field will be generated between the common electrode 140 and the data line 121d with a polarity different from that of the pixel electrode 130, and This abnormal electric field will interfere with the rotation of liquid crystal molecules in the liquid crystal layer 150 and cause grayscale distortion, thus reducing image quality.

However, since the second ribs 132 respectively overlap with the data lines 121d in each sub-pixel area SP1 and completely cover the portion of the data lines 121d located in the opening 122h, the second ribs 132 can shield the electric field, so as to The above-mentioned abnormal electric field is weakened or eliminated so that the liquid crystal molecules in the liquid crystal layer 150 can be driven by the normal electric field to rotate, thereby maintaining or improving image quality.

Referring to FIG. 1A , it is worth mentioning that a plurality of control elements 123 arranged in two adjacent rows along the first direction D1 are electrically connected to two adjacent data lines 121d respectively. Specifically, among the plurality of control elements 123 arranged in two adjacent columns along the first direction D1, each of the plurality of control elements 123 in one column is electrically connected to the data line 121d ( Like the two control elements 123 located at the top in Figure 1A), the other control elements 123 arranged in another column are each electrically connected to the data line 121d on the left side of the adjacent sub-pixel area SP1 (the two control elements 123 located at the bottom in Figure 1A). control element 123). In this way, a plurality of control elements 123 arranged in the same column along the second direction D2 can alternately electrically connect two adjacent data lines 121d.

During the period when the liquid crystal display panel 100 displays an image, the data lines 121d alternately output high and low pixel voltages to the pixel electrodes 130. Taking Figure 1A as an example, counting from left to right, the first and third data lines 121d will output a positive polarity (ie, high voltage) pixel voltage, while the second and fourth data lines 121d will output a negative polarity. The polarity of the pixel electrode 130 in the pixel area SP1 of the previous column is negative (the two pixel electrodes 130 located above in Figure 1A), and then the polarity of the pixel electrode 130 in the pixel area SP1 of the previous column is negative. The polarity of the pixel electrodes 130 in the pixel area SP1 is positive (the two pixel electrodes 130 located below in FIG. 1A ).

FIG. 2A is a partial top view schematic diagram of a liquid crystal display panel of another embodiment of the present invention, wherein the liquid crystal display panel 200a shown in FIG. 2A has a plurality of sub-pixel regions (not labeled), and FIG. 2A depicts a partial top view schematic diagram of the liquid crystal display panel 200a in a single sub-pixel region. Referring to FIG. 2A , the liquid crystal display panel 200a is similar to the aforementioned liquid crystal display panel 100, wherein the liquid crystal display panels 200a and 100 both include the same components, such as the first substrate 111 and the pixel circuit array 120, and the cross-sectional structures of the liquid crystal display panels 200a and 100 are substantially the same, that is, the liquid crystal display panel 200a has a cross-sectional structure substantially the same as that shown in FIG. 1D . The following mainly describes the differences between the liquid crystal display panels 200a and 100, and the same features of the two are basically not repeated and are not shown in the drawings.

The liquid crystal display panel 200a includes a plurality of pixel electrodes 230a, wherein these pixel electrodes 230a are arranged on the pixel circuit array 120 and are electrically connected to the drains 123d of a plurality of control elements 123 (not shown in Figure 2A), and each pixel electrode 230a is The element electrode 230a also includes a connecting shaft 139 and a plurality of ribs, wherein the ribs include at least two first ribs 131 and at least two second ribs 232, and two of the first ribs 131 and the second ribs 232 are adjacent. A slit S1 is also formed between them, as shown in Figure 2A.

Different from the pixel electrode 130, the ribs of each pixel electrode 230a essentially have two different widths. Specifically, the width W2a of each second rib 232 is greater than the width W1 of each first rib 131, so that the first rib 131 and the second rib 232 essentially have two different widths W1 and W2a respectively. Therefore, compared with the aforementioned pixel electrode 130, the pixel electrode 230a does not include the third rib 133 with the width W3. Furthermore, the width W2a may be greater than the width WS1 of the slit S1, and the width W1 may be greater than or equal to the width WS1.

In the embodiment shown in FIG. 2A , the first ribs 131 are located between the second ribs 232 , where the second ribs 232 not only overlap two adjacent data lines 121d in one of the sub-pixel regions, but also Moreover, it also overlaps with these electrode strips V22 in this pixel area, so each second rib 232 further overlaps with the slit S2 located between the adjacent data line 121d and the electrode strip V22. In other words, each second rib 232 not only completely covers the portion of the data line 121d located within the opening 122h, but also covers the slit S2 adjacent to the data line 121d, as shown in FIG. 2A.

Among the overlapping second ribs 232 and the data line 121d, the second ribs 232 also protrude from the two opposite long sides (not labeled) of the data line 121d, so that the second ribs 232 completely cover the data lines 121d in the opening. The part within 122h. Since the second rib 232 covers the slit S2, the distance between one long side (not labeled) of the second rib 232 and its adjacent long side of the data line 121d will be smaller than the other long side of the second rib 232 and its adjacent long side. The distance between the long sides of data line 121d.

In other words, there is a maximum distance and a minimum distance respectively between the two opposite long sides of the second rib 232 and the two opposite long sides of the adjacent data line 121d, where the minimum distance may be equal to the distance G12 shown in FIG. 1C, where It can be between 0.5 micron and 2 micron, such as 1.5 micron. The maximum distance includes the width of slit S2, which may be equal to width WS1. In this way, the second ribs 232 completely cover the portion of the data lines 121d located in the opening 122h, so that the liquid crystal molecules can be driven by the normal electric field to rotate, thereby maintaining or improving the image quality.

FIG. 2B is a partial top view of a liquid crystal display panel according to another embodiment of the present invention. The liquid crystal display panel 200b shown in FIG. 2B has multiple sub-pixel areas (not labeled), and FIG. 2B depicts the liquid crystal display panel 200b in a single A partial top-down view of a sub-pixel area. Referring to FIG. 2B , the liquid crystal display panel 200b is similar to the aforementioned liquid crystal display panel 100 , wherein both the liquid crystal display panels 200b and 100 include the same or similar components.

For example, both the liquid crystal display panels 200b and 100 include a first substrate 111, a pixel circuit array 220 and a plurality of pixel electrodes 230b, and the cross-sectional structures of the liquid crystal display panels 200a and 100 are substantially the same. Therefore, the same features of the liquid crystal display panels 200b and 100 will not be repeatedly described or shown in the drawings. The following mainly describes the differences between the liquid crystal display panels 200b and 100.

The pixel circuit array 220 includes a common electrode pattern 122 and a plurality of data lines 221d, where the data lines 221d are similar to the data lines 121d. However, different from the aforementioned pixel circuit array 120, in the same opening 122h of the liquid crystal display panel 200b, the distance between two adjacent data lines 221d is shorter, and the distance between the adjacent data lines 121d and the electrode strip V22 is The distance between them is longer, as shown in Figure 2B.

Each pixel electrode 230b includes a connecting shaft 139, at least two first ribs 131, at least two second ribs 132, and at least two third ribs 133. In the same sub-pixel area, the second ribs 132 overlap with the two adjacent data lines 221d, and the third ribs 133 respectively overlap with the electrode strips V22, wherein the second ribs 132 completely cover the data lines 221d. The portion located within the opening 122h allows the liquid crystal molecules to rotate driven by the normal electric field, thereby maintaining or improving image quality.

Different from the aforementioned pixel electrode 130, since the distance between two adjacent data lines 221d is shorter, and the distance between the adjacent data line 121d and the electrode strip V22 is longer, the liquid crystal display panel 200b has In a sub-pixel area, these second ribs 132 can be located between two of the first ribs 131, and at least one first rib 131 can be located between the adjacent second ribs 132 and third ribs 133, as shown in Figure As shown in 2B.

FIG. 3 is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention, and is a partial top schematic view of the liquid crystal display panel 300 . The liquid crystal display panel 300 also has a plurality of sub-pixel areas SP1, and FIG. 3 depicts four sub-pixel areas SP1 arranged in a 2×2 array as an example. Referring to FIG. 3 , the liquid crystal display panel 300 is similar to the aforementioned liquid crystal display panel 100 . The liquid crystal display panels 300 and 100 include the same components, such as the first substrate 111 and a plurality of pixel electrodes 130 , and the liquid crystal display panel 300 and the liquid crystal display panel 100 include the same components. 100The cross-sectional structures of the two are roughly the same.

Basically, the same features of the liquid crystal display panels 300 and 100 will not be repeatedly described or shown in the drawings. The following mainly describes the differences between the liquid crystal display panels 300 and 100 . Specifically, the liquid crystal display panel 300 includes a pixel circuit array 320, where the pixel circuit array 320 is similar to the aforementioned pixel circuit array 120 and includes a common electrode pattern 122, a plurality of data lines 121d, a plurality of scan lines 121s and a plurality of control element 123. The only difference between the pixel circuit arrays 320 and 120 is the electrical connection between the control elements 123 and the data lines 121d.

In the embodiment shown in FIG. 3 , a plurality of control elements 123 arranged in the same row along the second direction D2 alternately electrically connect two adjacent data lines 121d and are arranged among them along the first direction D1 A plurality of control elements 123 in a row are also electrically connected to the data lines 121d in turn. Taking FIG. 3 as an example, among the control elements 123 arranged in the upper row along the first direction D1, the control element 123 located at the upper left is electrically connected to the leftmost data line 121d, while the control element 123 located at the upper right is electrically connected. The rightmost data line 121d is electrically connected, but these control elements 123 are not electrically connected to the middle two data lines 121d.

Based on the above, among the control elements 123 arranged in the lower row along the first direction D1, the control element 123 located at the lower left is electrically connected to the data line 121d in the middle left, while the control element 123 located at the lower right is electrically connected. The data lines 121d on the right side of the center, but these control elements 123 are not electrically connected to the two outermost data lines 121d in Figure 3 . It can be seen from this that multiple control elements 123 in the same row are alternately electrically connected to two adjacent data lines 121d, and multiple control elements 123 in the same column are also alternately electrically connected to these data lines 121d.

The driving modes of the liquid crystal display panels 300 and 100 may be the same. For example, the liquid crystal display panel 300 can also be driven by a row inversion method or a dot inversion method to display images, but the frame inversion method is not used. In addition, during the period when the liquid crystal display panel 300 displays an image, the data lines 121d will alternately output high and low pixel voltages to the pixel electrodes 130.

Taking Figure 3 as an example, counting from left to right, the first and third data lines 121d will output a positive polarity (ie, high voltage) pixel voltage, while the second and fourth data lines 121d will output a negative polarity. (i.e., the voltage is low), so that the polarities of two adjacent pixel electrodes 130 arranged in the same column of pixel areas SP1 along the first direction D1 are opposite to each other, and the polarities of the two adjacent pixel electrodes 130 are opposite to each other along the second direction D1. D2 The polarities of two adjacent pixel electrodes 130 arranged in the same row of pixel areas SP1 are also opposite to each other, as shown in FIG. 3 .

It is worth mentioning that the pixel electrodes 230a and 230b shown in FIGS. 2A and 2B can also be applied to the liquid crystal display panels 100 and 300 in FIGS. 1A and 3 . Specifically, in the liquid crystal display panels 100 and 300 shown in FIG. 1A and FIG. 3 , the pixel electrodes 130 of the liquid crystal display panels 100 and 300 can be replaced with the pixel electrode 230a in FIG. 2A . Alternatively, in FIGS. 1A and 3 , the pixel circuit arrays 120 and 320 and each pixel electrode 130 can be replaced with the pixel circuit array 220 and the pixel electrode 230b in FIG. 2B respectively. Therefore, both the liquid crystal display panels 100 and 300 can also use the pixel electrodes 230a and 230b and the pixel circuit array 220 shown in FIG. 2A and FIG. 2B.

FIG. 4A is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention, and is a partial top schematic view of the liquid crystal display panel 400a. Please refer to FIG. 4A . The liquid crystal display panel 400 a has a plurality of sub-pixel areas SP4 . FIG. 4A depicts eight sub-pixel areas SP4 arranged in a 2×4 array as an example. The liquid crystal display panel 400a is similar to the aforementioned liquid crystal display panel 100, wherein the cross-sectional structures of the liquid crystal display panels 400a and 100 are substantially the same. The following mainly describes the differences between the liquid crystal display panels 400a and 100. Basically, the same features of the liquid crystal display panels 400a and 100 will not be repeated or shown in the drawings.

The liquid crystal display panel 400a includes a first substrate 111, a pixel circuit array 420a, and a plurality of pixel electrodes 430. The pixel circuit array 420a and the pixel electrodes 430 are both disposed on the first substrate 111, and the pixel electrodes 430 Electrically connected to the pixel circuit array 420a. The pixel circuit array 420a includes a plurality of data lines 121d, a plurality of scanning lines 421s, a plurality of control elements 123 and a common electrode pattern 422.

Different from the aforementioned pixel circuit array 120, in the embodiment shown in FIG. 4A, the same scanning line 421s is electrically connected to a plurality of control elements 123 in two adjacent columns of sub-pixel areas SP4, so that adjacent Multiple control elements 123 in two columns of sub-pixel areas SP4 can share one scan line 421s. Therefore, each scan line 421s can turn on and off a plurality of control elements 123 in two adjacent columns of sub-pixel areas SP4, thereby controlling these data lines 121d to input pixel voltages to two adjacent columns of sub-pixel areas SP4. A plurality of pixel electrodes 430. Compared with the pixel circuit array 120, the pixel circuit array 420a may have a smaller number of scan lines 421s to help improve the aperture ratio.

In addition, in the sub-pixel areas SP4 arranged in the same row, the pixel electrode 430 located in the sub-pixel area SP4 of the odd-numbered column is electrically connected to one of the data lines 121d, and the pixel electrode 430 located in the sub-pixel area SP4 of the even-numbered column is electrically connected to one of the data lines 121d. The pixel electrode 430 is electrically connected to another data line 121d. Taking FIG. 4A as an example, in the sub-pixel area SP4 arranged in the same row along the second direction D2, the first and third pixel electrodes 430 from the top are electrically connected to the data line 121d on the left, and The second and fourth pixel electrodes 430 are electrically connected to the right data line 121d.

Based on the above, during the period when the liquid crystal display panel 400a displays an image, the data lines 121d will alternately output high and low pixel voltages to the pixel electrodes 430. Taking FIG4A as an example, from left to right, the first and third data lines 121d will output positive (i.e., high) pixel voltages, and the second and fourth data lines 121d will output negative (i.e., low) pixel voltages, so that from the top, the polarities of the first and third rows of pixel electrodes 430 are positive, and the polarities of the second and fourth rows of pixel electrodes 430 are negative, as shown in FIG4A.

The pixel electrode 430 also includes a plurality of ribs with different widths extending along the second direction D2, such as a second rib (not labeled) that completely covers the data line 121d and has the thickest width, and a third rib that overlaps the common electrode pattern 422. Three ribs (not labeled) and a first rib (not labeled) that does not overlap the data line 121d and the common electrode pattern 422 and has the smallest width. However, different from the aforementioned pixel electrode 130, each pixel electrode 430 also includes a connecting rib 438, where the connecting rib 438 can extend along the first direction D1, so the extending direction of the connecting rib 438 and each rib is perpendicular. In the same pixel electrode 430, the connecting ribs 438 connect these ribs and electrically connect the control element 123, as shown in FIG. 4A.

The common electrode pattern 422 may include a plurality of common sub-electrodes 422p, wherein the common sub-electrodes 422p are arranged in an array and are respectively located in the sub-pixel areas SP4, that is, one common sub-electrode 422p is provided in each sub-pixel area SP4. Each common sub-electrode 422p also has an opening 422h, wherein the openings 422h are respectively located in the sub-pixel regions SP4, and the pixel electrodes 430 are respectively located in the openings 422h.

The common electrode pattern 422 is different from the common electrode pattern 122 of the previous embodiment. Specifically, the opening 422h is an open opening, and the shape of each common sub-electrode 422p may be U-shaped. In the sub-pixel area SP4 arranged in the same row along the second direction D2, two adjacent common sub-electrodes 422p and two adjacent pixel electrodes 430 are located between two adjacent scanning lines 421s. The openings 422h of two adjacent common sub-electrodes 422p are connected to each other to form a large-sized opening, wherein the large-sized opening can be distributed in two adjacent sub-pixel areas SP4 in the same row, and the aforementioned two adjacent pixels Electrodes 430 are distributed within this large-sized opening, as shown in Figure 4A.

FIG. 4B is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention, and is a partial top schematic view of the liquid crystal display panel 400b. Please refer to FIG. 4B. The liquid crystal display panel 400b also has a plurality of sub-pixel areas SP4. FIG. 4B also depicts eight sub-pixel areas SP4 arranged in a 2×4 array as an example.

The liquid crystal display panel 400b is similar to the aforementioned liquid crystal display panel 400a, in which the cross-sectional structures of the liquid crystal display panels 400a and 400b are substantially the same. That is, the liquid crystal display panel 400b has substantially the same cross-sectional structure as shown in FIG. 1D. The only difference between the liquid crystal display panels 400a and 400b is that the pixel circuit array 420b included in the liquid crystal display panel 400b is different from the pixel circuit array 420a.

Specifically, unlike the pixel circuit array 420a, in the embodiment of FIG. 4B, in the sub-pixel area SP4 arranged in the same row along the second direction D2, the two adjacent scan lines 421s are Each pixel electrode 430 is electrically connected to the same data line 121d, and the two pixel electrodes 430 located on opposite sides of any scanning line 421s are electrically connected to two different data lines 121d respectively. Taking FIG. 4B as an example, in the sub-pixel area SP4 arranged in the same row along the second direction D2, the two pixel electrodes 430 located on opposite sides of the upper scan line 421s are electrically connected to two different data lines respectively. 121d, in which the pixel electrode 430 located above the scan line 421s is electrically connected to the data line 121d on the left, and the pixel electrode 430 located below the scan line 421s is electrically connected to the data line 121d on the right.

Secondly, in the embodiment of FIG. 4B , the two pixel electrodes 430 located on opposite sides of the lower scan line 421s are also electrically connected to two different data lines 121d respectively. The pixel electrode 430 located above the scan line 421s is also electrically connected to two different data lines 121d. The data line 121d on the right is electrically connected, and the pixel electrode 430 located below the scan line 421s is electrically connected to the data line 121d on the left. In this way, the two pixel electrodes 430 located between the two adjacent scan lines 421s are electrically connected to the right data line 121d, as shown in FIG. 4B.

During the period when the liquid crystal display panel 400b displays an image, the data lines 121d alternately output high and low pixel voltages to the pixel electrodes 430. Taking Figure 4B as an example, counting from left to right, the first and third data lines 121d will output positive pixel voltages, while the second and fourth data lines 121d will output negative polarity pixel voltages. Counting from above, the polarity of the pixel electrodes 430 in the first and fourth columns is positive, and the polarity of the pixel electrodes 430 in the second and third columns is negative.

It should be noted that in the above embodiments shown in FIGS. 4A and 4B , the ribs of the pixel electrode 430 can actually have three different widths (such as the widths W1, W2, and W3 shown in FIG. 1B), but In other embodiments, the ribs of the pixel electrode 430 may actually have only two different widths, like the pixel electrode 230a shown in FIG. 2A .

Secondly, the liquid crystal display panels 400a and 400b shown in FIGS. 4A and 4B can also use the data lines 221d and pixel electrodes 230b shown in FIG. 2B. That is to say, the data line 121d and the pixel electrode 430 in FIG. 4A and FIG. 4B can be replaced by the data line 221d and the pixel electrode 230b shown in FIG. 2B respectively. Therefore, the embodiments disclosed in FIGS. 4A and 4B can also use the components shown in the previous embodiments, such as the pixel electrodes 230a, 230b and the data line 221d.

FIG. 5A is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention, and is a partial top schematic view of the liquid crystal display panel 500a. Please refer to FIG. 5A. The liquid crystal display panel 500a also has a plurality of sub-pixel areas SP5, and FIG. 5A depicts four sub-pixel areas SP5 arranged in a 2×2 array as an example. The liquid crystal display panel 500a is similar to the aforementioned liquid crystal display panel 400a. For example, the cross-sectional structures of the two are substantially the same. The following mainly describes the differences between the liquid crystal display panels 500a and 400a, and basically the same features between the two will not be repeatedly described.

The liquid crystal display panel 500a includes a pixel circuit array 520a and a plurality of pixel electrodes 531 and 532, wherein these pixel electrodes 531 and 532 are electrically connected to the pixel circuit array 520a. Different from the aforementioned liquid crystal display panel 400a, in this embodiment, two control elements 123 and two pixel electrodes 531 and 532 are provided in each sub-pixel area SP5. The shapes of the pixel electrodes 531 and 532 are the same as those described above. The shapes of the pixel electrodes of the embodiments are similar. For example, the shapes of the pixel electrodes 531 and 532 may be similar to the shapes of the pixel electrodes 130, 230a, 230b, and 430 in the previous embodiments. However, both the length and size of the pixel electrodes 531 and 532 may be smaller than the length and size of the pixel electrode 430 .

The pixel electrodes 531 and 532 have different sizes and lengths. From FIG. 5A , the size and length of the pixel electrode 531 are smaller than the size and length of the pixel electrode 532 . The pixel electrodes 531 and 532 in the same sub-pixel area SP5 are respectively electrically connected to two adjacent data lines 121d, so that each data line 121d is electrically connected to the pixel electrodes 531 and 532 alternatively. In other words, the data line 121d electrically connected to the pixel electrode 531 will not be electrically connected to the pixel electrode 532. Similarly, the data line 121d electrically connected to the pixel electrode 532 will not be electrically connected to the pixel electrode 531.

When the liquid crystal display panel 500a displays an image, the data lines 121d will alternately output high and low pixel voltages to the pixel electrodes 531 and 532. Taking FIG. 5A as an example, counting from left to right, the first and third data lines 121d will output positive polarity pixel voltages, while the second and fourth data lines 121d will output negative polarity pixel voltages. Since each data line 121d is electrically connected to the pixel electrodes 531 and 532 alternatively, the polarity of these pixel electrodes 531 is positive, and the polarity of these pixel electrodes 532 is negative. Therefore, during the period when the liquid crystal display panel 500a displays an image, the polarities of the pixel electrodes 531 and 532 are opposite to each other.

During the period when the liquid crystal display panel 500a displays an image, the pixel voltages received by the pixel electrodes 531 and 532 are different. The pixel electrode 531 will receive a higher pixel voltage, and the pixel electrode 532 will receive a higher pixel voltage. Low pixel voltage. In other words, when the liquid crystal display panel 500a displays an image, the voltage of the pixel electrode 531 will be higher than the voltage of the pixel electrode 532, where the voltage of the pixel electrode 532 may be 0.6 to 0.8 times the voltage of the pixel electrode 531. For example, 0.7 times. In this way, the voltages and polarities of the pixel electrodes 531 and 532 in the same sub-pixel area SP5 will be different from each other to generate four fields, so that the image quality of the liquid crystal display panel 500a is not easily affected by changes in viewing angle, thereby maintaining Or improve image quality.

FIG. 5B is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention, and is a partial top schematic view of the liquid crystal display panel 500b. Please refer to FIG. 5B. The liquid crystal display panel 500b also has a plurality of sub-pixel areas SP5, and FIG. 5B also depicts four sub-pixel areas SP5 arranged in a 2×2 array as an example. The liquid crystal display panel 500b is similar to the aforementioned liquid crystal display panel 500a. The only difference between the liquid crystal display panels 500a and 500b is that the pixel circuit array 520b included in the liquid crystal display panel 500b is different from the pixel circuit array 520a of the aforementioned embodiment.

Specifically, in this embodiment, in the sub-pixel area SP5 arranged in the same row along the second direction D2, one pixel electrode 531 and one pixel electrode 532 are disposed between two adjacent scan lines 421s. space, and are electrically connected to two different data lines 121d respectively. Taking FIG. 5B as an example, in the same row sub-pixel area SP5, the two pixel electrodes 531 and 532 located on opposite sides of the upper scanning line 421s are electrically connected to two different data lines 121d respectively. Among them, the two pixel electrodes 531 and 532 located on this scanning line The pixel electrode 532 above the scan line 421s is electrically connected to the data line 121d on the right, and the pixel electrode 531 below the scan line 421s is electrically connected to the data line 121d on the left.

Secondly, in FIG. 5B, the two pixel electrodes 531 and 532 located on opposite sides of the lower scanning line 421s are also electrically connected to two different data lines 121d respectively. The pixel electrode 532 located above the scanning line 421s is electrically connected. The data line 421d on the left is electrically connected, and the pixel electrode 531 located below the scan line 421s is electrically connected to the data line 121d on the right, so that the pixel electrodes 531 and 532 between the two adjacent scan lines 421s are both electrically connected. Connect the data line 121d on the left, as shown in Figure 5B.

During the period when the liquid crystal display panel 500b displays an image, the data lines 121d alternately output high and low pixel voltages to the pixel electrodes 531 and 532. Taking Figure 5B as an example, counting from left to right, the first and third data lines 121d will output positive pixel voltages, while the second and fourth data lines 121d will output negative polarity pixel voltages. So in FIG. 5B , the polarities of the uppermost pixel electrode 532 and the lowermost pixel electrode 531 are both negative, and the pixel electrode 531 located in the middle (that is, between two adjacent scan lines 421s) and The polarity of 532 is all positive.

In this way, when the liquid crystal display panel 500b displays an image, the pixel electrodes 531 and 532 located between two adjacent scan lines 421s can have the same polarity, and the pixel electrodes 531 and 532 in the same sub-pixel area SP5 The voltages and polarities of the liquid crystal display panel 500a will be different from each other to generate four fields, so that the image quality of the liquid crystal display panel 500a is not easily affected by changes in viewing angle, thereby maintaining or improving the image quality.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary skill in the technical field to which the present invention belongs may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention is The scope of invention protection shall be determined by the appended patent application scope.

100, 200a, 200b, 300, 400a, 400b, 500a, 500b: LCD panel 111: First substrate 112:Second substrate 120, 220, 320, 420a, 420b, 520a, 520b: pixel circuit array 121d, 221d, 421d: data line 121s, 421s: scan line 122, 422: Common electrode pattern 122h, 422h: Opening 122p, 422p: common sub-electrode 123:Control components 123c: Channel layer 123g:gate 123s: Source 123d: drain 124, 126: Insulation layer 130, 230a, 230b, 430, 531, 532: pixel electrode 131:First rib 132, 232: Second rib 132s, L12: long side 133:Third rib 139:Connecting shaft 140: Common electrode 150:Liquid crystal layer 171:Filter layer 172:Black Matrix 191:The first linear polarizer 192: Second linear polarizing plate 438:Connecting ribs A1, A2: included angle D1: first direction D2: second direction D3: Third direction D91: First polarization direction D92: Second polarization direction G12: distance H11:Contact window H21, H22: connecting strip S1, S2: slit SP1, SP4, SP5: sub-pixel area V22:Electrode strip W1, W2, W2a, W3, WS1: Width

1A is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention. FIG. 1B is a partial top view of the liquid crystal display panel in FIG. 1A . Figure 1C is a partially enlarged schematic diagram of Figure 1B. FIG. 1D is a schematic cross-sectional view drawn along line 1D-1D in FIG. 1B. FIG. 1E is a schematic diagram of the polarization directions of the first linear polarizing plate and the second linear polarizing plate in FIG. 1D. FIG. 2A is a partial top view of a liquid crystal display panel according to another embodiment of the present invention. FIG. 2B is a partial top view of a liquid crystal display panel according to another embodiment of the present invention. FIG. 3 is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention. FIG. 4A is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention. FIG. 4B is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention. FIG. 5A is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention. FIG. 5B is a schematic top view of a liquid crystal display panel according to at least one embodiment of the present invention.

100:LCD display panel

111: First substrate

121d: Data line

121s: scan line

122h:Open your mouth

122p: Common sub-electrode

123:Control components

123c: Channel layer

123g:gate

123s: source

123d: drain

130: Pixel electrode

131:First rib

132:Second rib

133:Third rib

139:Connecting shaft

D1: first direction

D2: second direction

H21, H22: connecting strip

S1: slit

V22:Electrode strip

W1, W2, W3, WS1: Width

Claims (14)

A liquid crystal display panel comprises: a first substrate; a pixel circuit array disposed on the first substrate and comprising a plurality of parallel data lines, wherein the pixel circuit array defines a plurality of sub-pixel areas arranged in an array on the first substrate, a portion of each of the data lines is located in one of the sub-pixel areas, and two adjacent data lines are distributed in each of the sub-pixel areas; a plurality of pixel electrodes disposed on the pixel circuit array and respectively located on the sub-pixel areas; The pixel electrodes are electrically connected to the pixel circuit array in each sub-pixel region, and in each sub-pixel region, the pixel electrode overlaps with two adjacent data lines, wherein during the period when the liquid crystal display panel displays an image, the voltages of the two adjacent data lines distributed in each sub-pixel region are different from each other, wherein each pixel electrode includes: a connecting axis extending along a first direction; a plurality of first ribs connecting the connecting axis; and two second ribs connecting the connecting axis. A connecting axis is provided, and overlaps with two adjacent data lines in one of the sub-pixel regions, wherein the first ribs and the second ribs extend outward from opposite sides of the connecting axis along a second direction and a direction opposite to the second direction, and a slit is formed between two adjacent ones of the first ribs and the second ribs; a second substrate; a liquid crystal layer is provided between the first substrate and the second substrate; a first linear polarizer is provided on the first substrate plate, and having a first polarization direction; and a second linear polarizer, disposed on the second substrate, and having a second polarization direction, wherein the first polarization direction is substantially perpendicular to the second polarization direction, the first direction is substantially perpendicular to the second direction, and the angle between the first polarization direction and the first direction is between 40 degrees and 50 degrees, and the angle between the second polarization direction and the second direction is between 40 degrees and 50 degrees. The liquid crystal display panel of claim 1, wherein in the same sub-pixel area, at least one first rib is located between the second ribs. The liquid crystal display panel of claim 1, wherein the second ribs are located between two of the first ribs in the same sub-pixel area. The liquid crystal display panel of claim 1, wherein the width of each second rib is greater than the width of each first rib. The liquid crystal display panel according to any one of claims 1 to 4, wherein each pixel electrode further includes: two third ribs connecting the connection axis and extending along the second direction and the second direction. In opposite directions, extending outward from opposite sides of the connecting shaft, the slit is formed between two adjacent ones of the first ribs, the second ribs and the third ribs. The liquid crystal display panel of claim 5, wherein the width of each second rib is greater than the width of each third rib and the width of each first rib. The liquid crystal display panel of claim 5, wherein the width of each first rib, the width of each second rib, and the width of each third rib are each greater than the width of the slit. The liquid crystal display panel of claim 1, wherein in the overlapping second rib and the data line, the second rib protrudes from two opposite long sides of the data line. The liquid crystal display panel of claim 8, wherein in the overlapping second rib and the data line, the distance between the long side of the second rib and the long side of the adjacent data line is between 0.5 microns. to 2 microns. The liquid crystal display panel of claim 1, wherein the pixel circuit array further includes: a common electrode pattern disposed on the first substrate and having a plurality of openings corresponding to the pixel electrodes; wherein in the liquid crystal When the display panel displays an image, the voltage of the common electrode pattern distributed in one of the sub-pixel areas is different from that of the adjacent two pixel areas. The voltage of the material line. The liquid crystal display panel of claim 10, wherein during the period when the liquid crystal display panel displays an image, in one of the sub-pixel regions, the voltage of the common electrode pattern is higher than the voltage of one of the data lines, and is lower than the voltage of one of the data lines. voltage on the other data line. The liquid crystal display panel of claim 10, wherein the common electrode pattern includes: a plurality of common sub-electrodes, arranged in an array, and located in the sub-pixel regions respectively, wherein each common sub-electrode includes two parallel Electrode strips, and the electrode strips of each common sub-electrode are distributed in one of the sub-pixel areas and located around one of the openings; wherein two adjacent data lines are distributed in one of the openings, and Located between the electrode strips of the same common sub-electrode. The liquid crystal display panel of claim 1, further comprising: a common electrode disposed on the second substrate, wherein the liquid crystal layer is sandwiched between the common electrode and the pixel circuit array, and the liquid crystal layer, The common electrode and the pixel circuit array are located between the first substrate and the second substrate. The liquid crystal display panel of claim 1, wherein the liquid crystal layer is a vertical alignment liquid crystal.

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