TWI829202B - Memory device and slew rate detector - Google Patents

Abstract

A memory device and a slew rate detector are provided. The slew rate detector includes a clock generator, a pulse signal generator, a plurality of sampler and comparators and a detection result generator. The clock generator multiplies a frequency of a base clock signal to generate a plurality of clock signals. The pulse signal generator generates a plurality of first pulse signals and a plurality of second pulse signals. Each of the sampler and comparators samples each of a plurality of transmission signals to generate a reference signal according to the first pulse signals, and samples each of the transmission signals to generate a compared signal according to the second pulse signals. The sampler and comparators respectively compare the reference signals with the compared signals to generate a plurality of comparison result. The detection result generator generates a plurality of detection results by performing operation on the comparison result.

Description

Memory device and its slew rate detector

The present invention relates to a memory device and a slew rate detector thereof, and in particular to a memory device that can adjust a transmission path according to a signal transmission rate and a slew rate detector thereof.

There are key signal transmission wires in memory products, and these signals have certain specifications in timing and transition time points. If each transmission wire is not separated by a shielding structure that receives a fixed voltage level, the coupling state between the transmission wires will become more serious, slowing down the speed of signal transmission, and even causing chip function failure.

In conventional technology, to reduce the above problems, a shielding structure can be provided between adjacent transmission wires. However, this will increase the circuit layout area and increase the circuit cost.

The present invention provides a slew rate detector that can effectively detect transmission signals with relatively large transmission delays among transmission signals.

The present invention also provides a memory device that can increase the transmission rate of transmission signals with large delays.

The slew rate detector of the present invention includes a clock signal generator, a pulse signal generator, a plurality of sampling comparators and a detection result generator. The clock signal generator multiplies a reference clock signal to generate multiple clock signals. The pulse signal generator is coupled to the clock signal generator and generates a plurality of pulse signals according to the clock signal. The pulse signal is divided into a plurality of first pulse signals and a plurality of second pulse signals. The sampling comparators receive multiple transmission signals respectively. Each sampling comparator samples each transmission signal according to the first pulse signal to generate a reference signal, and samples each transmission signal according to the second pulse signal to generate a comparison signal. The sampling comparator compares the reference signal with the comparison signal respectively to generate multiple comparison results. The detection result generator is coupled to the sampling comparator and performs operations according to the comparison results to generate multiple detection results.

The memory device of the present invention includes a first data transmission path, a second data transmission path and the slew rate detector as mentioned above. The data transmission rate of the second data transmission path is higher than the data transmission rate of the first data transmission path. The slew rate detector receives a plurality of transmission signals and detects the slew rate of the transmission signals to select each transmission signal to be transmitted through the first data transmission path or the second data transmission path.

Based on the above, the slew rate detector of the present invention can be used to detect transmission signals with relatively low transmission rates. And in the memory device, by selecting a data transmission path with a relatively fast transmission rate to improve the transmission action of a transmission signal with a relatively low transmission rate, the overall transmission rate of the transmission signal can be increased and the performance of the memory device can be increased.

Please refer to FIG. 1 , which is a schematic diagram of a slew rate detector according to an embodiment of the present invention. The slew rate detector 100 includes a clock signal generator 110, a pulse signal generator 120, sampling comparators 130~13n and a detection result generator 140. The clock signal generator 110 receives the reference clock signal CLK, and performs a frequency multiplication operation on the reference clock signal CLK to generate a plurality of clock signals CLK_t and CLK_c. In this embodiment, the clock signals CLK_t and CLK_c are two-period signals with complementary phases. The pulse signal generator 120 is coupled to the clock signal generator 110 . The pulse signal generator 120 receives the clock signals CLK_t and CLK_c, and generates a plurality of pulse signals latsr<m:0> according to the clock signals CLK_t and CLK_c. Among them, the pulse wave signal latsr<m:0> can be generated periodically, and in the same cycle, each of the pulse wave signals latsr<m:0> has only one pulse wave.

The sampling comparators 130~13n are coupled to the pulse signal generator 120 and receive the pulse signal latsr<m:0>. In addition, the sampling comparators 130~13n respectively receive the transmission signal CS<n:0>. Here, the pulse wave signal latsr<m:0> can be divided into two parts, which are a plurality of first pulse wave signals and a plurality of second pulse wave signals. If m=15 is taken as an example, the pulse signal latsr<7:0> can be the first pulse signal, and the pulse signal latsr<8:15> can be the second pulse signal. Wherein, the phase of the first pulse signal leads the second pulse signal. The sampling comparators 130~13n respectively sample the corresponding received transmission signal CS<n:0> according to the first pulse signal (pulse signal latsr<7:0>) to generate a reference signal, and generate a reference signal according to the second pulse signal (Pulse wave signal latsr<15:8>) The transmission signal CS<n:0> is sampled respectively to generate a comparison signal. The sampling comparators 130~13n compare the reference signal with the comparison signal respectively, and generate multiple comparison results Srate0<p:0>~Sraten<p:0>.

Please note here that taking the sampling comparator 130 as an example, the phase of the first pulse signal (pulse signal latsr<7:0>) is ahead of the second pulse signal (pulse signal latsr<15:8>). The sampling comparator 130 can sample the pre-transition level of the transmission signal CS<0> according to the pulse signal latsr<7:0>, and generate a reference signal. The sampling comparator 130 can also sample a comparison signal that can reflect the transition time point of the transmission signal CS<0> according to the pulse signal latsr<15:8>. The sampling comparator 130 compares the reference signal with the comparison signal to obtain the comparison result Srate0<p:0> corresponding to the transition time point of the transmission signal CS<0>. Among them, when m is equal to 15, p can be equal to 7.

In addition, the detection result generator 140 is coupled to the sampling comparators 130~13n. The detection result generator 140 receives the comparison results Srate0<p:0>~Sraten<p:0>, and performs operations on the comparison results Srate0<p:0>~Sraten<p:0> to generate multiple detection results DR0 ~DRn. Among them, the detection result generator 140 performs logical operations on the comparison results Srate0<p:0>~Sraten<p:0>, and calculates the detection results DR0~DRn. Among them, the comparison results Srate0<p:0>~Sraten<p:0> can respectively reflect the transition time point of the transmission signal CS<n:0>, and the detection result generator 140 calculates the transmission signal through logical operations. One or more signals in CS<n:0> that transition slowly.

Please refer to FIG. 2 below, which is a schematic diagram of a slew rate detector according to another embodiment of the present invention. The slew rate detector 200 includes a clock signal generator 210, a pulse signal generator 220, sampling comparators 230~23n and a detection result generator 240. In this embodiment, the clock signal generator 210 receives the reference clock signal CLK, and performs a frequency multiplication operation on the reference clock signal CLK to generate a plurality of clock signals CLK_t and CLK_c. The clock signals CLK_t and CLK_c have complementary phases. a two-period signal. The pulse signal generator 220 is coupled to the clock signal generator 210 and generates a plurality of pulse signals latsr<15:0> according to the clock signals CLK_t and CLK_c. Here, the pulse signal generator 220 can periodically and cyclically generate the pulse signal latsr<15:0>.

The sampling comparators 230~23n respectively include first-in-first-out buffers 231-0~231-n, latches 232-0~232-n, and comparators 233-0~233-n. The sampling comparators 230~23n respectively receive the transmission signal CS<n:0>. Taking the sampling comparator 230 as an example, the first-in-first-out buffer 231-0 records the reference signal Bit_ori<7:0>-0 generated by sampling the transmission signal CS<0> according to the pulse signal latsr<7:0>. The latch 232 records the comparison signal Bit_new<7:0>-0 generated by sampling the transmission signal CS<0> according to the pulse signal latsr<15:8>.

The comparators 233-0~233-n respectively make the reference signal Bit_ori<7:0>-0~ Bit_ori<7:0>-n and the comparison signal Bit_new<7:0>-0 ~ Bit_new<7:0>- n are compared respectively to generate comparison results Srate0<7:0> ~ Sraten<7:0> respectively.

On the other hand, the detection result generator 240 includes a logic operator 2410 and a plurality of comparators 2420~242n. The logic operator 2410 receives the comparison results Srate0<7:0>~Sraten<7:0> respectively generated by the sampling comparators 230~23n, and performs logical operations on the comparison results Srate0<7:0>~Sraten<7:0>. . In this embodiment, the logic operator 2410 can be an AND gate, and is used to perform AND logic operations on the comparison results Srate0<7:0>~Sraten<7:0> to generate the reference comparison result RCR<7:0> . In this embodiment, the comparison result Srate0<7:0> is taken as an example. The transition from logic 0 to logic 1 in the multiple bits of the comparison result Srate0<7:0> represents the transition of the transmission signal CS<0>. point. Therefore, by performing AND logical operations on the comparison results Srate0<7:0>~Sraten<7:0>, the comparison results Srate0<7:0>~Sraten<7:0> can have bits that are at least equal to logic 1 (bits equal to logic 0 at most) are equal to the reference comparison result RCR<7:0>.

The comparators 2420~242n are used to compare the reference comparison result RCR<7:0> with the comparison results Srate0<7:0>~Sraten<7:0> respectively, so as to obtain the comparison result Srate0<7:0 Which one of ＞~Sraten＜7:0＞ is equal to the reference comparison result RCR＜7:0＞, and generates a detection result DR0＜7:0＞ that can indicate the occurrence of the lowest transmission rate in the transmission signal CS＜n:0＞ ~DRn<7:0>.

In this embodiment, each of the comparators 2420~242n can be a logic operator, and can be constructed using multiple mutually exclusive OR gates or multiple anti-mutually exclusive OR gates, so that the reference comparison result RCR < Multiple bits of 7:0> perform exclusive-OR operations (exclusive-OR) with multiple bits of each comparison result Srate0<7:0>~Sraten<7:0> to generate corresponding detection results. DR0＜7:0＞~DRn＜7:0＞. Alternatively, each of the comparators 2420~242n can compare multiple bits of the reference comparison result RCR<7:0> with multiple bits of each comparison result Srate0<7:0>~Sraten<7:0> respectively. The elements perform an AND operation to generate multiple AND operation results, and perform an OR operation on the above AND operation results to generate corresponding detection results DR0<7:0>~DRn<7:0>. That is to say, each of the comparators 2420~242n can also be constructed using multiple And Or Inverters (AOI).

The comparators 233-0~233-n can be implemented using the same circuit architecture as the comparators 2420~242n, which will not be described in detail here.

In order to explain the implementation of the slew rate detector of the present invention more clearly, an implementation example with actual data is given below. Please refer to FIGS. 3A and 3B , which are schematic diagrams of an implementation of a slew rate detector according to an embodiment of the present invention. The hardware architecture can be referred to Figure 2. In FIG. 3A , the pulse signal generator 220 can generate a plurality of pulse signals latsr<8>~latsr<15> according to the clock signals CLK_t and CLK_c. Among them, the pulse wave signals latsr<8>~latsr<15> each have a plurality of sequentially generated pulse waves, and correspond in sequence to a plurality of sequentially and interleaved pulse waves generated in the clock signals CLK_t and CLK_c. It is worth mentioning that multiple pulse waves in the pulse signal latsr<8>~latsr<15> are distributed in the time interval when the transmission signal CS<n:0> transitions.

In Figure 3B, taking the transmission signals CS<1>, CS<2> and CS<3> as examples, through the sampling action of the pulse signals latsr<0>~latsr<15>, the corresponding transmission signal CS<1 can be obtained >The reference signal Bit_ori<7:0>-1 and the comparison signal Bit_new<7:0>-1; the reference signal Bit_ori<7:0>-2 and the comparison signal Bit_new<7:0 corresponding to the transmission signal CS<2> >-2; and the reference signal Bit_ori<7:0>-3 and the comparison signal Bit_new<7:0>-3 corresponding to the transmission signal CS<3>. Then, compare the reference signal Bit_ori<7:0>-1 and the comparison signal Bit_new<7:0>-1 bit by bit to generate the comparison result Srate1<7:0>; make the reference signal Bit_ori<7:0>-2 and the comparison signal Bit_new<7:0>-2 are compared bit by bit to produce the comparison result Srate2<7:0>; and, the reference signal Bit_ori<7:0>-3 and the comparison signal Bit_new<7:0>-3 Bit-by-bit comparison produces the comparison result Srate3<7:0>.

In this implementation, taking the transmission signal CS1 as an example, the pre-transition level of the transmission signal CS1 is logic 0, so the reference signal Bit_ori<7:0>-1 is equal to 0, 0, 0, 0, 0, 0, 0, 0. The transmission signal CS1 transitions to logic 1 at the 5th bit corresponding to the comparison signal Bit_new<7:0>-1, so the comparison signal Bit_new<7:0>-1 can be equal to 0, 0, 0, 0, 0, 1, 1, 1. Then, by comparing the reference signal Bit_ori<7:0>-1 and the comparison signal Bit_new<7:0>-1 bit by bit, the comparison result Srate1<7:0> is equal to 0, 0, 0, 0, 0 ,1,1,1.

According to the above description, corresponding to the transmission signals CS1 ~ CS3 respectively, the comparison results Srate1<7:0> ~ Srate3<7:0> can be generated respectively. By performing an AND operation on the comparison results Srate1＜7:0＞~Srate3＜7:0＞, you can obtain the values of the comparison results corresponding to the transmission signal with the slowest transmission rate and 0, 0, 0, 0, 0, 0 ,0,1.

In this way, 0, 0, 0, 0, 0, 0, 0, 1 are compared with the comparison results Srate1<7:0>~Srate3<7:0> through the comparators 2421~2423. Based on the comparison result Srate2 <7:0> is equal to 0, 0, 0, 0, 0, 0, 0, 1. It can be determined that the transmission signal CS2 has the slowest transmission rate. Based on the comparison result Srate2<7:0> equal to 0, 0, 0, 0, 0, 0, 0, 1, the comparator 2422 can generate a detection equal to 0, 0, 0, 0, 0, 0, 0, 0 The result is DR2<7:0>.

It is worth mentioning that the level before the transmission signal CS3 transitions is logic 1, and its transition time can also be detected using this implementation method.

Please refer to FIG. 4 below. FIG. 4 is a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 400 includes a memory cell array 401, a sense amplifier 402, a slew rate detector 410, drivers 403, 405 and 408, a multiplexer 404, a first-in-first-out buffer 406, a format converter 407 and a buffer 409. In this embodiment, the first data transmission path OPTH can be formed between the multiplexer 404, the driver 405 and the FIFO buffer 406, and the second data transmission path can be formed between the multiplexer 404 and the FIFO buffer 406. HPTH. The first transmission path OPTH does not have a shielding structure, and the second transmission path HPTH has a shielding structure. The so-called shielding structure is to set up a shielding structure between adjacent transmission wires to prevent the transmission wires from interfering with each other due to cross talk, which can improve the signal transmission rate and quality. In this embodiment, the signal transmission rate of the first transmission path OPTH is lower than the signal transmission rate of the second transmission path OPTH. The shielding structure may be coupled to ground, for example.

The slew rate detector 410 is coupled between the sensing signal amplifier 402 and the multiplexer 404, and is used to detect the transmission signal CS<n:0> provided by the sensing signal amplifier 402. The transmission signal CS<n:0> may be a critical signal among all signals provided by the sensing signal amplifier 402 . The slew rate detector 410 is used to detect the transmission rate of the transmission signal CS<n:0>, and provide the detection result to the multiplexer 404, so that one of the transmission signals CS<n:0> has a relatively low transmission rate. Or multiple transmission signals are transmitted through the second transmission path OPTH, and the transmission signal CS<n:0> with a relatively high transmission rate is transmitted through the first transmission path OPTH. In this way, low-speed transmission signals can be compensated for in transmission rate, effectively improving the overall performance of the memory device 400 .

Incidentally, the memory cell array 401 in the embodiment of the present invention can be a memory cell array known to those of ordinary skill in the art, and is not subject to certain form restrictions. In addition, the driver 408 can be an offline driver (Off-Chip Driver, OCD), and the format converter 407 can be a parallel-to-serial converter. The sense amplifier 402, drivers 403, 405 and 408, the multiplexer 404, the first-in-first-out buffer 406, the format converter 407 and the buffer 409 can all be implemented using relevant circuits known to those of ordinary skill in the art. Specific restrictions.

Please refer to FIG. 5 . FIG. 5 is a schematic diagram of an implementation method in which a slew rate detector generates a control signal for a multiplexer in the embodiment of FIG. 4 of the present invention. According to the description in the embodiment of FIG. 3B , all bits of the detection result corresponding to the transmission signal with the slowest transmission rate are logic 0. Therefore, the slew rate detector 410 can be configured with the logic operator 500 as shown in FIG. 5 to perform logic operations on the detection result DRx<7:0>. Here, the detection result DRx<7:0> represents one of the detection results DR0<7:0>~DRn<7:0> in the embodiment of FIG. 2 . The logic operator 500 is an AND gate and generates the control signal CTR according to whether the detection results DRx<7:0> are all logic 0. The control signal CTR is used to control the multiplexer to select and transmit the corresponding transmission signal to the fast or slow transmission path.

In summary, the memory device of the present invention detects the transmission rate of the transmission signal through the slew rate detector, and selects different transmission paths according to the detection results to perform transmission operations of transmission signals of different rates. In this way, without excessively increasing the circuit layout area, transmission signals with relatively slow transmission rates can be compensated, thereby improving the overall signal transmission rate in the memory device and increasing the performance of the memory device.

100, 200, 410: slew rate detector 110, 210: Clock signal generator 120, 220: Pulse signal generator 130~13n, 230~23n: Sampling comparator 140, 240: Detection result generator 231-0~231-n, 406: first-in-first-out buffer 232-0~232-n: latch 233-0~233-n, 2420~242n: comparator 2410, 500: Logic operator 400: Memory device 401: Memory cell array 402: Sense amplifier 403, 405, 408: drive 404: Multiplexer 407: Format Converter 409: Buffer Bit_new＜7:0＞-0~ Bit_new＜7:0＞-n: Comparison signal Bit_ori＜7:0＞-0~ Bit_ori＜7:0＞-n: reference signal CLK: reference clock signal CLK_t, CLK_c: clock signal CS＜n:0＞：Transmission signal CTR: control signal DR0~DRn, DR0＜7:0＞~DRn＜7:0＞, DRx＜7:0＞: detection result latsr＜m:0＞, latsr＜15:0＞: pulse signal OPTH, HPTH: data transmission path RCR<7:0>: Reference comparison result Srate0＜p:0＞~Sraten＜p:0＞, Srate0＜7:0＞ ~ Sraten＜7:0＞: comparison results

1 and 2 are schematic diagrams of slew rate detectors according to different embodiments of the invention. 3A and 3B are schematic diagrams of an implementation of a slew rate detector according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a memory device according to an embodiment of the invention. FIG. 5 is a schematic diagram of an implementation in which a slew rate detector generates a control signal for a multiplexer in the embodiment of FIG. 4 of the present invention.

100: Slew rate detector 110: Clock signal generator 120: Pulse signal generator 130~13n: Sampling comparator 140: Detection result generator CLK: reference clock signal CLK_t, CLK_c: clock signal CS＜n:0＞：Transmission signal DR0~DRn: detection results latsr<m:0>: pulse signal Srate0＜p:0＞~Sraten＜p:0＞: comparison results

Claims (10)

A slew rate detector includes: a clock signal generator that multiplies a reference clock signal to generate a plurality of clock signals; a pulse signal generator coupled to the clock signal generator, according to the clock signals pulse signals to generate multiple pulse signals, which are divided into multiple first pulse signals and multiple second pulse signals; multiple sampling comparators respectively receive multiple transmission signals, and each sample is compared The device samples each transmission signal according to the first pulse signals to generate a reference signal, and samples each transmission signal according to the second pulse signals to generate a comparison signal. The sampling comparators enable the The reference signal is compared with the comparison signals respectively to generate a plurality of comparison results; and a detection result generator is coupled to the sampling comparators and performs operations on the comparison results to generate a plurality of detection results. The slew rate detector of claim 1, wherein the detection result generator includes: a first logic operator that performs logical operations on the comparison results to generate a reference comparison result; and a plurality of comparators, The comparators compare the reference comparison results with the comparison results to generate the detection results respectively. The slew rate detector as described in claim 2, wherein the detection results correspond to the comparison results respectively. When the reference comparison result is the same as the comparison result, the corresponding comparator enables each detection result. test results. The slew rate detector of claim 2, wherein the first logic operator performs a AND logic operation on the comparison results. The slew rate detector of claim 2, wherein the transmission signal corresponding to the selected comparison result is the signal with the lowest transmission rate among the transmission signals. The slew rate detector of claim 2, wherein each comparator is a second logic operator, allowing multiple bits of the reference comparison result to perform logical operations with multiple bits of each comparison result. To generate corresponding detection results. The slew rate detector of claim 6, wherein each comparator performs an AND operation on a plurality of bits of the reference comparison result and a plurality of bits of each comparison result to generate a plurality of AND operation results, The second logic operator performs an OR operation on the AND operation results to generate corresponding detection results. The slew rate detector of claim 6, wherein each comparator performs a mutually exclusive OR operation on a plurality of bits of the reference comparison result and a plurality of bits of the comparison result to generate the corresponding respective bits. Detection results. The slew rate detector of claim 1, wherein each sampling comparator includes: a first-in-first-out buffer that samples each transmission signal according to the first pulse signals to generate the reference signal; A latch is used to sample each transmission signal according to the second pulse signals to generate the comparison signal; and a comparator is used to compare each reference signal with each comparison signal to generate each comparison result. A memory device, including: a first data transmission path; a second data transmission path, wherein the data transmission rate of the second data transmission path is higher than the data transmission rate of the first data transmission path; and as in claim 1 The slew rate detector receives a plurality of transmission signals and detects the slew rate of the transmission signals to select each transmission signal to be transmitted through the first data transmission path or the second data transmission path.

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