TWI816498B - Bus direct interrupt service device - Google Patents

Abstract

A bus direct interrupt service device is disclosed. The bus direct interrupt service device is coupled to a bus interface unit of the processor. The bus direct interrupt service device includes an interrupt command register bank and an interrupt request multiplexer. The interrupt command register bank stores a plurality of interrupt commands and bus addresses and operate commands corresponded to the plurality of interrupt commands. When the receiving end receives the interrupt request, the interrupt command register bank selects an interrupt control command corresponded to the interrupt request from the plurality of interrupt commands. The interrupt request multiplexer is coupled to the bus interface unit and the interrupt command register bank. When the interrupt request multiplexer receives the interrupt control command, the corresponding operate command of the interrupt control command is directly sent to the corresponding bus address through an output interface, so as to operate the peripheral device.

Description

bus direct interrupt service device

The present invention relates to a bus direct interrupt service device, and in particular to a bus direct interrupt service device that can directly and quickly execute interrupt request operations through an interrupt instruction register and an interrupt request multiplexer.

When peripheral hardware devices of the computer system need to perform specific events or operations, an interrupt request (IRQ) signal will be sent to the processor to let the processor know which devices or software need to act and send corresponding operation instructions. to control peripheral devices to perform corresponding operations. After these interrupt request signals enter the processor, they are scheduled and converted by relevant instructions to form executable control instructions, which are sent to the connected peripheral interface to perform related operations on the peripheral devices.

Existing processors have an interrupt service handler (Interrupt Service Routine, ISR) to handle these interrupt requests and convert the interrupt requests into required operation instructions. However, the operation through the interrupt service handler requires a certain period of conversion time. For interrupt requests that require immediate startup or operation timeliness, the delay time of these conversions will cause operation errors or affect the results of the operation, making it difficult to achieve interrupts. Request the desired action effect.

In summary, the inventor of the present invention thought about and designed a bus direct interrupt service device in order to improve the problems of the conventional technology and thereby enhance industrial implementation and utilization.

In view of the problems described in the prior art, the object of the present invention is to provide a bus direct interrupt service device that reduces the time required to perform operations and reduces the problem of device operation errors or errors caused by time delays.

Based on the above objectives, the present invention provides a bus direct interrupt service device, which is a bus interface unit coupled to a processor. The processor has a receiving end for receiving interrupt requests. The bus direct interrupt service device includes an interrupt instruction register and an interrupt. Request multiplexer. Among them, the interrupt command register is coupled to the receiving end. The interrupt command register stores a plurality of interrupt instructions and the bus positions and operation instructions corresponding to each plurality of interrupt instructions. When the receiving end receives an interrupt request, the interrupt command register is composed of a plurality of interrupt instructions. Select the interrupt control instruction corresponding to the interrupt request among the interrupt instructions. The interrupt request multiplexer is coupled to the bus interface unit and the interrupt command register. When the interrupt request multiplexer receives the interrupt control command, it directly transmits the operation command corresponding to the interrupt control command from the output interface to the corresponding bus location, and controls the peripheral The device performs the operation requested by the interrupt.

Preferably, the interrupt request multiplexer can receive processor control instructions from the processor through the bus interface unit, and output the processor control instructions through the output interface.

Preferably, the interrupt request multiplexer may include an instruction temporary storage area coupled to the bus interface unit. When the interrupt request multiplexer receives an interrupt control instruction, the simultaneously received processor control instruction is temporarily stored in the instruction temporary storage area. , forming a temporary storage area control instruction.

Preferably, the interrupt request multiplexer may include an arbiter coupled to the interrupt command register, the command temporary storage area and the bus interface unit, and the arbiter stores the interrupt command register, the command temporary storage area and the bus interface unit. Instruction execution rules.

Preferably, the order of priority of the instruction execution rules may be interrupt control instructions, temporary storage area control instructions and processor control instructions.

Preferably, the output interface may include interfaces from an Advanced Extensible Interface (AXI) to multiple Advanced High Performance Buses (AHB).

Preferably, the peripheral device may include an analog-to-digital converter, and the operation command triggers the analog-to-digital converter to perform echo sampling.

Preferably, the interrupt instruction register and the interrupt request multiplexer can be coupled to a power supply different from that of the processor.

Preferably, the power domain where the interrupt instruction register bank and the interrupt request multiplexer are located is different from the power domain where the processor is located.

Preferably, the operations of the interrupt instruction register bank and the interrupt request multiplexer can be independent of the operation of the processor.

Based on the above, the bus direct interrupt service device according to the present invention may have one or more of the following advantages:

(1) This bus direct interrupt service device can directly convert interrupt requests into executable control instructions through the interrupt command register and interrupt request multiplexer, so that the operation of peripheral devices can be more efficient and avoid unnecessary execution of operations. Time delay causes errors in operation results, improving the accuracy and timeliness of operations.

(2) This bus direct interrupt service device can set instruction execution rules through the interrupt request multiplexer, so that the interrupt request multiplexer can process interrupt control instructions, temporary storage area control instructions and processor The control instructions enable the bus direct interrupt service device to be compatible with existing processors, thereby improving device compatibility and reducing device development costs.

(3) This bus direct interrupt service device can be configured with different power supplies, so that the bus direct interrupt service device can still perform related interrupt request operations when the processor is in sleep mode or shut down, thereby reducing system power consumption. In order to achieve the effect of power saving.

10,30: Bus direct interrupt service device

11,31: Interrupt instruction register library

12,32: Interrupt request multiplexer

13,33:Output interface

20,40: Processor

21:Bus interface unit

22,42:Peripheral devices

34:Device power supply

41:Processor power supply

111: Interrupt instruction

112: Bus location

113: Operation instructions

121: Instruction temporary storage area

122:Arbiter

123: Execution of instruction rules

124: Interrupt control instruction

125: Temporary storage area control command

126: Processor control instructions

IR: interrupt request

In order to make the technical features, content and advantages of the present invention and the effects it can achieve more apparent, the present invention is described with reference to the following drawings:

Figure 1 is a schematic diagram of a bus direct interrupt service device according to an embodiment of the present invention.

Figure 2 is a schematic diagram of an interrupt command register according to an embodiment of the present invention.

Figure 3 is a schematic diagram of an interrupt request multiplexer according to an embodiment of the present invention.

Figure 4 is a schematic diagram of an execution instruction rule according to an embodiment of the present invention.

Figure 5 is a schematic diagram of a bus direct interruption service device according to another embodiment of the present invention.

In order to facilitate understanding of the technical features, contents and advantages of the present invention as well as the effects it can achieve, the present invention is described in detail below in conjunction with the accompanying drawings and in the form of embodiments. The drawings used therein are only for their main purpose. They are for illustration and auxiliary description purposes, and may not represent the actual proportions and precise configurations after implementation of the present invention. Therefore, the proportions and configuration relationships of the attached drawings should not be interpreted to limit the scope of rights of the present invention in actual implementation. Description.

Please refer to Figure 1. Figure 1 is a schematic diagram of a bus direct interruption service device according to an embodiment of the present invention. As shown in the figure, the bus direct interrupt service device 10 is coupled to the processor 20. It can be coupled through circuit connection or by adding relevant devices of the bus direct interrupt service device 10 to the processor chip during design. components within the original processor 20. The processor 20 has a receiving end for receiving the interrupt request IR. In the existing processing method, after receiving the interrupt request IR, the processor 20 needs to enter the status register and go through Fetch, Decode, and Execute. (Execute) and other interrupt service routines (ISR), the corresponding instructions are sent to the bus interface unit 21, output to the connected device through the connection interface, and the control device performs operations corresponding to the interrupt request IR. However, the original operation method requires many clock cycles to actually trigger the device operation, which may cause delays and errors in devices that need to perform operations immediately.

In this regard, the present disclosure provides a bus direct interrupt service device 10 to solve the above problem. The bus direct interrupt service device 10 includes an interrupt instruction register 11 and an interrupt request multiplexer 12. The interrupt instruction register 11 is coupled to the processor. At the receiving end of 20 , the interrupt request multiplexer 12 is coupled to the bus interface unit 21 of the processor 20 . When the processor 20 receives an interrupt request IR, the interrupt instruction register 11 receives the same interrupt request IR. The interrupt instruction register 11 compares the received interrupt request IR with a plurality of internally stored interrupt instructions. If the comparison is When the same interrupt instruction is received, the bus location and operation instruction corresponding to the interrupt instruction stored in the original register bank are output.

Please refer to Figure 2. Figure 2 is a schematic diagram of an interrupt command register according to an embodiment of the present invention. As shown in the figure, the interrupt instruction register 11 stores a plurality of interrupt instructions 111. Each interrupt instruction 111 stores the corresponding bus location 112 as the interrupt address, and stores the operation instruction 113 directly executed in the interrupt instruction 111. For example, when the interrupt request IR enters the interrupt instruction register 11 and the interrupt request IR is compared with the interrupt instruction 111 with storage number 1, the corresponding address of the first peripheral is compared with the execution address. The first instruction of the line operation is output, and after passing through the multiplexer, the output interface finally directly performs the first instruction operation on the connected first peripheral. Similarly, if the interrupt instruction 111 with number 2 is compared, the second peripheral and the second instruction are output, and so on for the others.

In this embodiment, the output bus location 112 is the address corresponding to the peripheral device, and the operation command 113 is an instruction command directly executed by the device. When output from the output interface 13 through the multiplexer, it does not need to go through the original processor. 20 internally enters the storage array and performs steps such as acquisition, decoding, and execution, but directly outputs the interrupt control instruction. The interrupt request IR can be directly converted into the required interrupt service and output to the corresponding peripheral device. The operation timeliness meets the requirements of the interrupt request IR and avoids the time delay caused by the interrupt service handler of the processor 20 and the device operation. error. Therefore, for the interrupt request IR that has immediate operation requirements for the operation of peripheral devices, the bus location 112 of the corresponding device and the directly executed operation command 113 can be stored in the interrupt command register 11 in advance, allowing these interrupts to Request IR can be directly converted into interrupt control instructions to achieve timeliness of immediate operations.

Returning to Figure 1, when the interrupt instruction register 11 receives the interrupt request IR, it selects the corresponding bus position and operation instruction from the plurality of interrupt instructions as the interrupt control instruction, and transmits it to the interrupt request multiplexer 12. The interrupt request multiplexer 12 is coupled to the interrupt command register 11. When the interrupt request multiplexer 12 receives the interrupt control command transmitted by the interrupt command register 11, it directly transmits the operation command corresponding to the interrupt control command from the output interface 13 to the corresponding bus position, and performs an interrupt request operation on the peripheral device 22 . The output interface 13 here can be an interface from an Advanced Extensible Interface (AXI) to multiple Advanced High Performance Buses (AHB), and is connected to an external peripheral device 22 through the output interface 13, such as a conversion devices, sensors, memories, etc.

In this disclosure, the bus direct interruption service device 10 can be used as an ultrasonic flow meter, which is installed on the waterway. After the ultrasonic wave is emitted by the ultrasonic generating device, the echo is sampled by the sampling device to detect the flow rate in the waterway. When the ultrasonic wave generating device emits ultrasonic waves, the analog-to-digital converter must be triggered within a predetermined echo time to perform sampling. The analog-to-digital converter is a peripheral device 22 connected to the processor 20. If the interrupt request IR is processed through the original interrupt request service program in the processor 20, when it is transmitted to the peripheral device 22, the predetermined echo time may have exceeded. The sample may not be the first echo, causing the device to deviate when judging the flow rate. In this embodiment, the interrupt request IR for echo sampling can be directly converted into an interrupt control instruction that can be directly executed by the output interface 13 through the interrupt instruction register 11 to instantly trigger the digital-to-analog converter for echo sampling. , so that the collected echo samples can correctly reflect the flow rate status of the waterway, and achieve the effect of accurately detecting the flow rate. In this disclosure, an ultrasonic flow meter is used as an example, but the disclosure is not limited thereto. The bus direct interrupt service device 10 of the disclosure may be applied to other peripheral devices 22 that need to process interrupt request IR in real time.

In addition to being coupled to the interrupt instruction register 11, the interrupt request multiplexer 12 is also coupled to the bus interface unit 21 of the processor 20. When the interrupt request IR does not have urgent timing requirements, it can still be processed through the original process. The processor 20 converts the interrupt request IR into a processor control instruction through the interrupt service handler, transmits it to the interrupt request multiplexer 12 through the bus interface unit 21, and then outputs it to the corresponding peripheral device 22 through the output interface 13. The interrupt request multiplexer 12 can sequentially output the received interrupt control instructions or processor control instructions in a first-in-first-out manner. In another embodiment, the interrupt request multiplexer 12 can also output the received interrupt control instructions or processor control instructions in a first-in-first-out manner. The instruction processing rules are set in 12. The following embodiments will further illustrate the setting features of the interrupt request multiplexer 12.

Please refer to Figure 3. Figure 3 is a schematic diagram of an interrupt request multiplexer according to an embodiment of the present invention. As shown in the figure, the interrupt request multiplexer 12 sets an instruction temporary storage area 121, and the instruction temporary storage area 121 is coupled to The bus interface unit 21, when the interrupt request multiplexer 12 receives the interrupt control instructions from the interrupt instruction register 11 and the processor control instructions from the bus interface unit 21, the interrupt request multiplexer 12 processes the interrupt control instructions first to avoid The content of the operation being performed is delayed. At this time, the processor control instructions received at the same time will be temporarily stored in the instruction temporary storage area 121 to form a temporary storage area control instruction. The temporary storage area control instructions can wait until the interrupt request multiplexer 12 completes executing the interrupt control instructions before executing these temporary storage area control instructions.

In order to execute instructions according to the designed priority order, the interrupt request multiplexer 12 is also provided with an arbiter 122, which is coupled to the interrupt instruction register 11, the instruction temporary storage area 121 and the bus interface unit 21. The arbiter 122 stores the judgment The instruction priority order execution instruction rules determine the execution order of instructions transmitted by the interrupt instruction register 11 , the instruction temporary storage area 121 and the bus interface unit 21 through the setting of the instruction execution rules. Please also refer to Figure 4. Figure 4 is a schematic diagram of an execution instruction rule according to an embodiment of the present invention. As shown in the figure, the arbiter 122 stores execution instruction rules 123, and the execution instruction rules 123 define a rule table of interrupt control instructions 124, temporary storage area control instructions 125, and processor control instructions 126. By executing the rule table of the instruction rule 123, it is decided which instruction to push to the output interface 13, and the peripheral device is operated to perform the operation action of the interrupt request IR. Among them, 1 in the rule table indicates push instructions, 0 indicates no instructions received, and X indicates no instructions pushed.

First of all, in order to ensure the execution timeliness of the interrupt instruction register 11, the interrupt control instruction 124 transmitted by the interrupt instruction register 11 has the highest priority. That is to say, when the arbiter 122 receives the interrupt control instruction 124, regardless of whether there is a temporary Neither the storage control instruction 125 nor the processor control instruction 126 will push instructions, and only the interrupt control instruction 124 will be processed first. At this time, if there is a temporary storage area control instruction 125 in the instruction temporary storage area 121, the temporary storage area control instruction 125 is maintained, and the push is not performed. If the processor control instruction 126 is received, it is converted into a temporary storage area control instruction 125, and is queued into the temporary storage area. In storage area 121.

When the arbiter 122 completes pushing all the interrupt control instructions 124 and does not receive a new interrupt control instruction 124, at this time, the temporary area control instruction 125 in the instruction temporary area 121 will be processed first, and the temporary area control instruction 125 will be processed first. 125 can push instructions in a first-in, first-out order. During execution, if a processor control instruction 126 is received, it will also be converted into a temporary storage area control instruction 125 and placed in the instruction temporary storage area 121.

After the arbiter 122 has pushed all the temporary area control instructions 125, if neither the interrupt instruction register 11 nor the instruction temporary area 121 transmits new instructions, if the bus interface unit 21 transmits the processor control instruction 126, There is no need to convert the buffer control instruction 125 into the temporary storage area control instruction 125 , and the arbiter 122 directly pushes the processor control instruction 126 to the output interface 13 .

Please refer to Figure 5. Figure 5 is a schematic diagram of a bus direct interruption service device according to another embodiment of the present invention. As shown in the figure, the bus direct interrupt service device 30 is coupled to the processor 40. The bus direct interrupt service device 30 includes an interrupt instruction register 31 and an interrupt request multiplexer 32. The interrupt instruction register 31 is coupled to the processor. The receiving end of the device 40 receives the interrupt request IR, and the interrupt instruction register 31 stores a plurality of interrupt instructions and the bus positions and operation instructions corresponding to each plurality of interrupt instructions. When the receiving end receives the interrupt request IR, the interrupt instruction register 31 The interrupt control instruction corresponding to the interrupt request IR is selected from a plurality of interrupt instructions.

The interrupt request multiplexer 32 is coupled to the bus interface unit of the processor 40 and the interrupt command register 31. When the interrupt request multiplexer 32 receives the interrupt control command, the operation command corresponding to the interrupt control command is directly sent from the output interface 33 to At the corresponding bus position, the interrupt request operation is performed on the peripheral device 42 .

In this embodiment, although the bus direct interrupt service device 30 is coupled to the processor 40, the bus direct interrupt service device 30 and the processor 40 may be coupled to different power supplies, as shown in the figure. As shown, the processor 40 can be powered by the processor power supply 41, and the bus direct interrupt service device 30 can be powered by the device power supply 34, that is, the interrupt instruction register 31 and the interrupt request multiplexer 32 in the bus direct interrupt service device 30 are located therein. The power domain in which the processor 40 is located is different from the power domain in which the processor 40 is located. When the processor 40 is in a sleep or shutdown state, the processor power supply 41 can be turned off or only partially powered to reduce the power consumption of the device. At this time, the interrupt request IR will not be converted into an execution instruction by the interrupt service handler of the processor 40. The interrupt request multiplexer 32 will not receive processor control instructions.

However, since the bus direct interrupt service device 30 is powered by an independent device power supply 34, when an interrupt request IR is received, the interrupt instruction register 31 can still transmit the interrupt control instruction corresponding to the interrupt request IR. The multiplexer 32 transmits the information to the corresponding bus device through the output interface 33, thereby controlling the operation of the corresponding peripheral device 42. That is to say, when the device is in hibernation or shut down, the interrupt service device 30 can still directly execute part of the pre-stored interrupt request IR through the bus without going through the interrupt service handler of the processor 40, thus reducing the time required to turn on the processor 40 and The power consumed achieves the effect of power saving when executing the operation of the peripheral device 42 .

The above is only illustrative and not restrictive. Any equivalent modifications or changes that do not depart from the spirit and scope of the present invention shall be included in the appended patent scope.

10: Bus direct interrupt service device

11: Interrupt instruction register library

12: Interrupt request multiplexer

13:Output interface

20: Processor

21:Bus interface unit

22:Peripheral devices

IR: interrupt request

Claims (10)

A bus direct interrupt service device is coupled to a bus interface unit of a processor. The processor has a receiving end for receiving an interrupt request. The bus direct interrupt service device includes: an interrupt instruction register, Coupled to the receiving end of the processor, the interrupt instruction register stores a plurality of interrupt instructions and a bus location corresponding to each of the plurality of interrupt instructions and an operation instruction. When the receiving end of the processor receives the interrupt When requesting, the interrupt instruction register receives the same interrupt request through the coupled receiving end, and selects an interrupt control instruction corresponding to the interrupt request from among the plurality of interrupt instructions; an interrupt request multiplexer is coupled to in the bus interface unit and the interrupt command register; and an output interface coupled to the interrupt request multiplexer and a peripheral device; wherein, after the interrupt request multiplexer receives the interrupt control command, it passes the output The interface sends the operation command corresponding to the interrupt control command to the peripheral device corresponding to the bus location to execute the operation requested by the interrupt. The bus direct interrupt service device as claimed in claim 1, wherein the interrupt request multiplexer receives a processor control command from the processor through the bus interface unit, and the output interface outputs the processor control command. The bus direct interrupt service device as described in claim 2, wherein the interrupt request multiplexer includes an instruction temporary storage area coupled to the bus interface unit, when the interrupt request multiplexer receives the interrupt control instruction , the processor control command received at the same time is temporarily stored in the command temporary storage area, forming a temporary storage area control command. The bus direct interrupt service device as described in claim 3, wherein the interrupt request multiplexer includes an arbiter coupled to the interrupt command register, the command temporary area and the bus interface unit, and the arbiter Store an instruction execution rule for the interrupt instruction register, the instruction temporary area and the bus interface unit. The bus direct interrupt service device as described in claim 4, wherein the order of priority of the instruction execution rule is the interrupt control instruction, the temporary storage area control instruction and the processor control instruction. The bus direct interrupt service device of claim 1, wherein the output interface includes an advanced extensible interface to an interface of a plurality of advanced high-performance buses. The bus direct interrupt service device as described in claim 1, wherein the peripheral device includes an analog-to-digital converter, and the operation command triggers the analog-to-digital converter to perform echo sampling. The bus direct interrupt service device of claim 1, wherein the interrupt instruction register and the interrupt request multiplexer are coupled to a power supply different from that of the processor. The bus direct interrupt service device as described in claim 1, wherein the interrupt instruction register and the interrupt request multiplexer are located in a power domain different from the power domain where the processor is located. The bus direct interrupt service device as claimed in claim 1, wherein the operations of the interrupt instruction register and the interrupt request multiplexer are independent of the operation of the processor.