TWI806263B - Electronic package and manufacturing method thereof - Google Patents

Abstract

An electronic package comprises an electronic structure with a plurality of conductive bodies, a plurality of conductive pillars, a protective layer covering the conductive bodies and the conductive pillars, and a encapsulating layer encapsulating the electronic structure, the protective layer and the conductive pillars. When the encapsulating layer is grinded, the surroundings of the conductive pillars and the conductors are restricted by the protective layer without copper burr, so that the conductive pillars and the conductors do not form with burr structure, so it can avoid the problem of short circuit during subsequent electrical testing.

Description

Electronic package and its manufacturing method

The invention relates to a semiconductor device, in particular to an electronic package and its manufacturing method.

In order to ensure the continued miniaturization and multi-functionality of electronic products and communication equipment, semiconductor packages need to be miniaturized to facilitate multi-pin connections and have high functionality. For example, in advanced process packaging, commonly used packaging types such as 2.5D packaging process, fan-out (Fan-Out) wiring combined with the process of embedded bridge (Embedded Bridge) components (referred to as FO-EB), among them, FO-EB Compared with the 2.5D packaging process system, it has the advantages of low cost and more material suppliers.

FIG. 1 is a schematic cross-sectional view of a semiconductor package 1 of a conventional FO-EB. The semiconductor package 1 is provided with a first semiconductor chip 11 (via adhesive 12 ) and a plurality of conductive pillars 13 on a substrate structure 14 with a circuit layer 140 , and then covers the first semiconductor with a first packaging layer 15 chip 11 and these conductive pillars 13, and then form a circuit structure 10 electrically connecting the first semiconductor chip 11 and these conductive pillars 13 on the first packaging layer 15, so as to arrange a plurality of circuits on the circuit structure 10. Connect the second semiconductor chips 16 of the circuit structure 10, and cover the second semiconductor chips 16 with a second encapsulation layer 18, wherein the circuit layer 140 and the circuit structure 10 adopt fan-out redistribution circuits layer (redistribution layer, referred to as RDL), and the first semiconductor chip 11 is used as a bridge die embedded in the first packaging layer 15 to electrically bridge two adjacent second semiconductor chips 16 .

The above-mentioned semiconductor package 1 mainly uses the substrate structure 14 to be placed on a packaging substrate 1a through a plurality of solder balls 17, and the conductive columns 13 are electrically connected to the circuit layer 140, and the packaging substrate 1a is connected to the packaging substrate 1a by soldering. The ball 19 is connected to a circuit board (not shown).

However, in the conventional semiconductor package 1, after the first packaging layer 15 wraps the first semiconductor chip 11 and the conductive pillars 13, the large copper pillar (that is, the conductive pillar 13) and the conductive pillars 13 will be ground by grinding. The small copper column (i.e. conductor 110) of the first semiconductor wafer 11 grinds out a contour plane, so during the grinding process, the grinding wheel or the grinding liquid will pull the soft material such as copper along the grinding tangent direction, which is the so-called The extension of copper (Cu burr) causes the conductive pillar 13 and the conductor 110 to expand outward to form a filamentary (burr) structure Z, causing a short circuit problem during subsequent electrical testing.

Therefore, how to overcome the problems of the above-mentioned conventional technologies has become an urgent problem to be solved at present.

In view of the various deficiencies of the above-mentioned conventional technologies, the present invention provides an electronic package, which includes: a cladding layer; an electronic structure embedded in the cladding layer and having a plurality of conductors; a plurality of conductive pillars embedded In the coating layer; and a protective layer, which is embedded in the coating layer and covers the plurality of conductors and the plurality of conductive columns, and makes part of the surface of the plurality of conductors and part of the surface of the plurality of conductive columns The protective layer and the covering layer are exposed.

The present invention also provides a method for manufacturing an electronic package, which includes: disposing a plurality of conductive pillars and an electronic structure with a plurality of conductors on a carrier; forming a protective layer on the electronic structure and On the plurality of conductive columns, so that the protective layer covers the plurality of conductors and the plurality of conductive columns; a coating layer is formed on the carrier, so that the coating layer covers the electronic structure, the protective layer and the plurality of conductive columns. The plurality of conductive pillars, and exposing the protection layer and the coating layer on the surface of the end surfaces of the plurality of conductive bodies and the ends of the plurality of conductive pillars; and removing the bearing member.

In the aforementioned electronic package and its manufacturing method, a flattening process is included, so that one surface of the cladding layer is flush with the surface of the protective layer, the surface of the end of the conductive post and the end surface of the conductor. For example, the leveling process removes part of the material of the protection layer and part of the material of the cladding layer by grinding. Further, the length of the protective layer covering the end of the conductive pillar is greater than the grinding depth.

In the aforementioned electronic package and its manufacturing method, the distance between adjacent conductive columns is less than 150 microns.

In the aforementioned electronic package and its manufacturing method, the protective layer is an insulating material.

In the aforementioned electronic package and its manufacturing method, the protective layer covers the ends of the conductive pillars but does not cover the entirety of the conductive pillars.

In the aforementioned electronic package and its manufacturing method, the length of the protective layer covering the conductive column is longer than the length of the protective layer covering the conductor.

In the aforementioned electronic package and its manufacturing method, the hardness of the protective layer is greater than that of the conductor.

In the aforementioned electronic package and its manufacturing method, the hardness of the protective layer is greater than that of the conductive pillar.

In the aforementioned electronic package and its manufacturing method, the hardness of the protective layer is greater than 400Mpa.

In the aforementioned electronic package and its manufacturing method, further comprising forming a circuit structure on the cladding layer and the protective layer, so that the circuit structure is electrically connected to the plurality of conductive pillars and the plurality of conductors. Further, it may include disposing electronic components on the circuit structure, and the electronic components are electrically connected to the circuit structure.

In the aforementioned electronic package and its manufacturing method, further comprising forming a wiring structure on the cladding layer, so that the wiring structure electrically connects the plurality of conductive pillars and the electronic structure. Further, it may include forming a plurality of conductive elements on the wiring structure, and the plurality of conductive elements are electrically connected to the wiring structure.

It can be seen from the above that in the electronic package and its manufacturing method of the present invention, the plurality of conductors and the plurality of conductive columns are mainly covered by the protective layer, so that when the leveling process is performed, the surroundings of the conductive columns and the conductors are Restricted by the protective layer, copper extension will not occur, so that the conductive pillar and the conductor will not expand outward into a filamentous structure. Therefore, compared with the conventional technology, the present invention can not only avoid the subsequent electrical testing. The problem of short circuit occurs, and when the distance between the conductive columns is shortened, the problem of short circuit of these conductive columns will not be caused.

1: Semiconductor package

1a,30: Package substrate

10,20: Line structure

11: The first semiconductor wafer

110,21a: Conductor

12: Viscose

13,23: Conductive column

14: Substrate structure

140,241: line layer

15: The first encapsulation layer

16: Second semiconductor wafer

17,19: solder ball

18: Second encapsulation layer

2,3,4: Electronic Packages

2a: Electronic structure

200: insulating layer

201: Line redistribution layer

202: Electrical contact pad

21: Electronic subject

210: Conductive perforation

22: Line Department

22a: external bump

22b: bonding layer

220: passivation layer

221: Conductive trace

23a: end

24: Wiring structure

24a: First side

24b: Second side

240: dielectric layer

25: cladding layer

25a: first surface

25b: second surface

26: Electronic components

26a: Conductive bump

260: Solder material

262: primer

27,300: Conductive components

27a: Under-bump metal layer

270: metal bump

271: Solder material

28: Encapsulation layer

29: Protective layer

31: Strong firmware

49: Overlay

9: Bearing parts

90: release layer

91: metal layer

d: depth

H, L1, L2: Length

S: cutting path

t: spacing

Z: filamentous structure

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package.

2A to 2F are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

FIG. 3 is a schematic cross-sectional view of the subsequent manufacturing process of FIG. 2F.

4A to 4B are schematic cross-sectional views of another manufacturing method corresponding to FIGS. 2A to 2F .

The implementation of the present invention is described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for the understanding and reading of those familiar with this technology, and are not used to limit the implementation of the present invention Therefore, it has no technical substantive meaning. Any modification of structure, change of proportional relationship or adjustment of size will not affect the effect and purpose of the present invention. below, all should still fall within the scope covered by the technical content disclosed in the present invention. At the same time, terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall also be regarded as the applicable scope of the present invention if there is no substantial change in the technical content.

2A to 2F are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A , a carrier 9 is provided, and an electronic structure 2 a and a plurality of conductive pillars 23 are disposed on the carrier 9 , and a protection layer 29 is formed on the electronic structure 2 a and the conductive pillars 23 .

The carrier 9 is, for example, a plate of semiconductor material (such as silicon or glass), on which a release layer 90 and a metal layer 91 such as titanium/copper are sequentially formed by, for example, coating, for a wiring The structure 24 is formed on the metal layer 91 .

In this embodiment, the wiring structure 24 has opposite first side 24 a and second side 24 b, and the wiring structure 24 is combined with the metal layer 91 by its second side 24 b.

Furthermore, the wiring structure 24 includes at least one dielectric layer 240 and a wiring layer 241 combined with the dielectric layer 240 . For example, the material forming the dielectric layer 240 is such as polybenzoxazole (Polybenzoxazole, referred to as PBO), polyimide (Polyimide, referred to as PI), prepreg (Prepreg, referred to as PP) or other dielectric materials. material, and the wiring layer 241 and the dielectric layer 240 can be formed by a wiring redistribution layer (redistribution layer, RDL for short) process.

The electronic structure 2a includes an electronic body 21, a circuit part 22, a plurality of conductors 21a formed on the electronic body 21, and a plurality of conductors 21a formed on the circuit part 22 and electrically connected to the circuit part 22 and the circuit Layer 241 circumscribes the bumps 22a, wherein a bonding layer 22b is formed on the circuit portion 22 to cover the circumscribed bumps 22a, so that the electronic structure 2a is bonded to the wiring structure 24 with the bonding layer 22b thereon on the first side 24a, and the circumscribed bump 22a is bonded to the circuit layer 241.

In this embodiment, the electronic main body 21 is a silicon substrate, such as a semiconductor wafer, which has a plurality of conductive through holes 210 penetrating through the electronic main body 21, such as a conductive through-silicon via (Through-silicon via, TSV for short), to electrically connect the line portion 22 and the plurality of conductors 21a. For example, the circuit part 22 includes at least one passivation layer 220 and a conductive trace 221 combined with the passivation layer 220, so that the conductive trace 221 electrically connects the conductive through hole 210 and the plurality of external bumps 22a. It should be understood that the structure of the device having the conductive through hole 210 can be various, and there is no special limitation.

Furthermore, the conductor 21a and the external bump 22a are metal pillars such as copper pillars, and the bonding layer 22b is a non-conductive film (Non-Conductive Film, referred to as NCF) or other materials that are easy to adhere to the dielectric layer 240 material.

The conductive column 23 is disposed on the first side 24 a of the wiring structure 24 and electrically connected to the circuit layer 241 .

In this embodiment, the material forming the conductive pillars 23 is metal material such as copper or solder material, and the distance t between adjacent conductive pillars 23 is less than 150 microns (um). For example, the conductive pillars 23 are formed by electroplating on the circuit layer 241 by exposure and development.

The protective layer 29 is an insulating material, such as nitride (silicon nitride (SiN)), and the protective layer 29 covers the peripheral surface of the end 23a of the conductive column 23 without covering the conductive column 23. The entire peripheral surface of the column, and the protective layer 29 covers the entire peripheral surface of the conductor 21a.

In this embodiment, the hardness of the protective layer 29 is greater than the hardness of the conductor 21a (such as a copper pillar) and the hardness of the conductive pillar 23 (such as a copper pillar). For example, the hardness of the protective layer 29 is greater than 400Mpa.

As shown in FIG. 2B, a cladding layer 25 is formed on the first side 24a of the wiring structure 24, so that the cladding layer 25 covers the electronic structure 2a, the protective layer 29 and the conductive pillars 23, wherein , the coating layer 25 has opposite first surface 25a and second surface 25b, and the surface of the protective layer 29, the end surface of the conductor 21a and the end portion 23a of the conductive post 23 are exposed to the coating layer The first surface 25a of the wiring structure 25, and the cladding layer 25 is bonded to the first side 24a of the wiring structure 24 with its second surface 25b.

In this embodiment, the cladding layer 25 is an insulating material, such as polyimide (polyimide, PI for short), dry film (dry film), packaging colloid or packaging material (molding) such as epoxy resin (epoxy). compound). For example, the manufacturing process of the cladding layer 25 can be formed on the wiring structure 24 by means of liquid compound, injection, lamination or compression molding.

Furthermore, the first surface 25a of the cladding layer 25 can be flushed with the top surface of the protective layer 29, the surface of the end 23a of the conductive pillar 23, and the end surface of the conductor 21a through a leveling process, so as to The surface of the end portion 23a of the conductive pillar 23 and the end surface of the conductor 21a are exposed to the first surface 25a of the coating layer 25 . For example, the leveling process removes part of the material of the protection layer 29 , part of the material of the conductive pillar 23 , part of the material of the conductor 21 a and part of the material of the cladding layer 25 by grinding. Further, the length H of the protection layer 29 covering the end portion 23a of the conductive pillar 23 is greater than the grinding depth d of the leveling process, as shown in FIG. 2A .

Moreover, the length L2 of the protection layer 29 covering the conductive column 23 is greater than the length L1 of the protection layer 29 covering the conductor 21a. For example, the difference between the two lengths L1 and L2 is at least 10 microns (ie L2-L1≧10).

As shown in FIG. 2C , a circuit structure 20 is formed on the first surface 25 a of the cladding layer 25 and the protection layer 29 , so that the circuit structure 20 is electrically connected to the conductive pillar 23 and the conductor 21 a.

In this embodiment, the circuit structure 20 includes at least one insulating layer 200 and a redistribution layer (redistribution layer, RDL) 201 disposed on the insulating layer 200, wherein the outermost insulating layer 200 can be used as an anti- Solder layer, and expose the solder resist layer on the outermost circuit redistribution layer 201 to serve as electrical contact pads 202, such as micro pads (commonly known as μ-pad).

Moreover, the material forming the line redistribution layer 201 is copper, and the material forming the insulating layer 200 is such as polybenzoxazole (Polybenzoxazole, PBO for short), polyimide (Polyimide, PI for short), Dielectric materials such as prepreg (PP for short), or solder resist materials such as green paint and ink.

As shown in FIG. 2D , a plurality of electronic components 26 are disposed on the circuit structure 20 , and then an encapsulation layer 28 is used to cover the electronic components 26 .

In this embodiment, the electronic component 26 is an active component, a passive component or a combination thereof, and the active component is such as a semiconductor chip, and the passive component is such as a resistor, a capacitor and an inductor. In one embodiment, the electronic component 26 is, for example, a semiconductor chip such as a graphics processing unit (GPU for short), a high bandwidth memory (High Bandwidth Memory, HBM for short), and the electronic structure 2a is used as a bridging component. (Bridge die), which is electrically connected to the circuit structure 20 through the conductor 21a to electrically bridge at least two electronic components 26 .

Moreover, the electronic component 26 has a plurality of conductive bumps 26a such as copper pillars, so as to electrically connect the electrical contact pads 202 with a plurality of solder materials 260 such as solder bumps, and the packaging layer 28 can be coated at the same time. The electronic components 26 and the conductive bumps 26a. In this embodiment, an Under Bump Metallurgy (UBM) (not shown) may be formed on the electrical contact pad 202 or the electronic component 26 to facilitate the bonding of the solder material 260 or the conductive bump 26a.

Also, the packaging layer 28 is an insulating material, such as polyimide (polyimide, referred to as PI), dry film (dry film), packaging colloid or packaging material (molding compound) such as epoxy resin (epoxy), which can be used Lamination or molding is formed on the circuit structure 20 . It should be understood that the material forming the encapsulation layer 28 may be the same as or different from the material of the cladding layer 25 .

In addition, the primer 262 may be formed between the electronic component 26 and the circuit structure 20 to cover the conductive bumps 26a and the solder material 260, and then the packaging layer 28 is formed to cover the primer 262 and the solder material 260. electronic components 26.

As shown in FIG. 2E , the carrier 9 and the release layer 90 thereon are removed, and then the metal layer 91 is removed to expose the second side 24 b of the wiring structure 24 .

In this embodiment, when the release layer 90 is peeled off, the metal layer 91 is used as a barrier to avoid damaging the dielectric layer 240 of the wiring structure 24, and the carrier 9 and its components are to be removed. After the release layer 90 is formed, the metal layer 91 is removed by etching, so that the circuit layer 241 is exposed.

As shown in FIG. 2F, the singulation process is performed along the cutting path S shown in FIG. 2E, and a plurality of conductive elements 27 are formed on the second side 24b of the wiring structure 24, so that these conductive elements 27 are electrically connected to the circuit. layer 241 to produce an electronic package 2 .

In this embodiment, the conductive element 27 includes a metal bump 270 such as copper and a solder material 271 formed on the metal bump 270 . For example, an under bump metallization (UBM) 27 a may be formed on the circuit layer 241 to facilitate the bonding of the metal bump 270 . It should be understood that when the number of contacts (IOs) is insufficient, the layer-up operation can still be performed through the RDL process to reconfigure the number and positions of the IOs of the wiring structure 24 .

Furthermore, part of the material of the encapsulation layer 28 can be removed by a leveling process, such as grinding, so that the upper surface of the encapsulation layer 28 is flush with the upper surface of the electronic component 26, as shown in FIG. 3 , so that The electronic component 26 exposes the encapsulation layer 28 .

Moreover, as shown in FIG. 3 , the conductive elements 27 can be disposed on a packaging substrate 30 . Further, the lower side of the packaging substrate 30 is subjected to a ball planting process to form a plurality of conductive elements 300 such as solder balls for subsequent manufacturing processes. The conductive elements 300 on the lower side of the packaging substrate 30 are arranged on a circuit board (not shown). superior.

In addition, a strong member 31 can be provided on the package substrate 30 as required, such as a metal frame as shown in FIG. 3 , to eliminate the problem of stress concentration and prevent the electronic package 3 from warping.

Therefore, the manufacturing method of the present invention mainly wraps the plurality of conductors 21a and the plurality of conductive pillars 23 by the protective layer 29, and the hardness of the protective layer 29 is greater than that of copper, so as to perform leveling as shown in FIG. 2B During the manufacturing process, copper extension will not occur around the large copper pillar (i.e. the conductive pillar 23) and the small copper pillar (i.e. the conductor 21a) due to the limitation of the protective layer 29, so compared with the prior art, this The conductive column 23 of the invention and the The conductor 21 a does not expand outwards into a filamentary structure, thus avoiding short circuit problems during subsequent electrical testing (such as electrical failure of the circuit redistribution layer 201 of the circuit structure 20 ).

Furthermore, because the protective layer 29 can prevent the plurality of conductors 21a and the plurality of conductive columns 23 from producing copper extension, so when the distance t between each of the conductive columns 23 is shortened, these conductive columns 23 will not be short-circuited. question.

Moreover, since the protection layer 29 is harder than copper, the protection layer 29 can also be a hard metal material, but the protection layers 29 between the conductive pillars 23 (or the conductors 21 a ) need to be separated from each other.

In addition, as shown in FIG. 4A , in the manufacturing process of FIG. 2A , the protection layer 29 is only formed on a part of the surface of the electronic structure 2 a and does not cover the entire top surface of the electronic body 21 . For example, the protective layer 29 is first formed along the peripheral surface and end surface of the conductor 21a, and then the protective layer 29 is covered with a covering layer 49, wherein the covering layer 49 is an insulating film, polyimide (Polyimide, referred to as PI) material, non-conductive film (Non-Conductive Film, NCF for short) or other insulating materials. Afterwards, another electronic package 4 is obtained according to the processes shown in FIGS. 2B to 2F , as shown in FIG. 4B . Therefore, the electronic structure 2a can cover the entire top surface of the electronic body 21 through two coating operations.

The present invention also provides an electronic package 2 , 4 , which includes: a cladding layer 25 , an electronic structure 2 a with a plurality of conductors 21 a , a plurality of conductive pillars 23 , and a protective layer 29 .

The electronic structure 2 a is embedded in the cladding layer 25 .

The conductive pillars 23 are embedded in the cladding layer 25 .

The protective layer 29 is embedded in the cladding layer 25 and covers the plurality of conductors 21a and the plurality of conductive columns 23, and makes part of the surface of the plurality of conductors 21a and part of the surface of the plurality of conductive columns 23 The protective layer 29 and the cladding layer 25 are exposed.

In one embodiment, the first surface 25a of the cladding layer 25 is flush with a surface of the protective layer 29 , a surface of the end portion 23a of the conductive pillar 23 and an end surface of the conductor 21a.

In one embodiment, the distance t between adjacent conductive pillars 23 is less than 150 microns.

In one embodiment, the protective layer 29 is an insulating material.

In one embodiment, the protective layer 29 covers the end portion 23 a of the conductive column 23 but does not cover the entire conductive column 23 .

In one embodiment, the length L2 of the protection layer 29 covering the conductive pillar 23 is greater than the length L1 of the protection layer 29 covering the conductor 21a.

In one embodiment, the hardness of the protection layer 29 is greater than that of the conductor 21a.

In one embodiment, the hardness of the protective layer 29 is greater than that of the conductive pillar 23 .

In one embodiment, the hardness of the protective layer 29 is greater than 400Mpa.

In one embodiment, the electronic package 2 further includes a circuit structure 20 formed on the cladding layer 25 and the protective layer 29, so that the circuit structure 20 is electrically connected to the plurality of conductive columns 23 and the Plural conductors 21a. Further, the electronic package 2 , 3 may further include at least one electronic component 26 disposed on the circuit structure 20 and electrically connected to the circuit structure 20 .

In one embodiment, the electronic package 2 further includes a wiring structure 24 formed on the cladding layer 25, so that the wiring structure 24 electrically connects the plurality of conductive pillars 23 and the electronic structure 2a. Further, the electronic package 2 may further include a plurality of conductive elements 27 formed on the wiring structure 24 and electrically connected to the wiring structure 24 .

To sum up, the electronic package of the present invention and its manufacturing method are based on the design of the protective layer, so that when the leveling process is performed, the surroundings of the conductive pillars and conductors will not be affected by the restrictions of the protective layer. Copper extension is generated, so that the conductive pillar and the conductor will not expand outward to form a filamentous structure, so the electronic package of the present invention can avoid the problem of short circuit during subsequent electrical testing, and when shortening the distance between each conductive pillar When the spacing is fixed, the problem of short circuit of these conductive columns will not be caused.

The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person familiar with the art can, without departing from the spirit and scope of the present invention, The above embodiments are modified. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of the patent application described later.

2: Electronic package

2a: Electronic structure

20: Line structure

21: Electronic subject

21a: Conductor

22: Line Department

22a: external bump

22b: bonding layer

23: Conductive column

24: Wiring structure

241: line layer

25: cladding layer

26: Electronic components

27: Conductive element

27a: Under-bump metal layer

270: metal column

271: Solder material

28: Encapsulation layer

29: Protective layer

Claims (28)

An electronic package, comprising: a cladding layer; an electronic structure embedded in the cladding layer and having a plurality of conductors; a plurality of conductive columns embedded in the cladding layer; and a protective layer embedded in the cladding layer. Buried in the covering layer and directly covering the plurality of conductors and the plurality of conductive pillars at the same time, and exposing part of the surface of the plurality of conductors and the plurality of conductive pillars to the protective layer and the covering layer. The electronic package according to claim 1, wherein a surface of the cladding layer is flush with a surface of the protective layer, a surface of the end of the conductive post, and an end surface of the conductor. The electronic package as claimed in claim 1, wherein the distance between adjacent conductive pillars is less than 150 microns. The electronic package according to claim 1, wherein the material forming the protective layer is an insulating material. The electronic package as claimed in claim 1, wherein the protective layer covers the ends of the conductive pillars but does not cover the entire conductive pillars. The electronic package according to claim 1, wherein the length of the protective layer covering the conductive column is longer than the length of the protective layer covering the conductor. The electronic package as claimed in claim 1, wherein the hardness of the protective layer is greater than that of the conductor. The electronic package as claimed in claim 1, wherein the hardness of the protective layer is greater than that of the conductive pillar. The electronic package as claimed in claim 1, wherein the hardness of the protective layer is greater than 400Mpa. The electronic package as claimed in claim 1 further includes a circuit structure formed on the cladding layer and the protective layer and electrically connecting the plurality of conductive columns and the plurality of conductors. The electronic package as claimed in claim 10 further includes electronic components disposed on the circuit structure and electrically connected to the circuit structure. The electronic package as claimed in claim 1 further includes a wiring structure formed on the cladding layer, and the wiring structure is electrically connected to the plurality of conductive columns and the electronic structure. The electronic package as claimed in claim 12 further includes a plurality of conductive elements formed on the wiring structure and electrically connected to the wiring structure. A method for manufacturing an electronic package, comprising: arranging a plurality of conductive pillars and an electronic structure with a plurality of conductors on a carrier; forming a protective layer on the electronic structure and the plurality of conductive pillars, so that the protective layer can be simultaneously directly covering the plurality of conductors and the plurality of conductive columns; forming a cladding layer on the carrier, so that the cladding layer covers the electronic structure, the protective layer and the plurality of conductive columns, and makes the plurality of conductive columns exposing the protection layer and the cladding layer on the end surface of the body and the ends of the plurality of conductive pillars; and removing the carrier. The method for manufacturing an electronic package as described in Claim 14 further includes a leveling process, so that one surface of the cladding layer is flush with the surface of the protective layer, the surface of the end of the conductive post and the end surface of the conductor . The method for manufacturing an electronic package according to claim 15, wherein the leveling process is to remove part of the material of the protective layer and part of the material of the coating layer by grinding. The method for manufacturing an electronic package according to claim 16, wherein the length of the protective layer covering the end of the conductive pillar is greater than the grinding depth. The method for manufacturing an electronic package according to claim 14, wherein the distance between adjacent conductive pillars is less than 150 microns. The method for manufacturing an electronic package according to claim 14, wherein the material forming the protective layer is an insulating material. The method for manufacturing an electronic package according to claim 14, wherein the protective layer covers the ends of the conductive pillars but does not cover the entire conductive pillars. The method for manufacturing an electronic package according to claim 14, wherein the length of the protective layer covering the conductive column is longer than the length of the protective layer covering the conductor. The method for manufacturing an electronic package according to claim 14, wherein the hardness of the protective layer is greater than that of the conductor. The method for manufacturing an electronic package according to claim 14, wherein the hardness of the protective layer is greater than the hardness of the conductive pillar. The method for manufacturing an electronic package according to claim 14, wherein the hardness of the protective layer is greater than 400 MPa. The method for manufacturing an electronic package according to claim 14 further includes forming a circuit structure on the cladding layer and the protective layer, so that the circuit structure is electrically connected to the plurality of conductive columns and the plurality of conductors. The method for manufacturing an electronic package as claimed in claim 25 further includes arranging electronic components on the circuit structure and electrically connecting the electronic components to the circuit structure. The method for manufacturing an electronic package according to claim 14 further includes forming a wiring structure on the cladding layer, so that the wiring structure electrically connects the plurality of conductive columns and the electronic structure. The method for manufacturing an electronic package as claimed in claim 27 further includes forming a plurality of conductive elements on the wiring structure, and electrically connecting the plurality of conductive elements to the wiring structure.

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