TWI803527B - Integrated circuits including via array and methods of manufacturing the same - Google Patents

Abstract

The present disclosure provides an integrated circuit (IC) and a method of manufacturing the same. The integrated circuit includes a via stack, and the via stack includes via arrays including a plurality of vias at the same level. A plurality of vias of a via array are arranged at intersections between tracks of adjacent conductive layers and arranged along a central line between the tracks. Also, a via overlap extends parallel to tracks of a conductive layer. Thus, the number of tracks sacrificed by the via array may be reduced, and the IC may have enhanced performance and a reduced area due to improved routability.

Description

Integrated circuit including array of vias and method of manufacturing the same

The present invention relates to an integrated circuit (IC), and more particularly to an integrated circuit including an array of vias and a method of manufacturing the same.

[Cross-reference to related applications]

This application claims Korean Patent Application No. 10-2017-0136613 filed with the Korean Intellectual Property Office on October 20, 2017 and Korean Patent Application No. 10-2018 filed with the Korean Intellectual Property Office on May 14, 2018 Priority of No. 2018-0055045, the entire content of said Korean patent application is incorporated into this application by reference.

As semiconductor processes are miniaturized, patterns included in integrated circuits may have reduced widths and/or thicknesses. Therefore, the influence of the voltage (IR) drop caused by the pattern may increase. In order to reduce an voltage drop (IR drop) between conductive patterns formed in different conductive layers, a via array including a plurality of via holes may be used. The vias included in the via array may be spaced apart from each other to comply with design rules, and the conductive patterns connected to the vias may include additional areas, which may be referred to as via overlaps. Thus, vias and via overlaps created by via arrays can reduce routability in the layout of integrated circuits and cause routing congestion.

The inventive concept provides an integrated circuit (IC) including a via array. More specifically, the inventive concept provides via arrays configured to provide improved routability, integrated circuits including the via arrays, and methods of fabricating the integrated circuits.

According to an aspect of the inventive concept, there is provided an integrated circuit comprising: a first conductive layer including conductive patterns on first tracks extending parallel to each other in a first lateral direction; The first conductive pattern; the second conductive layer, including the second conductive pattern and the third conductive pattern in the conductive pattern on the second trace extending parallel to each other in the second transverse direction; the third conductive layer, including the A fourth conductive pattern among the conductive patterns on the third traces extending parallel to each other in the first lateral direction; a first through hole array, comprising a first through hole and a second through hole, wherein the first through hole is connected to a top surface of the first conductive pattern and a bottom surface of the second conductive pattern, and wherein the second via is connected to the top surface of the first conductive pattern and the bottom of the third conductive pattern surface; and a second via array comprising a third via and a fourth via, wherein the third via is connected to a top surface of the second conductive pattern and a bottom surface of the fourth conductive pattern, and Wherein the fourth via hole is connected to the top surface of the third conductive pattern and the bottom surface of the fourth conductive pattern. The second conductive layer further includes a fifth conductive pattern aligned with one of the second traces between the second conductive pattern and the third conductive pattern, the fifth conductive pattern A fifth conductive pattern extends in the second lateral direction and is not coupled with the second conductive pattern and the third conductive pattern.

According to another aspect of the inventive concept, there is provided an integrated circuit comprising: a first conductive layer including first ones of conductive patterns on first traces extending parallel to each other in a first transverse direction; A conductive pattern and a first conductive pattern extending in the first lateral direction; a second conductive layer including the second conductive pattern and the first conductive pattern in the conductive patterns on the second traces extending parallel to each other in the second lateral direction Three conductive patterns, the second lateral direction is perpendicular to the first lateral direction; and a first through-hole array, including a first through-hole and a second through-hole, wherein the first through-hole is connected to the first through-hole a top surface of a conductive pattern and a bottom surface of the second conductive pattern, and wherein the second via is connected to the top surface of the first conductive pattern and the bottom surface of the third conductive pattern. Each of the first conductive pattern, the first via hole, and the second via hole has a length in the second lateral direction greater than that on the first trace of the first conductive layer. The length of the conductive pattern in the second lateral direction. The center of the first conductive pattern is aligned with one of the first traces of the first conductive layer or the center between two adjacent first traces of the first conductive layer Wire.

According to an aspect of the inventive concept, there is provided an integrated circuit comprising: a first conductive layer including first ones of conductive patterns on first traces extending parallel to each other in a first lateral direction a second conductive layer comprising a second conductive pattern and a third conductive pattern in the conductive patterns on second traces extending parallel to each other in a second lateral direction; a third conductive layer comprising a second conductive pattern in the first lateral direction A fourth conductive pattern in the conductive patterns on the third traces extending parallel to each other; a first via array, including first vias, each of which is connected to the first conductive the top surface of the pattern and at least one of the bottom surface connected to the second conductive pattern and the bottom surface of the third conductive pattern; and a second via array including a second via, the second via Each of the holes is connected to at least one of the top surface of the second conductive pattern and the top surface of the third conductive pattern, and is connected to a bottom surface of the fourth conductive pattern. The first vias of the first via array are located at intersections of the first trace and the second trace in plan view. The second vias of the second via array are located at intersections of the second trace and the third trace in the plan view.

According to another aspect of the inventive concept, a method of manufacturing an integrated circuit is provided. The method includes placing and routing a plurality of standard cells based on a cell library and input data defining the integrated circuit, wherein the placing and routing the plurality of standard cells includes adding a via stack , the via stack is configured to interconnect power rails and power meshes of the plurality of standard cells. Said adding said via stack includes arranging vias at intersections in plan view between traces of adjacent conductive layers of said integrated circuit.

FIG. 1 is a perspective view of a portion of an integrated circuit (IC) 100 according to an exemplary embodiment of the inventive concept. For simplicity, FIG. 1 shows only some of the layers included in integrated circuit 100 . As used herein, the X-axis direction and the Y-axis direction may be referred to as a first lateral direction and a second lateral direction, respectively, and the Z-axis direction may be referred to as a vertical direction. The first lateral direction and the second lateral direction may be orthogonal to each other. The plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane. Components located in a relative +Z (positive Z-axis) direction with respect to other components may be said to be located above other components. A component located in a relative -Z (negative Z axis) direction relative to other components may be said to be located below the other component. Also, among surfaces of the component, a surface of the component in the +Z-axis direction may be referred to as a top surface of the component, and a surface of the component in the −Z-axis direction may be referred to as a bottom surface of the component. The area of a component may be referred to as the area of the component in a surface parallel to the horizontal plane.

Referring to FIG. 1 , the integrated circuit 100 may include a Front End Of Line (FEOL) region FR and a Back End Of Line (BEOL) region BR. The FEOL region FR may include standard cells arranged in a plurality of rows. For example, as shown in FIG. 1 , the FEOL region FR may include a first row of standard cells C11 and C12, a second row of standard cells C21 to C24, and a third row of standard cells C31 to C33. The number of standard cells shown in the respective standard cells of the first row of standard cells, the second row of standard cells, and the third row of standard cells in FIG. limited to this. A standard cell may be a unit of a layout included in the integrated circuit 100 and may be configured to comply with a predetermined standard (eg, follow a predetermined design rule), and the integrated circuit 100 may include a plurality of different standard cells. For example, as shown in FIG. 1, standard cells (eg, C11, C21, and C31) may have a predetermined height (ie, length in the Y-axis direction), and power rails 111, 112, 113, 114 may be at The interface between each row of standard cells (for example, each row including standard cells C11 , C21 and C31 ) is spaced apart from each other in the Y-axis direction, and extends parallel to each other in the X-axis direction. In some embodiments, standard cells (eg, C11 , C21 , and C31 ) may include conductive patterns formed in some conductive layers of the BEOL region BR and vias connected to the conductive patterns.

Power rails 111-114 may supply power supply voltages to standard cells (eg, C11, C21, and C31). For example, a positive supply voltage (eg, VDD) may be applied to each of the first power rail 111 and the third power rail 113 and may be applied to each of the second power rail 112 and the fourth power rail 114 . One applies a negative supply voltage (eg, VSS or ground). That is, the power rail may supply the power supply voltage to the source of the transistor included in the standard cell. The terms "positive" and "negative" supply voltages (eg, VDD, VSS, or ground) are not intended to limit the voltage values supplied to the respective supply voltages. For example, in some embodiments, the "negative" supply voltage may be ground voltage. Positive and negative supply voltages may be provided to the power rails 111 to 114 through power lines 131 and 132 and via stacks 121 , 122 , 123 , 124 formed in the BEOL region BR. In some embodiments, the power supply lines 131 and 132 may have a width greater than that of the conductive patterns located under the power supply lines 131 and 132 (ie, a length greater than the length of the conductive patterns in the X-axis direction), and may Known as a power mesh.

The BEOL region BR may include power supply lines 131 and 132 and a plurality of conductive layers that may include conductive material (eg, metal) between the power supply rails 111 to 114 . Via stacks 121 - 124 may be used to reduce the voltage (IR) drop between power supply lines 131 and 132 and power supply rails 111 - 114 . For example, as described below with reference to FIGS. 2A-2C , via stacks 121 - 124 may include a plurality of vias connected to patterns of adjacent conductive layers. Therefore, a plurality of vias arranged at the same level and connected to the same node may be referred to as a via array. The via stacks 121 to 124 may include multiple arrays of vias at multiple levels. Accordingly, the IR drop between the power nets (ie, power lines 131 and 132 ) and the power rails 111 - 114 can be reduced.

As described above, reduced IR drop may be provided due to via stacks 121 - 124 , which may cause routing congestion in integrated circuit 100 . For example, each of the via stacks 121-124 may include a via array including a plurality of vias at the same level, and be connected to each of the vias included in the via array. The conductive pattern may include via overlaps. Accordingly, as described below with reference to FIGS. 2A to 2C , the via array may limit a space that may be formed by a conductive pattern for wiring in a conductive layer included in the BEOL region BR.

As described below with reference to the figures, in some embodiments, an array of vias included in a via stack may include vias arranged at intersections between traces of adjacent conductive layers. Therefore, routability in the integrated circuit 100 can be enhanced. For example, at least one conductive pattern connected to a different node than the via stack, not coupled to the via stack, and formed by the via stack may be formed. Interconnects can be optimized for improved routability without disrupting the structure of via stacks configured to reduce IR drop. Therefore, the performance of the integrated circuit 100 can be enhanced, and the area of the integrated circuit 100 can be reduced.

2A-2C are diagrams of examples of via stacks. Specifically, FIG. 2A is a perspective view of a via stack including a 1×2 via array, FIG. 2B is a perspective view of a via stack including a 2×2 via array, and FIG. 2C is a perspective view of a via stack including a 2×2 via array. A floor plan of the array's via stack. Hereinafter, redundant descriptions of FIGS. 2A to 2C will be omitted. Although the exemplary embodiments will be described herein with reference to 1x2 via arrays and 2x2 via arrays, it should be understood that the inventive concepts are applicable to 1-dimensional via arrays larger than 1x2 via arrays and A 2-dimensional via array larger than a 2×2 via array.

Referring to FIG. 2A, the conductive layer may have a preferred direction for wiring. For example, as shown in FIG. 2A , the Mx layer may have traces TR11 and TR12 that may extend parallel to each other in the X-axis direction. The conductive pattern of the Mx layer may be aligned with traces TR11 and TR12 and extend in the X-axis direction, as shown by the exemplary conductive pattern P11 of the Mx layer. Similarly, the Mx+1 layer may have traces TR21 to TR26 that may extend parallel to each other in the Y-axis direction. The conductive patterns of the Mx+1 layer may be aligned with the traces TR21-TR26 and extend in the Y-axis direction, as shown by the exemplary conductive patterns P21-P26 of the Mx+1 layer. In addition, the Mx+2 layer may have traces TR31 and TR32, which may extend parallel to each other in the X-axis direction. The conductive pattern of the Mx+2 layer may be aligned with traces TR31 and TR32 and extend in the X-axis direction, as shown in the exemplary conductive pattern P31 of the Mx+2 layer. Herein, it is assumed that each of the Mx layer and the Mx+2 layer has traces extending in the X-axis direction, and the Mx+1 layer has traces extending in the Y-axis direction. In some examples, the Mx+1 layer can be located above the Mx layer (eg, spaced apart in the positive Z direction), and the Mx+2 layer can be located above the Mx+1 layer. In addition, aligning the conductive pattern to the trace or aligning the conductive pattern along the trace may refer to aligning the conductive pattern such that the trace passes through the center of the conductive pattern, as shown in FIG. 2A . In some examples, the conductive pattern may be arranged such that the trace passes through a portion of the conductive pattern that is not located in the center of the conductive pattern. In some embodiments, a trace may be a path on which a conductive pattern is arrayed (eg, elements of an alignment grid).

The pitch between traces in the conductive layer can be determined according to design rules. For example, the traces TR21 to TR26 of the Mx+1 layer may be spaced apart from each other at regular intervals and extend in the Y-axis direction according to a pitch, and the pitch may be according to the width of the conductive pattern in the Mx+1 layer And the minimum distance between each conductive pattern in the conductive pattern is determined. In addition, as shown in FIG. 2A , the width (i.e., the Y-axis length) of the conductive patterns in the Mx+2 layer and the pitch between the traces may be different from the width and width of the conductive patterns in the Mx layer and the Mx+1 layer. The pitch between traces. To improve routability, adjacent conductive layers may have traces in different directions. For example, as shown in FIG. 2A , the Mx layer and the Mx+2 layer may have directions parallel to the X-axis direction, while the Mx+1 layer may have directions parallel to the Y-axis direction.

As shown in FIG. 2A , the via stack may include a 1×2 array of vias. For example, in the 1×2 via array between the Mx layer and the Mx+1 layer, the via V11 connected to the top surface of the conductive pattern P12 of the Mx layer and the bottom surface of the conductive pattern P27 of the Mx+1 layer and V12 may be spaced apart from each other in the X-axis direction. In some examples, vias V11 and V12 may be located at level Vx in the via stack. In the 1×2 via hole array between the Mx+1 layer and the Mx+2 layer, the via hole V21 connected to the top surface of the conductive pattern P27 of the Mx+1 layer and the bottom surface of the conductive pattern P32 of the Mx+2 layer and V22 may also be spaced apart from each other in the X-axis direction. In some examples, vias V21 and V22 may be located at a level Vx+1 in the via stack that is higher than level Vx (eg, separated in the positive Z-axis direction).

In the example shown in FIG. 2A, the vias may be arranged independently of the traces of the conductive layer. For example, vias may be arranged at intervals of a minimum distance between vias, which may be defined according to design rules in the via array. In addition, the conductive patterns P12, P27, and P32 of the via stack may include a via overlap. For example, as shown in FIG. 2A, the conductive patterns P12, P27, and P32 may extend beyond (eg, exceed) the interface between the via holes V11, V12, V21, and V22 in the X-axis direction, and the portion extending beyond May be referred to as via overlap. For example, the conductive pattern P12 of the Mx layer may extend in the X-axis direction along the trace TR12 in a similar direction (for example, the X-axis direction) of the Mx layer, and other conductive patterns of the Mx layer (for example, the conductive pattern P11 ) extend in the similar direction, while the conductive pattern P27 of the Mx+1 layer may extend in the X-axis direction which may be different from the direction of the Mx+1 layer (for example, the Y-axis direction), the other of the Mx+1 layer Conductive patterns (eg, conductive patterns P21 to P26 ) extend in the direction of the Mx+1 layer. Therefore, the extension of the conductive patterns P21 to P25 of the Mx+1 layer in the Y-axis direction may be limited by the conductive pattern P27. That is, the five traces P21 to P25 may be sacrificed (eg, reduced in size) due to the conductive pattern P27 .

Referring to FIG. 2B , the via stack may include a 2×2 via array. For example, in the 2×2 via array between the Mx layer and the Mx+1 layer, the four vias connected to the top surface of the conductive pattern P12 of the Mx layer and the bottom surface of the conductive pattern P27 of the Mx+1 layer The holes may be spaced apart from each other in the X-axis direction and the Y-axis direction. In the 2×2 via hole array between the Mx+1 layer and the Mx+2 layer, the four vias connected to the top surface of the conductive pattern P27 of the Mx+1 layer and the bottom surface of the conductive pattern P31 of the Mx+2 layer The holes may also be spaced apart from each other in the X-axis direction and the Y-axis direction. In the example shown in FIG. 2B, the vias of the 2x2 via array can be arranged independently of the traces of the conductive layer. For example, the through holes of the 2×2 through hole array can be arranged at intervals of the minimum distance between the through holes, and the minimum distance is designed according to the design rule.

The conductive pattern connected to the 2x2 via array may be integrally formed. For example, as shown in FIG. 2B, the conductive pattern P12 of the Mx layer, the conductive pattern P27 of the Mx+1 layer, and the conductive pattern P31 of the Mx+2 layer can have a conductive pattern that can extend along the traces of each conductive layer. The pattern (eg, the conductive patterns P21 to P26 and/or the conductive pattern P11 ) has a large width. Similar to the example of FIG. 2A , due to the conductive pattern P27 of the Mx+1 layer, the extension of the conductive patterns P21 to P25 of the Mx+1 layer in the Y-axis direction may be limited, and the five traces P21 to P25 may be sacrificed ( e.g. size reduction).

In examples such as the example shown in FIG. 2B , the minimum distance between a conductive pattern having a relatively large width and a conductive pattern adjacent to the conductive pattern in the same conductive layer may be defined as a relatively large value according to design rules. Therefore, as shown in FIG. 2B, due to the conductive pattern P12, not only the two traces TR13 and TR14 intersecting the conductive pattern P12 but also the trace TR12 not intersecting the conductive pattern P12 can be sacrificed in the Mx layer (for example, in the conductive pattern P12). patterns are not used in some conductive patterns).

Referring to FIG. 2C , the via stack may include a 2×2 via array, and vias included in the 2×2 via array may be connected to different conductive patterns. For example, as shown in FIG. 2C, in the via holes of the 2×2 via hole array, the first via hole V11 and the second via hole V12 may be connected to the top surface of the conductive pattern P11 of the Mx layer, and respectively connected to The bottom surfaces of the conductive patterns P21 and P22 of the Mx+1 layer. Similarly, among the vias of the 2×2 via array, the third via V13 and the fourth via V14 can be connected to the top surface of the conductive pattern P12 of the Mx layer, and respectively connected to the conductive pattern of the Mx+1 layer Bottom surfaces of P21 and P22. The conductive patterns P21 and P22 are not otherwise directly coupled to each other.

Compared with the example of FIG. 2B , in the example shown in FIG. 2C , the first via V11 to the fourth via V14 of the 2×2 via array may not be connected to the integrated conductive pattern, so that the via stack can be reduced. The minimum distance between the included conductive patterns P11, P12, P21 and P22 and the peripheral conductive patterns. However, the vias V11 to V14 may be arranged independently of the traces TR11 to TR16 of the Mx layer and the traces TR21 to TR26 of the Mx+1 layer. Thus, not only the external traces (e.g., TR12, TR15, TR22, and TR25) of the via array (e.g., traces outside the periphery of the via array) but also the internal traces (TR23, TR24, TR13, and TR14) (eg, traces within the periphery of the via array) may be sacrificed.

3A to 3C are diagrams of examples of via stacks according to exemplary embodiments of the inventive concept. Specifically, FIG. 3A is a perspective view of a via stack including a 1×2 via array, FIG. 3B is a perspective view of a via stack including a 2×2 via array, and FIG. 3C is a perspective view of a via stack including a 1×3 via array. Perspective view of the arrayed via stack. Hereinafter, the same description as referring to FIGS. 2A to 2C will be omitted in the description of FIGS. 3A to 3C .

Referring to FIGS. 3A-3C , in some embodiments, the vias of the via array may be arranged at intersections (eg, in plan view) between traces of adjacent conductive layers. As used herein, an intersection between traces of adjacent conductive layers refers to a region between two adjacent conductive layers along a line orthogonal to the two adjacent conductive layers. aligned and intersects the two traces (eg, the two traces overlap each other in the vertical direction). In other words, a portion of a via arranged at an intersection between traces of two adjacent conductive layers will intersect the first of the two traces in the first conductive layer, and the second A portion will intersect a second of the two traces in the second conductive layer that is adjacent to the first conductive layer. Furthermore, the conductive pattern connected to the vias of the via array may extend along the traces of the conductive layer of the conductive pattern. Accordingly, the number of traces sacrificed (ie, the number of traces whose use is limited) due to via stacking can be reduced. Therefore, wiring congestion can be reduced to improve routability.

Referring to FIG. 3A , the via stack may include a 1×2 via array, and vias included in the 1×2 via array may be arranged at intersections between traces. For example, in the 1×2 via array between the Mx layer and the Mx+1 layer, the via V11 connected to the top surface of the conductive pattern P12 of the Mx layer and the bottom surface of the conductive pattern P22 of the Mx+1 layer The vias that can be arranged at the intersection between the trace TR12 of the Mx layer and the trace TR22 of the Mx+1 layer, and connected to the top surface of the conductive pattern P12 of the Mx layer and the bottom surface of the conductive pattern P24 of the Mx+1 layer The hole V12 may be arranged at the intersection between the trace TR12 of the Mx layer and the trace TR24 of the Mx+1 layer. Similarly, in the 1×2 via hole array between the Mx+1 layer and the Mx+2 layer, the top surface of the conductive pattern P22 of the Mx+1 layer and the bottom surface of the conductive pattern P32 of the Mx+2 layer are connected The via hole V21 may be arranged at the intersection between the trace TR22 of the Mx+1 layer and the trace TR32 of the Mx+2 layer, and is connected to the top surface of the conductive pattern P24 of the Mx+1 layer and the conductive pattern of the Mx+2 layer. The bottom surface connected via V22 of P32 may be arranged at the intersection between the trace TR24 of the Mx+1 layer and the trace TR32 of the Mx+2 layer. In the example of FIG. 3A , the pitch between the traces of the Mx layer may be different from the pitch between the traces of the Mx+2 layer. Therefore, as shown in FIG. 3A , the vias V11 and V12 located under the Mx+1 layer may not be aligned with the vias V21 and V22 in the Z-axis direction on the Mx+1 layer.

In a via stack, conductive patterns P12, P22, P24, and P32 may extend along traces of the conductive layer and provide via overlap. For example, as shown in FIG. 3A , the conductive pattern P12 of the Mx layer may extend along the trace TR12 in the X-axis direction to provide the vias of the vias V11 and V12 to overlap, and the conductive pattern of the Mx+1 layer P22 and P24 may extend along traces TR22 and TR24 in the Y-axis direction to provide via overlap of vias V11 , V12 , V21 and V22 .

As described above, the vias of the via array may be arranged at intersections between traces (of adjacent layers), and the via overlap may extend along the traces such that the number of usable traces may be increased. For example, as shown in FIG. 3A , although the use of the traces TR22 and TR24 configured to provide via overlapping conductive patterns P22 and P24 in the Mx+1 layer is limited, the conductive patterns P21, P23, and P25 It may extend along other traces TR21 , TR23 and TR25 in the Y-axis direction. For example, the conductive pattern P23 of the Mx+1 layer may not be coupled with the conductive patterns P22 and P24 providing the via overlap, and may penetrate the via overlap and extend along the trace TR23 in the Y-axis direction. Thus, compared to the example of FIG. 2A in which portions of the five traces TR21 to TR25 of the Mx+1 layer are sacrificed, in the example of FIG. The number of can be reduced and good routability can be obtained.

In some embodiments, as shown in FIG. 3A , the conductive pattern (for example, conductive pattern P12 ) of the Mx layer that is part of the via array can be along the X-axis direction along a similar direction in the Mx layer (for example, the X-axis direction ), the other conductive patterns of the Mx layer (eg, conductive pattern P11 ) extend in the similar direction, and the conductive patterns of the Mx+1 layer that are part of the via array (eg, conductive pattern P22) may extend in the Y-axis direction which may be similar to the direction (for example, the Y-axis direction) of the Mx+1 layer, other conductive patterns of the Mx+1 layer (for example, conductive patterns P21, P23 and P25) The layer extends in said direction.

Referring to FIG. 3B , the via stack may include a 2×2 via array, and vias included in the 2×2 via array may be arranged at intersections between traces. For example, in the 2×2 via array between the Mx layer and the Mx+1 layer, the vias V11 and V12 connected to the top surface of the conductive pattern P13 of the Mx layer can be respectively arranged on the trace TR13 of the Mx layer At the intersections between the traces TR21 and TR23 of the Mx+1 layer, and the vias V13 and V14 connected to the top surface of the conductive pattern P11 of the Mx layer can be respectively arranged on the traces TR11 of the Mx layer and the Mx+1 layer The intersection between traces TR21 and TR23. In addition, in the 2×2 via hole array between the Mx+1 layer and the Mx+2 layer, the via holes V21 and V23 connected to the top surface of the conductive pattern P21 of the Mx+1 layer can be respectively arranged in the Mx+1 layer At the intersection between the trace TR21 of the Mx+2 layer and the trace TR32 and TR31 of the Mx+2 layer, and the via holes V22 and V24 connected to the top surface of the conductive pattern P23 of the Mx+1 layer can be respectively arranged in the Mx+1 layer The intersection between trace TR23 and traces TR32 and TR31 of the Mx+2 layer.

As shown in FIG. 3B , the conductive patterns P11 , P13 , P21 , P23 , P31 , and P32 of the via stack may extend along the traces of the conductive layer and provide via overlap. For example, conductive patterns P11 and P13 of the Mx layer may extend along traces TR11 and TR13 to provide a via overlap of vias V11 to V14. In addition, the conductive patterns P21 and P23 of the Mx+1 layer may extend along the traces TR21 and TR23 in the Y-axis direction to provide via overlaps of the vias V11 to V14 and V21 to V24.

As shown in FIG. 3B, since the traces TR11 and TR13 of the conductive patterns P11 and P13 providing via overlap are sacrificed in the Mx layer, the conductive patterns can be along other traces of the Mx layer in the X-axis direction ( For example, TR12) extension. Similarly, since the traces TR21 and TR23 of the conductive patterns P21 and P23 providing the via overlap are sacrificed in the Mx+1 layer, the conductive pattern (eg, P22) can be along the Mx+1 in the Y-axis direction. Other traces of the layer (for example, TR22) extend. Thus, compared to the example of FIG. 2B in which portions of the five traces TR21 to TR25 of the Mx+1 layer may be sacrificed and the example in which portions of the four traces TR22 to TR25 of the Mx+1 layer may be sacrificed, In the example of FIG. 3B , the number of sacrificed traces (eg, traces of reduced usable length) can be reduced and good routability can be achieved.

Referring to FIG. 3C , the via stack may be connected to a conductive pattern P41 having a large width (eg, wider than conductive patterns in other layers (eg, P22 and P24 )). As shown in FIG. 3C , the conductive pattern P41 may extend along the trace TR41 in the Y-axis direction in the Mx+3 layer, and is called fat metal. In some embodiments, the conductive pattern P41 may be a power line (eg, 131 and 132 of FIG. 1 ) included in the power grid. Although the trace TR41 of the Mx+3 layer extends in the Y-axis direction, the conductive pattern P41 of the Mx+3 layer can be routed via the The vias V31 to V33 (ie, 1×3 via array) connected to the conductive pattern P31 of the Mx+2 layer are arranged in the X direction, and the 1×3 via array can be repeated under the Mx+2 layer. For example, a 1×3 via array including three vias V21 to V23 may be located between layers Mx+2 and Mx+1, and a 1×3 via array including three vias V11 to V13 may be It is located between the Mx+1 layer and the Mx layer.

As shown in FIG. 3C , vias of a 1×3 via array can be arranged at intersections between traces so that available traces can be increased. For example, between conductive patterns that provide via overlap along traces TR21, TR23, and TR25 in the Mx+1 layer, conductive patterns P22 and P24 that are not coupled to the via stack may penetrate the via stack and It extends along the traces TR22 and TR24 in the Y-axis direction. Although a 1×3 via array is shown in FIG. 3C , the via stack may include a 1-dimensional via array that is 1×4 or greater in some embodiments or 2×3 or greater in some embodiments. 2D via arrays larger than 2×3.

FIG. 4 is a plan view of an example of a via stack according to an exemplary embodiment of the inventive concept. In particular, FIG. 4 shows an example of a via stack comprising a 2x2 array of vias located between the Mx layer and the Mx+1 layer. In FIG. 4 , hatching is used to indicate conductive patterns on different layers (for example, Mx layer and Mx+1 layer) separated in the Z-axis direction.

As shown in FIG. 4 , the vias V11 to V14 of the 2×2 via array may be respectively arranged at intersections between the traces TR12 and TR14 of the Mx layer and the traces TR22 and TR24 of the Mx+1 layer. The first via V11 and the second via V12 may be connected to the top surface of the conductive pattern P11 of the Mx layer, and connected to the bottom surfaces of the conductive patterns P21 and P22 of the Mx+1 layer, respectively. In addition, the third via hole V13 and the fourth via hole V14 may be connected to the top surface of the conductive pattern P12 of the Mx layer, and connected to the bottom surfaces of the conductive patterns P21 and P22 of the Mx+1 layer, respectively. In some embodiments, the through holes V11 and V13 of the 2×2 through hole array are separated from the through holes V12 and V14 in the X-axis direction by the distance S2 and the through holes V13 and V14 of the 2×2 through hole array are in the Y direction. The distance S1 separated from the through holes V11 and V12 in the axial direction may be greater than the minimum distance between the through holes defined according to the design rules. Therefore, the vias V11 to V14 of the 2×2 via array can obey the design rule. Although not shown in FIG. 4 , the conductive pattern insulated from the via stack may extend along the trace TR13 in the X-axis direction of the Mx layer, and the conductive pattern insulated from the via stack may extend along the Mx+1 layer. The trace TR23 extends in the Y-axis direction.

（1）When the vias are arranged at intersections between traces, the distance S1 by which the vias are spaced apart from each other in the Y-axis direction can be calculated as in Equation 1:

(1)

Where n may indicate a positive integer. n may be an integer equal to or greater than 2 when the minimum distance between via holes defined according to design rules is greater than the pitch between traces of the Mx layer. In Equation 1, {Mx trace pitch} may refer to the pitch between the traces of the Mx layer of FIG. The pitch between traces in the conductive layer with traces parallel to the X-axis. In Equation 1, {via length} may refer to the length of the vias (eg, vias V11 to V14 ) in the Y-axis direction. That is, the pitch between vias in the Y-axis direction in the via array may be a multiple of the pitch between traces of the Mx layer.

（2），Similarly, the distance S2 by which the vias are spaced apart from each other in the X-axis direction can be calculated as in Equation 2:

(2),

Where m can be a positive integer. When the minimum distance between via holes defined according to the design rules is greater than the pitch between traces of the Mx+1 layer, m may be an integer equal to or greater than 2. In Equation 2, {Mx+1 trace pitch} may refer to the pitch between the traces (eg, traces TR21 to TR25) of the Mx+1 layer of FIG. The pitch between the traces in the conductive layer with traces parallel to the Y-axis in the via-connected conductive layer. Also, in Equation 2, {via hole width} may refer to the length of the via holes (eg, via holes V11 to V14 ) in the X-axis direction. That is, the pitch between vias in the X-axis direction in the via array may be a multiple of the pitch between traces of the Mx+1 layer.

FIG. 5 is a perspective view of an example of a via stack according to an exemplary embodiment of the inventive concept. Specifically, FIG. 5 shows a via array including strip-shaped vias and a via stack including the via array.

Referring to FIG. 5 , in the via stack, the via array may include strip-shaped vias. The strip-shaped via may refer to a via having a relatively large length in the X-axis direction and/or the Y-axis direction, for example, the length is greater than the width of the conductive pattern (eg, greater than the width of one or more conductive patterns in adjacent layers) ) through holes. For example, as shown in FIG. 5, a 1×2 via array may include vias V11 and V12 having a large length in the Y-axis direction between the Mx layer and the Mx+1 layer, and the 1×2 vias The hole array may also include via holes V21 and V22 having a large length in the Y-axis direction between the Mx+1 layer and the Mx+2 layer. As the cross-sectional area of the via (ie, the area of the via in a surface parallel to the plane formed by the X and Y axes) increases, the IR drop caused by the via may decrease. Therefore, as shown in FIG. 5, a via hole having a large cross-sectional area can be used.

In some embodiments, the strip-shaped vias may be arranged along the trace and overlap the conductive pattern extending along the trace. For example, as shown in FIG. 5, a via V11 connected to the top surface of the conductive pattern P11 of the Mx layer and the bottom surface of the conductive pattern P21 of the Mx+1 layer may be aligned along the trace TR21 of the Mx+1 layer. The via hole V21 connected to the top surface of the conductive pattern P21 of the Mx+1 layer and the bottom surface of the conductive pattern P31 of the Mx+2 layer. Similarly, the vias V12 and V22 can also be aligned with each other along the trace TR23 of the Mx+1 layer. Accordingly, the conductive pattern P23 of the Mx+1 layer may extend along the trace TR22 in the Y-axis direction.

In some embodiments, the strip vias may be arranged to minimize sacrifice of traces. For example, vias V11, V12, V21, and V22 can be aligned with traces TR21 and TR23 to minimize the sacrifice of the traces of the Mx+1 layer, and vias V11, V12, V21 in the Y-axis direction The positions of V22 and V22 can be determined based on the lengths of the through holes V11, V12, V21 and V22 in the Y-axis direction. As described below with reference to FIG. 6 , the number of sacrificed traces may vary according to the location of the via sliver such that the location of the via sliver may be determined to minimize the number of traces that are sacrificed. Although an example of a 1×2 via array including strip-shaped vias is shown in FIG. Via arrays, and in other embodiments, via stacks may include 2×2 or greater than 2×2 2-dimensional via arrays including strip-shaped vias.

FIG. 6 is a diagram of an example of a via array according to an exemplary embodiment of the inventive concept. Specifically, FIG. 6 shows an example where the number of sacrificed traces changes according to the arrangement of the via array. As shown in FIG. 6 , the 1×2 via array may include vias V11 and V12 located between the Mx layer and the Mx+1 layer, and the vias V11 and V12 may be strip-shaped vias. The via holes V11 and V12 may have a length equal to the width of the conductive patterns P21 and P22 of the Mx+1 layer in the X-axis direction, and have a relatively large length W0 in the Y-axis direction (for example, greater than that of the Mx+1 layer). The width of the conductive patterns P21 and P22 in the X-axis direction).

Referring to the leftmost example of FIG. 6 , the vias V11 and V12 of the 1×2 via array may be arranged along the traces TR22 and TR24 of the Mx+1 layer, and along the trace TR13 of the Mx layer. That is, the vias V11 and V12 may be arranged such that the centers of the sections of the vias V11 and V12 overlap the traces TR22 and TR24 of the Mx+1 layer and the trace TR13 of the Mx layer. The conductive pattern P11 of the Mx layer may extend in the X-axis direction to provide a via overlap of the vias V11 and V12 and have a width equal to the length W0 of the vias V11 and V12 in the Y-axis direction. In addition, the conductive patterns P21 and P22 of the Mx+1 layer may extend in the Y-axis direction to provide via overlap of the vias V11 and V12.

Two traces TR22 and TR24 may be sacrificed in the Mx+1 layer due to conductive patterns P21 and P22, while three traces TR12-TR14 may be sacrificed in the Mx layer due to conductive pattern P11. Since the trace TR13 of the Mx layer crosses the conductive pattern P11, the trace TR13 of the Mx layer may be sacrificed. However, when the conductive pattern is arranged to extend along the traces TR12 and TR14 of the Mx layer in the X-axis direction, the distance between the conductive pattern and the conductive pattern P11 may violate the minimum distance defined according to the design rule, thus This allows traces TR12 and TR14 to be sacrificed. Therefore, in the leftmost example of FIG. 6 , performing wiring operations using three traces TR12 to TR14 among the traces of the Mx layer may be limited.

Referring to the rightmost example of FIG. 6 , the via stack shown in the leftmost example of FIG. 6 is repositionable in the Y-axis direction. Thus, as shown in the rightmost example of FIG. 6, vias V11 and V12 of the 1×2 via array may extend along traces TR22 and TR24 of layer Mx+1, and also along traces TR13 and TR24 of layer Mx. A centerline X1 extends between the traces TR14. That is, the vias V11 and V12 may be arranged such that the centers of the sections of the vias V11 and V12 overlap the centerline X1, which may extend along the center between the trace TR13 and the trace TR14 of the Mx layer. and extend in the X-axis direction.

Two traces TR22 and TR24 can be sacrificed in Mx+1 layer due to conductive patterns P21 and P22, while two traces TR13 and TR14 can be sacrificed in Mx layer due to conductive pattern P11 having length W0 in the Y-axis direction. was sacrificed. That is, since the traces TR13 and TR14 of the Mx layer cross the conductive pattern P11 , the traces TR13 and TR14 of the Mx layer may be sacrificed. However, even though the conductive patterns P12 and P13 are arranged to extend along the traces TR12 and TR15 of the Mx layer in the X-axis direction, since the conductive patterns P12 and P13 are spaced apart from the conductive pattern P11 by at least a minimum distance defined according to the design rule , so the design rules can be obeyed. Therefore, in the rightmost example of FIG. 6 , performing wiring operations using two traces TR13 and TR14 among the traces of the Mx layer may be limited. As noted above, the number of traces sacrificed may vary depending on the location of the same via array including the sliver vias. Hereinafter, an example of a via array arranged to reduce the number of sacrificed traces will be explained with reference to FIGS. 7A to 7C .

7A to 7C are diagrams of an example of a via array according to an exemplary embodiment of the inventive concept. Specifically, FIG. 7A shows a 1×2 via array including vias V11 and V12 arranged along the center line X2 between the trace TR13 and the trace TR14 of the Mx layer, and FIG. 7B and FIG. 7C respectively show A 1×2 via array comprising vias V11 and V12 arranged along trace TR13 of the Mx layer is produced. Hereinafter, redundant descriptions of FIGS. 7A to 7C will be omitted.

Referring to FIG. 7A , the through holes V11 and V12 may have a length W1 in the Y-axis direction. The vias V11 and V12 may be connected to the top surface of the conductive pattern P12 of the Mx layer, and connected to the bottom surfaces of the conductive patterns P21 and P22 of the Mx+1 layer, respectively. The traces TR13 and TR14 of the Mx layer may be sacrificed due to the conductive pattern P12 having a width W1, and the conductive patterns P11 and P13 may extend along the traces TR12 and TR15 in the X-axis direction.

In order to reduce the number of traces of the Mx layer sacrificed due to the via array, when the width W of the conductive pattern of the Mx layer due to the via array satisfies Equation 3, the vias of the via array can be along the adjacent centerline alignment between the traces.

（3）。

(3).

In FIG. 7A and Equation 3, W indicates the width of the conductive pattern of the Mx layer connected to the via array (for example, W1 of the conductive pattern P12), and M indicates the conductive pattern of the Mx layer not connected to the via array (for example, The width of the conductive pattern P11 ), P indicates the pitch of the Mx layer between traces, S indicates the minimum distance between the conductive patterns of the Mx layer, the minimum distance is defined according to design rules, and n indicates a positive integer. In a via array (or conductive pattern) satisfying Equation 3, an even number of traces can be sacrificed in the Mx layer.

Referring to FIG. 7B , the via holes V11 and V12 may have a width W2 in the Y-axis direction. The vias V11 and V12 may be connected to the top surface of the conductive pattern P12 of the Mx layer, and connected to the bottom surfaces of the conductive patterns P21 and P22 of the Mx+1 layer, respectively. The traces TR12 to TR14 of the Mx layer may be sacrificed for the conductive pattern P12 having a width W2, and the conductive patterns P11 and P13 may extend along the traces TR11 and TR15 in the X-axis direction.

In order to reduce the number of traces of the Mx layer sacrificed due to the via array, when the width W of the conductive pattern of the Mx layer due to the via array satisfies Equation 4, the vias of the via array can be along the trace arrangement.

（4），

(4),

In FIG. 7B and Equation 4, W may be the width of the conductive pattern of the Mx layer connected to the via array (for example, W2 of the conductive pattern P12), and M indicates the width of the Mx layer not connected to the via array (for example, Conductive pattern P11), P can be the pitch of the Mx layer between the traces, S can be the minimum distance between the conductive patterns of the Mx layer, the minimum distance is defined according to design rules, and n can be a positive integer . In a via array (or conductive pattern) satisfying Equation 4, an odd number of traces can be sacrificed in the Mx layer.

Referring to FIG. 7C , in some embodiments, the via hole may have a length smaller than the width of the conductive pattern. For example, as shown in FIG. 7C , the conductive pattern P12 of the Mx layer may have a width W3 in the Y-axis direction, and the via holes V11 and V12 may have a length L1 smaller than the width W3 in the Y-axis direction. The conductive pattern P12 of the Mx layer may be aligned with (eg, centered on) the trace TR13 of the Mx layer so as to satisfy Equation 4, and the vias V11 and V12 whose length L1 is smaller than the width W3 of the conductive pattern P12 of the Mx layer may be They are respectively arranged at the intersections of the trace TR13 of the Mx layer and the traces TR22 and TR24 of the Mx+1 layer, as shown in FIG. 7C .

FIG. 8 is a flowchart of a method of manufacturing an integrated circuit according to an exemplary embodiment of the inventive concept. In some embodiments, at least some of operations S200 , S400 , S600 and S800 shown in FIG. 8 may be performed by a computing system (eg, 300 shown in FIG. 12 ).

In operation S200 , a logic synthesis operation for generating netlist data D13 may be performed based on resistor-transistor logic (RTL) data D11 about the standard cell library D12 . The RTL data D11 can define the function of the integrated circuit and can be described in hardware such as very-high-speed integrated circuit (VHSIC) hardware description language (VHSIC hardware description language, VHDL) and Verilog (Verilog). description language (hardware description language, HDL), but the concept of the present invention is not limited thereto. The standard cell library D12 can define the functions and properties of standard cells. A semiconductor design tool (for example, a logic synthesis tool) may perform a logic synthesis operation based on the RTL data D11 of the standard cell library D12 and generate netlist data D13 including a bitstream (bitstream) and/or a netlist (netlist), To define the integrated circuit, that is to define a plurality of standard cells and the connection relationship between the standard cells.

In operation S400, a place & route (P&R) operation for generating layout data D15 may be performed based on the netlist data D13 of the standard cell library D12 and the design rule D14. The standard cell library D12 can define the layout of the standard cells, and the design rule D14 can define rules to be followed by the layout of the integrated circuit according to the semiconductor manufacturing process (for example, operation S800 ). For example, design rule D14 may define the direction and pitch of the traces of the conductive layer, the minimum distance between conductive patterns in the conductive layer, the width of the conductive patterns in the conductive layer, and the distance between via holes located at the same level. the minimum distance between.

A semiconductor design tool (for example, a P&R tool) can arrange a plurality of standard cells based on the netlist data D13 of the standard cell library D12 and input pins, output pins and power tabs for wiring. Routing operations may include creating interconnects including vias and/or conductive patterns. Additionally, semiconductor design tools can generate multiple via stacks to reduce IR drop. As described above with reference to the drawings, the vias of the via array included in each of the via stacks may in some embodiments be arranged between traces of a conductive layer (eg, adjacent conductive layers) intersections, or in other embodiments along the centerline between the traces. Thus, via stacking can provide reduced IR drop and reduce routing congestion. An example of operation S400 will be explained below with reference to FIG. 9 .

In operation S600, an operation of manufacturing a mask may be performed. For example, optical proximity correction (OPC) can be applied to the layout data D15, patterns on the mask can be defined to form patterns on multiple layers, and at least one mask (or photomask mold) to form a pattern on each of the plurality of layers.

In operation S800, an operation of fabricating an integrated circuit may be performed. For example, a plurality of layers may be patterned using at least one mask manufactured in operation S600, thereby fabricating an integrated circuit. As shown in FIG. 8, operation S800 may include operations S820 and S840.

In operation S820, a FEOL process may be performed. A FEOL process may refer to a process in which individual components (eg, transistors, capacitors, and/or resistors) are formed on a substrate during an integrated circuit fabrication process. For example, the FEOL process may include: planarizing and cleaning the wafer, forming trenches, forming wells, forming gate lines, and forming sources and drains. Thus, elements included in multiple standard cells can be formed.

In operation S840, a BEOL process may be performed. A BEOL process may refer to the process of interconnecting individual components (eg, transistors, capacitors, and/or resistors) in an integrated circuit fabrication process. For example, the BEOL process may include: siliciding the gate, source, and/or drain regions, adding dielectric material, performing a planarization process, forming holes, adding metal layers, forming vias, and/or forming passivation layer. The via stack may be formed in a BEOL process (ie, operation S840). Next, the integrated circuit may be packaged in a semiconductor package and used as a component for various applications.

FIG. 9 is a flowchart of an example of operation S400 shown in FIG. 8 according to an exemplary embodiment of the inventive concept. As described above with reference to FIG. 8 , in operation S400 ′ shown in FIG. 9 , a place and route (P&R) operation may be performed with reference to the standard cell library D12 and the design rule D14 . As shown in FIG. 9 , operation S400' may include a plurality of operations S420, S440 and S460. Hereinafter, the flowchart of FIG. 9 will be explained with reference to FIG. 8 .

In operation S420, an operation of adding a via stack may be performed. For example, after arranging a plurality of standard cells, an operation of adding a via stack configured to interconnect the power lines and power rails of the power net may be performed. In some embodiments, via stacks for signal rather than power supply voltages may be added. An example of operation S420 will be explained below with reference to FIG. 10 .

In operation S440, an operation of generating a conductive pattern by via stacking may be performed. The via stack added in operation S420 may include a via array including vias arranged along the traces of the conductive layer or at intersections between the traces of the conductive layer. Thus, the number of traces sacrificed due to via stacking can be reduced. As described above with reference to FIGS. 3A to 3C , when the minimum distance between via holes at the same level defined according to design rules is greater than the pitch between traces, a conductive pattern can be generated, which can passing between the through holes of the through hole array and insulated from the through holes. Accordingly, signal and/or power supply voltages may be routed using conductive patterns formed through via stacks.

In operation S460, an operation of generating layout data may be performed. As described above with reference to FIG. 8, the layout data D15 may define the layout of the integrated circuit, may have a format such as Graphic Data System II (GDSII), and may include geometric information about standard cells and interconnections. .

FIG. 10 is a flowchart of an example of operation S420 shown in FIG. 9 according to an exemplary embodiment of the inventive concept. As described above with reference to FIG. 9 , the operation of adding a via stack may be performed in operation S420 ′ of FIG. 10 . As shown in FIG. 10 , operation S420' may include operation S422 and operation S424. In some embodiments, operation S422 and operation S424 may be performed simultaneously.

In operation S422, an operation of arranging via holes at intersections between traces of adjacent conductive layers may be performed. For example, as described above with reference to FIG. 4 , the vias (eg, V11 to V14 ) of the via array may be arranged on traces (eg, TR12, TR14, TR22 and TR24). Thus, fewer traces are sacrificed, thereby increasing routable traces.

In operation S424, an operation of arranging the via array based on the length of the bar-shaped via may be performed. For example, as described above with reference to FIG. 6, the number of sacrificed traces may vary according to the location of the sliver via. Accordingly, as described with reference to FIGS. 7A to 7C , the via stripes may be arranged along the traces or the centerline between the traces based on the length of the via stripes. For example, when the width W of the via strips in one direction satisfies Equation 3, the via strips can be arranged along the centerline between the traces shown in FIG. 7A . On the other hand, when the width W of the via strips in one direction satisfies Equation 4, the via strips can be arranged along the trace shown in FIG. 7B . Accordingly, the number of sacrificial traces can be reduced by the via array including the stripe-shaped vias, and the routeable traces can be increased.

FIG. 11 is a block diagram of a System-on-Chip (SoC) 200 according to an exemplary embodiment of the inventive concept. The system on chip 200 , which may be a semiconductor device, may include an integrated circuit including a via stack according to an exemplary embodiment of the inventive concept. The SoC 200 may be implemented as a single chip integrated with complex functional blocks (eg, intellectual property (IP)) capable of performing various functions. A via stack according to an exemplary embodiment may be included in each of the functional blocks of the system on chip 200 . Therefore, a system-on-chip 200 with improved performance and reduced area may be obtained due to reduced IR drop and efficient routing of patterns.

Referring to FIG. 11 , the system-on-chip 200 may include a modem (modem) 220, a display controller 230, a memory 240, an external memory controller 250, a central processing unit (central processing unit, CPU) 260, and a transaction unit (transaction unit) 270 , a power management integrated circuit (power management integrated circuit, PMIC) 280 and a graphics processing unit (graphic processing unit, GPU) 290 , and each functional block of the system on chip 200 can communicate with each other through a system bus (system bus) 210 .

The CPU 260 may be configured to control the overall operation of the SoC 200 and may control the operations of other functional blocks of the SoC 200 . The modem 220 may demodulate a signal received from the outside of the system on chip 200 or modulate a signal generated from the inside of the system on chip 200 and transmit the demodulated signal or the modulated signal to the outside. The external memory controller 250 may control operations of transferring data to and receiving data from an external memory device connected to the system on chip 200 . For example, programs and/or data stored in the external memory device may be provided to the CPU 260 and/or the GPU 290 via the control of the external memory controller 250 . The graphics processing unit 290 may execute program instructions associated with graphics processing operations, but the inventive concept is not limited thereto. The graphics processing unit 290 may receive graphics data through the external memory controller 250 , and/or the graphics data processed by the graphics processing unit 290 may be transmitted to the outside of the SoC 200 via the external memory controller 250 . The transaction unit 270 can monitor the data transaction of each functional block, and the power management integrated circuit 280 can control the power supplied to each functional block through the control of the transaction unit 270 . The display controller 230 may control a display (or a display device) located outside the system on chip 200 and transfer data generated in the system on chip 200 to the display.

Memory 240 may include non-volatile memory, such as electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM), flash memory, phase-change random access memory (phase-change random access memory, PRAM), resistive random access memory (resistive RAM, RRAM), nano-floating gate memory (nano-floating gate memory, NFGM), polymer random access memory (polymer RAM, PoRAM) , magnetic random access memory (magnetic RAM, MRAM) and ferroelectric random access memory (ferroelectric RAM, FRAM); or volatile memory, such as dynamic random access memory (dynamic RAM, DRAM), static Random access memory (static RAM, SRAM), mobile DRAM, double-data-rate synchronous dynamic random access memory (double-data-rate synchronous dynamic RAM, DDR SDRAM), low-power double data rate (low-power DDR, LPDDR), synchronous dynamic random access memory (synchronous dynamic RAM, SDRAM), graphics double data rate (graphic DDR, GDDR) SDRAM and Rambus (Rambus) DRAM.

FIG. 12 is a block diagram of a computing system 300 including a memory 340 configured to store a program 341 according to an exemplary embodiment of the inventive concept. At least some operations included in a method of fabricating an integrated circuit (eg, the method shown in FIG. 8 ) according to example embodiments may be performed by the computing system 300 .

Computing system 300 may be a stationary computing system such as a desktop computer, workstation, and server, or a portable computing system such as a laptop computer. As shown in FIG. 12 , the computing system 300 may include a processor 310, an input/output (input/output, I/O) device 320, a network interface (network interface) 330, a random access memory (random access memory, RAM) 340 . A read only memory (read only memory, ROM) 350 and/or a storage device 360 . The processor 310 , the input/output device 320 , the network interface 330 , the random access memory 340 , the read-only memory 350 and the storage device 360 can be connected to the bus 370 and communicate with each other through the bus 370 .

The processor 310 may be referred to as a processing unit. For example, the processor 310 may include at least one core (for example, a microprocessor (microprocessor, MP)), an application processor (application processor, AP), a digital signal processor (digital signal processor, DSP) and a graphics processing unit (GPU)), the at least one core can execute an arbitrary instruction set (for example, Intel Architecture-32 (Intel Architecture-32, IA-32), 64-bit extension IA-32, x86-64, Power ) PC, Sparc, MIPS, Advanced RISC Machine (ARM), IA-64, etc.). For example, processor 310 can access memory (i.e., random access memory 340 and/or read-only memory 350) through bus 370 and execute 350 stored commands.

The random access memory 340 may store a program 341 and/or at least a part of the program 341 for manufacturing an integrated circuit according to example embodiments. The program 341 may enable the processor 310 to perform at least some operations included in the method of manufacturing an integrated circuit. That is, the program 341 may include a plurality of commands executable by the processor 310 . The plurality of commands included in the program 341 may enable the processor 310 to perform, for example, a logic synthesis operation of operation S200 of FIG. 8 and/or a place and route operation of operation S400 of FIG. 8 .

Even if the power supplied to the computing system 300 is interrupted, the storage device 360 will not lose the stored data. For example, storage device 360 may include a non-volatile memory device or storage media such as magnetic tape, optical disk, and magnetic disk. Furthermore, the storage device 360 may be detachably attached to the computing system 300 . In some embodiments, the storage device 360 may store the program 341 according to an exemplary embodiment. Before the processor 310 executes the program 341 , the program 341 or at least a part of the program 341 may be loaded from the storage device 360 into the random access memory 340 . In some embodiments, the storage device 360 can store a file written in a programming language, and the program 341 or at least a part of the program 341 generated by the compiler can be loaded into the random access memory 340 from the file. In addition, as shown in FIG. 12, the storage device 360 can store a database (database, DB) 361, and the database 361 can include information that can be used to design an integrated circuit (for example, the standard cell library D12 and/or the design rule D14 of FIG. 8 ).

The storage device 360 may store data to be processed by the processor 310 and/or data processed by the processor 310 . That is, according to the program 341 , the processor 310 may process data stored in the storage device 360 to generate data and/or store the generated data in the storage device 360 . For example, the storage device 360 can store the RTL data D11, the netlist data D13 and/or the layout data D15 of FIG. 8 .

Input/output devices 320 may include input devices such as a keyboard and/or pointing apparatus and/or output devices such as a display device and/or a printer. For example, the user can trigger the processor 310 to execute the program 341 via the input/output device 320 , input the RTL data D11 and/or the netlist data D13 of FIG. 8 and/or confirm the layout data D15 of FIG. 11 .

Network interface 330 may provide access to networks external to computing system 300 . For example, a network may include multiple computing systems and multiple communication links. Communication links may include wired links, optical links, wireless links, or any other type of link.

It should be understood that although the terms "first", "second", etc. are used herein to describe members, regions, layers, parts, sections, components and/or elements in exemplary embodiments of the inventive concept, the described A member, region, layer, part, section, component and/or element should not be limited by these terms. These terms are only used to distinguish one member, region, section, section, component or element from another member, region, section, section, component or element. Accordingly, a first member, region, part, section, component or element set forth below could also be termed a second member, region, part, section, component or element without departing from the scope of the inventive concept. . For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, all without departing from the scope of the inventive concept.

For ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper" and other spatially relative terms may be used herein to describe an element or feature shown in the drawings A relationship to another (other) element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a, an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that when the term "comprises, comprising, includes and/or including" is used herein, it indicates the existence of said features, integers, steps, operations, elements and/or components, but does not exclude The presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It should also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted to have a meaning consistent with their meanings in the context of this specification and related art, and that unless so defined herein, the terms are not Should be interpreted as having an ideal or overly formal meaning.

When a certain exemplary embodiment can be implemented differently, a specific process sequence can be performed differently from the described order. For example, two consecutively illustrated processes may be performed substantially simultaneously or in an order reverse to that described.

In the drawings, variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Thus, exemplary embodiments of the inventive concept should not be construed as limited to the particular shapes of regions illustrated herein but are to be construed as including deviations in shapes that result, for example, from manufacturing processes. For example, an etched region shown as a rectangular shape could be a circular shape or some curved shape. Thus, the regions shown in the figures are schematic and their shapes are intended to illustrate the particular shape of a region of a device and are not intended to limit the scope of the inventive concept. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when preceding a list element, modify the entire list element and do not modify the individual elements of the list.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Other words used to describe the relationship between elements or layers should be construed in a like fashion (e.g., "between" vs "directly between", "adjacent" vs "immediately adjacent ", "on" versus "directly on").

Like numbers refer to like elements throughout. Therefore, even if the same or similar numbers are not mentioned or illustrated in the corresponding drawings, the same or similar numbers may still be explained with reference to other drawings. In addition, elements without reference numbers may be explained with reference to other drawings.

While the inventive concepts have been particularly shown and described with reference to embodiments thereof, it should be understood that various changes in form and details could be made without departing from the spirit and scope of the above claimed claims.

100‧‧‧Integrated circuit FR‧‧‧Front end of line (FEOL) area BR‧‧‧Back end of line (BEOL) area C11, C12, C21~C24, C31~C33‧‧‧Standard cells 111, 112, 113, 114‧‧‧Power Rails 131, 132‧‧‧Power Lines 121,122,123,124‧‧‧Through Hole Stacking 200‧‧‧System on Chip 210‧‧‧System Bus 220‧‧‧Modem 230‧‧‧Display Control 240‧‧‧memory 250‧‧‧external memory controller 260‧‧‧central processing unit 270‧‧‧business unit 280‧‧‧power management integrated circuit 290‧‧‧graphics processing unit 300‧‧‧calculation System 310‧‧‧processor 320‧‧‧input/output device 330‧‧‧network interface 340‧‧‧random access memory 341‧‧‧program 350‧‧‧read-only memory 360‧‧‧storage device 361 ‧‧‧Database 370‧‧‧Bus TR11~TR16, TR21~TR26, TR31, TR32, TR41‧‧‧Trace P11~P13, P21~P27, P31, P32, P41‧‧‧Conductive pattern V11~V14, V21 ~V24, V31~V33‧‧‧Through hole S, S1, S2‧‧‧distance W0, L1‧‧‧length W, W1, W2, W3, M‧‧‧width P‧‧‧pitch X1, X2‧ ‧‧Center line D11‧‧‧RTL data D12‧‧‧standard cell library D13‧‧netlist data D14‧‧‧RTL data D15‧‧‧layout data S200 , S400, S400', S420, S420', S422, S424, S440, S460, S600, S800, S820, S840‧‧‧operation

Embodiments of the inventive concept will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings in which: FIG. 1 is an integrated circuit (IC) according to an exemplary embodiment of the inventive concept Perspective view of part of . 2A-2C are diagrams of examples of via stacks. 3A to 3C are diagrams of examples of via stacks according to exemplary embodiments of the inventive concept. FIG. 4 is a plan view of an example of a via stack according to an exemplary embodiment of the inventive concept. FIG. 5 is a perspective view of an example of a via stack according to an exemplary embodiment of the inventive concept. FIG. 6 is a diagram of an example of a via array according to an exemplary embodiment of the inventive concept. 7A to 7C are diagrams of an example of a via array according to an exemplary embodiment of the inventive concept. FIG. 8 is a flowchart of a method of manufacturing an integrated circuit according to an exemplary embodiment of the inventive concept. FIG. 9 is a flowchart of an example of operation S400 shown in FIG. 8 according to an exemplary embodiment of the inventive concept. FIG. 10 is a flowchart of an example of operation S420 shown in FIG. 9 according to an exemplary embodiment of the inventive concept. FIG. 11 is a block diagram of a system-on chip (SoC) according to an exemplary embodiment of the inventive concept. Referring to FIG. FIG. 12 is a block diagram of a computing system including a memory configured to store a program, according to an exemplary embodiment of the inventive concept.

TR11, TR12, TR21~TR25, TR31, TR32‧‧‧trace

P11, P12, P21~P25, P31, P32‧‧‧conductive pattern

V11, V12, V21, V22‧‧‧through hole

Claims (25)

An integrated circuit comprising: a first conductive layer including first ones of conductive patterns on first traces extending parallel to each other in a first lateral direction; a second conductive layer including The second conductive pattern and the third conductive pattern in the conductive patterns on the second traces extending parallel to each other; the third conductive layer, including the conductive patterns on the third traces extending parallel to each other in the first lateral direction In the fourth conductive pattern, wherein the third trace is not vertically aligned with the first trace; the first via array includes a first via and a second via, wherein the first via A hole is connected to the top surface of the first conductive pattern and the bottom surface of the second conductive pattern, and wherein the second via is connected to the top surface of the first conductive pattern and the third conductive pattern. a bottom surface of the pattern; and a second via array comprising a third via and a fourth via, wherein the third via is connected to the top surface of the second conductive pattern and the bottom of the fourth conductive pattern surface, and wherein the fourth via is connected to the top surface of the third conductive pattern and the bottom surface of the fourth conductive pattern, wherein the second conductive layer further includes a fifth conductive pattern, the A fifth conductive pattern is aligned with one of the second traces between the second conductive pattern and the third conductive pattern, the fifth conductive pattern extends in the second lateral direction and does not coupled with the second conductive pattern and the third conductive pattern. The integrated circuit described in item 1 of the scope of the patent application, wherein the first pitch between the first through hole and the second through hole and the distance between the third through hole and the fourth through hole The second pitch between the traces is a multiple of the third pitch between the second traces. The integrated circuit as described in item 1 of the patent scope of the application, wherein the first conductive layer further includes a sixth conductive pattern among the conductive patterns on the first trace, wherein the first via hole array is further including a fifth via hole and a sixth via hole, wherein the fifth via hole is connected to the top surface of the sixth conductive pattern and the bottom surface of the second conductive pattern, and wherein the sixth via hole connected to the top surface of the sixth conductive pattern and the bottom surface of the third conductive pattern. The integrated circuit described in item 3 of the scope of the patent application, wherein the first pitch between the first through hole and the fifth through hole and the distance between the second through hole and the sixth through hole The second pitch between the traces is a multiple of the third pitch between the first traces. The integrated circuit described in item 1 of the scope of the patent application, wherein the third conductive layer further includes a sixth conductive pattern among the conductive patterns on the third trace, wherein the second via hole array is further including a fifth via hole and a sixth via hole, wherein the fifth via hole is connected to the top surface of the second conductive pattern and the bottom surface of the sixth conductive pattern, and wherein the sixth via hole connected to the top surface of the third conductive pattern and the bottom surface of the sixth conductive pattern. The integrated circuit described in item 5 of the scope of the patent application, wherein the first pitch between the third through hole and the fifth through hole and the distance between the fourth through hole and the sixth through hole The second pitch between the third traces is a multiple of the third pitch between the third traces. The integrated circuit described in claim 1 of the scope of the patent application further includes: a fourth conductive layer including a sixth conductive pattern among the conductive patterns on the fourth traces extending parallel to each other in the second lateral direction; And a third via array including a plurality of vias each connected to the top surface of the fourth conductive pattern and the bottom surface of the sixth conductive pattern. The integrated circuit as described in item 7 of the scope of the patent application, wherein the length of the sixth conductive pattern in the first lateral direction is greater than the node between the plurality of via holes of the third via hole array distance. The integrated circuit described in item 1 of the scope of the patent application further includes: a plurality of transistors, under the bottom surface of the third conductive layer, wherein the first through hole array and the second through hole The array is configured to supply a source of at least one of the plurality of transistors with a power supply voltage. The integrated circuit as described in item 1 of the patent scope of the application further includes: a plurality of standard cells arranged under the bottom surface of the third conductive layer, wherein the first through-hole array and the second The via array is configured to power the plurality of standard cells. The integrated circuit according to claim 1, wherein the first pitch between the first traces is different from the second pitch between the third traces. An integrated circuit comprising: A first conductive layer comprising first ones of conductive patterns on first traces extending parallel to each other in a first lateral direction; a second conductive layer comprising second conductive patterns extending parallel to each other in a second lateral direction. a second conductive pattern and a third conductive pattern in the conductive patterns on the trace, the second lateral direction being orthogonal to the first lateral direction; and a first array of vias comprising a first via and a second via , wherein the first via is connected to the top surface of the first conductive pattern and the bottom surface of the second conductive pattern, and wherein the second via is connected to the top surface of the first conductive pattern surface and the bottom surface of the third conductive pattern, wherein the length of each of the first conductive pattern, the first via hole and the second via hole in the second lateral direction is greater than the The length of the conductive pattern on the first trace of the first conductive layer in the second lateral direction, and wherein the center of the first conductive pattern is aligned with the first trace of the first conductive layer One of the traces is aligned to a centerline between two adjacent first traces of the first conductive layer. The integrated circuit described in item 12 of the scope of the patent application, wherein if the width W of the first conductive pattern satisfies the equation: 2nP-M-2S<W

(2n+1)PM-2S, the first conductive pattern is aligned to the centerline between the two adjacent first traces of the first conductive layer, and wherein if the first The width W of a conductive pattern satisfies the equation: (2n+1)PM-2S<W

(2n+2)PM-2S, the first conductive pattern is aligned with the one of the first traces of the first conductive layer, wherein M and P respectively represent the first conductive layer The width and pitch of the conductive pattern on the first trace, S represents the shortest distance between the conductive patterns of the first conductive layer, W represents the first conductive pattern on the second The width in the horizontal direction, and n is a positive integer. The integrated circuit according to claim 12, wherein the first conductive pattern, the first through hole and the second through hole have the same length in the second transverse direction. The integrated circuit described in claim 12, wherein the first pitch between the first via hole and the second via hole is between the second traces of the second conductive layer Multiples of the second pitch between. The integrated circuit as described in claim 12 of the scope of the patent application further includes: a third conductive layer including a fourth conductive pattern among the conductive patterns on the third traces extending parallel to each other in the first lateral direction; and a third via hole and a fourth via hole, wherein the third via hole is connected to the top surface of the second conductive pattern and the bottom surface of the fourth conductive pattern, and wherein the fourth via hole is connected to the top surface of the third conductive pattern and the bottom surface of the fourth conductive pattern. The integrated circuit according to claim 16, wherein the length of each of the fourth conductive pattern, the third via hole and the fourth via hole in the second lateral direction greater than the length of the conductive pattern on the third trace of the third conductive layer in the second lateral direction, and wherein the center of the fourth conductive pattern is aligned with the Said the first One of the three traces or the centerline between two third traces of the third conductive layer is aligned. An integrated circuit comprising: a first conductive layer including first ones of conductive patterns on first traces extending parallel to each other in a first lateral direction; a second conductive layer including The second conductive pattern and the third conductive pattern in the conductive patterns on the second traces extending parallel to each other; the third conductive layer, including the conductive patterns on the third traces extending parallel to each other in the first lateral direction The fourth conductive pattern in; the first via array, including first vias, each of the first vias is connected to the top surface of the first conductive pattern and is connected to the second conductive pattern and at least one of the bottom surface of the third conductive pattern; and a second via array including second vias, each of which is connected to the second conductive pattern. at least one of the top surface of the pattern and the top surface of the third conductive pattern, and connected to the bottom surface of the fourth conductive pattern, wherein the first vias of the first via array are located in the The intersection of the first trace and the second trace in a plan view, wherein the second via hole of the second via array is located at the intersection of the second trace and the third trace The intersection in the plan view, wherein the integrated circuit further includes: a plurality of transistors, under the bottom surface of the third conductive layer, wherein the first through-hole array and the second through-hole array is configured to the A source of at least one of the plurality of transistors supplies a power supply voltage. The integrated circuit as described in claim 18 of the patent application, wherein the second conductive layer further includes a fifth conductive pattern, and the fifth conductive pattern is aligned with the second conductive pattern located in the second trace. One between the third conductive pattern, the fifth conductive pattern extends in the second lateral direction and is not coupled with the second conductive pattern and the third conductive pattern. The integrated circuit as described in item 18 of the patent scope of the application, wherein the first conductive layer further includes a fifth conductive pattern, and the fifth conductive pattern extends in the first lateral direction, wherein the first via The hole array further includes third vias each connected to a top surface of the fifth conductive pattern and to bottom surfaces of the third conductive pattern and the second conductive pattern In at least one of the embodiments, the third via hole is located at an intersection of the first trace and the second trace in the plan view. The integrated circuit as described in item 18 of the scope of the patent application, wherein the third conductive layer further includes a fifth conductive pattern, and the fifth conductive pattern extends in the first lateral direction, wherein the second via The array of holes further includes third vias each connected to at least one of the top surfaces of the third conductive pattern and the second conductive pattern and connected to the fifth conductive pattern. The bottom surface of the conductive pattern, the third through hole is located at the intersection of the second trace and the third trace in the plan view. A method of manufacturing an integrated circuit, the method comprising: placing and routing a plurality of standard cells based on a library of cells and input data defining the integrated circuit, wherein the placing and routing the plurality of standard cells The cell includes: adding a via stack configured to interconnect power rails and power nets of the plurality of standard cells, wherein adding the via stack includes: arranging the vias An intersection in plan view between traces of adjacent conductive layers of the integrated circuit. The method according to claim 22, wherein the placing and routing the plurality of standard cells further includes: generating a conductive pattern through the via stack, and the conductive pattern is insulated from the via stack. The method of claim 22, wherein the adding the via stack further comprises: arranging the via array based on the length of the via bar. The method according to claim 22, wherein the placing and routing the plurality of standard cells includes: generating layout data for defining the layout of the integrated circuit, and the method further includes: using a method based on A mask fabricated by the layout data is used to pattern the via stack.

Images