TWI857363B - Semiconductor substrate structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor substrate structure includes a first group of circuit structure and a second group of circuit structure. The first group of circuit structure includes a plurality of first wiring layers and a plurality of first conductive connectors, and each of the first conductive connectors includes a conductive cap. The second group of circuit structure includes a plurality of second wiring layers and a plurality of second conductive connectors. The first group of circuit structure and the second group of circuit structure are electrically connected through the bonding of the first conductive connectors and the second conductive connectors to form a multilayer redistribution structure. A manufacturing method of the semiconductor substrate structure is also provided.

Description

Semiconductor substrate structure and manufacturing method thereof

The present invention relates to a semiconductor substrate structure and a manufacturing method thereof.

In integrated circuit applications, a redistribution wiring layer (RDL) is a multi-layer structure formed by conductive materials and dielectric materials, and the RDL is often manufactured on a temporary substrate. However, the materials used in the multi-layer structure and the materials used in the temporary substrate have a mismatch in coefficient of thermal expansion (CTE). Therefore, the process of continuously forming the multi-layer structure (continuously forming at least four layers) on the temporary substrate is prone to warping problems. The more layers there are, the more obvious the warping problem will be. As a result, the yield and electrical performance of the semiconductor substrate structure will be adversely affected.

The present invention provides a semiconductor substrate structure and a manufacturing method thereof, which can maintain better yield and electrical performance while having a multi-layer redistribution structure.

A semiconductor substrate structure of the present invention includes a first set of circuit structures and a second set of circuit structures. The first set of circuit structures includes multiple first circuit layers and multiple first conductive connectors, and each first conductive connector includes a conductive cover. The second set of circuit structures includes multiple second circuit layers and multiple second conductive connectors. The first set of circuit structures and the second set of circuit structures are electrically connected by bonding multiple first conductive connectors and multiple second conductive connectors to form a multi-layer redistribution structure.

A method for manufacturing a semiconductor substrate structure of the present invention comprises at least the following steps: forming a first set of circuit structures on a first temporary carrier, wherein the first set of circuit structures comprises a plurality of first circuit layers and a plurality of first conductive connectors, and each first conductive connector comprises a conductive cover; forming a second set of circuit structures on a second temporary carrier, wherein the second set of circuit structures comprises a plurality of second circuit layers and a plurality of second conductive connectors; the plurality of first conductive connectors of the first set of circuit structures are bonded to the plurality of second conductive connectors of the second set of circuit structures to form an electrical connection and form a multi-layer redistribution structure.

Based on the above, the present invention first separately manufactures multiple sets of circuit structures on a temporary substrate, and then directly joins and assembles the aforementioned multiple sets of circuit structures into a multi-layer redistribution structure. In this way, compared with a multi-layer redistribution structure manufactured continuously at one time, the degree of warping can be effectively reduced, so that the semiconductor substrate structure can maintain better yield and electrical performance while having a multi-layer redistribution structure.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The following will refer to the drawings to fully describe the exemplary embodiments of the present invention, but the present invention can also be implemented in many different forms and should not be construed as being limited to the embodiments described herein. In the drawings, for the sake of clarity, the size and thickness of each region, part and layer may not be drawn according to the actual scale. For ease of understanding, the same elements in the following description will be described with the same symbols.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

Directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings and are not intended to imply an absolute orientation.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

1A to 1C are partially schematic cross-sectional views showing a method for manufacturing a semiconductor substrate structure according to some embodiments of the present invention. FIG. 1D is a schematic diagram showing the bonding of a conductive connector of another alternative embodiment of FIG. 1C. FIG. 1E and FIG. 1F are partially schematic cross-sectional views showing semiconductor substrate structures according to other embodiments of the present invention. Referring to FIG. 1A, a first set of circuit structures 110 is formed on a first temporary carrier 10, wherein the first temporary carrier 10 can be made of glass, plastic, silicon, metal or other suitable materials, as long as the material can withstand subsequent processes and simultaneously support the structure formed thereon.

In some embodiments, a first release layer 12 (e.g., a light-to-heat conversion film or other suitable release layer) may be optionally applied between the first temporary carrier 10 and the first set of circuit structures 110 to enhance the releasability between the first temporary carrier 10 and the first set of circuit structures 110 in subsequent processes and to improve the planarity of the first set of circuit structures 110, but the present invention is not limited thereto.

In this embodiment, a first set of circuit structures 110 including multiple first circuit layers 111 (three layers are schematically shown in FIG. 1A ) and multiple first conductive connectors 112 may be formed on the first temporary carrier 10, wherein each first circuit layer 111 may include a first conductive pattern 111a, a first dielectric layer 111b and/or a first conductive via 111c, and each first conductive connector 112 may include a conductive column 112a and a conductive cover 112b. Here, the first conductive pattern 111a and the first conductive via 111c may be embedded in the first dielectric layer 111b, and the conductive cover 112b may be located on the conductive column 112a, but the present invention is not limited thereto. In an embodiment not shown, the conductive column 112a may be omitted, that is, the conductive cover 112b may be directly formed on the first circuit layer 111 to directly serve as the first conductive connector 112.

In some embodiments, a deposition process, a lithography process, an etching process or other suitable processes may be used to form a first conductive pattern 111a on the first temporary carrier 10. Next, a first dielectric layer 111b including a plurality of openings may be formed on the first temporary carrier 10 using, for example, a coating process, a lithography etching process or other suitable processes, wherein the openings expose at least a portion of the first conductive pattern 111a for electrical connection. Then, a conductive material may be formed in the openings of the first dielectric layer 111b to form a first conductive via 111c using a suitable deposition process. Then, the above steps are performed multiple times to form a multi-layer first circuit layer 111. It should be noted that the first group of circuit structures 110 shown in FIG. 1A is merely exemplary, and the first group of circuit structures 110 may be formed with more or fewer layers according to circuit design requirements. As long as the first group of circuit structures 110 includes at least two first circuit layers 111 and a plurality of conductive connectors 112, they are within the protection scope of the present invention.

In some embodiments, the material of the first conductive pattern 111a and the first conductive via 111c may include copper, gold, nickel, aluminum, platinum, tin, a combination thereof, an alloy thereof, or other suitable conductive materials, and the material of the first dielectric layer 111b may include polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), an inorganic dielectric material (such as silicon oxide, silicon nitride, etc.) or other suitable electrical insulating materials, but the present invention is not limited thereto.

In some embodiments, the material of the conductive pillar 112a may include copper, and the material of the conductive cover 112b may include solder, but the present invention is not limited thereto, and the conductive pillar 112a and the conductive cover 112b may be other appropriate conductive materials.

In this embodiment, the first group of circuit structures 110 includes a bottom surface 110b close to the first temporary carrier 10, wherein the first conductive pattern 111a and the first dielectric layer 111b at the bottom surface 110b may be substantially flush. In addition, the first conductive via 111c gradually becomes thicker (such as the width or diameter gradually becomes thicker) in the direction toward the plurality of conductive connectors 112. In other words, the first conductive via 111c gradually becomes thinner (such as the width or diameter gradually becomes thinner) in the direction toward the first temporary carrier 10, but the present invention is not limited thereto.

In some embodiments, the distribution density of the first conductive pattern 111a on the bottom surface 110b of the first set of circuit structures 110 must be sufficient for subsequent mounting of a semiconductor chip, but the present invention is not limited thereto.

In some embodiments, the top surface of the conductive cap 112b on the conductive pillar 112a may be optionally planarized (e.g., a grinding process, fly cutting, a chemical mechanical polishing (CMP) process, or a combination thereof) to ensure the top flatness of the first conductive connector 112, but the present invention is not limited thereto.

Referring to FIG. 1B , a second set of circuit structures 120 is formed on the second temporary substrate 20, wherein the second set of circuit structures 120 includes a plurality of second circuit layers 121 (three layers are schematically shown in FIG. 1B ) and second conductive connectors 122, and each second circuit layer 121 may include a second conductive pattern 121a, a second dielectric layer 121b and/or a second conductive via 121c. Here, the second conductive pattern 121a and the second conductive via 121c may be embedded in the second dielectric layer 121b, but the present invention is not limited thereto.

In this embodiment, the second group of circuit structures 120 includes a bottom surface 120b close to the second temporary carrier 20, wherein the second conductive pattern 121a and the second dielectric layer 121b at the bottom surface 120b may be substantially flush. In addition, the second conductive via 121c gradually becomes thicker (e.g., the width or diameter gradually becomes thicker) in the direction toward the plurality of second conductive connectors 122. In other words, the second conductive via 121c gradually becomes thinner (e.g., the width or diameter gradually becomes thinner) in the direction toward the second temporary carrier 20, but the present invention is not limited thereto.

In some embodiments, the second conductive connector 122 may be in a pad form, a conductive pillar form, or other suitable forms, and the present invention is not limited thereto. In addition, in an embodiment not shown, the second conductive connector 122 may be composed of a first seed layer, a second seed layer (material such as titanium/copper (Ti/Cu)) and an electroplating layer. (material is, for example, copper) are sequentially stacked, but the present invention is not limited thereto. In other embodiments, the second conductive connector 122 may include other suitable conductive materials such as silver, gold, nickel or their alloys, for example, Cu, Cu/Ni/Au, Cu/Ti, Cu/Ag or the like. For example, an adhesive layer (material is, for example, titanium) may be formed on a conductive pad (material is, for example, copper), and then a metal layer (material is, for example, silver) may be formed on the adhesive layer by electroplating, sputtering or other suitable deposition methods, wherein the thickness of the adhesive layer may be less than the thickness of the metal layer, but the present invention is not limited thereto, and the form of the second conductive connector 122 may be selected according to actual design requirements.

In some embodiments, the second conductive pattern 121a of the bottom surface 120b of the second set of circuit structures 120 may be used for subsequent mounting of a substrate or an external terminal, but the present invention is not limited thereto.

It should be noted that other specific details of forming the second set of circuit structures 120 (such as materials, formation methods and the arrangement of the second release layer 22) are similar to those of forming the first set of circuit structures 110, and will not be elaborated herein.

Please refer to FIG. 1C , the structure shown in FIG. 1B is flipped upside down, and the first set of wiring structures 110 and the second set of wiring structures 120 are directly bonded, so that the first conductive connector 112 is bonded to the second conductive connector 122 to form a multi-layer redistribution wiring structure RDL. In addition, optionally, a primer 101 can be set between the first set of wiring structures 110 and the second set of wiring structures 120, and the primer 101 can fill the gap between the first conductive connector 112 and the second conductive connector 122, so that the primer 101 can surround the first conductive connector 112 and the second conductive connector 122 to further improve the bonding reliability, but the present invention is not limited thereto. The semiconductor substrate structure 100 of this embodiment has been substantially completed through the above-mentioned production.

In this embodiment, the semiconductor substrate structure 100 includes a first set of wiring structures 110 and a second set of wiring structures 120. The first set of wiring structures 110 includes a plurality of first wiring layers 111 and a plurality of first conductive connectors 112. The second set of wiring structures 120 includes a plurality of second wiring layers 121 and a plurality of second conductive connectors 122. The first set of wiring structures 110 and the second set of wiring structures 120 are electrically connected to each other by bonding the plurality of first conductive connectors 112 and the plurality of second conductive connectors 122 and form a multi-layer redistribution wiring structure RDL. Accordingly, in this embodiment, multiple sets of circuit structures (the first set of circuit structures 110 and the second set of circuit structures 120) are first fabricated separately on temporary carriers (the first temporary carrier 10 and the second temporary carrier 20), and then the multiple sets of circuit structures are directly joined and assembled into a multi-layer redistribution wiring structure (multi-layer redistribution wiring structure RDL). In this way, compared with the one-time continuous fabrication of the multi-layer redistribution wiring structure, the warp degree can be effectively reduced, so that the semiconductor substrate structure 100 can maintain a better yield and electrical performance while having the multi-layer redistribution wiring structure RDL.

Furthermore, due to process limitations, the difficulty is positively correlated with the number of layers to be manufactured. Therefore, the more layers are to be manufactured, the higher the probability that the entire redistribution structure will be damaged during the manufacturing process, and the yield and cost issues cannot be effectively controlled. In this embodiment, the multi-layer redistribution structure RDL is split into multiple groups of circuit structures with fewer layers and manufactured separately, thereby avoiding the problem of continuously stacking multiple layers and being unable to effectively control the yield and cost, but the present invention is not limited to this.

In some embodiments, since the first set of wiring structures 110 and the second set of wiring structures 120 have a bonding interface formed by the conductive cap 112b including solder, the connection of the multi-layer redistribution structure RDL can be regarded as including a solder-containing connection, but the present invention is not limited thereto.

In some embodiments, the first set of circuit structures 110 and the second set of circuit structures 120 may be aligned and joined to each other, so the first conductive connector 112 and the second conductive connector 122 may be joined in a one-to-one manner, but the present invention is not limited thereto.

In some embodiments, the height of the conductive post 112a of the first conductive connector 112 may be greater than the height of the second conductive connector 122, but the present invention is not limited thereto. In other alternative embodiments, as shown in FIG. 1D , the height of the conductive post 112a of the first conductive connector 112 may be substantially equal to the height of the second conductive connector 122. In other words, the height of the conductive post 112a of the first conductive connector 112 and the height of the second conductive connector 122 may be adjusted according to actual design requirements, and the present invention is not limited thereto.

In some embodiments, a reflow process may be performed on the conductive cover 112 b of the first conductive connector 112 to electrically couple the second conductive connector 122 to the conductive pillar 112 a , but the present invention is not limited thereto.

In some embodiments, when the line pitch/spacing (L/S) (e.g., line width) of the line is finer, the process requirements will be more stringent, so it will be more difficult to form a multi-layer redistribution wiring structure. The present embodiment uses a method of joining and assembling multiple sets of line structures to produce a fine line pitch/spacing structure, which can have greater advantages in yield and electrical performance compared to a continuously formed structure. For example, the first set of line structures 110 and the second set of line structures 120 can both have a fine line pitch/spacing of at least less than 7 microns, so the first set of line structures 110 and the second set of line structures 120 can be joined and assembled to form a multi-layer redistribution wiring structure RDL with a fine line pitch/spacing, but the present invention is not limited to this.

In some embodiments, as shown in FIG. 1C , each first circuit layer 111 includes two adjacent first circuits, and the center points of the two adjacent first circuits have a first spacing 111s, and each second circuit layer 121 includes two adjacent second circuits, and the center points of the two adjacent second circuits have a second spacing 121s, and the first spacing 111s of each first circuit layer 111 is smaller than the second spacing 121s of each second circuit layer 121, and the spacing of each layer gradually increases from the first group of circuit structures 110 toward the second group of circuit structures 120. Here, the first spacing 111s and the second spacing 121s are the minimum spacings of each layer, but the present invention is not limited thereto, and in other embodiments, the first spacing 111s and the second spacing 121s may be the average spacings of each layer.

Fig. 5A is a partial schematic cross-sectional view showing the pitch of the circuit structure. Fig. 5B is a partial schematic top view corresponding to Fig. 5A. Furthermore, as shown in FIG. 5A and FIG. 5B , the circuit layer may have a fine spacing F and a coarse spacing C, and the spacing may be, for example, the distance between the center points of two adjacent circuits, such as the distance between the center points of two adjacent circuits L1 is the fine spacing F, and the distance between the center points of two adjacent circuits L2 is the coarse spacing C, or the distance between two adjacent pads, such as the distance between the center points of two adjacent pads P1 is the fine spacing F, and the distance between the center points of two adjacent pads P2 is the coarse spacing C. Therefore, the aforementioned first spacing 111s and the second spacing 121s may use those designs according to actual design requirements, and the present invention is not limited thereto.

In some embodiments, the first conductive via 111c gradually becomes thicker (e.g., the width or diameter gradually becomes thicker) in a direction toward the first conductive connector 112, and the second conductive via 121c gradually becomes thicker (e.g., the width or diameter gradually becomes thicker) in a direction toward the second conductive connector 122. In other words, the first conductive via 111c gradually becomes thicker in a direction toward the first temporary load. The first conductive via 111c gradually tapers in the direction toward the second temporary carrier 20 (e.g., the width or the diameter gradually tapers), and the second conductive via 121c gradually tapers in the direction toward the second temporary carrier 20 (e.g., the width or the diameter gradually tapers). That is, after the bonding process, the direction in which the first conductive via 111c gradually tapers is opposite to the direction in which the second conductive via 121c gradually tapers.

It should be noted that, according to the requirements of actual applications, the first temporary carrier 10 and/or the second temporary carrier 20 may be optionally removed to expose the first conductive pattern 111a and/or the second conductive pattern 121a and electrically connect with other components. Here, the release layer may be peeled off by applying external energy between the bottom surface of the circuit structure and the temporary carrier.

In some embodiments, the number of groups of wiring structures may not be limited to two groups. For example, the multi-layer redistribution structure RDL1 of the semiconductor structure 100A shown in FIG. 1E may further include a third group of wiring structures 130, wherein the third group of wiring structures 130 includes a plurality of third wiring layers 131 and a third conductive connector 132. Further, the second group of wiring structures 120 is disposed between the first group of wiring structures 110 and the third group of wiring structures 130 and is electrically connected to each other. The second group of wiring structures 120 has another conductive connector 123 relative to the first group of wiring structures 110, and the other conductive connector is bonded to the third conductive connector 132, but the present invention is not limited thereto. In addition, another primer 102 may be disposed between the second circuit structure 120 and the third circuit structure 130, and the primer 102 may fill the gap between the fourth conductive connector 123 and the third conductive connector 132, so that the primer 102 may surround the fourth conductive connector 123 and the third conductive connector 132 to further improve the bonding reliability, but the present invention is not limited thereto.

In some embodiments, the semiconductor structure 100A is completed by, for example, the following steps. The semiconductor structure 100A may be continued from FIG. 1C , the second temporary carrier 20 is removed, a fourth conductive connection 123 is formed on the second set of wiring structures 110, and a third set of wiring structures 130 is formed on the third temporary carrier 30 formed with the third release layer 32, and then the fourth conductive connection 123 and the third conductive connection 132 are joined to form a multi-layer redistribution structure RDL1, but the present invention is not limited thereto.

In some embodiments, the number of first circuit layers 111 of the first group of circuit structures 110 (six-layer structure) is the same as the number of second circuit layers 121 of the second group of circuit structures 120 (six-layer structure), as shown in FIG. 1C . However, there may be different implementations. For example, in the semiconductor substrate structure 100A shown in FIG. 1E , the number of first circuit layers 111 of the first group of circuit structures 110 (six-layer structure) is different from the number of third group of circuit structures 130 (four-layer structure), and the aforementioned quantity difference may be one layer or two layers.

In some embodiments, each third circuit layer includes two adjacent third circuits, and there is a third spacing 131s between the center points of the two adjacent third circuits. The second spacing 121s of each second circuit layer 121 is smaller than the third spacing 131s of each third circuit layer 131, and the spacing of each layer gradually increases from the first group of circuit structures 110 toward the third group of circuit structures 130.

In some embodiments, the thickness of the first circuit layer 111 of the first group of circuit structures 110 (six-layer structure) is the same as the thickness of the second circuit layer 121 of the second group of circuit structures 120 (six-layer structure), but there may also be different implementations. For example, in the semiconductor substrate structure 100B shown in FIG. 1F , the thickness of the first circuit layer 111 of the first group of circuit structures 110 and the thickness of the second circuit layer 121 of the second group of circuit structures 120 are different from the thickness of the third group of circuit structures 130 to form a multi-layer redistribution structure RDL2, but the present invention is not limited to this.

It must be noted here that the following embodiments continue to use the component numbers and part of the contents of the above embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments, and the following embodiments will not be repeated.

FIG. 2 is a partial schematic cross-sectional view showing semiconductor structures according to some other embodiments of the present invention. Referring to FIG. 2 , the semiconductor substrate structure 200 of the present embodiment is different from the semiconductor structure 100 of FIG. 1C in that the second group of wiring structures 220 has a coarse line pitch/spacing of at least 7 microns, that is, in the present embodiment, the multi-layer redistribution wiring structure RDL3 can be a combination of a coarse line pitch/spacing wiring structure and a fine line pitch/spacing wiring structure, and has more application flexibility. In addition, the primer 101 can be omitted in the present embodiment, but the primer 101 can also be further configured.

Furthermore, the second circuit structure 220 includes multiple second circuit layers 221 (three layers are schematically shown in FIG. 2 ) and second conductive connectors 222, and each second circuit layer 221 may include a second conductive pattern 221a, a second dielectric layer 221b and/or a second conductive via 221c. Here, the second conductive pattern 221a and the second conductive via 221c may be embedded in the second dielectric layer 221b, which will not be described in detail.

In this embodiment, the density of the second conductive pattern 221a of the second circuit layer 221 close to the second conductive connector 222 may be denser than the density of the second conductive pattern 221a of the second circuit layer 221 far from the second conductive connector 222. In other words, the density of the conductive pattern in the second set of circuit structures 220 may present a sparse to dense circuit distribution from the second temporary carrier 20 toward the second conductive connector 222, but the present invention is not limited thereto.

In the present embodiment, the material and formation method of the second conductive pattern 221a and/or the second conductive via 221c are similar to those of the second conductive pattern 121a and/or the second conductive via 121, but the material of the second dielectric layer 221b is different from that of the second dielectric layer 121b. For example, the material of the second dielectric layer 221b may be ABF (Ajinomoto Build-up Film), PP (Polypropylene) or the like, and the second dielectric layer 221b may be formed by an appropriate deposition process.

In some embodiments, the total thickness T2 of the second set of wiring structures 220 is greater than the total thickness T1 of the second set of wiring structures 120 in FIG. 1C , so the multi-layer redistribution structure RDL3 may be a thick film RDL, but the present invention is not limited thereto.

3A to 3E are partially schematic cross-sectional views showing methods for manufacturing semiconductor structures according to some further embodiments of the present invention. Referring to FIG3A , in continuation of FIG1C , the second temporary carrier 20 and the second release layer 22 are removed to expose the second conductive pattern 121a and the second dielectric layer 121b (which can be regarded as the terminal end of the multi-layer redistribution wiring structure RDL) of the bottom surface 120b of the second set of wiring structures 120. Here, the height of the conductive pillar 112a of the first conductive connector 112 as shown in FIG1D can be selected to be substantially equal to the height of the second conductive connector 122.

Next, a plurality of fifth conductive connectors 340 may be formed on the second conductive pattern 121a of the bottom surface 120b of the second set of circuit structures 120, wherein the fifth conductive connector 340 includes a conductive column 341 and a conductive cover 342 formed thereon. Here, the conductive column 341 may be made of copper, and the conductive cover 342 may be made of solder, but the present invention is not limited thereto, and the conductive column 341 and the conductive cover 342 may also be made of other suitable materials.

Referring to FIG. 3B , the multi-layer redistribution wiring structure RDL is bonded to the substrate 350 via the fifth conductive connector 340. In some embodiments, the conductive cover 342 of the fifth conductive connector 340 may be subjected to a reflow process to electrically couple the multi-layer redistribution wiring structure RDL to the substrate 350, but the present invention is not limited thereto. Here, the substrate 350 may be a ceramic substrate, a laminated organic substrate, a packaging substrate, an integrated substrate, or the like.

In some embodiments, the substrate 350 includes a core layer 351, a build-up layer structure 352 and a plurality of through-holes 351a, wherein the build-up layer structure 352 is formed on two sides of the build-up layer structure 352, respectively, and the plurality of through-holes 351a penetrate the core layer 351 to electrically connect the build-up layer structures 352 on both sides, wherein the build-up layer structure 352 includes a conductive pattern 352a embedded in a dielectric layer, but the present invention is not limited thereto, and in embodiments not shown, the substrate 350 may not have a core layer 351.

3C , the first temporary carrier 10 and the first release layer 12 are removed to expose the first conductive pattern 111a and the first dielectric layer 111b (which can be regarded as the chip end of the multi-layer redistribution wiring structure RDL) of the bottom surface 110b of the first set of wiring structures 110. In addition, the gap between the multi-layer redistribution wiring structure RDL and the substrate 350 in FIG. 3C can be selectively filled with the primer 103.

Referring to FIG. 3D , a plurality of chip connectors 360 are formed on the first conductive pattern 111a of the bottom surface 110b of the first set of circuit structures 110, wherein the chip connector 360 includes a conductive column 361 and a conductive cover 362 formed thereon. Here, the conductive column 361 can be made of copper, and the conductive cover 362 can be made of solder, but the present invention is not limited thereto, and the conductive column 361 and the conductive cover 362 can also be made of other suitable materials. In addition, a plurality of external terminals 370 can be formed on the substrate 350, wherein the multi-layer redistribution wiring structure RDL is electrically connected to the external terminal 260 through the substrate 350. Here, the distribution density of the plurality of chip connectors 360 can be greater than the distribution density of the plurality of fifth conductive connectors 340.

3E , the semiconductor chip 40 can be connected to the bottom surface 110 b of the first set of circuit structures 110 using, for example, flip chip bonding. For example, the conductive bumps 42 of the semiconductor chip 40 can be bonded to the conductive caps 362 of the chip connector 360. In other words, the conductive bumps 42 of the semiconductor chip 40 can be in direct contact with the conductive caps 362 of the chip connector 360 to form a heterogeneous integration module or system.

In some embodiments, the semiconductor chip 40 is, for example, a logic chip, a memory chip, a three-dimensional integrated circuit (3DIC) chip (such as a high bandwidth memory chip), and/or the like, wherein the 3DIC chip includes a plurality of layers stacked on each other and through silicon vias (TSVs) are formed to provide vertical electrical connections between the layers, but the present invention is not limited thereto.

In some embodiments, the height 42h of the conductive bump 42 may be greater than the height 360h of the corresponding chip connector 360, but the present invention is not limited thereto. The height 42h of the conductive bump 42 and the height 360h of the chip connector 360 may be determined according to actual design requirements.

In some embodiments, the bottom glue 104 may be formed on the bottom surface 110b of the first set of wiring structures 110 to fill the gap between the bottom surface 110b and the semiconductor chip 40, thereby enhancing the reliability of flip chip bonding. In some embodiments, more than one semiconductor chip 40 performing the same or different functions may be arranged on the first set of wiring structures 110. In this case, the plurality of semiconductor chips 40 may be electrically connected to the first set of wiring structures 110 and electrically connected to each other through the first set of wiring structures 110. The number of semiconductor chips 40 arranged on the first set of wiring structures 110 does not constitute a limitation of the present disclosure. The semiconductor structure 300 of the present embodiment has been substantially completed through the above-mentioned production.

In some embodiments, the external terminal 370 may be a solder ball and may be formed using a ball implantation process to be placed on the second conductive pattern 121a of the second set of wiring structures 120, and a welding process and a reflow process may be selectively performed to enhance adhesion between the external terminal 370 and the second conductive pattern 121a, but the present invention is not limited thereto.

In an embodiment not shown, the semiconductor structure 200 may be further disposed on a circuit carrier (e.g., a printed circuit board (PCB), a system board, a motherboard, etc.), a package and/or other components to form an electronic device. For example, the external terminal 370 is disposed on the circuit carrier, and the semiconductor chip 40 is electrically connected to other components on or in the circuit carrier via a multi-layer redistribution wiring structure RDL, but the present invention is not limited thereto.

In some embodiments, the semiconductor structure 300 is a wafer level semiconductor packaging structure, but the present invention is not limited thereto.

FIG. 4 is a partial schematic cross-sectional view showing a semiconductor structure according to some other embodiments of the present invention. Referring to FIG. 4 , the semiconductor structure 400 of the present embodiment is different from the semiconductor structure 300 of FIG. 3E in that the semiconductor structure 400 of the present embodiment further includes a module frame 480 and a heat sink 490, wherein the module frame 480 is disposed on the bottom surface 110b of the first group of circuit structures 110 and surrounds the semiconductor chip 40, and the heat sink 490 is disposed on the semiconductor chip 40 and forms a space for framing the semiconductor chip 40 together with the module frame 480, but the present invention is not limited thereto. Here, the module frame 480 and the heat sink 490 can be selected and assembled according to actual design requirements, and the present invention is not limited thereto.

In summary, the present invention first separately manufactures multiple sets of circuit structures on a temporary substrate, and then directly joins and assembles the aforementioned multiple sets of circuit structures into a multi-layer redistribution structure. In this way, compared with a multi-layer redistribution structure manufactured continuously at one time, the degree of warping can be effectively reduced, so that the semiconductor structure can maintain better yield and electrical performance while having a multi-layer redistribution structure.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10, 20, 30: temporary carrier 12, 22, 32: release layer 40: semiconductor chip 42: conductive bump 42h, 360h: conductive bump 100, 100A, 100B, 200, 300, 400: semiconductor structure 101, 102, 103, 104: bottom glue 110, 120, 120A, 130, 220: circuit structure 110b, 120b: bottom surface 111, 121, 131, 221: circuit layer 111s, 121s, 131s, F, C: spacing 111a, 121a, 221a, 352a: conductive pattern 111b, 121b, 221b: dielectric layer 111c, 121c, 221c: conductive vias 112, 122, 123, 132, 222, 340: conductive connectors 112a, 341, 361: conductive pillars 112b, 342, 362: conductive caps 350: substrate 351: core layer 351a: perforations 352: build-up structure 360: chip connectors 370: external terminals 480: module frame 490: heat sink L1, L2: lines P1, P2: pads RDL, RDL1, RDL2, RDL3: multi-layer redistribution structure T1, T2: thickness

Figures 1A to 1C are partially schematic cross-sectional views showing a method for manufacturing a semiconductor substrate structure according to some embodiments of the present invention. Figure 1D is a schematic diagram showing the bonding of a conductive connector of another alternative embodiment of Figure 1C. Figures 1E and 1F are partially schematic cross-sectional views showing semiconductor substrate structures according to other embodiments of the present invention. Figure 2 is a partially schematic cross-sectional view showing a semiconductor substrate structure according to some other embodiments of the present invention. Figures 3A to 3E are partially schematic cross-sectional views showing a method for manufacturing a semiconductor structure according to some other embodiments of the present invention. Figure 4 is a partially schematic cross-sectional view showing a semiconductor structure according to some other embodiments of the present invention. Figure 5A is a partially schematic cross-sectional view showing the spacing of a circuit structure. Figure 5B is a partially schematic top view corresponding to Figure 5A.

10, 20: Temporary carrier board

12, 22: Release layer

100:Semiconductor structure

101: Base glue

110, 120: Circuit structure

111s, 121s: Spacing

111c, 121c: conductive vias

112, 122: Conductive connectors

112a: Conductive column

112b: Conductive cover

RDL: Multi-layer redistribution structure

T1:Thickness

Claims (9)

A semiconductor substrate structure includes: a first set of circuit structures, including multiple first circuit layers and multiple first conductive connectors, and each of the first conductive connectors includes a conductive cover; and a second set of circuit structures, including multiple second circuit layers and multiple second conductive connectors, wherein the first set of circuit structures and the second set of circuit structures are electrically connected by bonding the multiple first conductive connectors and the multiple second conductive connectors; a third set of circuit structures, including multiple third circuit layers and multiple third conductive connectors, wherein the second set of circuit structures is disposed between the first set of circuit structures and the third set of circuit structures and is electrically connected to each other, and the second set of circuit structures has another conductive connector relative to the first set of circuit structures, and the other conductive connector is bonded to the third conductive connector to form a multi-layer redistribution structure. A semiconductor substrate structure as described in claim 1, wherein each of the first circuit layers includes two adjacent first circuits, the center points of the two adjacent first circuits have a first spacing, each of the second circuit layers includes two adjacent second circuits, the center points of the two adjacent second circuits have a second spacing, the first spacing of each first circuit layer is smaller than the second spacing of each second circuit layer, and the spacing of each layer gradually increases from the first group of circuit structures toward the second group of circuit structures. A semiconductor substrate structure as described in claim 2, wherein the first spacing and the second spacing are the minimum spacings of each layer. A semiconductor substrate structure as described in claim 1, wherein the number of the first circuit layers of the first group of circuit structures is the same as the number of the second circuit layers of the second group of circuit structures. A semiconductor substrate structure as described in claim 1, wherein the number of the first circuit layers of the first group of circuit structures is different from the number of the second circuit layers of the second group of circuit structures. A semiconductor substrate structure as described in claim 5, wherein the difference between the number of the first circuit layers of the first group of circuit structures and the number of the second circuit layers of the second group of circuit structures is one layer or two layers. A semiconductor substrate structure as described in claim 1, wherein each of the first circuit layers includes two adjacent first circuits, the center points of the two adjacent first circuits have a first spacing, each of the second circuit layers includes two adjacent second circuits, the center points of the two adjacent second circuits have a second spacing, each of the third circuit layers includes two adjacent third circuits, the center points of the two adjacent third circuits have a third spacing, the first spacing of each of the first circuit layers is smaller than the second spacing of each of the second circuit layers, the second spacing of each of the second circuit layers is smaller than the third spacing of each of the third circuit layers, and the spacing of each layer gradually increases from the first group of circuit structures toward the third group of circuit structures. The semiconductor substrate structure as described in claim 1 further includes a primer, which is disposed between the first set of circuit structures and the second set of circuit structures and fills the gaps between the first plurality of conductive connectors and the second plurality of conductive connectors. A method for manufacturing a semiconductor substrate structure includes: forming a first set of circuit structures on a first temporary carrier, wherein the first set of circuit structures includes a plurality of first circuit layers and a plurality of first conductive connectors, and each of the first conductive connectors includes a conductive cover; forming a second set of circuit structures on a second temporary carrier, wherein the second set of circuit structures includes a plurality of second circuit layers and a plurality of second conductive connectors; forming a third set of circuit structures, wherein the third set of circuit structures includes a plurality of third circuit layers and a plurality of third conductive connectors; Conductive connector; and the first plurality of first conductive connectors of the first group of wiring structures are joined to the second plurality of second conductive connectors of the second group of wiring structures to form an electrical connection, and the second group of wiring structures are arranged between the first group of wiring structures and the third group of wiring structures and are electrically connected to each other, the second group of wiring structures has another conductive connector relative to the first group of wiring structures, and the other conductive connector is joined to the third conductive connector to form a multi-layer redistribution structure.

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