TWI847148B - Semiconductor device with t-shaped landing pad structure - Google Patents

Abstract

The present application discloses a method for fabricating a semiconductor device including providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming a failed hard mask layer to fill the via opening; forming a second mask layer on the failed hard mask layer; removing the second mask layer and the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and forming a trench in the trench opening.

Description

Semiconductor device having T-shaped landing pad structure

This application claims priority to U.S. Patent Application Nos. 17/716,109 and 17/716,165 (i.e., priority date is "April 8, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a T-shaped landing pad structure.

Semiconductor components are indispensable for many modern applications. With the development of electronic technology, the size of semiconductor components is getting smaller and smaller, while providing more functions and including more integrated circuits. Due to the miniaturization of semiconductor components, various types and sizes of semiconductor components providing different functions are integrated and packaged into a single module. In addition, many manufacturing operations are implemented to integrate various types of semiconductor components.

However, the fabrication and integration of semiconductor devices involve many complex steps and operations. The integration of semiconductor devices is becoming increasingly complex. The increased complexity of the fabrication and integration of semiconductor devices may lead to defects, such as poor electrical interconnections due to misalignment between upper and lower conductive features. Therefore, there is a constant need to improve the fabrication process of semiconductor devices in order to address these issues.

The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present case.

In one embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate, and a conductive contact penetrating the first dielectric layer. The semiconductor device also includes a T-shaped landing pad structure disposed on the conductive contact and directly contacting the conductive contact. The T-shaped landing pad structure includes a lower landing pad and an upper landing pad disposed on the lower landing pad, and a width of the upper landing pad is greater than a width of the lower landing pad. The semiconductor device further includes a capacitor disposed on the T-shaped landing pad structure and in direct contact with the T-shaped landing pad structure, and a second dielectric layer disposed on the first dielectric layer and surrounding the T-shaped landing pad structure and the capacitor.

In one embodiment, a width of the upper landing pad is greater than a width of the capacitor. In one embodiment, a bottom surface of the upper landing pad is in direct contact with the second dielectric layer. In one embodiment, a top surface of the upper landing pad is in direct contact with the second dielectric layer. In one embodiment, the upper landing pad and the lower landing pad include the same material. In one embodiment, the upper landing pad and the lower landing pad include tungsten (W). In one embodiment, the upper landing pad has a protrusion covering an upper sidewall of the lower landing pad.

In another embodiment of the present disclosure, a method for preparing a semiconductor element is provided. The method includes forming a first dielectric layer on a semiconductor substrate, and forming a conductive contact penetrating the first dielectric layer. The method also includes forming a lower landing pad on the conductive contact, and forming a second dielectric layer covering the lower landing pad. The method also includes etching the second dielectric layer to form a first opening exposing the lower landing pad, and forming an upper landing pad in the first opening. The lower landing pad and the upper landing pad form a T-shaped landing pad structure.

In one embodiment, a width of the first opening is greater than a width of the lower landing pad. In one embodiment, after forming the T-shaped landing pad structure, a top surface of the second dielectric layer is higher than a top surface of the upper landing pad. In one embodiment, after forming the T-shaped landing pad structure, the second dielectric layer is removed. In one embodiment, the preparation method further includes forming a third dielectric layer covering the T-shaped landing pad structure, etching the third dielectric layer to form a second opening of the upper landing pad that partially exposes the T-shaped landing pad structure, and forming a capacitor in the second opening, wherein the capacitor is electrically connected to the conductive contact through the T-shaped landing pad structure. In one embodiment, the first opening includes an extension portion extending to the second dielectric layer to partially expose a side wall of the lower landing pad. In one embodiment, forming the upper landing pad includes filling the extension portion of the first opening with a portion of the upper landing pad.

In another embodiment of the present disclosure, a method for preparing a semiconductor element is provided. The preparation method includes forming a first dielectric layer on a semiconductor substrate, and forming a conductive contact penetrating the first dielectric layer. The preparation method also includes forming a lower landing pad on the conductive contact, and forming a second dielectric layer covering the lower landing pad. The preparation method also includes etching the second dielectric layer to form a first opening exposing a top surface of the lower landing pad, and forming an upper landing pad in the first opening. A width of the upper landing pad is greater than a width of the lower landing pad. In addition, the preparation method also includes forming a capacitor on the upper landing pad. The width of the upper landing pad is greater than a width of the capacitor.

In one embodiment, a width of the first opening is greater than the width of the lower landing pad. In one embodiment, the preparation method further includes forming a pattern mask on the second dielectric layer, and etching the second dielectric layer using the pattern mask as a mask to form the first opening. In one embodiment, the preparation method further includes removing the pattern mask and the second dielectric layer after forming the upper landing pad, and forming a third dielectric layer covering the upper landing pad before forming the capacitor. In one embodiment, the material of the lower landing pad is the same as the material of the upper landing pad. In one embodiment, before forming the upper landing pad, a top surface of the lower landing pad is higher than a bottom surface of the first opening.

The present disclosure provides an embodiment of a semiconductor element and a method for preparing the element. In some embodiments, the semiconductor element includes a T-shaped landing pad structure disposed on a conductive contact. The T-shaped landing pad structure includes a lower landing pad and an upper landing pad, and the width of the upper landing pad is greater than the width of the lower landing pad. The T-shaped landing pad structure helps to increase the landing area of the upper conductive feature (such as a capacitor). Therefore, the contact resistance can be reduced, and the misalignment problem between the landing pad structure and the upper conductive feature can be prevented or reduced. Therefore, the overall element performance can be improved and the yield rate of the semiconductor element can be improved.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the art to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the art to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached patent application scope.

1 is a cross-sectional view illustrating a semiconductor device 100 according to some embodiments. In some embodiments, the semiconductor device 100 includes a semiconductor substrate 101, a dielectric layer 103 (also referred to as a first dielectric layer) disposed on the semiconductor substrate 101, and a plurality of conductive contacts 125 disposed on the semiconductor substrate 101 and penetrating the dielectric layer 103. In some embodiments, the semiconductor device 100 includes a dielectric layer 175 (also referred to as a third dielectric layer) disposed on the dielectric layer 103, and a plurality of landing pad structures 165 (also referred to as a T-shaped landing pad structure) and a plurality of capacitors 197 disposed in the dielectric layer 175.

In some embodiments, each pad structure 165 includes a lower pad 143 and an upper pad 163, which together form a pad structure 165 having a T-shaped cross section. In some embodiments, each capacitor 197 includes a bottom electrode 191, a top electrode 195, and a dielectric layer 193 sandwiched between the bottom electrode 191 and the top electrode 195. Each capacitor 197 is electrically connected to a respective bottom conductive contact 125 through the pad structure 165 therebetween. In some embodiments, the semiconductor device 100 is part of a dynamic random access memory (DRAM).

Since the landing pad structure 165 has a T-shaped cross section, the landing area of the capacitor 197 is increased. In addition, the contact resistance between the landing pad structure 165 and the capacitor 197 is reduced, and the risk of misalignment between the landing pad structure 165 and the capacitor 197 can be prevented or reduced. Therefore, the overall device performance can be improved and the yield rate of the semiconductor device 100 can be improved.

FIG2 is a cross-sectional view illustrating a semiconductor device 200 according to some embodiments. The semiconductor device 200 in FIG2 is similar to the semiconductor device 100 in FIG1, wherein the same reference numerals refer to the same elements, and certain details or descriptions of the same elements are not repeated. However, in FIG2, according to some embodiments, each upper landing pad has a protrusion covering the upper sidewall of the lower landing pad.

In some embodiments, the semiconductor device 200 includes a dielectric layer 275 disposed on the dielectric layer 103 (similar to the dielectric layer 175 in the semiconductor device 100, the dielectric layer 275 is also called a third dielectric layer), and a plurality of landing pad structures 265 disposed in the dielectric layer 275 (similar to the landing pad structure 165 in the semiconductor device 100, the landing pad structure 265 is also called a T-shaped landing pad structure) and a plurality of capacitors 297 (similar to the capacitor 197 of the semiconductor device 100).

In some embodiments, each landing pad structure 265 includes a lower landing pad 143 and an upper landing pad 263, which together form a landing pad structure 265 having a T-shaped cross section. It should be noted that, according to some embodiments, each upper landing pad 263 has a protrusion 263P covering the opposite upper sidewalls of the respective underlying lower landing pad 143. In some embodiments, each capacitor 297 includes a bottom electrode 291, a top electrode 295, and a dielectric layer 293 sandwiched between the bottom electrode 291 and the top electrode 295. Each capacitor 297 is electrically connected to a respective underlying conductive contact 125 via a landing pad structure 265 therebetween. In some embodiments, semiconductor device 200 is part of a dynamic random access memory (DRAM).

Since the landing pad structure 265 has a T-shaped cross section, the landing area of the capacitor 297 is increased. In addition, the contact resistance between the landing pad structure 265 and the capacitor 297 is reduced, and the risk of misalignment between the landing pad structure 265 and the capacitor 297 can be prevented or reduced. Therefore, the overall device performance can be improved and the yield rate of the semiconductor device 200 can be improved.

FIG3 is a flow chart illustrating a method 10 for preparing a semiconductor device (including a semiconductor device 100 and a modified semiconductor device 200) according to some embodiments. The method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, and S27. Steps S11 to S27 of FIG3 will be described in conjunction with the following figure.

4 to 18 are cross-sectional views illustrating intermediate stages of manufacturing a semiconductor device 100 according to some embodiments. As shown in FIG4 , a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer.

Alternatively or additionally, the semiconductor substrate 101 may include an elementary semiconductor material, a composite semiconductor material, and/or an alloy semiconductor material. Elementary semiconductor materials, for example, may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Composite semiconductor materials, for example, may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Alloy semiconductor materials, for example, may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.

In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor substrate on an insulator, which may include a substrate, a buried oxide layer on the substrate, and a semiconductor layer on the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-insulator (SGOI) substrate, or a germanium-insulator (GOI) substrate. The semiconductor substrate on an insulator may be prepared using separation by oxygen implantation (SIMOX), wafer bonding, and/or other suitable methods. Furthermore, in some embodiments, a plurality of source/drain regions (not shown) are formed in the semiconductor substrate 101.

A dielectric layer 103 is formed on a semiconductor substrate 101, and a pattern mask 105 having a plurality of openings 110 is formed on the dielectric layer 103, as shown in FIG4, according to some embodiments. The corresponding step is shown in step S11 of the preparation method 10 shown in FIG3. In some embodiments, the dielectric layer 103 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. In some embodiments, the manufacturing technology of the dielectric layer 103 includes a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other suitable methods. In some embodiments, the dielectric layer 103 and the pattern mask 105 include different materials, so that the etching selectivity can be different in the subsequent etching process.

Next, an etching process is performed on the dielectric layer 103 using the pattern mask 105 as a mask, thereby forming a plurality of openings 120 in the dielectric layer 103, as shown in FIG5 , according to some embodiments. In some embodiments, the openings 120 penetrate the dielectric layer 103, thereby exposing the semiconductor substrate 101 through the openings 120. The etching process may be a wet etching process, a dry etching process, or a combination thereof.

Subsequently, a conductive material 123 is formed on the pattern mask 105, as shown in FIG6, according to some embodiments. In some embodiments, the openings 110 and 120 shown in FIG5 are filled with the conductive material 123. In some embodiments, the conductive material 123 includes copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), combinations thereof, or other suitable conductive materials. The manufacturing technology of the conductive material 123 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a sputtering process, another suitable method, or a combination thereof.

Then, a planarization process is performed on the conductive material 123, thereby forming a plurality of conductive contacts 125 in the dielectric layer 103, as shown in FIG. 7 , according to some embodiments. In some embodiments, each conductive contact 125 penetrates the dielectric layer 103 and contacts and electrically connects to a respective underlying source/drain region (not shown). The corresponding step is shown in step S13 of the preparation method 10 shown in FIG. 3 .

The planarization process may include a chemical mechanical polishing (CMP) process. After the planarization process, the top surface of the conductive contact 125 is substantially coplanar with the top surface of the dielectric layer 103. In the scope of the present disclosure, the term "substantially" preferably refers to at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

Next, a conductive material 127 is formed covering the dielectric layer 103 and the conductive contacts 125, and a pattern mask 129 having a plurality of openings 130 is formed on the conductive material 127, as shown in FIG. 8 , according to some embodiments. In some embodiments, the conductive material 127 includes tungsten (W). However, other suitable conductive materials, such as copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), and combinations thereof, may also be used. Some processes used to prepare the conductive material 127 are similar or identical to the processes used to prepare the conductive material 123, and the details are not repeated here. In addition, the conductive material 127 and the pattern mask 129 include different materials, so that the selectivity of the etching can be different in a subsequent etching process.

Subsequently, an etching process is performed on the conductive material 127 using the pattern mask 129 as a mask, thereby forming a plurality of lower landing pads 143 on the conductive contacts 125, as shown in FIG. 9 , according to some embodiments. The corresponding step is shown in step S15 of the preparation method 10 shown in FIG. 3 . In some embodiments, during the etching process, a plurality of openings 140 are formed between the lower landing pads 143, and the dielectric layer 103 is exposed by the openings 140.

The etching process may be a wet etching process, a dry etching process, or a combination thereof. After forming the lower landing pad 143, the pattern mask 129 may be removed. In some embodiments, the removal technique of the pattern mask 129 includes a stripping process, an ashing process, an etching process, or another suitable process.

After removing the pattern mask 129, as shown in FIG. 10, according to some embodiments, a dielectric layer 145 is formed to cover the lower landing pad 143 and the dielectric layer 103. The corresponding step is shown in step S17 of the preparation method 10 shown in FIG. 3. In some embodiments, the dielectric layer 145 includes a dielectric material, such as silicon oxide. However, other suitable dielectric materials, such as silicon nitride and silicon oxynitride, may also be used. Some processes used to prepare the dielectric layer 145 are similar or identical to the processes used to prepare the dielectric layer 103, and the details thereof will not be repeated here.

Then, as shown in FIG. 11 , according to some embodiments, a pattern mask 147 having a plurality of openings 150 is formed on the dielectric layer 145. In some embodiments, the pattern mask 147 may be a photoresist patterned by a suitable lithography process. In some embodiments, the pattern mask 147 and the dielectric layer 145 include different materials so that the etching selectivity can be different in a subsequent etching process.

Next, as shown in FIG. 12 , according to some embodiments, an etching process is performed on the dielectric layer 145 using the pattern mask 147 as a mask, so that the top surface 143T of the lower landing pad 143 is exposed by a plurality of openings 160. The corresponding step is shown in step S19 of the preparation method 10 shown in FIG. 3 . In some embodiments, each lower landing pad 143 has a width W1, each opening 160 has a width W2, and the width W2 is greater than the width W1. The etching process can be a wet etching process, a dry etching process, or a combination thereof.

Subsequently, as shown in FIG. 13 , according to some embodiments, a plurality of upper landing pads 163 are formed in the opening 160. The corresponding step is shown in step S21 in the preparation method 10 shown in FIG. 3 . In some embodiments, the opening 160 is not completely filled with the upper landing pad 163. In other words, the opening 160 partially filled with the upper landing pad 163 becomes a remaining opening 160′. In some embodiments, the top surface 163T of the upper landing pad 163 is lower than the top surface 145T of the dielectric layer 145.

In addition, the width of each upper landing pad 163 is substantially the same as the width W2 of the opening 160 shown in FIG. 12. As described above, the width W2 of the upper landing pad 163 is greater than the width W1 of the lower landing pad 143. In some embodiments, the upper landing pad 163 includes tungsten (W). However, other suitable conductive materials may also be used, such as copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), and combinations thereof. In some embodiments, the upper landing pad 163 includes the same material as the lower landing pad 143, such as tungsten (W). Some processes for preparing the upper landing pad 163 are similar or identical to the processes for preparing the conductive material 123, and the details thereof are not repeated here. After forming the upper landing pad 163, a landing pad structure 165 having a T-shaped cross section is obtained.

After forming the upper landing pad 163, as shown in FIG14, according to some embodiments, the pattern mask 147 is removed. In some embodiments, the removal technique of the pattern mask 147 includes a stripping process, an ashing process, an etching process, or another suitable process.

Then, as shown in FIG. 15 , according to some embodiments, the dielectric layer 145 is removed. The corresponding step is shown in step S23 in the preparation method 10 shown in FIG. 3 . In some embodiments, the removal technique of the dielectric layer 145 includes an etching process. For example, the removal technique of the dielectric layer 145 includes a wet etching process. After removing the dielectric layer 145, according to some embodiments, any two adjacent landing pad structures 165 are separated by openings 170. As shown in FIG. 15 , each opening 170 has an inverted T shape.

Next, as shown in FIG. 16 , according to some embodiments, a dielectric layer 175 is formed to cover the pad structure 165 (including the lower pad 143 and the upper pad 163) and the dielectric layer 103. The corresponding step is shown in step S25 of the preparation method 10 shown in FIG. 3 . In some embodiments, the opening 170 having an inverted T shape as shown in FIG. 15 is filled with the dielectric layer 175. The process and some materials used to prepare the dielectric layer 175 are similar or the same as the process and materials used to prepare the dielectric layer 103, and the details thereof will not be repeated here.

Then, according to some embodiments, a pattern mask 177 having a plurality of openings 180 is formed on the dielectric layer 175, as shown in FIG17. In some embodiments, the pattern mask 177 and the dielectric layer 175 include different materials, so that the etching selectivity can be different in the subsequent etching process.

Then, an etching process is performed on the dielectric layer 175 using the pattern mask 177 as a mask, so that the top surface 163T of the upper landing pad 163 is exposed by a plurality of openings 190, as shown in FIG. 18, according to some embodiments. In some embodiments, each opening 190 has a width W3, each upper landing pad 163 has a width W2, and the width W2 is greater than the width W3. The etching process can be a wet etching process, a dry etching process, or a combination thereof. After the openings 190 are formed, the pattern mask 177 can be removed.

Next, as shown in FIG. 1 , according to some embodiments, a plurality of capacitors 197 are formed in the opening 190 on the upper landing pad 163. The corresponding step is shown in step S27 of the preparation method 10 shown in FIG. 3 . In some embodiments, the capacitors 197 are metal-insulator-metal (MIM) capacitors. As described above, each capacitor 197 includes a bottom electrode 191, a top electrode 195, and a dielectric layer 193 sandwiched between the bottom electrode 191 and the top electrode 195.

Forming capacitor 197 may include sequentially depositing a conductive material, a dielectric material, and another conductive material in opening 190 (see FIG. 18 ), extending on dielectric layer 175, and performing a planarization process (e.g., a CMP process) to remove excess portions of the two conductive materials and the dielectric material. In some embodiments, bottom electrode 191 includes titanium nitride (TiN), dielectric layer 193 includes a dielectric material such as silicon dioxide (SiO2), helium dioxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), or a combination thereof, and top electrode 195 includes titanium nitride (TiN), low stress silicon germanium (SiGe), or a combination thereof.

In some embodiments, capacitor 197 is electrically connected to a source/drain region (not shown) in semiconductor substrate 101 through landing pad structure 165 and conductive contact 125. After capacitor 197 is formed, semiconductor device 100 is obtained. In some embodiments, semiconductor device 100 is part of a DRAM. In some embodiments, the width W2 of upper landing pad 163 of landing pad structure 165 is greater than the width W3 of capacitor 197, thereby creating a larger landing area for capacitor 197. In addition, in some embodiments, the top surface 163T and the bottom surface 163B of upper landing pad 163 are in direct contact with dielectric layer 175.

As shown in FIG1 , since the landing pad structure 165 has a T-shaped cross section, the landing area of the capacitor 197 is increased. In addition, the contact resistance between the landing pad structure 165 and the capacitor 197 is reduced, and the risk of misalignment can be prevented or reduced. Therefore, the overall device performance can be improved and the yield rate of the semiconductor device 100 can be increased.

19 to 21 are cross-sectional views illustrating intermediate stages of the preparation of the semiconductor device 200 of some embodiments. It should be noted that the operations of preparing the semiconductor device 200 before the structure shown in FIG. 19 are substantially the same as the operations of preparing the semiconductor device 100 shown in FIG. 4 to FIG. 11 , and the relevant detailed description can be referred to the aforementioned paragraphs and will not be discussed here.

After forming a pattern mask 147 having openings 150 on the dielectric layer 145, an etching process is performed on the dielectric layer 145 using the pattern mask 147 as a mask, so that the top surface 143T and the upper sidewall 143S of the lower landing pad 143 are exposed by a plurality of openings 260, as shown in FIG. 19. According to some embodiments, the corresponding step is shown in step S19 of the preparation method 10 shown in FIG. 3. The etching process can be a wet etching process, a dry etching process, or a combination thereof.

In some embodiments, the opening 260 has an extension portion 260E to expose the upper sidewall 143S of the lower landing pad 143. In addition, in some embodiments, the bottom surface 260B (i.e., the bottommost surface) of the opening 260 is lower than the top surface 143T of the lower landing pad 143. In addition, in some embodiments, each lower landing pad 143 has a width W4, each opening 260 has a width W5, and the width W5 is greater than the width W4.

Subsequently, as shown in FIG. 20 , according to some embodiments, a plurality of upper landing pads 263 are formed in the opening 260. The corresponding step is shown in step S21 in the preparation method 10 shown in FIG. 3 . In some embodiments, the opening 260 is not completely filled with the upper landing pad 263. In other words, the opening 260 partially filled with the upper landing pad 263 becomes a residual opening 260 ′. In some embodiments, the top surface 263T of the upper landing pad 263 is lower than the top surface 145T of the dielectric layer 145.

In addition, according to some embodiments, the extension portion 260E of the opening 260 shown in FIG19 is filled by a portion of the upper landing pad 263 (also referred to as the protrusion 263P of the upper landing pad 263). In addition, the width of each upper landing pad 263 is substantially the same as the width W5 of the opening 260 shown in FIG19. As described above, the width W5 of the upper landing pad 263 is greater than the width W4 of the lower landing pad 143. In some embodiments, the upper landing pad 263 includes the same material as the lower landing pad 143, such as tungsten (W). The process and some materials used to prepare the upper landing pad 263 are similar or the same as the process and materials used to prepare the upper landing pad 163 in the semiconductor device 100, and the details are not repeated here. After forming the upper landing pad 263, a landing pad structure 265 with a T-shaped cross section is obtained.

Then, as shown in FIG. 21 , according to some embodiments, the pattern mask 147 and the dielectric layer 145 are removed. The corresponding step is shown in step S23 of the preparation method 10 shown in FIG. 3 . In some embodiments, the removal technique of the pattern mask 147 includes a stripping process, an ashing process, an etching process or another suitable process, and the removal technique of the dielectric layer 145 includes an etching process, such as a wet etching process. After removing the pattern mask 147 and the dielectric layer 145, according to some embodiments, any two adjacent landing pad structures 265 are separated by openings 270. As shown in FIG. 21 , each opening 270 has an inverted T shape.

Next, a dielectric layer 275 is formed to cover the pad structure 265 (including the lower pad 143 and the upper pad 263) and the dielectric layer 103, an etching process is performed on the dielectric layer 275 to form an opening (not shown) exposing the upper pad 263, and a plurality of capacitors 297 are formed in the opening on the upper pad 163, as shown in FIG. 2 , according to some embodiments. The corresponding steps are shown in steps S25 and S27 in the preparation method 10 shown in FIG. 3 . The process and some materials used to prepare the dielectric layer 275 and the opening exposing the upper landing pad 263 are similar or the same as the process and materials used to prepare the dielectric layer 175 and the opening 190 of the semiconductor device 100 (see FIGS. 16 to 18 ), and the details are not repeated here.

In some embodiments, capacitor 297 is a MIM capacitor. As described above, each capacitor 297 includes a bottom electrode 291, a top electrode 295, and a dielectric layer 293 sandwiched between the bottom electrode 291 and the top electrode 295. The processes and some materials used to prepare the bottom electrode 291, the dielectric layer 293, and the top electrode 295 are similar or the same as the processes and materials used to prepare the bottom electrode 191, the dielectric layer 193, and the top electrode 195 of the semiconductor device 100, and the details are not repeated here.

In some embodiments, capacitor 297 is electrically connected to source/drain regions (not shown) in semiconductor substrate 101 through landing pad structure 265 and conductive contact 125. After capacitor 297 is formed, semiconductor device 200 is obtained. In some embodiments, semiconductor device 200 is part of a DRAM. In some embodiments, the width W5 of upper landing pad 263 of landing pad structure 265 is greater than the width W6 of capacitor 297, thereby creating a larger landing area for capacitor 297. In addition, in some embodiments, the top surface 263T and the bottom surface 263B of upper landing pad 263 are in direct contact with dielectric layer 275.

As shown in FIG2 , since the landing pad structure 265 has a T-shaped cross section, the landing area of the capacitor 297 is increased. In addition, the contact resistance between the landing pad structure 265 and the capacitor 297 is reduced, and the risk of misalignment can be prevented or reduced. Therefore, the overall device performance can be improved and the yield rate of the semiconductor device 200 can be increased.

The present disclosure provides an embodiment of a semiconductor element and a method for preparing the element. In some embodiments, the semiconductor element includes a T-shaped landing pad structure disposed on a conductive contact. The T-shaped landing pad structure includes a lower landing pad and an upper landing pad, and the width of the upper landing pad is greater than the width of the lower landing pad. The T-shaped landing pad structure helps to increase the landing area of the upper conductive feature (such as a capacitor). Therefore, the contact resistance can be reduced, and the misalignment problem between the landing pad structure and the upper conductive feature can be prevented or reduced. Therefore, the overall element performance can be improved and the yield rate of the semiconductor element can be improved.

In one embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate, and a conductive contact penetrating the first dielectric layer. The semiconductor device also includes a T-shaped landing pad structure disposed on the conductive contact and directly contacting the conductive contact. The T-shaped landing pad structure includes a lower landing pad and an upper landing pad disposed on the lower landing pad, and a width of the upper landing pad is greater than a width of the lower landing pad. The semiconductor device further includes a capacitor disposed on the T-shaped landing pad structure and in direct contact with the T-shaped landing pad structure, and a second dielectric layer disposed on the first dielectric layer and surrounding the T-shaped landing pad structure and the capacitor.

In another embodiment of the present disclosure, a method for preparing a semiconductor element is provided. The method includes forming a first dielectric layer on a semiconductor substrate, and forming a conductive contact penetrating the first dielectric layer. The method also includes forming a lower landing pad on the conductive contact, and forming a second dielectric layer covering the lower landing pad. The method also includes etching the second dielectric layer to form a first opening exposing the lower landing pad, and forming an upper landing pad in the first opening. The lower landing pad and the upper landing pad form a T-shaped landing pad structure.

In another embodiment of the present disclosure, a method for preparing a semiconductor element is provided. The preparation method includes forming a first dielectric layer on a semiconductor substrate, and forming a conductive contact penetrating the first dielectric layer. The preparation method also includes forming a lower landing pad on the conductive contact, and forming a second dielectric layer covering the lower landing pad. The preparation method also includes etching the second dielectric layer to form a first opening exposing a top surface of the lower landing pad, and forming an upper landing pad in the first opening. A width of the upper landing pad is greater than a width of the lower landing pad. In addition, the preparation method also includes forming a capacitor on the upper landing pad. The width of the upper landing pad is greater than a width of the capacitor.

Embodiments of the present disclosure have some advantageous features. In some embodiments, a semiconductor device includes a T-shaped landing pad structure having a lower landing pad and an upper landing pad, and the width of the upper landing pad is greater than the width of the lower landing pad. The T-shaped landing pad structure helps to increase the landing area of the upper conductive feature (such as a capacitor). Therefore, the contact resistance can be reduced, and the risk of misalignment between the landing pad structure and the upper conductive feature can be prevented or reduced. Therefore, the performance, reliability and yield of the semiconductor device can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure defined by the scope of the patent application. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machines, manufactures, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

10: Preparation method 100: Semiconductor element 101: Semiconductor substrate 103: Dielectric layer 105: Pattern mask 110: Opening 120: Opening 123: Conductive material 125: Conductive contact 127: Conductive material 129: Pattern mask 130: Opening 140: Opening 143: Lower landing pad 143S: Upper sidewall 143T: Top surface 145: Dielectric layer 147: Pattern mask 150: Opening 160: Opening 160': Remaining opening 163: Upper landing pad 163B: Bottom surface 163T: Top surface 165: Landing pad structure (T-shaped landing pad structure) 170: Opening 175: Dielectric layer 177: Pattern mask 180: Opening 190: Opening 191: Bottom electrode 193: Dielectric layer 195: Top electrode 197: Capacitor 200: Semiconductor element 260: Opening 260': Remaining opening 260B: Bottom surface 260E: Extended portion 263: Upper landing pad 263P: Part (protrusion) 263T: Top surface 265: Landing pad structure (T-shaped landing pad structure) 270: Opening 275: dielectric layer 291: bottom electrode 293: dielectric layer 295: top electrode 297: capacitor S11: step S13: step S15: step S17: step S19: step S21: step S23: step S25: step S27: step W1: width W2: width W3: width W4: width W5: width W6: width

When referring to the embodiments and the drawings together with the scope of the patent application, a more comprehensive understanding of the disclosure of the present application can be obtained. The same element symbols in the drawings refer to the same elements. FIG. 1 is a cross-sectional view illustrating a semiconductor element of some embodiments. FIG. 2 is a cross-sectional view illustrating a semiconductor element of some embodiments. FIG. 3 is a flow chart illustrating a method for preparing a semiconductor element of some embodiments. FIG. 4 is a cross-sectional view illustrating an intermediate stage of forming a first dielectric layer on a semiconductor substrate during the preparation of a semiconductor element of some embodiments. FIG. 5 is a cross-sectional view illustrating an intermediate stage of forming an opening in a first dielectric layer during the preparation of a semiconductor element of some embodiments. FIG. 6 is a cross-sectional view illustrating an intermediate stage of forming a conductive material in an opening and on a first dielectric layer during the preparation of a semiconductor device of some embodiments. FIG. 7 is a cross-sectional view illustrating an intermediate stage of planarizing a conductive material to form a conductive contact in a first dielectric layer during the preparation of a semiconductor device of some embodiments. FIG. 8 is a cross-sectional view illustrating an intermediate stage of forming a conductive material covering the first dielectric layer and the conductive contact during the preparation of a semiconductor device of some embodiments. FIG. 9 is a cross-sectional view illustrating an intermediate stage of etching a conductive material to form a lower landing pad during the preparation of a semiconductor device of some embodiments. FIG. 10 is a cross-sectional view illustrating an intermediate stage of forming a second dielectric layer covering a lower landing pad during the preparation of a semiconductor device of some embodiments. FIG. 11 is a cross-sectional view illustrating an intermediate stage of forming a pattern mask on the second dielectric layer during the preparation of a semiconductor device of some embodiments. FIG. 12 is a cross-sectional view illustrating an intermediate stage of etching the second dielectric layer to form an opening exposing the top surface of the lower landing pad during the preparation of a semiconductor device of some embodiments. FIG. 13 is a cross-sectional view illustrating an intermediate stage of forming an upper landing pad at the opening during the preparation of a semiconductor device of some embodiments. FIG. 14 is a cross-sectional view illustrating an intermediate stage of removing a pattern mask during the preparation of a semiconductor device of some embodiments. FIG. 15 is a cross-sectional view illustrating an intermediate stage of removing a second dielectric layer during the preparation of a semiconductor device of some embodiments. FIG. 16 is a cross-sectional view illustrating an intermediate stage of forming a third dielectric layer covering a landing pad during the preparation of a semiconductor device of some embodiments. FIG. 17 is a cross-sectional view illustrating an intermediate stage of forming a pattern mask on a third dielectric layer during the preparation of a semiconductor device of some embodiments. FIG. 18 is a cross-sectional view illustrating an intermediate stage of etching a third dielectric layer to form an opening exposing the top surface of an upper landing pad during the preparation of a semiconductor device of some embodiments. FIG. 19 is a cross-sectional view illustrating an intermediate stage of etching a second dielectric layer to form an opening exposing an upper sidewall and a top surface of a lower landing pad during the preparation of a semiconductor device of some embodiments. FIG. 20 is a cross-sectional view illustrating an intermediate stage of forming a protrusion having an upper sidewall covering a lower landing pad during the preparation of a semiconductor device of some embodiments. FIG. 21 is a cross-sectional view illustrating an intermediate stage of removing a patterned mask and a second dielectric layer during the preparation of a semiconductor device of some embodiments.

1A: Semiconductor components

100:Semiconductor components

101:Semiconductor substrate

103: Dielectric layer

125: Conductive contact

143: Landing pad

163: On the landing pad

163B: Bottom

163T: Top

165: Landing pad structure

175: Dielectric layer

191: Bottom electrode

193: Dielectric layer

195: Top electrode

197:Capacitor

W2: Width

W3: Width

Claims (12)

A semiconductor element includes: a first dielectric layer disposed on a semiconductor substrate; a conductive contact penetrating the first dielectric layer; a T-shaped landing pad structure disposed on the conductive contact and in direct contact with the conductive contact, wherein the T-shaped landing pad structure includes a lower landing pad and an upper landing pad disposed on the lower landing pad, and a width of the upper landing pad is greater than a width of the lower landing pad; a capacitor disposed on the T-shaped landing pad structure and in direct contact with the T-shaped landing pad structure; and a second dielectric layer disposed on the conductive contact. The first dielectric layer is provided around the T-shaped landing pad structure and the capacitor; wherein the lower landing pad includes a conductive material, and wherein the conductive material contacts the conductive contact and contacts the upper landing pad; wherein a bottom surface of the upper landing pad directly contacts the second dielectric layer, wherein a top surface of the upper landing pad directly contacts the second dielectric layer, and wherein a portion of the second dielectric layer directly contacting the bottom surface of the upper landing pad and a portion of the second dielectric layer directly contacting the top surface of the upper landing layer have the same material. A semiconductor device as described in claim 1, wherein the width of the upper landing pad is greater than a width of the capacitor. A semiconductor device as described in claim 1, wherein the upper landing pad and the lower landing pad include the same material. A semiconductor device as described in claim 1, wherein the conductive material includes tungsten (W). A semiconductor device as described in claim 1, wherein the upper landing pad has a protrusion covering an upper side wall of the lower landing pad. A semiconductor element includes: a first dielectric layer disposed on a semiconductor substrate; a conductive contact disposed in the first dielectric layer; a lower landing pad disposed on the conductive contact, and a bottom surface of the lower landing pad contacts the conductive contact; a second dielectric layer covering the lower landing pad; an upper landing pad disposed in the second dielectric layer and directly contacts a top surface of the lower landing pad, wherein a width of the upper landing pad is greater than a width of the lower landing pad; and a capacitor disposed on the upper landing pad. wherein the width of the upper landing pad is greater than a width of the capacitor; wherein the bottom surface of the lower landing pad and the top surface of the lower landing pad have the same conductive material; wherein a bottom surface of the upper landing pad is in direct contact with the second dielectric layer; wherein a top surface of the upper landing pad is in direct contact with the second dielectric layer, and wherein a portion of the second dielectric layer in direct contact with the bottom surface of the upper landing pad and a portion of the second dielectric layer in direct contact with the top surface of the upper landing layer have the same material. The semiconductor device as described in claim 6 further includes a third dielectric layer covering the upper landing pad. A semiconductor device as described in claim 6, wherein the material of the lower landing pad is the same as the material of the upper landing pad. A semiconductor device as described in claim 6, wherein the width of the upper landing pad is greater than a width of the capacitor. A semiconductor device as described in claim 6, wherein the upper landing pad and the lower landing pad include the same material. A semiconductor device as described in claim 6, wherein the conductive material includes tungsten (W). A semiconductor device as described in claim 6, wherein the upper landing pad has a protrusion covering an upper side wall of the lower landing pad.

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