TWI841263B - Method of manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing semiconductor device includes: forming a mask on a stacked structure, in which the mask includes a tungsten layer; performing a first etching process to form an opening in the stacked structure; and removing at least a part of the mask by performing a second etching process, in which the second etching process uses a second gas mixture that is different from the first gas mixture. The first etching process includes: introducing a first gas mixture, in which the first gas mixture at least includes CHF ₃and Ar, the pressure of the first gas mixture is between about 5 mtorr to about 30 mtorr, and a molecule molar ratio of CHF ₃and Ar is between about 5 to about 20; applying a radiation frequency to plasmatize the first gas mixture; and applying a bias voltage on the stacked structure.

Description

Method for manufacturing semiconductor device

The present disclosure relates to a method for manufacturing a semiconductor device.

With the continuous advancement of advanced manufacturing processes, the research and development of semiconductor devices is committed to miniaturizing device size and improving device performance. For example, for dynamic random access memory (DRAM), the performance improvement can be achieved by miniaturizing capacitor size and making structures with higher aspect ratios. However, due to the excessive thickness of the mask, the lithography process is limited.

Therefore, how to come up with a method for manufacturing semiconductor devices that can solve the above problems is one of the problems that the industry is eager to invest research and development resources to solve.

In view of this, one aspect of the present disclosure is to provide a method for manufacturing a semiconductor device that can effectively solve the above-mentioned problem.

The present disclosure relates to a method for manufacturing a semiconductor device, comprising: forming a mask on a stacked structure, wherein the mask at least comprises a tungsten layer; applying a bias voltage to the stacked structure; performing a first etching process on the stacked structure through the mask to form an opening in the stacked structure; and performing a second etching process to remove a portion of the mask, wherein the second etching process uses a second gas different from the first gas. The first etching process comprises: introducing a first gas, wherein the first gas at least comprises CHF ₃ and Ar, the gas pressure of the first gas is in the range of about 5 mtorr to about 30 mtorr, and the molecular molar ratio of CHF ₃ and Ar is in the range of about 5 to about 20; applying a radiation frequency to plasmatize the first gas; and applying a bias voltage to the stacked structure.

In some embodiments, the first etching process further includes: making the first gas have a first pressure, wherein the first gas having the first pressure has a first etching rate; and making the first gas have a second pressure, wherein the first gas having the second pressure has a second etching rate higher than the first etching rate, wherein the first pressure is greater than the second pressure.

In some embodiments, the maximum selective etching ratio of the first gas to the stack structure and the tungsten layer is about 78.

In some embodiments, the radiation frequency provides RF power to the first gas per unit time, and the RF power ranges from about 3000 W to about 20000 W.

In some embodiments, the step of plasmatizing the first gas further includes: providing a first RF power to plasmatize the first gas, wherein the plasmatized first gas has a first etching rate; and providing a second RF power to plasmatize the first gas, wherein the first RF power is less than the second RF power, and the plasmatized first gas has a second etching rate greater than the first etching rate.

In some embodiments, the bias provides a bias power to the stack structure per unit time, and the bias power ranges from about 2000 W to about 8000 W.

In some embodiments, the second etching process includes: introducing a second gas, the second gas including at least Cl ₂ and SF ₆ , and the gas pressure of the second gas is in a range of about 3 mtorr to about 30 mtorr; applying a radiation frequency to plasmatize the second gas; and applying a bias voltage to the stack structure.

In some embodiments, the second gas further comprises at least one of N ₂ , He, and O ₂ .

In some embodiments, the thickness of the tungsten layer ranges from about 20 nm to about 80 nm.

In some embodiments, the step of performing a first etching process on the stacked structure through a mask is to form an opening through the stacked structure to form a through hole.

In some embodiments, the aspect ratio of the opening is at least greater than about 12.

In summary, the method of manufacturing semiconductor devices of some embodiments of the present disclosure can form an opening with a high aspect ratio in a stacked structure through a mask including a tungsten layer and a first gas after plasma. The reason is that since the tungsten layer and the stacked structure have a high selective etching ratio, the thickness of the mask can be thinned and its etching aspect ratio can be reduced. In this way, etching the stacked structure using the first gas after plasma can form an opening with a higher aspect ratio in the stacked structure. In addition, the formula of the first gas can provide high anisotropy in the etching process, reduce the local electrical poor contact phenomenon caused by the etching process to the stacked structure and improve the process yield.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat component symbols and/or letters in various examples. This repetition is for simplification and clarity purposes, and does not itself represent the relationship between the various embodiments and/or configurations discussed.

Additionally, for simplicity of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (additional) element or feature as illustrated in the figures. Such spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, "approximately", "about", "approximately" or "substantially" generally means falling within 20%, or within 10%, or within 5% of a given value or range. The numerical values given herein are approximate values, indicating that the terms used, such as "approximately", "about", "approximately" or "substantially" can be inferred when not explicitly stated.

Please refer to FIG. 1. FIG. 1 is a flow chart of a method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. A method M1 for manufacturing a semiconductor device includes: forming a mask on a stacked structure, wherein the mask at least includes a tungsten layer (step S110); performing a first etching process on the stacked structure through the mask to form an opening in the stacked structure (step S120) and performing a second etching process to remove a portion of the mask (step S130), and the second etching process uses a second gas different from the first gas. Please refer to FIG. 2. FIG. 2 is a flow chart of step S120 according to some embodiments of the present disclosure. Step S120 includes: introducing a first gas, wherein the first gas contains at least CHF ₃ and Ar, the gas pressure of the first gas is in the range of about 5 mtorr to about 30 mtorr, and the molecular molar ratio of CHF ₃ and Ar is in the range of about 5 to about 20 (step S121); applying radio frequency (RF) to plasmatize the first gas (step S122); and applying a bias voltage to the stack structure (step S123).

FIGS. 4A to 4F are schematic cross-sectional views of several stages of a method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. It should be noted that, although not shown in FIGS. 4A to 4F, several stages of the method M1 for manufacturing a semiconductor device are performed inside a vacuum chamber. In step S110, in the vacuum chamber, a mask 200 is formed on a stacked structure 100, and the mask 200 includes at least a tungsten layer 240. Specifically, the stacked structure 100 is located on a substrate 50. In one embodiment, the substrate 50 includes a plurality of electronic components and circuit structures formed in a front-end-of-line (FEOL) process and a middle-of-line (MOL) process. In one embodiment, the stacked structure 100 at least includes a nitride (e.g., a first nitride layer 110 and a second nitride layer 130) and an oxide (e.g., an oxide layer 140). In one embodiment, the stacked structure 100 further includes a dielectric layer 120. In one embodiment, the dielectric layer 120 includes boro-phospho-sillicate glass (BPSG).

Please continue to refer to FIG. 1 and FIG. 4A. The mask 200 is located on the stacked structure 100. In one embodiment, the mask 200 further includes a mask nitride layer 210, a mask semiconductor layer 220, a mask oxide layer 230, and an anti-reflection layer 250. In one embodiment, the mask nitride layer 210, the mask semiconductor layer 220, the mask oxide layer 230, the tungsten layer 240, and the anti-reflection layer 250 are sequentially stacked on the stacked structure 100 from bottom to top. In one embodiment, the total thickness of the mask 200 is in the range of about 350 nm to about 900 nm. In one embodiment, the thickness of the mask nitride layer 210 is in the range of about 50 nm to about 120 nm. In one embodiment, the mask semiconductor layer 220 includes at least polysilicon, and the thickness of the mask semiconductor layer 220 is in the range of about 150 nm to about 300 nm. In one embodiment, the thickness of the mask oxide layer 230 is in the range of about 80 nm to about 200 nm. In one embodiment, the thickness of the tungsten layer 240 is in the range of about 20 nm to about 80 nm. In one embodiment, the anti-reflective layer 250 includes at least a dielectric anti-reflective coating (DARC), and the thickness of the anti-reflective layer 250 is in the range of about 50 nm to about 200 nm.

In the etching process (e.g., the first etching process of step S120), the tungsten layer 240 has a high selective etching ratio for the stacked structure 100 compared to general mask materials (e.g., carbon-containing compounds), so that the mask 200 can have a thinner thickness but has sufficient etching resistance to resist the etching of subsequent processes and provide sufficient protection for the stacked structure 100. In addition, thinning the mask 200 can also reduce the etching aspect ratio of the mask 200, so that the etching process (e.g., the first etching process in step S120) performed through the mask 200 can form an opening with a higher aspect ratio (e.g., the opening 150 in FIG. 4F) in the stacked structure 100. Please refer to the following description.

Please refer to FIG. 4B. In one embodiment, step S110 includes: patterning the mask by a mask etching process (step S112). In one embodiment, the photoresist layer 300 is formed on the mask 200. The photoresist layer 300 is patterned by a lithography process or other similar processes.

Please refer to FIG. 4C. Then, a mask etching process is performed on the mask 200 through the patterned photoresist layer 300. In one embodiment, the mask etching process at least includes a transformer-coupled-plasma (TCP) process, and the mask etching process uses a mask etching gas that at least includes _SF6 and _O2 . The vacuum chamber has a gas inlet, and the mask etching gas enters the vacuum chamber through the gas inlet. In some embodiments, the mask etching process forms at least one opening 260 in the mask 200, and the opening 260 penetrates the tungsten layer 240. Since the products (eg, WF _x or WO _x F _y ) generated by the tungsten layer 240 and the mask etching gas during the mask etching process have low volatility, the sidewalls of the opening 260 can be passivated effectively and the lateral expansion of the opening 260 can be prevented. In this way, the pattern of the photoresist layer 300 can be completely transferred to the tungsten layer 240 .

Please refer to FIG. 4D. In one embodiment, the mask etching process is terminated after the opening 260 penetrates the mask 200. Subsequently, the photoresist layer 300 and the anti-reflection layer 250 are removed. It should be particularly noted that in another embodiment, the mask etching process is terminated after the opening 260 penetrates the tungsten layer 240 (as shown in the stage of FIG. 4C). In one embodiment, a portion of the mask 200 (e.g., the mask oxide layer 230 and the anti-reflective layer 250) is formed into an opening 260 by a mask etching process, and the opening 260 is extended and penetrates other layers of the mask 200 (e.g., the mask nitride layer 210, the mask semiconductor layer 220, and the mask oxide layer 230) by a first etching process in step S120. The steps of the first etching process will be described below.

Please refer to FIG. 1 and FIG. 4E. In step S120, a first etching process is performed on the stacked structure 100 through the mask 200, and the opening 150 is formed in the stacked structure 100 according to the position of the opening 260.

Please refer to FIG. 2 and FIG. 4E. In one embodiment, the first etching process at least includes a transformer-coupled plasma process. Step S120 further includes step S121, step S122, and step S123. In step S121, a first gas is introduced into the vacuum chamber from a gas inlet, the first gas at least includes CHF ₃ and Ar, and the molecular molar ratio of CHF ₃ and Ar is in the range of about 5 to about 20, and the gas pressure of the first gas in the vacuum chamber is in the range of about 5 mtorr to about 30 mtorr. Then in step S122, a specific radiation frequency is applied to the coil of the vacuum chamber to release electromagnetic waves and plasmatize the first gas. Then, in step S123, the bias voltage applied to the stacked structure 100 forms an electric field around the stacked structure 100, and the electric field guides the charged ions in the plasma to move toward the stacked structure 100 along the direction of the electric field. The electric field attracts ions in the plasma-formed first gas, such as O ions or Ar ions, to bombard the mask 200 and the stacked structure 100 to achieve etching of the stacked structure 100.

Continuing from the above paragraph, in step S121, Ar can increase the selective etching ratio of the first gas to the tungsten layer 240 and the stacked structure 100, and improve the etching rate of the first gas and improve the anisotropy of the etching process. In one embodiment, the maximum selective etching ratio of the first gas to the stacked structure 100 and the tungsten layer 240 is about 78. In one embodiment, the first gas further includes O ₂ . O ₂ can help passivate the sidewalls of the opening 150 to prevent the opening 150 from expanding laterally. Therefore, using the first gas containing at least CHF ₃ , Ar and/or O ₂ allows the first etching process to be used to form an opening 150 with a higher aspect ratio. In addition, the first gas can reduce the local electrical contact missing phenomenon and clogging phenomenon caused by the etching process to the stacked structure 100, so as to improve the pattern abnormal defect and improve the process yield. In one embodiment, the gas flow rate of the first gas is in the range of about 50 sccm to about 200 sccm. In one embodiment, the radiation frequency provides radio frequency power to the first gas per unit time, and the radio frequency power is in the range of about 3000 W to about 20000 W. In one embodiment, the bias provides bias power to the stacked structure 100 per unit time, and the bias power is in the range of about 2000 W to about 8000 W.

Please refer to FIG. 2. In one embodiment, step S120 further includes: making the first gas have a first pressure, and the first gas having the first pressure has a first etching rate after being plasmatized (step S124); and making the first gas have a second pressure, and the first gas having the second pressure has a second etching rate higher than the first etching rate after being plasmatized, wherein the first pressure is greater than the second pressure (step S125). In other words, the lower the pressure of the first gas in the vacuum chamber, the more the etching rate of the first gas after being plasmatized on the stacked structure 100 and the etching ratio of the first gas after being plasmatized relative to the tungsten layer 240 and the stacked structure 100 can be improved. The reason is that the ionization degree of the first gas increases under low pressure, which can increase the chemical reaction rate of the first etching process. In addition, the low pressure reduces the collision probability between ions and atoms, which can maintain the movement trajectory of ions in the electric field and increase the non-selective etching rate of the first etching process.

Please continue to refer to FIG. 2. In one embodiment, the radiation frequency provides radio frequency power to the first gas per unit time, and step S120 further includes: providing the first radio frequency power to plasmatize the first gas, wherein the first gas after plasmatization has a first etching rate (step S126); and providing the second radio frequency power to plasmatize the first gas, wherein the first radio frequency power is less than the second radio frequency power, and the first gas after plasmatization has a second etching rate greater than the first etching rate (step S127). In other words, providing a radiation frequency with a greater radio frequency power per unit time to the first gas can increase the etching rate of the stacked structure 100 by the first gas after plasmatization. The reason is that Ar ions have higher energy in the state of high RF power, and thus can break more chemical bonds on the surface of the stacked structure 100 and form defects, thereby increasing the chemical reaction rate of the first etching process.

It should be particularly noted that the operator can selectively perform step S124, step S125, step S126 and step S127 simultaneously or alternately according to the expected cross-sectional profile of the opening 150. For example, if an opening 150 with a high aspect ratio is to be formed, step S125 and step S127 can be selectively performed on the stacking structure 100. In one embodiment, the aspect ratio of the opening 150 is at least greater than about 12. In one embodiment, step S120 is to form a through hole by allowing the opening 150 to penetrate the stacking structure 100. In one embodiment, the opening 150 is a portion of a capacitor structure. The opening 150 with a high aspect ratio can form a high-density capacitor element and is applied to various electronic components, such as dynamic random access memory (DRAM), to reduce the size of the electronic component and improve the performance of the electronic component.

Please refer to FIG. 1. In step S130, a portion of the mask 200 is removed by a second etching process, and the second etching process uses a second gas different from the first gas.

Please refer to FIG. 3 and FIG. 4F. FIG. 3 is a flow chart of step S130 according to some embodiments of the present disclosure. In one embodiment, the second etching process at least includes a transformer-coupled plasma process. In one embodiment, the second etching process includes: a second gas is introduced into the vacuum chamber from a gas inlet of the vacuum chamber, the second gas at least includes Cl ₂ and SF ₆ , and the gas pressure of the second gas in the vacuum chamber is in the range of about 3 mtorr to about 30 mtorr (step S131); applying a radiation frequency to plasmatize the second gas (step S132); and applying a bias voltage to the stack structure (step S133). In one embodiment, the gas flow rate of the second gas in step S131 is in the range of about 30 sccm to about 130 sccm. In another embodiment, the second gas of step S131 further comprises at least one of N ₂ , He and O ₂ . In one embodiment, the gas flow rate of N ₂ is in the range of about 20 sccm to about 120 sccm. In one embodiment, the gas flow rate of He is in the range of about 0 sccm to about 300 sccm. In one embodiment, the gas flow rate of O ₂ is in the range of about 0 sccm to about 50 sccm. In one embodiment, the radiation frequency of step S132 provides RF power to the first gas per unit time, and the RF power is in the range of about 400 W to about 1000 W. In one embodiment, the bias in step S133 provides bias power to the stack structure 100 per unit time, and the bias power is in a range of about 50 W to about 200 W.

From the above detailed description of the specific implementation methods of the present disclosure, it can be clearly seen that the method of manufacturing semiconductor devices of some embodiments of the present disclosure can form an opening with a high aspect ratio in a stacked structure through a mask including a tungsten layer and a first gas after plasma. The reason is that since the tungsten layer and the stacked structure have a high selective etching ratio, the thickness of the mask can be thinned and its etching aspect ratio can be reduced. In this way, etching the stacked structure using the first gas after plasma can form an opening with a higher aspect ratio in the stacked structure. In addition, the formula of the first gas can provide high anisotropy in the etching process, reduce the local electrical poor contact phenomenon caused by the etching process to the stacked structure and improve the process yield.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and replacements herein without departing from the spirit and scope of the present disclosure.

50: substrate 100: stacking structure 110: first nitride layer 120: dielectric layer 130: second nitride layer 140: oxide layer 150: opening 200: mask 210: mask nitride layer 220: mask semiconductor layer 230: mask oxide layer 240: tungsten layer 250: anti-reflective layer 260: opening 300: photoresist layer M1: method S110, S112, S120, S121, S122, S123, S124, S125, S126, S127, S130, S131, S132, S133: steps

The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the sizes of the various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1 to 3 are flow charts of methods for manufacturing semiconductor devices according to some embodiments of the present disclosure. Figure 2 is a flow chart of several steps of the method for manufacturing semiconductor devices according to some embodiments of the present disclosure. Figure 3 is a flow chart of several steps of the method for manufacturing semiconductor devices according to some embodiments of the present disclosure. Figures 4A to 4F are cross-sectional schematic diagrams of several stages of the method for manufacturing semiconductor devices according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

M1: Methods

S110, S120, S130: Steps

Claims (10)

A method for manufacturing a semiconductor device comprises: forming a mask on a stacked structure, wherein the mask comprises at least a tungsten layer; performing a first etching process on the stacked structure through the mask to form an opening in the stacked structure, wherein the first etching process comprises: introducing a first gas, wherein the first gas comprises at least CHF ₃ and Ar, wherein a pressure of the first gas is in a range of about 5 mtorr to about 30 mtorr, and CHF ₃ and Ar have a molecular molar ratio ranging from about 5 to about 20; applying a radiation frequency to plasmatize the first gas, comprising: applying the radiation frequency to provide a first radio frequency power to the first gas, wherein the first gas plasmatized by the first radio frequency power has a first etching rate; and applying the radiation frequency to provide a second radio frequency power to the first gas, wherein the second radio frequency power A RF power is less than the second RF power, and the first gas after being plasmatized by the second RF power has a second etching rate greater than the first etching rate, wherein the first RF power and the second RF power are in the range of about 3000W to about 20000W; and a bias is applied to the stacked structure; and a second etching process is performed to remove at least a portion of the mask, wherein the second etching process uses a second gas different from the first gas. The method for manufacturing a semiconductor device as described in claim 1, wherein the first etching process further comprises: making the first gas have a first pressure, wherein the first gas having the first pressure has a third etching rate after plasma formation; and making the first gas have a second pressure, wherein the first pressure is greater than the second pressure, and the first gas having the second pressure has a fourth etching rate higher than the third etching rate after plasma formation. A method for manufacturing a semiconductor device as described in claim 1, wherein the maximum selective etching ratio of the first gas to the stacked structure and the tungsten layer is about 78. A method for manufacturing a semiconductor device as described in claim 1, wherein the radiation frequency provides a radio frequency power to the first gas within a unit time, and the radio frequency power is in the range of about 3000W to about 20000W. A method for manufacturing a semiconductor device as described in claim 1, wherein the bias provides a bias power to the stack structure within a unit time, and the bias power is in the range of about 2000W to about 8000W. A method for manufacturing a semiconductor device as described in claim 1, wherein the second etching process includes: introducing the second gas, the second gas containing at least _Cl2 and _SF6 , and a pressure of the second gas is in the range of about 3mtorr to about 30mtorr; applying a radiation frequency to plasmatize the second gas; and applying a bias to the stack structure. The method for manufacturing a semiconductor device as described in claim 6, wherein the second gas further comprises at least one of _N2 , He and _O2 . A method for manufacturing a semiconductor device as described in claim 1, wherein a thickness of the tungsten layer is in the range of about 20 nm to about 80 nm. The method for manufacturing a semiconductor device as described in claim 1, wherein the step of performing the first etching process on the stacked structure through the mask is to make the opening penetrate the stacked structure to form a through hole. A method for manufacturing a semiconductor device as described in claim 1, wherein the aspect ratio of the opening is at least greater than about 12.

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