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TWI737254B - 積體電路封裝體及其製造方法 - Google Patents

積體電路封裝體及其製造方法 Download PDF

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Publication number
TWI737254B
TWI737254B TW109111684A TW109111684A TWI737254B TW I737254 B TWI737254 B TW I737254B TW 109111684 A TW109111684 A TW 109111684A TW 109111684 A TW109111684 A TW 109111684A TW I737254 B TWI737254 B TW I737254B
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Taiwan
Prior art keywords
die
connector
layer
conductive material
reflowable
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TW109111684A
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English (en)
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TW202119509A (zh
Inventor
郭宏瑞
蔡惠榕
汪嘉偉
張育慈
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台灣積體電路製造股份有限公司
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Abstract

在一實施例中，一種元件包含：半導體基底；位於半導體 基底上的接觸墊；位於接觸墊及半導體基底上的鈍化層；延伸穿過鈍化層的晶粒連接件，晶粒連接件實體耦接且電性耦接至接觸墊，晶粒連接件包含第一導電材料，第一導電材料為具有第一酸軟硬指數的路易斯酸；位於晶粒連接件及鈍化層上的介電層；以及安置於介電層與晶粒連接件之間的保護層，保護層環繞晶粒連接件，保護層包含第一導電材料與唑的配位錯合物，唑為具有第一配位體軟硬指數的路易斯鹼，其中第一酸軟硬指數與第一配位體軟硬指數的乘積為正值。

Description

積體電路封裝體及其製造方法
本發明實施例是有關於一種積體電路封裝體及其製造方法。
半導體行業基於多種電子組件(例如，電晶體、二極體、電阻器、電容器等)的整合密度的持續改良而經歷快速發展。主要而言，整合密度改良歸因於最小特徵尺寸(minimum feature size)的反覆減小，此允許將更多組件整合至一個給定區域中。隨著對於縮小的電子元件的需求之增長，對於半導體晶粒的更小且具更創造性的封裝技術的需要已出現。此類封裝系統的實例為疊層封裝(Package-on-Package；PoP)技術。在PoP元件中，頂部半導體封裝堆疊於底部半導體封裝的頂部上，以提供高階(high level)的整合及組件密度。PoP技術通常使得能夠產生在印刷電路板(printed circuit board；PCB)上具有增強之功能性及較小之佔據面積的半導體元件。
根據一些實施例，提供一種積體電路封裝體的製造方法， 所述的方法包括：接收積體電路晶粒，所述積體電路晶粒包含：接觸墊，位於半導體基底上；鈍化層，位於所述接觸墊及所述半導體基底上；晶粒連接件，延伸穿過所述鈍化層，所述晶粒連接件實體耦接且電性耦接至所述接觸墊，所述晶粒連接件包含第一導電材料，所述第一導電材料為具有第一酸軟硬指數的路易斯酸；以及可回焊連接件，位於所述晶粒連接件上，所述可回焊連接件包含第二導電材料，所述第二導電材料為具有第二酸軟硬指數的路易斯酸；以及使用蝕刻溶液蝕刻所述可回焊連接件及所述晶粒連接件，所述蝕刻溶液包含用於所述第一導電材料的防護劑及用於所述第二導電材料的蝕刻劑，所述防護劑為唑，所述唑為具有第一配位體軟硬指數的路易斯鹼，其中所述第一酸軟硬指數與所述第一配位體軟硬指數的乘積為正值，且所述第二酸軟硬指數與所述第一配位體軟硬指數的乘積為負值。
根據一些實施例，提供一種積體電路封裝體的製造方法，所述的製造方法包括：在半導體基底上形成接觸墊；在所述接觸墊及所述半導體基底上沈積鈍化層；於所述鈍化層中圖案化暴露出所述接觸墊的開口；在所述開口中及所述接觸墊上鍍覆晶粒連接件，所述晶粒連接件包含第一導電材料；在所述晶粒連接件上回焊可回焊連接件；以及使用蝕刻溶液蝕刻所述可回焊連接件及所述晶粒連接件以移除所述可回焊連接件，所述蝕刻溶液包含蝕刻劑及防護劑，所述防護劑為含有用於接合至所述第一導電材料的多個活性部位的五員雜環化合物。
根據一些實施例，提供一種積體電路，所述的積體電路包括：半導體基底；接觸墊，位於所述半導體基底上；鈍化層，位於 所述接觸墊及所述半導體基底上；晶粒連接件，延伸穿過所述鈍化層，所述晶粒連接件實體耦接且電性耦接至所述接觸墊，所述晶粒連接件包含第一導電材料，所述第一導電材料為具有第一酸軟硬指數的路易斯酸；介電層，位於所述晶粒連接件及所述鈍化層上；以及保護層，安置於所述介電層與所述晶粒連接件之間，所述保護層環繞所述晶粒連接件，所述保護層包含所述第一導電材料與唑的配位錯合物，所述唑為具有第一配位體軟硬指數的路易斯鹼，其中所述第一酸軟硬指數與所述第一配位體軟硬指數的乘積為正值。
3:區域
50:積體電路晶粒
50A:第一積體電路晶粒
50B:第二積體電路晶粒
52:半導體基底
52A:第一元件區
52B:第二元件區
54:內連線結構
56:接觸墊
58:鈍化層
60:晶粒連接件
62:開口
64:晶種層
64A:鈦層
64B:銅層
66:光阻
68A:第一導電材料層
68B:第二導電材料層
68C:第三導電材料層
70:可回焊連接件
72:晶片探針
74:蝕刻製程
76:保護層
78、108、112、142、146、150、154、162、166、170:介電層
80:單體化製程
82:基底穿孔
100:第一封裝體組件
100A:第一封裝區
100B:第二封裝區
102:載體基底
104:釋放層
110、144、148、152、164、166、168、172、174、176、178:金屬化圖案
116:穿孔
128:黏著劑
130:包封體
140:重佈線結構/前側重佈線結構
140A:精細特徵部分
140B:粗糙特徵部分
156:凸塊下金屬
158:導電連接件
200:第二封裝體組件
202:基底
204A、204B:堆疊晶粒
206:導通孔
208、210、304:接合墊
212:線接合
214:模製材料
300:封裝基底
302:基底芯
306:阻焊劑
308:底部填充物
R1、R2:減小量
T1、T2、T3、T4、T5、T6、T7:厚度
W1、W2:寬度
結合附圖閱讀以下詳細描述會最佳地理解本揭露的各態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，出於論述清晰起見，可任意地增大或減小各種特徵的尺寸。
圖1至圖5示出根據一些實施例的用於形成積體電路晶粒的製程期間的中間步驟的橫截面視圖。
圖6A及圖6B示出根據各種實施例的積體電路晶粒的橫截面視圖。
圖7至圖14示出根據一些實施例的用於形成封裝體組件的製程期間的中間步驟的橫截面視圖。
圖15及圖16示出根據一些實施例的元件堆疊的形成及實施。
圖17示出根據一些其他實施例的封裝體組件的橫截面視圖。
圖18示出根據一些其他實施例的封裝體組件的橫截面視圖。
圖19示出根據一些其他實施例的封裝體組件的橫截面視圖。
圖20示出根據一些其他實施例的封裝體組件的橫截面視圖。
圖21示出根據一些其他實施例的封裝體組件的橫截面視圖。
以下揭露內容提供用於實施本揭露的不同特徵的許多不同實施例或實例。以下描述組件及配置的特定實例以簡化本揭露。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵形成於第二特徵上方或第二特徵上可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可形成於第一特徵與第二特徵之間以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的，且本身並不規定所論述的各種實施例及/或配置之間的關係。
另外，為易於描述，本文中可使用諸如「在...之下」、「在...下方」、「下部」、「在...上方」、「上部」以及其類似者的空間相對術語，以描述如圖式中所示出的一個部件或特徵相對於另一部件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語還意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據一些實施例，晶片探針附接至晶粒連接件且用以對良好晶粒(known good dies；KGDs)進行測試。晶片探針與可回焊連接件附接。在移除晶片探針之後，透過濕式蝕刻製程來移除可 回焊連接件。濕式蝕刻製程包含使用具有防護劑的蝕刻溶液來蝕刻可回焊連接件。防護劑為軟路易斯鹼(soft Lewis base)，諸如唑化合物，其與晶粒連接件的材料形成強共價鍵(covalent bond)。因此，可在濕式蝕刻製程期間保護晶粒連接件。
圖1至圖5示出根據一些實施例的用於形成積體電路晶粒50的製程期間的中間步驟的橫截面視圖。積體電路晶粒50將在後續處理中經封裝以形成積體電路封裝體。每個積體電路晶粒50可為邏輯晶粒(例如，中央處理單元(central processing unit；CPU)、圖形處理單元(graphics processing unit；GPU)、系統晶片(system-on-a-chip；SoC)、應用程式處理器(application processor；AP)、微控制器等)、記憶體晶粒(例如，動態隨機存取記憶體(dynamic random access memory；DRAM)晶粒、靜態隨機存取記憶體(static random access memory；SRAM)晶粒等)、功率管理晶粒(例如，功率管理積體電路(power management integrated circuit；PMIC)晶粒)、射頻(radio frequency；RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system；MEMS)晶粒、信號處理晶粒(例如，數位信號處理(digital signal processing；DSP)晶粒)、前端晶粒(例如，類比前端(analog front-end；AFE)晶粒)，類似者或其組合。
在圖1中，提供半導體基底52。半導體基底52可為經摻雜或未經摻雜的矽，或絕緣層上有半導體(semiconductor-on-insulator；SOI)基底的作用層。半導體基底52可包含其他半導體材料，諸如：鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、 AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層基底(multi-layered substrate)或梯度基底(gradient substrate)。半導體基底52具有有時被稱作前側的主動表面(例如，圖1中面向上的表面)及有時被稱作背側的非主動表面(例如，圖1中面向下的表面)。多個元件形成於半導體基底52的主動表面處。上述多個元件可為主動元件(例如，電晶體、二極體等)或被動元件(例如，電容器、電阻器、電感器等)。
半導體基底52具有多個元件區，且積體電路晶粒50形成於元件區中的每一者中及/或元件區中的每一者上。示出第一元件區52A及第二元件區52B，但應瞭解，半導體基底52可具有任何數目的元件區。
內連線結構54形成於半導體基底52上方。內連線結構54使半導體基底52的元件互連以在元件區52A及元件區52B中的每一者中形成積體電路。內連線結構54可由例如在多個介電層中的多個金屬化圖案形成。上述多個金屬化圖案包含形成於一或多個低介電常數(low-k)介電層中的多個金屬線及多個通孔。內連線結構54可由鑲嵌製程(damascene process)(諸如單鑲嵌製程、雙鑲嵌製程或類似者)形成。內連線結構54的金屬化圖案電性耦接至半導體基底52的元件。
在圖2中，多個接觸墊56形成於積體電路晶粒50的前側上，諸如形成於內連線結構54中及/或內連線結構54上。接觸墊56可為進行外部連接的鋁焊墊、銅焊墊或類似者。在一些實施例中，接觸墊56為內連線結構54的最頂部金屬化圖案的部分。
一或多個鈍化層58形成於接觸墊56及內連線結構54 上。鈍化層58可由一或多種合適的介電材料製成，上述介電材料例如是氧化矽、氮化矽、低介電常數介電質(諸如碳摻雜氧化物(carbon doped oxide))、極低介電常數介電質(諸如摻多孔碳二氧化矽(porous carbon doped silicon dioxide))、聚合物(諸如聚醯亞胺、阻焊劑、聚苯并噁唑(polybenzoxazole；PBO)、苯環丁烷(benzocyclobutene；BCB))、模製化合物、類似者或其組合。鈍化層58可由旋轉塗佈、層壓、化學氣相沈積(chemical vapor deposition；CVD)、類似者、或其組合形成。
多個晶粒連接件60(諸如多個導電柱(例如，由諸如銅金屬形成))延伸穿過鈍化層58形成，以實體耦接且電性耦接至接觸墊56。晶粒連接件60因此電性耦接積體電路晶粒50的相應積體電路。晶粒連接件60可被稱作導通孔。圖3A至圖3F為根據一些實施例的用於形成晶粒連接件60的製程期間的中間步驟的橫截面視圖。具體而言，更詳細地繪示圖2中的區域3。儘管示出單個晶粒連接件60的形成，但應瞭解，多個晶粒連接件60為同時形成的。
在圖3A中，鈍化層58經圖案化以形成多個開口62，所述多個開口62暴露出接觸墊56的多個部分。上述圖案化透過可接受的製程(諸如當鈍化層58為感光性材料時將鈍化層58暴露於光或使用例如非等向性蝕刻來進行蝕刻)來進行。若鈍化層58為感光性材料，則鈍化層58可在曝光之後顯影。
在將鈍化層58圖案化之後，晶種層64形成於鈍化層58上方及暴露出接觸墊56的開口62中。在一些實施例中，晶種層64為金屬層，金屬層可為單層或包括由不同材料形成的多個子層 的複合層。在一些實施例中，晶種層64包括鈦層64A及在鈦層64A上方的銅層64B。可使用例如物理氣相沈積(physical vapor deposition；PVD)或類似者形成晶種層64。晶種層64可形成為在約0.01微米至約2.0微米範圍內的厚度T1。
在圖3B中，光阻66於晶種層64上形成以及圖案化。光阻66可透過旋轉塗佈或類似者形成，且可暴露於光以用於圖案化。光阻66的圖案對應於晶粒連接件60。上述圖案化形成貫穿光阻66的多個開口，以暴露出晶種層64。
多個第一導電材料層68A隨後形成於光阻66的開口中及晶種層64的暴露部分上。第一導電材料層68A可透過鍍覆形成，諸如電鍍(electroplating)或無電鍍覆(electroless plating)，或類似者。第一導電材料層68A可包括金屬，如銅、鈦、鎢、鋁或類似者。在一些實施例中，第一導電材料層68A為銅。第一導電材料層68A可形成為在約1微米至約50微米範圍內(諸如約15微米)的厚度T2。
多個第二導電材料層68B可視情況地形成於第一導電材料層68A上。第二導電材料層68B可以與第一導電材料層68A類似的方式形成，且可由與第一導電材料層68A不同的材料形成。在一些實施例中，第二導電材料層68B為鎳。第二導電材料層68B可形成為約0.1微米至約20微米範圍內(諸如約3微米)的厚度T3。形成鎳層可有助於防止第一導電材料層68A的銅在進一步處理期間氧化。
多個第三導電材料層68C可視情況地形成於第二導電材料層68B上。第三導電材料層68C可以與第一導電材料層68A類 似的方式形成，且可由與第一導電材料層68A相同的材料形成。在一些實施例中，第三導電材料層68C為銅。第三導電材料層68C可形成為在約0.1微米至約20微米(諸如約2微米)範圍內的厚度T4。形成銅層可有助於防止當可回焊連接件隨後形成於晶粒連接件60上時金屬間化合物(inter-metallic compounds；IMC)在第二導電材料層68B中及/或第二導電材料層68B上形成。
光阻66中的開口(也因此導電材料層68A、導電材料層68B以及導電材料層68C)可形成為在約1微米至約150微米範圍內的寬度W1。導電材料層68A、導電材料層68B以及導電材料層68C的組合與下覆之部分的晶種層64形成晶粒連接件60。
在圖3C中，移除光阻66及晶種層64上未形成導電材料層68A、導電材料層68B以及導電材料層68C的部分。光阻66透過可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除。一旦移除光阻66，則透過使用可接受的蝕刻製程(諸如濕式蝕刻或乾式蝕刻)來移除晶種層64的被暴露部分。
在圖3D中，可回焊連接件70形成於晶粒連接件60上。可回焊連接件70可包含導電材料，諸如焊料、金、銀、錫、類似者或其組合。在一些實施例中，可回焊連接件70最初透過經由蒸鍍、電鍍、印刷、焊料轉移、植球或類似方法形成焊料層而形成。可回焊連接件70可在移除光阻66之後形成，或可在移除光阻66之前形成於光阻66的開口中。一旦焊料層已形成於晶粒連接件60上，則可視情況地進行回焊(reflow)以將材料塑形成所希望的凸塊形狀。可回焊連接件70為較厚的。舉例而言，可回焊連接件70可形成為在約1微米至約50微米範圍內(諸如約15微米)的厚 度T5。
在圖3E中，透過使用晶片探針72來測試積體電路晶粒50。晶片探針72透過回焊可回焊連接件70實體耦接且電性耦接至晶粒連接件60，其可將可回焊連接件70塑形成凸塊形狀。可對積體電路晶粒50執行晶片探針測試以確定積體電路晶粒50是否為良好晶粒(KGDs)。因此，僅有作為良好晶粒的積體電路晶粒50將經歷後續處理及封裝，且未通過晶片探針測試的積體電路晶粒50將不被封裝。上述測試可包含對各種積體電路晶粒50的功能性的測試，或可包含對基於積體電路元件的設計之預期的已知開路或已知短路的測試。
在圖3F中，晶片探針72自晶粒連接件60脫離且移除。上述脫離可透過回焊可回焊連接件70實現。在脫離晶片探針72之後，執行蝕刻製程74以移除可回焊連接件70的剩餘部分。蝕刻製程74對可回焊連接件70的材料為有選擇性的，使得蝕刻可回焊連接件70的材料比晶粒連接件60的材料更快。
儘管蝕刻製程74對所需材料(例如，可回焊連接件70的材料)為有選擇性的，但一些非所需材料(例如，晶粒連接件60的材料)的蝕刻仍然出現。另外，非所需材料的蝕刻可能以不同速率出現。舉例而言，蝕刻製程74可以高於蝕刻銅的速率來蝕刻焊料，且可以高於蝕刻鈦及高於蝕刻鎳的速率來蝕刻銅。因而，導電材料層68A與導電材料層68C以及銅層64B的尺寸可透過蝕刻製程74減小，而導電材料層68B(例如，鎳)及鈦層64A的尺寸可不以明顯的量減小。在移除可回焊連接件70之後，導電材料層68B及鈦層64A可實質上保留初始寬度W1，但導電材料層68A及導 電材料層68C以及銅層64B可減小至更小寬度W2，諸如在約0.7微米至約149微米範圍內的寬度W2。減小量R1可在約0.0005微米至約45微米的範圍內，諸如約0.1微米，其可占初始寬度W1的約0.05%至約30%。另外，導電材料層68C的厚度可減小至更小厚度T6，諸如在約0.07微米至約19.99微米範圍內的厚度T6。減小量R2可為在約0.001微米至約6微米的範圍內，諸如約0.1微米，其可占初始厚度T4的約0.05%至約30%。
在一些實施例中，蝕刻製程74為使用水基蝕刻溶液(water-based etching solution)執行的濕式蝕刻，所述水基蝕刻溶液包含用於可回焊連接件70的材料的蝕刻劑及用於晶粒連接件60的材料的防護劑。蝕刻劑與可回焊連接件70的材料反應以將其自固相轉換成液相。在一些實施例中，蝕刻劑為氧化金屬離子。舉例而言，可使用氧化鐵(III)、氧化銅(II)或類似者來移除可回焊連接件70的材料。防護劑(在下文中進一步論述)與晶粒連接件60的材料反應以形成減小晶粒連接件60的蝕刻速率的保護層76。蝕刻劑和防護劑溶解於溶劑中，上述溶劑可以為能夠溶解蝕刻劑及防護劑的任何溶劑。上述溶劑的實例包含硝酸、硫酸及類似者。蝕刻溶液中的防護劑的濃度可能較小。舉例而言，蝕刻溶液可包含1ppm至20000ppm的防護劑，其可表示防護劑的濃度在約0.0001%至約2%範圍內。相對而言，蝕刻溶液可包含濃度為在約0.1%至約20%範圍內的蝕刻劑，且可包含濃度為在約0.5%至約50%範圍內的溶劑。
在蝕刻製程74期間，可透過使用若干種技術將蝕刻溶液施配於中間結構(intermediate structure)(包含晶粒連接件60及 可回焊連接件70)上。在一些實施例中，中間結構浸沒於蝕刻溶液的浴槽中。在一些實施例中，蝕刻溶液噴施於中間結構上。上述之在中間結構上噴施蝕刻溶液可包含在使蝕刻溶液於中間結構上方流動時旋轉中間結構。中間結構可在低速下旋轉，諸如在約100轉/分鐘至約3000轉/分鐘之範圍內的速度下旋轉。同樣地，蝕刻溶液可在高速下流動，諸如在約0.2升/分鐘至約2升/分鐘範圍內的流動速率下流動。在不考慮如何施配蝕刻溶液的情況下，蝕刻製程74可在低溫下進行，諸如在約5℃至約50℃範圍內的溫度下進行。另外，可執行蝕刻製程74達任何所需持續時間，諸如在約0.1分鐘至約120分鐘範圍內的持續時間。
如上文所指出，蝕刻溶液中的防護劑與晶粒連接件60的材料反應以形成減小晶粒連接件60的蝕刻速率的保護層76。具體而言，防護劑為有機配位體(organic ligand)，其與導電材料層68A及導電材料層68C以及銅層64B的材料(例如，銅)反應以在膜層的暴露表面處形成配位錯合物(coordination complex)的保護層76。配位錯合物化學地阻止蝕刻劑與經暴露銅發生反應。有利地，保護層76的形成使得在蝕刻製程74期間的減小量R1及減小量R2較小。在一些實施例中，保護層76為位於導電材料層68A及導電材料層68C以及銅層64B的表面處的單層(monolayer)。在一些實施例中，保護層76至少部分延伸至導電材料層68A及導電材料層68C以及銅層64B中，使得上述膜層具有包含配位錯合物的外部區及不含配位錯合物的內部區。保護層76較薄，具有可在約1埃至約100埃範圍內的厚度T7。保護層76可在蝕刻製程74之後保留，且可為所得積體電路晶粒50的一部分。
晶粒連接件60及可回焊連接件70的金屬為路易斯酸(Lewis acid)，且防護劑的配位體為路易斯鹼(Lewis base)。根據皮爾森氏硬軟酸鹼(Pearson's Hard Soft Acid Base；HSAB)定理，「硬」路易斯酸(例如，具有高電荷密度及小的半徑)與「硬」路易斯鹼形成強離子鍵，且「軟」路易斯酸(例如，具有低電荷密度及大的半徑)與「軟」路易斯鹼形成強共價鍵。儘管路易斯酸及路易斯鹼通常定性地歸類為「硬」或「軟」，但已作出努力以量化路易斯酸及路易斯鹼的精確硬度/軟度。舉例而言，Xu等人在「用於金屬陽離子及配位體的化學硬度/軟度的自然指數(Natural Indices for the Chemical Hardness/Softness of Metal Cations and Ligands)」，ACS Omega 2017 2(10)之第7185頁至第7193頁(其以全文引用的方式併入本文)中，提出陽離子(△G°f,M n+)形成的吉布斯能量為用於路易斯酸的硬度/軟度的自然指數。根據此定義，具有正△G°f,M n+值的酸為「軟」路易斯酸，且具有負△G°f,M n+值的酸為「硬」路易斯酸。Xu等人進一步提出係數α*ML可自用於各種路易斯鹼的實驗資料導出，且各係數α*ML為用於對應路易斯鹼的硬度/軟度的指數。正α*ML值指示「軟」路易斯鹼，且負α*ML值指示「硬」路易斯鹼。基於這些指數，錯合物中的給定之路易斯酸與路易斯鹼之間的鍵結強度可透過計算用於路易斯酸及路易斯鹼的軟硬指數的乘積來憑經驗判定。當乘積為正(正值)(例如，大於零)時，則強鍵(離子鍵或共價鍵)將形成於路易斯酸與路易斯鹼之間。當乘積為負(負值)(例如，小於零)時，則弱鍵將形成於路易斯酸與路易斯鹼之間。
銅為「軟」路易斯酸(例如，具有正△G°f,M n+值)。相對 而言，錫及鎳為「硬」路易斯酸(例如，具有負△G°f,M n+值)。根據一些實施例，蝕刻溶液中的防護劑為「軟」路易斯鹼(例如具有正α*ML值)。基於皮爾森氏HSAB定理，防護劑將因此與銅形成有強共價鍵，及將與錫或鎳不形成有強鍵。換言之，防護劑將與導電材料層68A及導電材料層68C以及銅層64B的材料(例如，銅)反應，實質上不與導電材料層68B、鈦層64A以及可回焊連接件70的材料(例如，錫/鎳)反應。
防護劑可為任何「軟」路易斯鹼，但唑衍生(azole-derived)的路易斯鹼可能尤其可行，因為其具有較大正α*ML值(例如，至少0.0794)，並為無毒的，且與其他路易斯鹼相比具有低成本。唑為含有多個氮原子的五員雜環化合物，其使得唑化合物具有多於一個活性部位以用於與銅接合。可使用若干類型的唑。舉例而言，唑可為：吡唑化合物(pyrazole compound)(例如，甲基吡唑(methylpyrazole))、咪唑化合物(imidazole compound)(例如，甲基咪唑(methylimidazole))、三唑化合物(triazole compound)(例如，苯并三唑(benzotriazole))、四唑化合物(tetrazole compound)(例如，苯基四唑(phenyltetrazole)或苯基-巰基四唑(phenyl-mercaptotetrazole))或五唑化合物(pentazole compound)(例如，五唑(例如，HN5))。應瞭解，其他類型的唑，且實際上，其他「軟」路易斯鹼亦可用於防護劑。
儘管描述為單個製程，但應瞭解，圖3A至圖3F中所示出的步驟可拆分成多個製程。舉例而言，可執行包括圖3A至圖3D中所示出步驟的第一製程以獲得中間結構。可在自第一製程獲得或接收中間結構之後執行包括圖3E至圖3F中所示出步驟的第二 製程。
在圖4中，介電層78形成於積體電路晶粒50的前側上，諸如形成於鈍化層58上及晶粒連接件60上。介電層78橫向地包封晶粒連接件60。介電層78可為聚合物，諸如PBO、聚醯亞胺、BCB或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似者；類似者；或其組合。介電層78可例如透過旋轉塗佈、層壓、CVD或類似者形成。最初，介電層78可掩埋晶粒連接件60，使得介電層78的最頂部表面在晶粒連接件60的最頂部表面上方。在一些實施例中，晶粒連接件60在積體電路晶粒50的形成期間經由介電層78暴露。在一些實施例中，晶粒連接件60保持掩埋且在用於封裝積體電路晶粒50的後續製程期間暴露。
當介電層78為諸如PBO的聚合物時，在形成介電層78之前自晶粒連接件60移除可回焊連接件70，可防止在介電層78的固化製程期間之焊料潤濕(solder wetting)。另外，透過蝕刻製程74代替其他製程(諸如CMP)移除可回焊連接件70，可有助於減少介電層78中焊料殘渣的量。最後，透過蝕刻製程74移除可回焊連接件70對晶粒連接件60的損害較小，其可有助於增加晶粒連接件60的可靠性及電性效能。
在圖5中，透過沿著多個切割道區(例如在元件區52A與元件區52B之間)鋸割來執行單體化製程80。單體化製程80單體化元件區52A及元件區52B。所得單體化積體電路晶粒50來自元件區52A及元件區52B。圖6A及圖6B為根據各種實施例的所得積體電路晶粒50的橫截面視圖。
圖6A繪示第一類型的積體電路晶粒50A。第一積體電路晶粒50A具有單個半導體基底52，且與關於圖1至圖5所論述的實施例類似。第一積體電路晶粒50A可為邏輯元件，諸如中央處理單元(CPU)、圖形處理單元(GPU)、系統晶片(SoC)、微控制器或類似者。
圖6B繪示第二類型的積體電路晶粒50B。第二積體電路晶粒50B可為記憶體元件，諸如動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒、混合記憶體立方(hybrid memory cube；HMC)模組、高頻寬記憶體(high bandwidth memory；HBM)模組或類似者。第二積體電路晶粒50B為包含多個半導體基底52的堆疊元件。舉例而言，第二積體電路晶粒50B可為包含多個記憶體晶粒的記憶體元件，諸如混合記憶體立方(HMC)模組、高頻寬記憶體(HBM)模組，或類似者。半導體基底52可透過部分地延伸至半導體基底52中或完全地延伸穿過半導體基底52的多個基底穿孔(through-substrate vias；TSV)82互連。堆疊的半導體基底52可共用內連線結構54或各半導體基底52可具有自己的內連線結構54。另外，包封體84可形成於堆疊的半導體基底52周圍。包封體84可為模製化合物、環氧樹脂或類似者。
圖7至圖14示出根據一些實施例的用於形成第一封裝體組件100的製程期間的中間步驟的橫截面視圖。第一封裝體組件100具有多個封裝區，且積體電路晶粒50中的一或多者經封裝以在封裝區中的每一者中形成積體電路封裝體。示出第一封裝區100A及第二封裝區100B，但應瞭解，第一封裝體組件100可具有任何數目個封裝區。形成之後，封裝區中的每一者中的積體電路封 裝體經單體化。所得積體電路封裝體亦可稱為整合扇出型(integrated fan-out；InFO)封裝體。
在圖7中，提供載體基底102，且釋放層104形成於載體基底102上。載體基底102可為玻璃載體基底、陶瓷載體基底或類似者。載體基底102可為晶圓，以使得多個封裝體可同時在載體基底102上形成。釋放層104可由聚合物類材料形成，可將所述材料連同載體基底102一起自將在後續步驟中形成的上覆結構移除。在一些實施例中，釋放層104為在加熱時損失其黏著性質的環氧類熱釋放材料，諸如光-熱轉換(light-to-heat-conversion；LTHC)釋放塗層。在其他實施例中，釋放層104可為在暴露於UV光時損失其黏著性質的紫外線(ultra-violet；UV)黏膠。釋放層104可以液態來施配且再固化，可為層壓至載體基底102上的層壓膜，或可為類似者。釋放層104的頂部表面可為平坦的，且可具有高平面度。
在圖8中，背側重佈線結構106可形成於釋放層104上。在所示實施例中，背側重佈線結構106包含介電層108、金屬化圖案110(有時稱為多個重佈線層或多個重佈線)以及介電層112。可視情況選用背側重佈線結構106。在一些實施例中，無金屬化圖案的介電層代替背側重佈線結構106形成於釋放層104上。
介電層108可形成於釋放層104上。介電層108的底部表面可與釋放層104的頂部表面接觸。在一些實施例中，介電層108由聚合物形成，諸如：聚苯并噁唑(PBO)、聚醯亞胺、苯環丁烷(BCB)或類似者。在其他實施例中，介電層108由下述各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷矽酸鹽玻璃 (PSG)、硼矽酸鹽玻璃(BSG)、硼摻磷矽酸鹽玻璃(BPSG)或類似者；或類似者。介電層108可透過任何可接受的沈積製程形成，諸如旋轉塗佈、CVD、層壓、類似製程或其組合。
金屬化圖案110形成於介電層108上。作為用以形成金屬化圖案110的實例，晶種層形成於介電層108上方。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層以及鈦層上方的銅層。晶種層可使用例如PVD或類似者來形成。隨後在晶種層上形成光阻且使所述光阻圖案化。光阻可透過旋轉塗佈或類似者形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案110。所述圖案化形成穿過光阻的多個開口以暴露出晶種層。導電材料在光阻的開口中及晶種層的暴露部分上形成。導電材料可透過鍍覆形成，諸如電鍍或無電鍍覆，或類似者。導電材料可包含金屬，如銅、鈦、鎢、鋁或類似者。隨後，移除光阻及晶種層上未形成導電材料的部分。透過可接受的灰化或剝離製程來移除光阻，諸如使用氧電漿或類似者。一旦移除光阻，則諸如透過使用可接受的蝕刻製程(諸如濕式蝕刻或乾式蝕刻)來移除晶種層的暴露部分。晶種層及導電材料的剩餘部分形成金屬化圖案110。
介電層112可形成於金屬化圖案110及介電層108上。在一些實施例中，介電層112由聚合物形成，所述聚合物可為以使用微影罩幕來圖案化的感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層112由下述者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似者。介電層112可透過旋轉塗佈、層壓、CVD、類似者或其組合來形 成。
應瞭解，背側重佈線結構106可包含任何數目的介電層及金屬化圖案。若將形成更多介電層及金屬化圖案，則可重複上述步驟及製程。金屬化圖案可包含多個導電線及多個導通孔。可在金屬化圖案的形成期間透過在底層介電層的開口中形成金屬化圖案的晶種層及導電材料來形成導通孔。導通孔可因此互連且電性耦接各種導電線。
接著，多個穿孔116形成為延伸穿過且遠離背側重佈線結構106的最頂部介電層(例如，介電層112)。視情況選用穿孔116；且如下文進一步論述，可省略穿孔116。舉例而言，在省略背側重佈線結構106的實施例中可(或可不)省略穿孔116。作為用以形成穿孔116的實例，介電層112可經圖案化以形成多個開口，來暴露出金屬化圖案110的多個部分。上述圖案化透過可接受的製程形成，諸如在介電層112為感光性材料時透過將介電層112暴露於光，或透過使用例如非等向性蝕刻來進行蝕刻。若介電層112為感光性材料，則介電層112可在曝光之後顯影。晶種層隨後形成於介電層112及透過開口而暴露出的金屬化圖案110的部分上方。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及在鈦層上方的銅層。可使用例如PVD或其類似者形成晶種層。在晶種層上形成且使所述光阻圖案化。光阻可透過旋轉塗佈或類似者形成，且可暴露於光以用於圖案化。光阻的圖案對應於導通孔。上述圖案化形成穿過光阻的多個開口以暴露出晶種層。導電材料在光阻的開口中及晶種層的暴露部分上形成。導電材料可透 過鍍覆形成，諸如電鍍或無電鍍覆，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。移除光阻及晶種層上未形成導電材料的部分。透過可接受的灰化或剝離製程來移除光阻，諸如使用氧電漿或類似者。一旦移除光阻，則諸如透過使用可接受的蝕刻製程(諸如濕式蝕刻或乾式蝕刻)來移除晶種層的暴露部分。晶種層及導電材料的剩餘部分形成穿孔116。
在圖9中，積體電路晶粒50透過黏著劑128黏著至介電層112。所需類型及數量的積體電路晶粒50黏著於封裝區100A及封裝區100B中的每一者中。在所示實施例中，多個積體電路晶粒50，諸如第一積體電路晶粒50A及第二積體電路晶粒50B在各封裝區中彼此相鄰黏著。黏著劑128位於積體電路晶粒50A及積體電路晶粒50B的背側上，且將積體電路晶粒50A及積體電路晶粒50B黏著至背側重佈線結構106，例如是黏著至介電層112。黏著劑128可為任何合適的黏著劑、環氧樹脂、晶粒貼合膜(die attach film；DAF)或類似者。黏著劑128可塗覆至積體電路晶粒50A及積體電路晶粒50B的背側或可塗覆於載體基底102的表面上方。舉例而言，可在執行單體化製程80(參見圖5)之前將黏著劑128塗覆至積體電路晶粒50A及積體電路晶粒50B的背側。
在圖10中，包封體130形成於各種組件上及各種組件的周圍。在其形成之後，包封體130包封穿孔116及積體電路晶粒50。包封體130可為模製化合物、環氧樹脂或類似者。包封體130可透過壓縮模製、轉移模製或類似者來塗覆，且可在載體基底102上方形成以使得穿孔116及/或積體電路晶粒50被掩埋或覆蓋。包封體130進一步在積體電路晶粒50之間的間隙區中形成(若存 在)。包封體130可以液體或半液體形式塗覆且隨後固化。
對包封體130執行平坦化製程以暴露出穿孔116及晶粒連接件60。平坦化製程可移除穿孔116、介電層78及/或晶粒連接件60的材料直至暴露出晶粒連接件60及穿孔116為止。在平坦化製程之後，穿孔116、晶粒連接件60、介電層78以及包封體130的頂部表面為共面的。平坦化製程可為例如CMP、研磨製程或類似製程。在平坦化製程期間，拋光晶粒連接件60的頂部表面，這可移除第二導電材料層68B及/或第三導電材料層68C(參見圖3F)。在執行平坦化製程之前使用蝕刻製程74移除可回焊連接件70，可有助於減少介電層78中焊料殘渣的量。
在圖11中，前側重佈線結構140在包封體130、穿孔116以及積體電路晶粒50上方形成。前側重佈線結構140包含多個介電層142、146、150、154以及多個金屬化圖案144、148、152。金屬化圖案亦可稱為重佈線層或重佈線。前側重佈線結構140經繪示為具有三層金屬化圖案的實例。更多或更少介電層及金屬化圖案可形成於前側重佈線結構140中。若將形成更少的介電層及金屬化圖案，則可省略下文論述的步驟及製程。若將形成更多介電層及金屬化圖案，則可重複下文所論述的步驟及製程。
作為用以形成前側重佈線結構140的實例，介電層142可在包封體130、穿孔116以及晶粒連接件60上沈積。在一些實施例中，介電層142由諸如PBO、聚醯亞胺、BCB或其類似者的感光性材料形成，感光性材料可使用微影罩幕圖案化。介電層142可透過旋轉塗佈、層壓、CVD、類似者或其組合來形成。隨後圖案化介電層142。上述圖案化形成多個開口，以暴露出穿孔116及晶 粒連接件60的多個部分。所述圖案化透過可接受製程，諸如當介電層142為感光性材料時將介電層142暴露於光或使用例如非等相性蝕刻來進行蝕刻。若介電層142為感光性材料，則介電層142可在曝光之後顯影。
隨後形成金屬化圖案144。金屬化圖案144包含在介電層142的主表面上且沿所述主表面延伸的多個導線部分(亦被稱作導電線)。金屬化圖案144更包含延伸穿過介電層142以實體耦接且電性耦接穿孔116及積體電路晶粒50的多個通孔部分(亦被稱作導通孔)。作為形成金屬化圖案144的實例，晶種層形成於介電層142上方及延伸穿過介電層142的開口中。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層以及鈦層上方的銅層。可使用例如PVD或其類似者形成晶種層。隨後在晶種層上形成光阻且使所述光阻圖案化。光阻可透過旋轉塗佈或類似者形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案144。上述圖案化形成穿過光阻的多個開口以暴露出晶種層。導電材料隨後在光阻的開口中及晶種層的暴露部分上形成。導電材料可透過鍍覆形成，諸如電鍍或無電鍍覆，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。導電材料與晶種層的底層部分的組合形成金屬化圖案144。移除光阻及晶種層上未形成導電材料的部分。透過可接受的灰化或剝離製程來移除光阻，諸如使用氧電漿或類似者。一旦移除光阻，則諸如透過使用可接受的蝕刻製程(諸如濕式蝕刻或乾式蝕刻)來移除晶種層的暴露部分。
介電層146隨後沈積於金屬化圖案144及介電層142上。 介電層146可透過與介電層142類似的方式形成，且可由與介電層142類似的材料形成。
隨後形成金屬化圖案148。金屬化圖案148包含在介電層146的主表面上且沿所述主表面延伸的多個導線部分。金屬化圖案148更包含延伸穿過介電層146以實體耦接且電性耦接金屬化圖案144的多個通孔部分。金屬化圖案148可透過與金屬化圖案144類似的方式且由與所述金屬化圖案144類似的材料形成。在一些實施例中，金屬化圖案148具有與金屬化圖案144不同的大小。舉例而言，金屬化圖案148的導電線及/或導通孔可比金屬化圖案144的導電線及/或導通孔更寬或更厚。另外，金屬化圖案148可形成為比金屬化圖案144更大的間距。
介電層150隨後沈積於金屬化圖案148及介電層146上。介電層150可透過與介電層142類似的方式形成，且可由與介電層142類似的材料形成。
隨後形成金屬化圖案152。金屬化圖案152包含在介電層150的主表面上且沿所述主表面延伸的多個導線部分。金屬化圖案152更包含延伸穿過介電層150以實體耦接且電性耦接金屬化圖案148的多個通孔部分。金屬化圖案152可透過與金屬化圖案144類似的方式且由與所述金屬化圖案144類似的材料形成。金屬化圖案152為前側重佈線結構140的最頂部金屬化圖案。因而，前側重佈線結構140的所有中間金屬化圖案(例如，金屬化圖案144及金屬化圖案148)安置於金屬化圖案152與積體電路晶粒50之間。在一些實施例中，金屬化圖案152具有與金屬化圖案144及金屬化圖案148不同的大小。舉例而言，金屬化圖案152的導電 線及/或導通孔可比金屬化圖案144及金屬化圖案148的導電線及/或導通孔更寬或更厚。另外，金屬化圖案152可形成為比金屬化圖案148更大的間距。
介電層154隨後沈積於金屬化圖案152及介電層150上。介電層154可透過與介電層142類似的方式形成，且可由與介電層142類似的材料形成。
在圖12中，多個凸塊下金屬(under-bump metallurgy；UBM)156形成至前側重佈線結構140以用作外部連接。凸塊下金屬156具有在介電層154的主表面上且沿所述主表面延伸的多個凸塊部分，且具有延伸穿過介電層154以實體耦接且電性耦接金屬化圖案152的多個通孔部分。因此，凸塊下金屬156電性耦接至穿孔116及積體電路晶粒50。凸塊下金屬156可由與金屬化圖案144相同的材料形成。在一些實施例中，凸塊下金屬156具有與金屬化圖案144、金屬化圖案148以及金屬化圖案152不同的大小。
接著，多個導電連接件158形成於凸塊下金屬156上。導電連接件158可為球柵陣列(ball grid array；BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection；C4)凸塊、微凸塊、無電式鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)技術形成的凸塊，或類似者。導電連接件158可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，導電連接件158最初透過經由蒸鍍、電鍍、印刷、焊料轉移、植球或類似者形成焊料層來形成。一旦焊料層已形成於結構 上之後，則可執行回焊以將材料塑形成所需凸塊形狀。在另一實施例中，導電連接件158包括透過濺鍍、印刷、電鍍、無電鍍覆、CVD，或其類似者形成的金屬柱(諸如銅柱)。金屬柱可並無焊料且具有實質上豎直的側壁。在一些實施例中，金屬頂蓋層在金屬柱的頂部上形成。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可由鍍覆製程形成。
在圖13中，執行載體基底剝離以將載體基底102自背側重佈線結構106(例如介電層108)脫離(或「剝離」)。根據一些實施例，上述剝離包含使諸如雷射光或UV光的光投射於釋放層104上，以使得釋放層104在光的熱能下分解且可移除載體基底102。隨後將整個結構翻轉且置放於載帶上。
在圖14中，多個導電連接件160經形成為延伸穿過介電層108以接觸金屬化圖案110。多個開口經形成為穿過介電層108以暴露出金屬化圖案110的多個部分。上述的多個開口可例如使用雷射鑽孔、蝕刻或類似者形成。導電連接件160形成於開口中。在一些實施例中，導電連接件160包括焊劑且形成於焊劑浸漬製程中。在一些實施例中，導電連接件160包括諸如焊料膏、銀膏或類似者的導電膏，且施配於印刷製程中。在一些實施例中，導電連接件160以與導電連接件158類似的方式形成，且可由與導電連接件158類似的材料形成。
圖15及圖16示出根據一些實施例的元件堆疊的形成及實施。元件堆疊由形成於第一封裝體組件100中的積體電路封裝體形成。元件堆疊亦可被稱作疊層封裝(PoP)結構。
在圖15中，多個第二封裝體組件200耦接至第一封裝體 組件100。第二封裝體組件200中的一者耦接於封裝區100A及封裝區100B中的一者中以在第一封裝體組件100的各區中形成積體電路元件堆疊。
第二封裝體組件200包含基底202及耦接至基底202的一或多個晶粒。在所示出的實施例中，晶粒包含堆疊晶粒204A及堆疊晶粒204B。在一些實施例中，晶粒(或晶粒堆疊)可經安置為並排(side-by-side)耦接至基底202的相同表面。基底202可由諸如矽、鍺、金剛石、或類似者的半導體材料製成。在一些實施例中，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷鎵、磷化銦鎵、上述組合以及類似者。另外，基底202可為絕緣層上有矽(silicon-on-insulator；SOI)基底。一般而言，SOI基底包含一層的半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、絕緣層上有矽鍺(silicon germanium on insulator；SGOI)或其組合。在一個替代實施例中，基底202是基於諸如玻璃纖維強化樹脂芯的絕緣芯。一種實例芯材料為玻璃纖維樹脂，諸如FR4。芯材料的替代物包含雙馬來亞醯胺-三嗪(bismaleimide-triazine；BT)樹脂，或可替代地包含其他印刷電路板(PCB)材料或膜層。諸如味之素累積膜(Ajinomoto build-up film；ABF)的累積膜或其他層壓物可用作基底202。
基底202可包含多個主動元件及多個被動元件(未示出)。可使用諸如電晶體、電容器、電阻器、上述組合以及類似者的廣泛多種元件來產生設計第二封裝體組件200的結構性及功能性要求。可使用任何合適的方法來形成元件。
基底202亦可包含多個金屬化層(未示出)以及多個導 通孔206。金屬化層可形成於主動元件及被動元件上方，且經設計以連接各種元件從而形成功能性電路。金屬化層可由介電質(例如，低介電常數介電材料)與導電材料(例如，銅)的交替層形成，其中導通孔206使導電材料層互連且可經由任何合適的製程(諸如沈積、鑲嵌、雙鑲嵌、或類似者)來形成。在一些實施例中，基底202實質上不含主動元件及被動元件。
基底202可在基底202的第一側上具有多個接合墊208以耦接至堆疊晶粒204A及堆疊晶粒204B，且在基底202的第二側上具有多個接合墊210以耦接至導電連接件160，所述第二側與基底202的第一側相對。在一些實施例中，透過形成多個凹槽在基底202的第一側及第二側上的介電層中來形成接合墊208及接合墊210。上述凹槽可被形成以允許將接合墊208及接合墊210嵌入至介電層中。在其他實施例中，由於接合墊208及接合墊210可形成於介電層上，故省略凹槽。在一些實施例中，接合墊208及接合墊210包含由銅、鈦、鎳、金、鈀、類似者或其組合製成的薄晶種層(thin seed layer)。接合墊208及接合墊210的導電材料可沈積於薄晶種層上方。導電材料可透過電化學鍍覆製程、無電鍍覆製程、CVD、原子層沈積(atomic layer deposition；ALD)、PVD、類似者或其組合來形成。在一些實施例中，接合墊208及接合墊210的導電材料為銅、鎢、鋁、銀、金、類似者或其組合。
在一些實施例中，接合墊208及接合墊210為包含三個導電材料層(諸如，鈦層、銅層以及鎳層)的凸塊下金屬。可利用材料及膜層的其他配置，諸如鉻/鉻銅合金/銅/金的配置、鈦/鈦鎢/銅的配置或銅/鎳/金的配置，來形成接合墊208及接合墊210。可 用於接合墊208及接合墊210的任何合適的材料或材料層全部意欲包含於當前申請案的範疇內。在一些實施例中，導通孔206延伸穿過基底202且將接合墊208中的至少一者耦接至接合墊210中的至少一者。
在所示出的實施例中，堆疊晶粒204A及堆疊晶粒204B透過線接合(wire bond)212耦接至基底202，但可使用其他連接件，諸如導電凸塊。在一些實施例中，堆疊晶粒204A及堆疊晶粒204B為堆疊記憶體晶粒。舉例而言，堆疊晶粒204A及堆疊晶粒204B可為諸如低功率(low-power；LP)雙資料速率(double data rate；DDR)記憶體模組的記憶體晶粒，諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似記憶體模組。
堆疊晶粒204A及堆疊晶粒204B以及線接合212可透過模製材料214包封。可例如使用壓縮模製將模製材料214模製於堆疊晶粒204A、204B以及線接合212上。在一些實施例中，模製材料214為模製化合物、聚合物、環氧樹脂、氧化矽填料材料、類似者或其組合。可執行固化製程以固化模製材料214；固化製程可為熱固化、UV固化、類似者，或其組合。
在一些實施例中，堆疊晶粒204A、204B以及線接合212掩埋於模製材料214中，且在固化模製材料214之後，執行諸如研磨的平面化步驟以移除模製材料214的過量部分且為第二封裝體組件200提供實質上平坦的表面。
在形成第二封裝體組件200之後，第二封裝體組件200借助於導電連接件160、接合墊208及接合墊210以及背側重佈線結構106的金屬化圖案機械地接合且電性接合至第一封裝體組件 100。在一些實施例中，堆疊晶粒204A及堆疊晶粒204B可經由線接合212、接合墊208及接合墊210、導通孔206、導電連接件160、背側重佈線結構106、穿孔116以及前側重佈線結構140耦接至積體電路晶粒50。
在一些實施例中，阻焊劑形成於與堆疊晶粒204A及堆疊晶粒204B相對的基底202的側面上。導電連接件160可安置於阻焊劑中的多個開口中以電性耦接且機械地耦接至基底202中的導電特徵(例如，接合墊210)。阻焊劑可用於保護基底202的區域不受外部損害。
在一些實施例中，導電連接件160具有環氧樹脂焊劑，所述環氧樹脂焊劑在其與在第二封裝體組件200附接至第一封裝體組件100之後剩餘的環氧樹脂焊劑的環氧樹脂部分中的至少一些進行回焊之前形成於所述導電連接件160上。
在一些實施例中，底部填充物可形成於第一封裝體組件100與第二封裝體組件200之間，從而環繞導電連接件160。底部填充物可減小應力且保護由導電連接件160的回焊所產生的多個接合點。底部填充物可在第二封裝體組件200附接之後透過毛細流動製程(capillary flow process)來形成，或可在第二封裝體組件200附接之前透過合適的沈積方法來形成。在形成環氧樹脂焊劑的實施例中，環氧樹脂焊劑可充當底部填充物。
在圖16中，透過沿例如第一封裝區100A與第二封裝區100B之間的切割道區鋸割來執行單體化製程。所述鋸割將第一封裝區100A自第二封裝區100B單體化。所得單體化元件堆疊來自第一封裝區100A或第二封裝區100B中的一者。在所示出的實施 例中，在第二封裝體組件200耦接至第一封裝體組件100之後執行單體化製程。在其他實施例中，在第二封裝體組件200耦接至第一封裝體組件100之前執行單體化製程，諸如在剝離載體基底102且形成導電連接件160之後。
隨後使用導電連接件158將自第一封裝體組件100單體化的每一積體電路封裝體安裝至封裝基底300。封裝基底300包含基底芯302及基底芯302上方的多個接合墊304。基底芯302可由諸如矽、鍺、鑽石或類似者的半導體材料製成。或者，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷鎵、磷化銦鎵、上述組合以及類似者。另外，基底芯302可為SOI基底。一般而言，SOI基底包含諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合的半導體材料層。在一個替代實施例中，基底芯302是基於諸如玻璃纖維強化樹脂芯的絕緣芯。一種實例芯材料為玻璃纖維樹脂，諸如FR4。芯材料的替代物包含雙馬來亞醯胺-三嗪(BT)樹脂，或可替代地包含其他PCB材料或膜層。諸如ABF的累積膜或其他層壓物可作為基底芯302。
基底芯302可包含多個主動元件及多個被動元件(未示出)。如於本領域具有通常知識者將認識到，諸如電晶體、電容器、電阻器、上述組合以及類似者的多種元件可用以產生設計元件堆疊的結構性及功能性要求。可使用任何合適的方法來形成元件。
基底芯302亦可包含多個金屬化層及多個通孔(未示出)，其中接合墊304實體耦接及/或電性耦接至金屬化層及通孔。金屬化層可形成於主動元件及被動元件上方，且經設計以連接各種元件從而形成功能性電路。金屬化層可由介電質(例如，低介電常數 介電材料)與導電材料(例如，銅)的交替層形成，其中通孔使導電材料層互連且可經由任何合適的製程(諸如沈積、鑲嵌、雙鑲嵌、或類似者)來形成。在一些實施例中，基底芯302實質上不含主動元件及被動元件。
在一些實施例中，回焊導電連接件158以將第一封裝體組件100附接至接合墊304。導電連接件158將封裝基底300(包含基底芯302中的金屬化層)電性耦接及/或實體耦接至第一封裝體組件100。在一些實施例中，阻焊劑306形成於基底芯302上。導電連接件158可安置於阻焊劑306的多個開口中以電性耦接且機械地耦接至接合墊304。阻焊劑306可用於保護基底202的區域不受外部損害。
導電連接件158可具有環氧樹脂焊劑，所述環氧樹脂焊劑在其與第一封裝體組件100附接至封裝基底300之後剩餘的環氧樹脂焊劑的環氧樹脂部分中的至少一些進行回焊之前形成於所述導電連接件158上。此剩餘環氧基部分可充當底部填充物以減小應力且保護由回焊導電連接件158而產生的多個接合點。在一些實施例中，底部填充物308可形成於第一封裝體組件100與封裝基底300之間，且環繞導電連接件158。底部填充物308可在附接第一封裝體組件100之後透過毛細流動製程形成或可在附接第一封裝體組件100之前透過合適的沈積方法形成。
在一些實施例中，亦可將多個被動元件(例如，表面安裝元件(surface mount devices；SMDs)，未示出)附接至第一封裝體組件100(例如，凸塊下金屬156)或附接至封裝基底300(例如，接合墊304)。舉例而言，被動元件可接合至與導電連接件158相 同的第一封裝體組件100的表面或封裝基底300的表面。被動元件可在將第一封裝體組件100安裝於封裝基底300上之前附接至第一封裝體組件100，或可在將第一封裝體組件100安裝於封裝基底300上之前或之後附接至封裝基底300。
應瞭解，第一封裝體組件100可實施於其他元件堆疊中。舉例而言，示出一個PoP結構，但其第一封裝體組件100亦可實施於倒裝晶片球柵陣列(Flip Chip Ball Grid Array；FCBGA)封裝體中。在此類實施例中，第一封裝體組件100安裝至諸如封裝基底300的基底，但省略第二封裝體組件200。替代地，可將封蓋或散熱器附接至第一封裝體組件100。當省略第二封裝體組件200時，亦可省略背側重佈線結構106及穿孔116。
其他特徵及製程亦可被包含。舉例而言，可包含測試結構以幫助對3D封裝或3DIC元件的驗證測試。測試結構可包含例如形成於重佈線層中或基底上的測試墊，從而允許測試3D封裝或3DIC、使用探針及/或探針卡及其類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合併有對良好晶粒的中間驗證的測試方法使用，以提高良率及降低成本。
圖17示出根據一些其他實施例的第一封裝體組件100的橫截面視圖。此實施例與圖12的實施例類似，但省略穿孔116及背側重佈線結構106。此實施例的第一封裝體組件100可在後續處理中單體化且用以實施元件堆疊，諸如關於圖15及圖16所描述的元件堆疊。
圖18示出根據一些其他實施例的第一封裝體組件100的橫截面視圖。在此實施例中，前側重佈線結構140具有精細特徵 部分140A及粗糙特徵部分140B。重佈線結構140的精細特徵部分140A包含介電層142、介電層146、介電層150以及介電層154，以及金屬化圖案144、金屬化圖案148以及金屬化圖案152。重佈線結構140的粗糙特徵部分140B包含介電層162、介電層166以及介電層170，以及金屬化圖案164、金屬化圖案167以及金屬化圖案168。重佈線結構140的精細特徵部分140A及粗糙特徵部分140B包含不同大小的金屬化圖案及介電層。舉例而言，介電層142、介電層146、介電層150以及介電層154形成為比介電層162、介電層166以及介電層170具有更小的厚度，且金屬化圖案144、金屬化圖案148以及金屬化圖案152形成為比金屬化圖案164、金屬化圖案167以及金屬化圖案168具有更小的厚度。介電層162、介電層166以及介電層170可以與介電層142、介電層146、介電層150以及介電層154類似的方式形成，且可由與介電層142、介電層146、介電層150以及介電層154類似的材料形成。或者，介電層162、介電層166以及介電層170可由與介電層142、介電層146、介電層150以及介電層154不同的材料形成。在一些實施例中，介電層142、介電層146、介電層150以及介電層154包括諸如PBO、聚醯亞胺、BCB或類似者的感光性材料，且介電層162、介電層166以及介電層170包括模製化合物、環氧樹脂或類似者。此實施例的第一封裝體組件100可在後續處理中單體化且用以實施元件堆疊，諸如關於圖15及圖16所描述的元件堆疊。
圖19示出根據一些其他實施例的第一封裝體組件100的橫截面視圖。此實施例與圖18的實施例類似，但省略穿孔116及 背側重佈線結構106。此實施例的第一封裝體組件100可在後續處理中單體化且用以實施元件堆疊，諸如關於圖15及圖16所描述的元件堆疊。
圖20示出根據一些其他實施例的第一封裝體組件100的橫截面視圖。在此實施例中，前側重佈線結構140包含金屬化圖案172、金屬化圖案174、金屬化圖案176以及金屬化圖案178，所述結構使用與金屬化圖案144、金屬化圖案148以及金屬化圖案152不同的技術形成。金屬化圖案172僅包含延伸穿過介電層142的多個通孔部分，且不包含沿著介電層142的主表面延伸的多個導線部分。金屬化圖案174及金屬化圖案176包含分別沿介電層142及介電層146的主表面延伸的多個導線部分，且亦包含分別延伸穿過介電層146及介電層150的多個通孔部分。金屬化圖案174及金屬化圖案176中的每一者的形成可包含使用多個罩幕。舉例而言，第一罩幕可用以鍍覆導線部分，且第二罩幕可用以鍍覆通孔部分。金屬化圖案178僅包含沿介電層154的主表面延伸的多個導線部分，且不包含延伸穿過介電層150的通孔部分。凸塊下金屬156形成為延伸穿過介電層154以耦接金屬化圖案178。此實施例的第一封裝體組件100可在後續處理中單體化且用以實施元件堆疊，諸如關於圖15及圖16所描述的元件堆疊。
圖21示出根據一些其他實施例的第一封裝體組件100的橫截面視圖。此實施例與圖20的實施例類似，但省略穿孔116及背側重佈線結構106。此實施例的第一封裝體組件100可在後續處理中單體化且用以實施元件堆疊，諸如關於圖15及圖16所描述的元件堆疊。
多種實施例可達成多個優點。在形成介電層78之前自晶粒連接件60移除可回焊連接件70可防止焊料在介電層78的固化製程期間潤濕。另外，透過蝕刻製程74代替透過CMP移除可回焊連接件70可有助於減少積體電路晶粒50中焊料殘渣的量。
在一個實施例中，一種方法包含：接收積體電路晶粒，所述積體電路晶粒包含：接觸墊，位於半導體基底上；鈍化層，位於所述接觸墊及所述半導體基底上；晶粒連接件，延伸穿過所述鈍化層，所述晶粒連接件實體耦接且電性耦接至所述接觸墊，所述晶粒連接件包含第一導電材料，所述第一導電材料為具有第一酸軟硬指數的路易斯酸；以及可回焊連接件，位於所述晶粒連接件上，所述可回焊連接件包含第二導電材料，所述第二導電材料為具有第二酸軟硬指數的路易斯酸；以及使用蝕刻溶液蝕刻所述可回焊連接件及所述晶粒連接件，所述蝕刻溶液包含用於所述第一導電材料的防護劑及用於所述第二導電材料的蝕刻劑，所述防護劑為唑，所述唑為具有第一配位體軟硬指數的路易斯鹼，其中所述第一酸軟硬指數與所述第一配位體軟硬指數的乘積為正值，且所述第二酸軟硬指數與所述第一配位體軟硬指數的乘積為負值。
在所述方法的一些實施例中，所述唑為含有多個氮原子的五員雜環化合物。在所述方法的一些實施例中，所述五員雜環化合物為包含甲基吡唑的吡唑化合物。在所述方法的一些實施例中，所述五員雜環化合物為包含甲基咪唑的咪唑化合物。在所述方法的一些實施例中，所述五員雜環化合物為包含苯并三唑的三唑化合物。在所述方法的一些實施例中，所述五員雜環化合物為包含苯基四唑或苯基-巰基四唑的四唑化合物。在所述方法的一些實施例 中，所述五員雜環化合物為包含五唑(HN5)的五唑化合物。在所述方法的一些實施例中，所述晶粒連接件包含：第一導電層，包含所述第一導電材料；及第二導電層，位於第一導電層上，第二導電層包含第三導電材料，第三導電材料為具有第三酸軟硬指數的路易斯酸，其中所述第三酸軟硬指數與所述第一配位體軟硬指數的乘積為負值，其中蝕刻所述可回焊連接件將所述第一導電層的第一寬度減小0.05%至30%範圍內的量，且其中蝕刻所述可回焊連接件並不減小所述第二導電層的第二寬度。在一些實施例中，所述方法更包含：在蝕刻所述可回焊連接件及所述晶粒連接件之前，測試所述積體電路晶粒。在一些實施例中，所述方法更包含：在蝕刻所述可回焊連接件及所述晶粒連接件之後，在所述晶粒連接件及所述鈍化層上沈積介電層。
在一個實施例中，一種方法包含：在半導體基底上形成接觸墊；在所述接觸墊及所述半導體基底上沈積鈍化層；於所述鈍化層中圖案化暴露出所述接觸墊的開口；在所述開口中及所述接觸墊上鍍覆晶粒連接件，所述晶粒連接件包含第一導電材料；在所述晶粒連接件上回焊可回焊連接件；以及使用蝕刻溶液蝕刻所述可回焊連接件及所述晶粒連接件以移除所述可回焊連接件，所述蝕刻溶液包含蝕刻劑及防護劑，所述防護劑為含有用於接合至所述第一導電材料的多個活性部位的五員雜環化合物。
在所述方法的一些實施例中，蝕刻所述可回焊連接件及所述晶粒連接件包含將所述可回焊連接件及所述晶粒連接件浸入所述蝕刻溶液的浴槽中。在所述方法的一些實施例中，蝕刻所述可回焊連接件及所述晶粒連接件包含將所述蝕刻溶液噴施於所述可 回焊連接件及所述晶粒連接件上。在所述方法的一些實施例中，噴施所述蝕刻溶液包含在所述蝕刻溶液以0.2升/分鐘至2升/分鐘範圍內的流動速率流動於所述半導體基底上方時以100轉/分鐘至3000轉/分鐘範圍內的速度旋轉所述半導體基底。在所述方法的一些實施例中，蝕刻所述可回焊連接件及所述晶粒連接件包含在5℃至50℃範圍內的溫度下蝕刻所述可回焊連接件及所述晶粒連接件達0.1分鐘至120分鐘範圍內的持續時間。在所述方法的一些實施例中，所述蝕刻溶液包含濃度為0.0001%至2%範圍內的所述防護劑、濃度在0.1%至20%範圍內的所述蝕刻劑以及濃度在0.5%至50%範圍內的溶劑。在所述方法的一些實施例中，所述蝕刻劑為鐵(III)或銅(II)，且所述溶劑為硝酸或硫酸。
在一個實施例中，一種元件包含：半導體基底；接觸墊，位於所述半導體基底上；鈍化層，位於所述接觸墊及所述半導體基底上；晶粒連接件，延伸穿過所述鈍化層，所述晶粒連接件實體耦接且電性耦接至所述接觸墊，所述晶粒連接件包含第一導電材料，所述第一導電材料為具有第一酸軟硬指數的路易斯酸；介電層，位於所述晶粒連接件及所述鈍化層上；以及保護層，安置於所述介電層與所述晶粒連接件之間，所述保護層環繞所述晶粒連接件，所述保護層包含所述第一導電材料與唑的配位錯合物，所述唑為具有第一配位體軟硬指數的路易斯鹼，其中所述第一酸軟硬指數與所述第一配位體軟硬指數的乘積為正值。
在所述元件的一些實施例中，所述晶粒連接件具有包含所述第一導電材料及所述配位錯合物的化合物的外部區及不包含配位錯合物的內部區。在所述元件的一些實施例中，所述保護層具 有1埃至100埃範圍內的厚度。
前文概述若干實施例的特徵，以使得所屬領域中具通常知識者可更佳地理解本揭露的態樣。所屬領域中具通常知識者應理解，其可易於使用本揭露作為設計或修改用於實現本文中所引入實施例的相同目的及/或達成相同優勢的其他方法及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
3:區域
54:內連線結構
56:接觸墊
58:鈍化層
60:晶粒連接件
64:晶種層
64A:鈦層
64B:銅層
68A:第一導電材料層
68B:第二導電材料層
68C:第三導電材料層
74:蝕刻製程
76:保護層
R1、R2:減小量
T6、T7:厚度
W2:寬度

Claims (10)

  1. 一種積體電路封裝體的製造方法，包括：接收積體電路晶粒，所述積體電路晶粒包括：接觸墊，位於半導體基底上；鈍化層，位於所述接觸墊及所述半導體基底上；晶粒連接件，延伸穿過所述鈍化層，所述晶粒連接件實體耦接且電性耦接至所述接觸墊，所述晶粒連接件包括第一導電材料，所述第一導電材料為具有第一酸軟硬指數的路易斯酸；以及可回焊連接件，位於所述晶粒連接件上，所述可回焊連接件包括第二導電材料，所述第二導電材料為具有第二酸軟硬指數的路易斯酸；以及使用蝕刻溶液蝕刻所述可回焊連接件及所述晶粒連接件，所述蝕刻溶液包括用於所述第一導電材料的防護劑及用於所述第二導電材料的蝕刻劑，所述防護劑為唑，所述唑為具有第一配位體軟硬指數的路易斯鹼，其中所述第一酸軟硬指數與所述第一配位體軟硬指數的乘積為正值，且所述第二酸軟硬指數與所述第一配位體軟硬指數的乘積為負值。
  2. 如申請專利範圍第1項所述的製造方法，其中所述唑為含有多個氮原子的五員雜環化合物。
  3. 如申請專利範圍第1項所述的製造方法，其中所述晶粒連接件包括：第一導電層，包括所述第一導電材料；以及 第二導電層，位於所述第一導電層上，所述第二導電層包括第三導電材料，所述第三導電材料為具有第三酸軟硬指數的路易斯酸，其中所述第三酸軟硬指數與所述第一配位體軟硬指數的乘積為負值，其中所述蝕刻所述可回焊連接件將所述第一導電層的第一寬度減小0.05%至30%範圍內的量，以及其中所述蝕刻所述可回焊連接件並不減小所述第二導電層的第二寬度。
  4. 如申請專利範圍第1項所述的製造方法，更包括：在蝕刻所述可回焊連接件與所述晶粒連接件之前，測試所述積體電路晶粒。
  5. 如申請專利範圍第1項所述的製造方法，更包括：在蝕刻所述可回焊連接件與所述晶粒連接件之後，在所述晶粒連接件及所述鈍化層上沈積介電層。
  6. 一種積體電路封裝體的製造方法，包括：在半導體基底上形成接觸墊；在所述接觸墊及所述半導體基底上沈積鈍化層；在所述鈍化層中圖案化暴露出所述接觸墊的開口；在所述開口中及在所述接觸墊上鍍覆晶粒連接件，所述晶粒連接件包括第一導電材料；在所述晶粒連接件上回焊可回焊連接件；以及使用蝕刻溶液蝕刻所述可回焊連接件及所述晶粒連接件以移除所述可回焊連接件，所述蝕刻溶液包括蝕刻劑及防護劑，所述防 護劑為含有用於接合至所述第一導電材料的多個活性部位的五員雜環化合物。
  7. 如申請專利範圍第6項所述的製造方法，其中蝕刻所述可回焊連接件及所述晶粒連接件包括將所述可回焊連接件及所述晶粒連接件浸入於所述蝕刻溶液的浴槽中。
  8. 如申請專利範圍第6項所述的製造方法，其中蝕刻所述可回焊連接件及所述晶粒連接件包括將所述蝕刻溶液噴施於所述可回焊連接件及所述晶粒連接件上。
  9. 一種積體電路封裝體，包括：半導體基底；接觸墊，位於所述半導體基底上；鈍化層，位於所述接觸墊及所述半導體基底上；晶粒連接件，延伸穿過所述鈍化層，所述晶粒連接件實體耦接且電性耦接至所述接觸墊，所述晶粒連接件包括第一導電材料，所述第一導電材料為具有第一酸軟硬指數的路易斯酸；介電層，位於所述晶粒連接件及所述鈍化層上；以及保護層，安置於所述介電層與所述晶粒連接件之間，所述保護層環繞所述晶粒連接件，所述保護層包括所述第一導電材料與唑的配位錯合物，所述唑為具有第一配位體軟硬指數的路易斯鹼，其中所述第一酸軟硬指數與所述第一配位體軟硬指數的乘積為正值。
  10. 如申請專利範圍第9項所述的積體電路封裝體，其中所述晶粒連接件具有包括所述第一導電材料與所述配位錯合物的化合物的外部區以及不含所述配位錯合物的內部區。
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