TWI726885B - Audio device and multimedia device including audio device - Google Patents
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Abstract
Description
根據例示性實施例的設備及方法是有關於一種電子裝置,且更具體而言,是有關於一種音訊裝置及包含所述音訊裝置的多媒體裝置。 The apparatus and method according to the exemplary embodiments relate to an electronic device, and more specifically, to an audio device and a multimedia device including the audio device.
智慧型電話、智慧型平板電腦(smart pad)等多媒體裝置能夠產生並播放視訊資料及音訊資料。音訊資料可經由揚聲器來播放,或者可經由個人播放單元(例如,耳機或頭戴式耳機)來播放。多媒體裝置在未連接有個人播放單元時一般經由揚聲器來播放音訊資料,而在有連接個人播放單元時則經由個人播放單元來播放音訊資料。針對此類功能,多媒體裝置可包括插頭偵測電路,所述插頭偵測電路用於偵測個人播放單元的插頭是否插入插頭槽中。當插頭與插頭槽耦接或與所述插頭槽分離時,可能會產生各種雜訊,而這些雜訊可能會無意地經由個人播放單元而播放,進而給使用者造成不便。因此,為進一步方便使用者,需要一種在插頭與插頭槽耦接或與插頭槽分離時可用於防止產生無意 的雜訊的單元或方法。 Multimedia devices such as smart phones and smart pads can generate and play video data and audio data. The audio data can be played via speakers, or can be played via a personal playback unit (for example, earphones or headphones). When a multimedia device is not connected to a personal playback unit, it generally plays audio data through a speaker, and when a personal playback unit is connected, it plays audio data through the personal playback unit. For such functions, the multimedia device may include a plug detection circuit for detecting whether the plug of the personal playback unit is inserted into the plug slot. When the plug is coupled to the plug slot or separated from the plug slot, various noises may be generated, and these noises may be unintentionally played through the personal playback unit, thereby causing inconvenience to the user. Therefore, in order to further facilitate the user, there is a need for a plug that can be used to prevent unintentional The unit or method of the noise.
例示性實施例提供一種用於提高使用者方便性(user convenience)的音訊裝置及包含此音訊裝置的多媒體裝置。 Exemplary embodiments provide an audio device for improving user convenience and a multimedia device including the audio device.
根據例示性實施例的態樣,提供一種音訊裝置,此音訊裝置包括:音訊編解碼器電路,連接至第一通道電極、第二通道電極及麥克風偵測電極;以及插頭偵測電路,連接至第一通道偵測電極、接地偵測電極及所述麥克風偵測電極,且因應於所述第一通道偵測電極的電壓及所述接地偵測電極的電壓對應於接地電壓,所述插頭偵測電路偵測插頭的插入,而對所述接地偵測電極施加所述接地電壓,並對所述麥克風偵測電極施加偏置電壓。 According to an aspect of an exemplary embodiment, an audio device is provided. The audio device includes: an audio codec circuit connected to a first channel electrode, a second channel electrode, and a microphone detection electrode; and a plug detection circuit connected to The first channel detection electrode, the ground detection electrode, and the microphone detection electrode, and in response to the voltage of the first channel detection electrode and the voltage of the ground detection electrode corresponding to the ground voltage, the plug detection The detection circuit detects the insertion of the plug, applies the ground voltage to the ground detection electrode, and applies a bias voltage to the microphone detection electrode.
根據另一例示性實施例的態樣,提供一種多媒體裝置,所述多媒體裝置包括:應用處理器;隨機存取記憶體;儲存裝置;視訊編解碼器,用以藉由所述應用處理器的控制而處理視訊資料;顯示器,用以藉由所述視訊編解碼器的控制而顯示視訊訊號;插頭槽,供外部插頭插入;音訊編解碼器,連接至所述插頭槽中的第一通道電極、第二通道電極及麥克風偵測電極,並用以藉由所述應用處理器的控制而處理音訊資料;以及插頭偵測電路,連接至所述插頭槽中的第一通道偵測電極、接地偵測電極及所述麥克風偵測電極,且因應於所述第一通道偵測電極的電壓及所述接地偵測電極的電壓對應於接地電壓,所述插頭偵測電路偵測所述外部插頭插入所述插頭槽中,而對所述接地偵測電極施加所述接 地電壓,並對所述麥克風偵測電極施加偏置電壓。 According to an aspect of another exemplary embodiment, a multimedia device is provided. The multimedia device includes: an application processor; a random access memory; a storage device; Control and process video data; display for displaying video signals through the control of the video codec; plug slot for external plug insertion; audio codec connected to the first channel electrode in the plug slot , The second channel electrode and the microphone detection electrode are used to process audio data under the control of the application processor; and the plug detection circuit is connected to the first channel detection electrode and the ground detection electrode in the plug slot The measuring electrode and the microphone detection electrode, and in response to the voltage of the first channel detection electrode and the voltage of the ground detection electrode corresponding to the ground voltage, the plug detection circuit detects the insertion of the external plug In the plug slot, and applying the connection to the ground detection electrode Ground voltage, and apply a bias voltage to the microphone detection electrode.
根據又一例示性實施例的態樣,提供一種音訊裝置,所述音訊裝置包括:邏輯閘電路,用以因應於插頭槽中的第一通道偵測電極的電壓及接地偵測電極的電壓為接地電壓而輸出第一位凖訊號,並因應於所述插頭槽中所述第一通道偵測電極的所述電壓及所述接地偵測電極的所述電壓中的至少一者為所述接地電壓而輸出第二位凖訊號;電晶體,用以因應於所述邏輯閘電路輸出所述第一位凖訊號而將所述接地偵測電極連接至被供應所述接地電壓的接地節點;以及偏置電壓產生器,用以因應於所述邏輯閘電路輸出所述第一位凖訊號而產生偏置電壓並將所述偏置電壓施加至麥克風偵測電極,並因應於所述邏輯閘電路輸出所述第二位凖訊號而將所述接地電壓施加至所述麥克風偵測電極。 According to another aspect of the exemplary embodiment, an audio device is provided. The audio device includes a logic gate circuit for responding to the voltage of the first channel detection electrode and the ground detection electrode in the plug slot. Ground voltage to output a first bit signal, and at least one of the voltage of the first channel detection electrode and the voltage of the ground detection electrode in the plug slot is the ground Voltage to output a second bit signal; a transistor for connecting the ground detection electrode to the ground node supplied with the ground voltage in response to the logic gate circuit outputting the first bit signal; and A bias voltage generator for generating a bias voltage in response to the first bit signal output from the logic gate circuit and applying the bias voltage to the microphone detection electrode in response to the logic gate circuit The second bit signal is output and the ground voltage is applied to the microphone detection electrode.
根據又一例示性實施例的態樣,提供一種偵測電路,所述偵測電路包括:或邏輯閘,用以根據第一通道偵測電極電壓及接地偵測電極電壓而產生邏輯訊號,所述邏輯訊號為高電壓及低電壓中的一者;第一電晶體,用以根據所述邏輯訊號而選擇性地對麥克風偵測電極施加接地訊號;以及第二電晶體,用以根據所述邏輯訊號而選擇性地對所述接地偵測電極施加所述接地訊號。 According to another aspect of the exemplary embodiment, a detection circuit is provided. The detection circuit includes: an OR logic gate for generating a logic signal according to the first channel detection electrode voltage and the ground detection electrode voltage, so The logic signal is one of a high voltage and a low voltage; a first transistor for selectively applying a ground signal to the microphone detection electrode according to the logic signal; and a second transistor for applying a ground signal to the microphone detection electrode according to the logic signal; The logic signal selectively applies the ground signal to the ground detection electrode.
10:多媒體裝置 10: Multimedia device
11:應用處理器 11: Application processor
12:隨機存取記憶體 12: Random access memory
13:儲存裝置 13: storage device
14:電力管理電路 14: Power management circuit
15:電源供應器 15: power supply
16:視訊編解碼器 16: Video codec
17:顯示器 17: display
18:照相機 18: camera
19:音訊編解碼器 19: Audio codec
20:揚聲器 20: speaker
21:麥克風 21: Microphone
22:數據機 22: Modem
23:天線 23: Antenna
100、100a、100b、100c:插頭偵測器 100, 100a, 100b, 100c: plug detector
200:插頭槽 200: plug slot
210:主體 210: main body
220:第一通道電極 220: first channel electrode
225:第一通道偵測電極 225: The first channel detection electrode
230:第二通道電極 230: second channel electrode
240:接地電極 240: Ground electrode
245:接地偵測電極 245: Ground detection electrode
255:麥克風偵測電極 255: Microphone detection electrode
300:插頭 300: plug
310:第一極 310: first pole
315:第一絕緣體 315: first insulator
320:第二極 320: second pole
325:第二絕緣體 325: second insulator
330:第三極 330: third pole
335:第三絕緣體 335: third insulator
340:第四極 340: The Fourth Pole
400:插頭 400: plug
410:第一極 410: first pole
415:第一絕緣體 415: first insulator
420:第二極 420: second pole
425:第二絕緣體 425: second insulator
430:第三極 430: third pole
BG:偏置電壓產生電路 BG: Bias voltage generating circuit
BIAS:偏置電壓 BIAS: Bias voltage
CP:比較器/電流路徑 CP: Comparator/current path
CP2:第二比較器 CP2: second comparator
EN:致能訊號 EN: Enabling signal
OR:邏輯閘電路 OR: logic gate circuit
OT:輸出端 OT: output terminal
OUT:輸出訊號 OUT: output signal
PG:脈波產生電路 PG: Pulse wave generating circuit
PUR1:第一上拉電阻 PUR1: first pull-up resistor
PUR2:第二上拉電阻 PUR2: second pull-up resistor
R1:第一電阻 R1: first resistance
R2:第二電阻 R2: second resistor
R3:第三電阻 R3: third resistor
R4:第四電阻 R4: Fourth resistor
R5:第五電阻 R5: Fifth resistor
S110、S120、S130、S140、S150:步驟 S110, S120, S130, S140, S150: steps
S210、S220、S230、S240、S250:步驟 S210, S220, S230, S240, S250: steps
SG:訊號產生器 SG: signal generator
T1:第一時間點 T1: the first point in time
T2:第二時間點 T2: second time point
T3:第三時間點 T3: The third time point
T4:第四時間點 T4: The fourth time point
T5:第五時間點 T5: Fifth time point
T6:第六時間點 T6: The sixth time point
T7:第七時間點 T7: Seventh time point
TR1:第一電晶體 TR1: The first transistor
TR2:第二電晶體 TR2: second transistor
TR3:第三電晶體 TR3: third transistor
V1:第一電壓 V1: first voltage
VDD:電源電壓 VDD: power supply voltage
VSS:接地電壓 VSS: Ground voltage
VREF:參考電壓 VREF: Reference voltage
藉由結合附圖閱讀以下說明,以上及其他目的及特徵將變得顯而易見,在附圖中: The above and other purposes and features will become apparent by reading the following description in conjunction with the accompanying drawings. In the accompanying drawings:
圖1是說明根據例示性實施例的多媒體裝置的方塊圖。 FIG. 1 is a block diagram illustrating a multimedia device according to an exemplary embodiment.
圖2是根據例示性實施例所繪示的外部個人播放單元插入插頭槽的插頭的實例。 Fig. 2 is an example of a plug of an external personal playback unit inserted into a plug slot according to an exemplary embodiment.
圖3是根據例示性實施例所繪示的外部個人播放單元插入插頭槽的插頭的實例。 Fig. 3 is an example of a plug of an external personal playback unit inserted into a plug slot according to an exemplary embodiment.
圖4是根據例示性實施例所繪示的插頭偵測器的電路圖。 FIG. 4 is a circuit diagram of a plug detector drawn according to an exemplary embodiment.
圖5是根據例示性實施例所繪示的偵測插頭是否插入插頭槽的方法流程圖。 FIG. 5 is a flowchart of a method for detecting whether a plug is inserted into a plug slot according to an exemplary embodiment.
圖6是根據例示性實施例所繪示的插入插頭槽或與所述插頭槽分離的3極插頭(3-pole jack)的連接。 Fig. 6 illustrates the connection of a 3-pole jack inserted into or separated from the plug slot according to an exemplary embodiment.
圖7是根據例示性實施例所繪示的插頭偵測器中所涉及的電壓變化的時序圖。 FIG. 7 is a timing diagram of voltage changes involved in the plug detector according to an exemplary embodiment.
圖8是根據例示性實施例所繪示的插頭偵測器的應用的電路圖。 FIG. 8 is a circuit diagram of an application of a plug detector according to an exemplary embodiment.
圖9是根據例示性實施例所繪示的一種執行插頭插入的方法的流程圖。 Fig. 9 is a flowchart of a method for performing plug insertion according to an exemplary embodiment.
圖10是根據例示性實施例所繪示的插頭偵測器中所涉及的電壓變化的時序圖。 FIG. 10 is a timing diagram of voltage changes involved in the plug detector according to an exemplary embodiment.
圖11是根據例示性實施例所繪示的插頭偵測器的應用的流程圖。 FIG. 11 is a flowchart of the application of the plug detector according to an exemplary embodiment.
在下文中,將結合附圖來闡述例示性實施例。提供該些例示性實施例是為了使此揭露內容透徹及完整,並向熟習此項技 術者充分傳達本發明概念的範圍。因此,儘管本文中闡述例示性實施例,然而所述揭露內容應被視為包含各種潤飾、等效形式及/或替代形式。就圖示說明而言,相同的參考編號指代相同的元件。 Hereinafter, exemplary embodiments will be explained with reference to the accompanying drawings. These exemplary embodiments are provided to make this disclosure content thorough and complete, and to familiarize yourself with this technique. The operator fully conveys the scope of the concept of the present invention. Therefore, although exemplary embodiments are described herein, the disclosed content should be regarded as including various modifications, equivalent forms, and/or alternative forms. For illustration purposes, the same reference numbers refer to the same elements.
本文所用術語僅用於闡述例示性實施例,而並非旨在限制本發明概念。當此說明書中使用用語「包括」時,是指所陳述的特徵、整數、步驟、操作、元件及/或組件的存在,但不排除一或多個其他特徵、整數、步驟、操作、元件、組件及/或其群組的存在或附加。 The terms used herein are only used to illustrate exemplary embodiments, and are not intended to limit the concept of the present invention. When the term "including" is used in this specification, it refers to the existence of the stated features, integers, steps, operations, elements and/or components, but does not exclude one or more other features, integers, steps, operations, elements, The presence or addition of components and/or groups thereof.
此外,應理解,儘管本文中可能使用「第一」、「第二」等用語來闡述各種元件、組件、區、層及/或區段,然而這些元件、組件、區、層及/或區段不應受這些用語限制。因此,在不背離本發明概念教示內容的條件下,以下所論述的第一元件、組件、區、層或區段可被稱為第二元件、組件、區、層或區段。 In addition, it should be understood that although terms such as "first" and "second" may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or regions The paragraph should not be restricted by these terms. Therefore, the first element, component, region, layer or section discussed below may be referred to as a second element, component, region, layer or section without departing from the concept and teaching content of the present invention.
除非另外定義,否則本文所用的全部用語(包括技術及科學用語)的含義皆與本發明概念所屬技術領域中具有通常知識者所通常理解的含義相同。更應理解,這些用語(例如常用字典中所定義的用語)應被解釋為具有與其在相關技術的上下文中的意義一致的含義,且除非本文中進行明確定義,否則不應將其解釋為具有理想化或過於正式的意義。本文所用用語「及/或」包括相關列出項其中的一或多個項的任意及所有組合。例如「…中的至少一者」等表達當出現在一系列元件之前時,是修飾整個系列的元件,而並非修飾所述系列中的各別元件。 Unless otherwise defined, the meanings of all terms (including technical and scientific terms) used herein are the same as those commonly understood by those with ordinary knowledge in the technical field to which the concept of the present invention belongs. It should be understood that these terms (such as those defined in commonly used dictionaries) should be interpreted as having meanings consistent with their meanings in the context of related technologies, and unless clearly defined in this article, they should not be interpreted as having Ideal or too formal meaning. The term "and/or" as used herein includes any and all combinations of one or more of the related listed items. For example, expressions such as "at least one of" when appearing before a series of elements modify the entire series of elements, rather than modify individual elements in the series.
圖1是說明根據例示性實施例的多媒體裝置10的方塊圖。作為實例,多媒體裝置10可包含於智慧型電話、智慧型平板電腦、智慧型電視、平板電腦(tablet computer)、膝上型電腦、個人數位助理(personal digital assistant,PDA)、可攜式多媒體播放機(portable multimedia player,PMP)、數位照相機、音樂播放器、可攜式遊戲機(portable game console)、導航系統及例如智慧型手錶、腕帶型電子裝置、項鏈型電子裝置、眼鏡型電子裝置等任意穿戴式裝置。參照圖1,多媒體裝置10可包括應用處理器11、隨機存取記憶體12、儲存裝置13、電力管理電路14、電源供應器15、視訊編解碼器16、顯示器17、照相機18、音訊編解碼器19、揚聲器20、麥克風21、數據機22、天線23、插頭偵測器100及插頭槽200。
FIG. 1 is a block diagram illustrating a
應用處理器11可執行用於控制多媒體裝置10的控制功能,且可執行用於處理各種資料的算術功能。應用處理器11可執行作業系統及各種應用。
The
隨機存取記憶體12可用作應用處理器11的主記憶體單元。舉例而言,隨機存取記憶體12可儲存由應用處理器11所處理的程序碼(process code)及各種資料。隨機存取記憶體12可包括動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)、靜態隨機存取記憶體(Static RAM,SRAM)、相變隨機存取記憶體(Phase-change RAM,PRAM)、磁性隨機存取記憶體(Magnetic RAM,MRAM)、鐵電式隨機存取記憶體(Ferroelectric
RAM,FeRAM)或電阻式隨機存取記憶體(Resistive RAM,RRAM)。
The
儲存裝置13可用作應用處理器11的輔助記憶體單元。舉例而言,儲存裝置13可儲存各種應用的原始碼或作業系統的原始碼或出於長期儲存目的而儲存的由應用或作業系統產生的各種資料。儲存裝置13可包括快閃記憶體、相變隨機存取記憶體、磁性隨機存取記憶體、鐵電式隨機存取記憶體或電阻式隨機存取記憶體。
The
電力管理電路14可將電力自電源供應器15分配或供應至多媒體裝置10的各組件。電力管理電路14可根據多媒體裝置10的狀況或由多媒體10所執行的工作量來調整要分配或供應到多媒體裝置10各組件的電量。舉例而言,電力管理電路14可控制多媒體裝置10的省電模式或多媒體裝置10的組件的省電模式。
The
視訊編解碼器16可產生或播放視訊資料。舉例而言,視訊編解碼器16可對相機18產生的訊號進行編碼,以產生視訊資料。視訊編解碼器16可對相機18產生的視訊資料或儲存於儲存裝置13中或隨機存取記憶體12中的視訊資料進行解碼,並可藉由顯示器17來播放所解碼的視訊資料。舉例而言,顯示器17可包括液晶顯示器(Liquid Crystal Display,LCD)、有機發光二極體(Organic Light Emitting Diode,OLED)、主動矩陣式有機發光二極體(Active Matrix OLED,AMOLED)、可撓式顯示器或電子墨水。
The
音訊編解碼器19可產生或儲存音訊資料。舉例而言,音訊編解碼器19可對麥克風21產生的訊號進行編碼,以產生音訊資料。音訊編解碼器19可對麥克風21產生的音訊資料或儲存於儲存裝置13中或隨機存取記憶體12中的音訊資料進行解碼,並可藉由揚聲器20來播放所解碼的音訊資料。
The
音訊編解碼器19可連接至插頭偵測器100及插頭槽200。插頭偵測器100可偵測外部個人播放單元的插頭是否插入插頭槽200,並可將偵測結果作為輸出訊號OUT提供至音訊編解碼器19。若有外部個人播放單元插入插頭槽200,則音訊編解碼器19可藉由所連接的個人播放單元來播放音訊資料。
The
插頭偵測器100可偵測插入插頭槽200的外部個人播放單元是否包括麥克風。若外部個人播放單元包括麥克風,則音訊編解碼器19可基於自外部個人播放單元的麥克風接收到的訊號來產生音訊資料。
The
舉例而言,音訊編解碼器19及插頭偵測器100可實作於一個半導體封裝中。舉例而言,插頭偵測器100可包含於音訊編解碼器19中。
For example, the
數據機22可藉由天線23與外部裝置通訊。舉例而言,數據機22可基於以下多種無線通訊模式中的至少一者而與外部裝置通訊:例如長期演進(Long Term Evolution,LTE)、WiMax、全球行動系統(Global System for Mobile,GSM)通訊、分碼多工存取(Code Division Multiple Access,CDMA)、藍芽(Bluetooth)、
近場通訊(Near Field Communication,NFC)、WiFi、射頻識別(Radio Frequency Identification,RFID)等等;或是基於各種有線通訊模式,例如通用序列匯流排(Universal Serial Bus,USB)、序列先進技術附接(Serial AT Attachment,SATA)、高速晶片互連(High Speed InterChip,HSIC)、小型電腦系統介面(Small Computer System Interface,SCSI)、火線(Firewire)、周邊元件互連(Peripheral Component Interconnection,PCI)、快速周邊元件互連(PCI express,PCIe)、快速非揮發性記憶體(NonVolatile Memory express,NVMe)、通用快閃儲存器(Universal Flash Storage,UFS)、安全數位(Secure Digital,SD)、安全數位輸入輸出(SDIO)、通用非同步收發器(Universal Asynchronous Receiver Transmitter,UART)、序列週邊介面(Serial Peripheral Interface,SPI)、高速序列週邊介面(High Speed SPI,HS-SPI)、RS232、內部整合電路(Inter-Integrated Circuit,I2C)、高速內部整合電路(HS-I2C)、晶片間音訊(Integrated-Interchip Sound,I2S)、索尼/菲力浦數位介面(Sony/Philips Digital Interface,S/PDIF)、多媒體卡(MultiMedia Card,MMC)、嵌入式多媒體卡(embedded MMC,eMMC)等等。
The
圖2繪示外部個人播放單元的插頭300插入插頭槽200的實例。舉例而言,圖2繪示4極插頭300的例示性插入特徵。
FIG. 2 shows an example in which the
參照圖1及圖2,插頭槽200可包括主體210、第一通道電極220、第二通道電極230、接地電極240、第一通道偵測電極
225、接地偵測電極245及麥克風偵測電極255。主體210可形成於例如多媒體裝置10的機箱(case)、模具或框架中。
1 and 2, the
第一通道電極220及第二通道電極230可連接至音訊編解碼器19。當插頭300未與插頭槽200耦接時,音訊編解碼器19可對第一通道電極220及第二通道電極230施加電源電壓。當插頭300與插頭槽200耦接時,音訊編解碼器19可分別將音訊訊號傳遞至第一通道電極220及第二通道電極230。
The
接地電極240可連接至音訊編解碼器19或插頭偵測器100,且可連接至音訊編解碼器19的接地節點或插頭偵測器100的接地節點。所述接地節點可為被供應接地電壓的節點。
The
第一通道偵測電極225及接地偵測電極245可連接至插頭偵測器100。插頭偵測器100可基於第一通道偵測電極225的電壓及接地偵測電極245的電壓而偵測插頭300是否與插頭槽200耦接。
The first
麥克風偵測電極255可連接插頭偵測器100及音訊編解碼器19。當插頭300未與插頭槽200耦接時,插頭偵測器100可將接地電壓傳遞至麥克風偵測電極255。若偵測到插頭300插入插頭槽200,則插頭偵測器100可對麥克風偵測電極255施加偏置電壓,且可藉此偵測插入插頭槽200的個人播放單元是否包括麥克風。在確定插入插頭槽200的個人播放單元不包括麥克風時,插頭偵測器100可對麥克風偵測電極255施加接地電壓。而在確定插入插頭槽200的個人播放單元包括麥克風時,插頭偵測器100
可對麥克風偵測電極255連續施加偏置電壓。音訊編解碼器19可基於麥克風偵測電極255的電壓變化而獲得音訊資料。
The
舉例而言,插入插頭槽200的插頭300可包括4個極310、320、330及340。第一極310可自第一通道電極220接收第一通道的音訊訊號,即,左通道的音訊訊號。第二極320可自第二通道電極230接收音訊訊號,即,右通道的音訊訊號。第三極330可自接地電極240接收接地電壓。第四極340可藉由麥克風偵測電極255而將音訊訊號傳遞至音訊編解碼器19。
For example, the
第一極310與第二極320可藉由第一絕緣體315而彼此電性隔離。第二極320與第三極330可藉由第二絕緣體325而彼此電性隔離。第三極330與第四極340可藉由第三絕緣體335而彼此電性隔離。
The
舉例而言,插頭槽200的接地電極240及接地偵測電極245在插頭槽200中可不對齊。舉例而言,由於加工錯誤或根據規格中的定義,接地偵測電極245及接地電極240可不置於與第一絕緣體315、第二絕緣體325及第三絕緣體335平行的軸線上。
For example, the
圖3繪示外部個人播放單元的插頭400插入插頭槽200的實例。舉例而言,圖3繪示3極插頭400的例示性插入特徵。圖3所示的插頭槽200具有與圖2所示的插頭槽200相同的結構。因此,將不再對插頭槽200予以贅述。
FIG. 3 shows an example in which the
舉例而言,插入插頭槽200的插頭400可包括3個極410、420及430。第一極410可自第一通道電極220接收第一通
道的音訊訊號,例如,左通道的音訊訊號。第二極420可自第二通道電極230接收第二通道的音訊訊號,例如,右通道的音訊訊號。第三極430可自接地電極240接收接地電壓。與圖2所示的插頭300相比,插頭400的第三極430可延伸至與圖2所示插頭300的第四極340對應的位置。插頭400可不具有被分配至麥克風的極,且連接至插頭400的個人播放單元可不具有麥克風。
For example, the
第一極410與第二極420可藉由第一絕緣體415而彼此電性隔離。第二極420與第三極430可藉由第二絕緣體425而彼此電性隔離。
The
圖4是根據例示性實施例所繪示的插頭偵測器100的應用100a的電路圖。參照圖2至圖4,插頭偵測器100可包括第一電阻R1、第二電阻R2、比較器CP、第一上拉電阻PUR1、邏輯閘電路OR、第二上拉電阻PUR2、第一電晶體TR1、訊號產生器SG及偏置電壓產生電路BG。
FIG. 4 is a circuit diagram of an
第一電阻R1及第二電阻R2可串聯於被供應電源電壓VDD的電源節點與被供應接地電壓的接地節點之間。位於第一電阻R1與第二電阻R2之間的節點的電壓可為第一電壓V1。 The first resistor R1 and the second resistor R2 may be connected in series between the power node supplied with the power supply voltage VDD and the ground node supplied with the ground voltage. The voltage of the node between the first resistor R1 and the second resistor R2 may be the first voltage V1.
比較器CP係建構用以為將第一電壓V1與第一通道偵測電極225的電壓進行比較。若第一通道偵測電極225的電壓等於或高於第一電壓V1,則比較器CP可輸出高位凖訊號。若第一通道偵測電極225的電壓低於第一電壓V1,則比較器CP可輸出低位凖訊號。比較器CP的輸出可被傳遞至邏輯閘電路OR。
The comparator CP is configured to compare the first voltage V1 with the voltage of the first
上拉電阻PUR1可連接於電源節點與第一通道偵測電極225之間。上拉電阻PUR1可將電源電壓VDD傳遞至第一通道偵測電極225,藉此使得第一通道偵測電極225的電壓在插頭300或400未與插頭槽200耦接時等於電源電壓VDD。
The pull-up resistor PUR1 can be connected between the power node and the first
邏輯閘電路OR可對比較器CP的輸出及接地偵測電極245的電壓執行OR運算。邏輯閘電路OR的輸出可作為輸出訊號OUT而經由輸出端OT傳遞至音訊編解碼器19。舉例而言,當邏輯閘電路的輸出處於低位準時(即,當第一通道偵測電極225的電壓及接地偵測電極245的電壓為接地電壓或近似於接地電壓的低電壓時),可偵測到插頭300或400與插頭槽200耦接。當邏輯閘電路OR的輸出處於高位準時(即,當第一通道偵測電極225的電壓及接地偵測電極245的電壓中的至少一者為電源電壓或近似於電源電壓的正電壓時),可偵測到插頭300或400未與插頭槽200耦接。
The logic gate circuit OR can perform an OR operation on the output of the comparator CP and the voltage of the
第一電晶體TR1可連接於麥克風偵測電極255與被供應接地電壓的接地節點之間,並可在邏輯閘電路OR的控制下運作。當邏輯閘電路OR的輸出處於高位準時(即,當插頭300或400未與插頭槽200耦接時),第一電晶體TR1將接地電極與麥克風偵測電極255連接。亦即,可對麥克風偵測電極255供應接地電壓。當邏輯閘電路OR的輸出處於低位準時(即,當插頭300或400與插頭槽200耦接時),第一電晶體TR1可斷開。亦即,麥克風偵測電極255的電壓可由偏置電壓產生電路BG控制。
The first transistor TR1 can be connected between the
訊號產生器SG可輸出致能訊號EN。舉例而言,當邏輯閘電路OR的輸出處於高位準時(即,當插頭300或400未與插頭槽200耦接時),可停用致能訊號EN。當邏輯閘電路OR的輸出處於低位準時(即,當插頭300或400與插頭槽200耦接時),可啟用致能訊號EN。
The signal generator SG can output the enable signal EN. For example, when the output of the logic gate circuit OR is at a high level (ie, when the
當致能訊號EN被啟用時,偏置電壓產生電路BG可對麥克風偵測電極255供應偏置電壓BIAS。當致能訊號EN被停用時,偏置電壓產生電路BG可被禁能而不輸出偏置電壓BIAS。舉例而言,偏置電壓產生電路BG可輸出接地電壓。
When the enable signal EN is enabled, the bias voltage generating circuit BG can supply the bias voltage BIAS to the
偏置電壓產生電路BG可包括第二比較器CP2、第二電晶體TR2、第三電阻R3、第四電阻R4及第五電阻R5。 The bias voltage generating circuit BG may include a second comparator CP2, a second transistor TR2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5.
第三電阻R3與第四電阻R4串聯於第二電晶體TR2與被供應接地電壓的接地節點之間。位於第三電阻R3與第四電阻R4之間的節點可連接至第二比較器CP2的正輸入端。參考電壓VREF可被施加至第二比較器CP2的負輸入端。 The third resistor R3 and the fourth resistor R4 are connected in series between the second transistor TR2 and the ground node supplied with the ground voltage. The node between the third resistor R3 and the fourth resistor R4 may be connected to the positive input terminal of the second comparator CP2. The reference voltage VREF may be applied to the negative input terminal of the second comparator CP2.
第二電晶體TR2可連接於第三電阻R3與被供應電源電壓VDD的電源節點之間。第二電晶體TR2可由第二比較器CP2的輸出控制。位於第二電晶體TR2與第三電阻R3之間的節點的電壓可為偏置電壓BIAS。偏置電壓BIAS可經由第五電阻R5而傳遞至麥克風偵測電極255。偏置電壓產生電路BG可調整偏置電壓BIAS,以使位於第三電阻R3與第四電阻R4之間的節點的電壓與參考電壓VREF相等。
The second transistor TR2 can be connected between the third resistor R3 and the power supply node to which the power supply voltage VDD is supplied. The second transistor TR2 can be controlled by the output of the second comparator CP2. The voltage at the node between the second transistor TR2 and the third resistor R3 may be the bias voltage BIAS. The bias voltage BIAS can be transmitted to the
圖5是根據例示性實施例所繪示的偵測插頭300或400是否插入插頭槽200的方法流程圖。
FIG. 5 is a flowchart of a method for detecting whether the
參照圖2至圖5,在步驟S110中,對第一通道電極220、接地電極240及麥克風偵測電極255施加接地電壓VSS。舉例而言,在插頭300未插入插頭槽200的情況下,音訊編解碼器19可對第一通道電極220、第二通道電極230及接地電極240施加接地電壓VSS。由於插頭偵測器100的邏輯閘電路OR的輸出在插頭300未插入插頭槽200中的情況下處於高位凖,因此可藉由電晶體TR1對麥克風偵測電極255供應接地電壓VSS。
2 to 5, in step S110, a ground voltage VSS is applied to the
在步驟S120中,若插頭300與插頭槽200耦接,則第一通道電極220可藉由第一極310連接至第一通道偵測電極225。因此,第一通道偵測電極225的電壓可藉由第一通道電極220的接地節點而減小至接地電壓VSS。另外,接地偵測電極245可藉由第三極330電性連接至接地電極240。因此,接地偵測電極245的電壓可藉由接地電極240的接地節點而減小至接地電壓VSS。如此一來,若插頭300與插頭槽200耦接,則第一通道偵測電極225的電壓及接地偵測電極245的電壓可減小至接地電壓VSS,且輸出訊號OUT可減小至低位凖。
In step S120, if the
由於發現插頭300未插入插頭槽200(除非邏輯閘電路OR的輸出訊號OUT處於低位凖),因此偵測操作將被終止。若邏輯閘電路OR的輸出訊號OUT處於低位凖,則在步驟S130中可偵測到插頭300插入插頭槽200。在此之後,第一電晶體TR1可
將麥克風偵測電極255與接地節點電性隔離,且偏置電壓產生電路BG可將偏置電壓BIAS傳遞至麥克風偵測電極255。
Since it is found that the
在步驟S140中,可確定麥克風偵測電極255的電壓低於偏置電壓BIAS或低於在位凖上與偏置電壓BIAS近似的電壓。舉例而言,如圖3所示,在3極插頭400插入插頭槽200的情況下,麥克風偵測電極255可藉由第三極430而連接至接地電極。因此,麥克風偵測電極224的電壓可減小至較偏置電壓BIAS為低的電壓(即,可減小至接地電壓VSS),並可偵測到個人播放單元中不具有麥克風。如圖2所示,在4極插頭300插入插頭槽200中的情況下,第四極340可連接至個人播放單元的麥克風。舉例而言,麥克風可具有範圍為1.35千歐(kΩ)至33千歐的電阻。麥克風偵測電極255的電壓可變為藉由利用第五電阻R5及麥克風的電阻對第三電阻R3與第二電晶體TR2之間的節點的電壓進行分壓而設定的偏置電壓BIAS。因此,在步驟S150中,可偵測到個人播放單元具有麥克風。
In step S140, it can be determined that the voltage of the
舉例而言,若偵測到個人播放單元具有麥克風,則偏置電壓產生電路BG可將偏置電壓BIAS連續地傳遞至麥克風偵測電極255。個人播放單元的麥克風可使用所述偏置電壓來獲得音訊訊號。所獲得的音訊訊號可表現於麥克風偵測電極255的電壓變化中。
For example, if it is detected that the personal playback unit has a microphone, the bias voltage generating circuit BG can continuously transmit the bias voltage BIAS to the
圖6繪示當3極插頭400插入插頭槽200或與插頭槽200分離時的連接狀態。參照圖6,接地電極240與接地偵測電極245
在插頭槽200中未對齊。因此,接地電極240在與第二絕緣體425對齊的位置處未電性連接至插頭400。接地偵測電極245及麥克風偵測電極255可連接至第三極430。在此種狀態中,電流路徑CP可由位於接地偵測電極245與麥克風偵測電極255之間的第三極430形成,且第三極430的電壓可取決於接地偵測電極245的電壓及麥克風偵測電極255的電壓。
FIG. 6 illustrates the connection state when the 3-
圖7繪示在圖6所示連接狀態中插頭偵測器100中所涉及的電壓變化的時序圖。參照圖5、圖6及圖7,插頭槽200及3極插頭400可如圖6中所示彼此連接。第一通道偵測電極225可藉由第一上拉電阻PUR1連接至電源節點。因此,如在第一時間點T1之前所示,當插頭400未插入插頭槽200時,第一通道偵測電極225的電壓可為電源電壓VDD。如圖6中所示,若第一通道偵測電極225藉由第一極410連接至第一通道電極220,則第一通道偵測電極225的電壓可如在第一時間點T1處所示的因接地電壓VSS被供應至第一通道電極220而減小至接地電壓VSS。
FIG. 7 shows a timing diagram of voltage changes involved in the
接地偵測電極245可藉由第二上拉電阻PUR2連接至電源節點。因此,當插頭400未插入插頭槽200時,接地偵測電極245的電壓可如在第一時間點T1之前所示的為電源電壓VDD。如圖6中所示,若接地偵測電極245藉由第三極430連接至麥克風偵測電極255,則接地偵測電極245的電壓可如在第一時間點T1處所示的因麥克風偵測電極255的接地電壓VSS而藉由被接通的第一電晶體TR1減小至接地電壓VSS。
The
當插頭400未插入插頭槽200時,第一通道偵測電極225的電壓及接地偵測電極245的電壓可變為電源電壓VDD或近似於電源電壓VDD的電壓。因此,如在第一時間點T1之前所示,比較器CP可輸出具有高位凖的輸出訊號且邏輯閘電路OR可輸出具有高位凖的輸出訊號OUT。當插頭400如圖6中所示的插入插頭槽200時,第一通道偵測電極225的電壓及接地偵測電極245的電壓可減小至接地電壓VSS或近似於接地電壓VSS的電壓。因此,如在第一時間點T1處所示,比較器CP可輸出低位凖訊號且邏輯閘電路OR可輸出具有低位凖的輸出訊號OUT。
When the
在插頭400未插入插頭槽200的情況下,輸出訊號OUT可如在第一時間點T1之前所示的處於高位凖。因此,第一電晶體TR1可將接地節點與麥克風偵測電極255連接,且麥克風偵測電極255的電壓可如在第一時間點T1之前所示的變為接地電壓VSS。若輸出訊號OUT如在第一時間點T1處所示的自高位凖轉變至低位凖,則可啟用致能訊號EN。因此,在第二時間點T2處,電晶體TR1可斷開且偏置電壓產生電路BG可輸出偏置電壓BIAS。因此,麥克風偵測電極255的電壓可自接地電壓VSS增大。
When the
若麥克風偵測電極255的電壓在第二時間點T2處自接地電壓VSS增大,則此後,在第三時間點T3處,藉由第三極430連接至麥克風偵測電極255的接地偵測電極245的電壓亦可因電流路徑CP而增大。舉例而言,接地偵測電極245的電壓可增大至自麥克風偵測電極255供應的偏置電壓BIAS、藉由第二上拉電阻
PUR2供應的電源電壓VDD或處於偏置電壓BIAS與電源電壓VDD之間的中間電壓。
If the voltage of the
若接地偵測電極245的電壓增大,則邏輯閘電路OR的輸出訊號OUT可在第三時間點T3處自低位凖轉變至高位凖。若輸出訊號OUT轉變至高位凖,則第一電晶體TR1可被接通且偏置電壓產生電路BG可被禁能。因此,在第四時間點T4處,麥克風偵測電極255的電壓可減小至接地電壓VSS。
If the voltage of the
隨著麥克風偵測電極255的電壓減小至接地電壓VSS,在第五時間點T5處,接地偵測電極245的電壓亦可減小至接地電壓VSS。邏輯閘電路OR的輸出訊號OUT可在第五時間點T5處自高位凖轉變至低位凖。在第六時間點T6處,第一電晶體TR1可斷開且偏置電壓產生電路BG可輸出偏置電壓BIAS。因此,麥克風偵測電極255的電壓可在第六時間點T6處自接地電壓VSS增大至偏置電壓BIAS。
As the voltage of the
隨著麥克風偵測電極255的電壓增大至偏置電壓BIAS,在第七時間點T7處,接地偵測電極245的電壓可增大。
As the voltage of the
如圖7所示,在如圖6所示的接地偵測電極245與麥克風偵測電極255短路且接地電極240浮動的情況下,邏輯閘電路OR的輸出訊號OUT可在高位凖與低位凖之間週期性地轉變。儘管輸出訊號OUT週期性地轉變,然而第三極430的電壓可隨著接地偵測電極245或麥克風偵測電極255的變化而變化。
As shown in FIG. 7, in the case where the
個人播放單元可基於第一極410與第三極430之間的電
壓差而播放第一通道的音訊訊號,並可基於第二極420與第三極430之間的電壓差而播放第二通道的音訊訊號。如圖7中所示,若第三極430的電壓週期性地變化,則可藉由個人播放單元而週期性地產生並聽到干擾雜訊。
The personal playback unit can be based on the electrical connection between the
因此,例示性實施例可在偵測到插頭400的插入之後對接地偵測電極245施加接地電壓。
Therefore, an exemplary embodiment may apply a ground voltage to the
圖8繪示圖4所示的插頭偵測器100的應用100b的電路圖。參照圖8,插頭偵測器100b可包括第一電阻R1、第二電阻R2、比較器CP、第一上拉電阻PUR1、邏輯閘電路OR、第二上拉電阻PUR2、第一電晶體TR1、訊號產生器SG、偏置電壓產生電路BG及第三電晶體TR3。與圖4所示的插頭偵測器100相比,插頭偵測器100b可更包括第三電晶體TR3。以下將不再贅述圖4所示的插頭偵測器100與圖8所示的插頭偵測器100b中的共同元件。
FIG. 8 is a circuit diagram of an
第三電晶體TR3可連接於接地偵測電極245與被供應接地電壓的接地節點之間,並可藉由偏置電壓BIAS來控制。若偏置電壓產生電路BG被致能(例如,第二電晶體TR2被接通)以輸出偏置電壓BIAS(其為藉由第二電晶體TR2、第三電阻R3及第四電阻R4對電源電壓VDD進行分壓而產生的正電壓),則第三電晶體TR3可被接通。隨後,所述接地節點可連接至接地偵測電極245。若偏置電壓產生電路BG被禁能(例如,第二電晶體被斷開)以輸出藉由第三電阻R3及第四電阻R4傳遞的接地電壓,則第三電晶體TR3可被斷開。隨後,所述接地節點可自接地偵測電極245
隔離。
The third transistor TR3 can be connected between the
圖9繪示一種在圖8所示的插頭偵測器100b中執行插頭插入的方法的流程圖。參照圖8及圖9,在步驟S210中,可將接地電壓供應至第一通道電極220、接地電極240及麥克風偵測電極255。步驟S210可以用與圖5中步驟S110相同的方式來執行。
FIG. 9 shows a flowchart of a method for performing plug insertion in the
在步驟S220中,可判斷邏輯閘電路OR的輸出訊號OUT是否處於低位凖。步驟S220可以用與圖5中步驟S120相同的方式來執行。 In step S220, it can be determined whether the output signal OUT of the logic gate circuit OR is low. Step S220 can be performed in the same manner as step S120 in FIG. 5.
若邏輯閘電路OR的輸出訊號OUT處於高位凖,則可偵測不到插頭插入而可終止所述程序。若邏輯閘電路OR的輸出訊號OUT處於低位凖,則可偵測到插頭插入並可執行步驟S230。 If the output signal OUT of the logic gate circuit OR is at a high level, the plug insertion can not be detected and the procedure can be terminated. If the output signal OUT of the logic gate circuit OR is low, the plug insertion can be detected and step S230 can be executed.
在步驟S230中,由於偵測到插頭插入,因此可對麥克風偵測電極255施加偏置電壓BIAS,且可對接地偵測電極245施加接地電壓VSS。舉例而言,可對偏置電壓產生電路BG進行致能,以對麥克風偵測電極255施加偏置電壓BIAS。可藉由偏置電壓BIAS接通第三電晶體TR3,以將接地電壓VSS傳遞至接地偵測電極245。
In step S230, since plug insertion is detected, the bias voltage BIAS can be applied to the
在步驟S240中,可判斷麥克風偵測電極255的電壓是否低於偏置電壓BIAS。步驟S240可以用與圖5中步驟S140相同的方式來執行。
In step S240, it can be determined whether the voltage of the
若麥克風偵測電極255的電壓低於偏置電壓BIAS,則可偵測不到麥克風而可終止所述程序。若麥克風偵測電極255的電
壓近似於偏置電壓BIAS,則可在步驟S250中偵測到麥克風。步驟S250可以用與圖5中步驟S150相同的方式來執行。
If the voltage of the
圖10繪示在圖6所示連接狀態中圖8的插頭偵測器100b中所涉及的電壓變化的時序圖。參照圖6、圖8及圖10,在第一時間點T1處,若3極插頭400如圖6中所示的與插頭槽200耦接,則第一通道偵測電極225的電壓可自電源電壓VDD減小至接地電壓VSS。接地偵測電極245的電壓可自電源電壓VDD減小至接地電壓VSS。因此,邏輯閘電路OR的輸出訊號OUT可自高位凖轉變至低位凖。隨後,可偵測到插頭400的插入。
FIG. 10 is a timing diagram of voltage changes involved in the
在第二時間點T2處,第一電晶體TR1可斷開且偏置電壓產生電路BG可輸出偏置電壓BIAS。因此,麥克風偵測電極255的電壓可自接地電壓VSS增大至偏置電壓BIAS。另外,第三電晶體TR3可藉由偏置電壓BIAS而接通,且接地偵測電極245可連接至接地節點。因此,儘管麥克風偵測電極255的電壓增大至偏置電壓BIAS,接地偵測電極245的電壓仍可保持在接地電壓VSS。
At the second time point T2, the first transistor TR1 can be turned off and the bias voltage generating circuit BG can output the bias voltage BIAS. Therefore, the voltage of the
隨後,自第三時間點T3至第七時間點T7,接地偵測電極245的電壓可保持在接地電壓。因此,如以上結合圖7所述,可防止插頭400的第三極430的電壓發生變化,藉此防止雜訊。因此,可提高使用者方便性。
Subsequently, from the third time point T3 to the seventh time point T7, the voltage of the
圖11繪示圖8所示的插頭偵測器100b的應用100c的電路圖。參照圖11,插頭偵測器100c可包括第一電阻R1、第二電阻R2、比較器CP、第一上拉電阻PUR1、邏輯閘電路OR、第二
上拉電阻PUR2、第一電晶體TR1、訊號產生器SG、偏置電壓產生電路BG及第三電晶體TR3。與圖8所示的插頭偵測器100b相比,插頭偵測器100c可更包括脈波產生電路PG。第三電晶體TR3可藉由脈波產生電路PG的輸出脈波取代偏置電壓BIAS來控制。
FIG. 11 is a circuit diagram of an
參照圖11,脈波產生電路PG係建構為可因應致能訊號EN而輸出脈波訊號。舉例而言,脈波產生電路PG可輸出脈波訊號,此脈波訊號在致能訊號EN啟用時自低位凖轉變至高位凖,且在工作時間(duty time)之後自高位凖轉變至低位凖。舉例而言,工作時間可等於或長於用於偵測個人播放單元是否包括麥克風的時間。舉例而言,工作時間可為用於偵測麥克風的時間。 Referring to FIG. 11, the pulse wave generating circuit PG is constructed to output a pulse signal in response to the enable signal EN. For example, the pulse wave generating circuit PG can output a pulse signal that changes from low to high when the enable signal EN is enabled, and from high to low after the duty time. . For example, the working time may be equal to or longer than the time used to detect whether the personal playback unit includes a microphone. For example, the working time may be the time used to detect the microphone.
若脈波產生電路PG的輸出脈波自低位凖轉變至高位凖,則第三電晶體TR3可被接通。因此,與圖6中所示的連接狀態類似,接地偵測電極245可連接至接地節點,且可防止接地偵測電極245的電壓隨麥克風偵測電極255的電壓變化。若在對麥克風的偵測結束之後,脈波產生電路PG的輸出脈波自高位凖轉變至低位凖,則第三電晶體TR3可被斷開。隨後,接地偵測電極245可自接地節點隔離,而由連接至接地偵測電極245的第二上拉電阻PUR2對其作用。舉例而言,若插頭400與插頭槽200分離,則接地偵測電極245的電壓可藉由第二上拉電阻PUR2及電源節點而增大至電源電壓VDD。亦即,若第二上拉電阻PUR2對其作用,則接地偵測電極245可偵測到插頭400與插頭槽200分離。
If the output pulse wave of the pulse wave generating circuit PG changes from a low level to a high level, the third transistor TR3 can be turned on. Therefore, similar to the connection state shown in FIG. 6, the
上述的例示性實施例是提供用以充分闡釋與3極插頭
400及4極插頭300相關的技術概念。然而,例示性實施例並非僅限於所述的3極插頭400及4極插頭300,而是可被廣泛地應用於n極插頭(n是正整數)。
The above-mentioned exemplary embodiment is provided for full explanation and 3-
根據各種例示性實施例,即使當插頭與插頭槽耦接或與所述插頭槽分離時接地偵測電極與麥克風偵測電極發生短路,仍可防止產生雜訊。 According to various exemplary embodiments, even if the ground detection electrode and the microphone detection electrode are short-circuited when the plug is coupled to or separated from the plug groove, the generation of noise can still be prevented.
儘管已闡述了各種例示性實施例,然而對於熟習此項技術者將顯而易見,可作出各種變化及潤飾,而此並不背離本發明概念的精神及範圍。因此,應理解,上述例示性實施例並非限制性的,而是說明性的。 Although various exemplary embodiments have been described, it will be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the concept of the present invention. Therefore, it should be understood that the above-described exemplary embodiments are not restrictive, but illustrative.
10‧‧‧多媒體裝置 10‧‧‧Multimedia device
11‧‧‧應用處理器 11‧‧‧Application Processor
12‧‧‧隨機存取記憶體 12‧‧‧Random access memory
13‧‧‧儲存裝置 13‧‧‧Storage device
14‧‧‧電力管理電路 14‧‧‧Power Management Circuit
15‧‧‧電源供應器 15‧‧‧Power Supply
16‧‧‧視訊編解碼器 16‧‧‧Video Codec
17‧‧‧顯示器 17‧‧‧Display
18‧‧‧照相機 18‧‧‧Camera
19‧‧‧音訊編解碼器 19‧‧‧Audio Codec
20‧‧‧揚聲器 20‧‧‧Speaker
21‧‧‧麥克風 21‧‧‧Microphone
22‧‧‧數據機 22‧‧‧Modem
23‧‧‧天線 23‧‧‧antenna
100‧‧‧插頭偵測器 100‧‧‧Plug detector
200‧‧‧插頭槽 200‧‧‧Plug slot
OUT‧‧‧輸出訊號 OUT‧‧‧Output signal
Claims (19)
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KR10-2015-0146221 | 2015-10-20 |
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CN101159991A (en) * | 2006-10-03 | 2008-04-09 | 索尼株式会社 | Audio equipment |
US20110150234A1 (en) * | 2007-01-05 | 2011-06-23 | Timothy Johnson | Audio i o headset plug and plug detection circuitry |
US20140038460A1 (en) * | 2012-08-03 | 2014-02-06 | Fairchild Semiconductor Corporation | Accessory detection circuit with improved functionality |
US20140072129A1 (en) * | 2012-09-11 | 2014-03-13 | Samsung Electronics Co., Ltd. | Method and apparatus for detecting insertion of external audio outputting device in electronic device |
TW201517642A (en) * | 2013-10-29 | 2015-05-01 | Realtek Semiconductor Corp | Audio codec with audio jack detection function and audio jack detection method |
Also Published As
Publication number | Publication date |
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KR20170005360A (en) | 2017-01-12 |
TW201724875A (en) | 2017-07-01 |
KR102345047B1 (en) | 2021-12-31 |
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