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TWI722959B - 晶片封裝結構 - Google Patents

晶片封裝結構 Download PDF

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Publication number
TWI722959B
TWI722959B TW109128362A TW109128362A TWI722959B TW I722959 B TWI722959 B TW I722959B TW 109128362 A TW109128362 A TW 109128362A TW 109128362 A TW109128362 A TW 109128362A TW I722959 B TWI722959 B TW I722959B
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TW
Taiwan
Prior art keywords
chip
substrate
bumps
bridge
electrically connected
Prior art date
Application number
TW109128362A
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English (en)
Other versions
TW202209617A (zh
Inventor
曾子章
林溥如
柯正達
譚瑞敏
Original Assignee
欣興電子股份有限公司
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Application filed by 欣興電子股份有限公司 filed Critical 欣興電子股份有限公司
Priority to TW109128362A priority Critical patent/TWI722959B/zh
Priority to US17/098,436 priority patent/US11410971B2/en
Application granted granted Critical
Publication of TWI722959B publication Critical patent/TWI722959B/zh
Priority to TW110141784A priority patent/TWI778858B/zh
Priority to CN202111329395.6A priority patent/CN114512456B/zh
Priority to US17/567,883 priority patent/US20220130781A1/en
Publication of TW202209617A publication Critical patent/TW202209617A/zh

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Abstract

一種晶片封裝結構，包括一基板、一第一晶片、一第二晶片、一橋接器、多個第一凸塊、多個第二凸塊、多個第三凸塊以及多個焊球。第一晶片的一第一主動表面及第二晶片的一第二主動表面朝向基板的一第一表面。橋接器包括一高分子聚合物層以及位於高分子聚合物層上的一接墊層。第一晶片透過第一凸塊與基板電性連接。第二晶片透過第二凸塊與基板電性連接。第一晶片與第二晶片分別透過第三凸塊與接墊層電性連接。第一凸塊與第二凸塊具有相同尺寸。焊球設置於基板的一第二表面上且與基板電性連接。

Description

晶片封裝結構
本發明是有關於一種封裝結構，且特別是有關於一種晶片封裝結構。
目前，在多個晶片互連的封裝結構中，會採用嵌入式多晶片互連橋接（embedded multi-die interconnect bridge，EMIB）技術將晶片設置在線路載板上，並利用內埋於線路載板的矽橋接器來連接多個晶片。然而，矽橋接器因製程而使得其接墊的大小會明顯的小於一般線路基板上的接墊尺寸，因而導致連接矽橋接器與晶片之間的微凸塊大小（如55微米）不同於連接晶片與線路基板之間的微凸塊大小（如130微米），進而導致晶片在組裝上良率表現不佳。
本發明提供一種晶片封裝結構，其凸塊的尺寸皆相同，可有效地解決習知晶片組裝良率過低的問題，可具有較佳的結構可靠度。
本發明的晶片封裝結構，包括一基板、一第一晶片、一第二晶片、一橋接器、多個第一凸塊、多個第二凸塊、多個第三凸塊以及多個焊球。基板具有彼此相對的一第一表面與一第二表面。第一晶片配置於基板的第一表面上，且具有朝向第一表面的一第一主動表面，以及包括配置於第一主動表面上的多個第一接墊。第二晶片配置於基板的第一表面上，且具有朝向第一表面的一第二主動表面，以及包括配置於第二主動表面上的多個第二接墊。橋接器包括一高分子聚合物層以及位於高分子聚合物層上的一接墊層。第一凸塊配置於第一晶片與基板之間，其中第一晶片透過第一凸塊與基板電性連接。第二凸塊配置於第二晶片與基板之間，其中第二晶片透過第二凸塊與基板電性連接。第三凸塊配置於第一晶片與橋接器之間以及第二晶片與橋接器之間。第一晶片與第二晶片分別透過第三凸塊與橋接器的接墊層電性連接。第一凸塊與第二凸塊具有相同尺寸。焊球設置於基板的第二表面上且與基板電性連接。
在本發明的一實施例中，上述的第三凸塊的尺寸與第一凸塊的尺寸相同。
在本發明的一實施例中，上述的第三凸塊的尺寸與第一凸塊的尺寸不同。
在本發明的一實施例中，上述的第一晶片包括至少一第一矽穿孔，而第二晶片包括至少一第二矽穿孔。第一晶片與第二晶片位於橋接器與基板之間，且橋接器透過第三凸塊與第一矽穿孔及第二矽穿孔電性連接。
在本發明的一實施例中，上述的橋接器於基板上的正投影部分重疊於第一晶片與第二晶片於基板上的正投影。
在本發明的一實施例中，上述的晶片封裝結構更包括一第一重配置線路層。第一重配置線路層配置於基板的第一表面上，且位於第一晶片與基板之間以及第二晶片與基板之間。第一晶片透過第一凸塊及第一重配置線路層與基板電性連接。
在本發明的一實施例中，上述的晶片封裝結構更包括一第二重配置線路層。第二重配置線路層配置於基板的第二表面上，且位於基板與焊球之間。焊球透過第二重配置線路層與基板電性連接。基板包括至少一導電通孔，電性連接第一重配置線路層與第二重配置線路層。第二晶片透過第二凸塊及第二重配置線路層與基板電性連接。
在本發明的一實施例中，上述的晶片封裝結構更包括一晶片組。晶片組配置於橋接器上，且透過橋接器及第三凸塊與第一晶片的第一矽穿孔電性連接。
在本發明的一實施例中，上述的晶片封裝結構更包括一整合式被動元件。整合式被動元件配置於橋接器上，且透過橋接器及第三凸塊與第二晶片的第二矽穿孔電性連接。
在本發明的一實施例中，上述的晶片封裝結構更包括一第一重配置線路層。第一重配置線路層配置於基板的第一表面上，且橋接器與第一重配置線路層位於第一晶片與基板之間以及第二晶片與基板之間。第一晶片透過第一凸塊及第一重配置線路層與基板電性連接。
在本發明的一實施例中，上述的晶片封裝結構更包括一第二重配置線路層。第二重配置線路層配置於基板的第二表面上，且位於基板與焊球之間。焊球透過第二重配置線路層與基板電性連接。基板包括至少一第一導電通孔，電性連接第一重配置線路層與第二重配置線路層。第二晶片透過第二凸塊及第二重配置線路層與基板電性連接。
在本發明的一實施例中，上述的橋接器內埋於第一重配置線路層或者是配置於第一重配置線路層上。
在本發明的一實施例中，上述的第一重配置線路層包括至少一第二導電通孔，電性連接橋接器與基板。
基於上述，在本發明的晶片封裝結構中，在每個晶片與基板之間的凸塊大小相同，意即第一凸塊以及第二凸塊具有相同尺寸，因此可提高晶片在組裝上的良率，進而使得本發明的晶片封裝結構可具有較佳的結構可靠度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1是依照本發明的一實施例的一種晶片封裝結構的剖面示意圖。請參考圖1，在本實施例中，晶片封裝結構100a包括一基板110a、一第一晶片120a、一第二晶片130a、一橋接器140a、多個第一凸塊150、多個第二凸塊160、多個第三凸塊170以及多個焊球175。由於本實施例的晶片封裝結構100a包括第一晶片120a與第二晶片130a，因此可是為是一種多晶片的晶片封裝結構。
詳細來說，本實施例的基板110a具有彼此相對的一第一表面111與一第二表面113，且包括配置於第一表面111上的接墊112及配置於第二表面113上的接墊114。意即，本實施例的基板110a具體化為線路基板，其中基板110a的材質例如是玻璃或有機材料，而接墊112、114的材質例如是銅，但不以此為限。於本實施例中，接墊112、114是分別配置於第一表面111與第二表面113上，但於其他實施例中，接墊112、114亦可內埋於基板110a內，此仍屬於本發明所欲保護的範圍。
再者，本實施例的第一晶片120a配置於基板110a的第一表面111上，且具有朝向第一表面111的一第一主動表面121，以及包括配置於第一主動表面121上的多個第一接墊122。第二晶片130a配置於基板110a的第一表面111上，且具有朝向第一表面111的一第二主動表面131，以及包括配置於第二主動表面131上的多個第二接墊132。此處，第一晶片120a的性質與第二晶片130a的性質相同，例如是第一晶片120a與第二晶片130a皆可為邏輯晶片，但不以此為限。於另一實施例中，第一晶片120a的性質可不同於第二晶片130a的性質，意即第一晶片120a可為邏輯晶片，而第二晶片130a可為記憶體晶片，但不以此為限，此即為將異質晶片整合於單一模組內。
請再參考圖1，在本實施例中，橋接器140a包括一高分子聚合物層142a以及位於高分子聚合物層142a上的一接墊層144a。意即，本實施例的橋接器140a不是以矽為基底，而是以高分子聚合物（如聚醯亞胺（Polyimide，PI），但不以此為限）為基底。更進一步來說，本實施例的橋接器140a還包括至少一圖案化線路層146a（示意地繪示一層圖案化線路層146a）以及至少一導電通孔148a（示意地繪示多個導電通孔148a）。圖案化線路層146a內埋於高分子聚合物層142a內，且透過導電通孔148a與接墊層144a電性連接。在製程上，先提供玻璃基板並於玻璃基板上形成離型膜，接著，於離型膜上形成高分子聚合物層142a、圖案化線路層146a、導電通孔148a以及接墊層144a，而形成橋接器140a。此處，橋接器140a可視為一種重配置線路層橋接器（RDL bridge），其中圖案化線路層146a及接墊層144a的線寬與線距例如分別為2微米至5微米。由於玻璃基板具有高度平整性與強度，因而於玻璃基板上可製作出具有超微細線路的橋接器140a，可具有高密度連接的效果。
此外，本實施例的第一凸塊150配置於第一晶片120a與基板110a之間，其中第一晶片120a透過第一凸塊150與基板110a電性連接。意即，第一晶片120a的第一接墊122透過第一凸塊150與基板110的接墊112電性連接。第二凸塊160配置於第二晶片130a與基板110a之間，其中第二晶片130a透過第二凸塊160與基板110a電性連接。意即，第二晶片130a的第二接墊132透過第二凸塊160與基板110a的接墊112電性連接。第三凸塊170配置於第一晶片120a與橋接器140a之間以及第二晶片130a與橋接器140a之間。第一晶片120a與第二晶片130a分別透過第三凸塊170與橋接器140a的接墊層144a電性連接。
更進一步來說，請再參考圖1，本實施例的第一晶片120a包括至少一第一矽穿孔124（示意地繪是示一個第一矽穿孔124），而第二晶片130a包括至少一第二矽穿孔134（示意地繪是示一個第二矽穿孔134）。第一晶片120a與第二晶片130a位於橋接器140a與基板110a之間，且橋接器140a透過第三凸塊170與第一矽穿孔124及第二矽穿孔134電性連接。意即，橋接器140a的接墊層144a透過第三凸塊170與第一晶片120a的第一矽穿孔124及第二晶片130a的第二矽穿孔134電性連接。此處，橋接器140a於基板110a上的正投影部分重疊於第一晶片120a與第二晶片130a於基板110a上的正投影。
特別是，本實施例的第一凸塊150與第二凸塊160具有相同尺寸。意即，第一凸塊150與第二凸塊160的大小、形狀皆相同，其中第一凸塊150以及第二凸塊160可例如是微凸塊（例如20微米至60微米）。第三凸塊170的尺寸與第一凸塊150的尺寸可相同或不同，其中第三凸塊170的尺寸可例如是20微米至200微米。在製程上，第一凸塊150與第二凸塊160會先形成在第一晶片120a與第二晶片130a上，接著，進行第一晶片120a及第二晶片130a與基板110a的接合。之後，形成第三凸塊170於第一晶片120a的第一矽穿孔124及第二晶片130a的第二矽穿孔134上，最後，進行橋接器140a與第一晶片120a及第二晶片130a的接合。
由於本實施例的第一凸塊150以及第二凸塊160具有相同尺寸，因此第一晶片120a與第二晶片130a與基板110a組裝時，無須考慮連接的凸塊大小，可具有較高的組裝良率，進而可提升晶片封裝結構100a的結構可靠度。另外，焊球175設置於基板110a的第二表面113上且與基板110a電性連接，其中晶片封裝結構100a可透過焊球175與外部電路電性連接。
簡言之，在本實施例的晶片封裝結構100a中，第一凸塊150與第二凸塊160具有相同尺寸，因此可提高第一晶片120a與第二晶片130a在組裝上的良率，進而使得本實施例的晶片封裝結構100a可具有較佳的結構可靠度。此外，若第一晶片120a的性質不同於第二晶片130a的性質，則表示本實施例的晶片封裝結構100a可將異質整合於單一模組內。
在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。
圖2是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。請同時參考圖1與圖2，本實施例的晶片封裝結構100b與圖1的晶片封裝結構100a相似，兩者的差異在於：本實施例的晶片封裝結構100b還包括一第一重配置線路層RDL1。第一重配置線路層RDL1配置於基板110b的第一表面111上，且位於第一晶片120a與基板110b之間以及第二晶片130a與基板110b之間。第一重配置線路層RDL1覆蓋基板110b的第一表面111及接墊112，且第一晶片120a透過第一凸塊150及第一重配置線路層RDL1與基板110b電性連接。第二晶片130a透過第二凸塊160及第二重配置線路層RDL2與基板110b電性連接。再者，如圖2所示，本實施例的晶片封裝結構100b還可包括一第二重配置線路層RDL2。第二重配置線路層RLD2配置於基板110b的第二表面113上，且位於基板110b與焊球175之間。焊球175透過第二重配置線路層RLD2與基板110b電性連接。
此外，本實施例的基板110b還包括至少一導電通孔116（示意地繪示多個導電通孔116），其中導電通孔116電性連接第一重配置線路層RDL1與第二重配置線路層RDL2。此外，如圖2所示，本實施例的晶片封裝結構100b更包括一晶片組180。晶片組180配置於橋接器140b上，且透過橋接器140b及第三凸塊170與第一晶片120a的第一矽穿孔124電性連接。另外，本實施例的晶片封裝結構100b可更包括一整合式被動元件190，其中整合式被動元件190配置於橋接器140b上，且透過橋接器140b及第三凸塊170與第二晶片130a的第二矽穿孔134電性連接。此處，第一晶片120a的性質與第二晶片130a的性質相同，其中第一晶片120a與第二晶片130a例如皆可為邏輯晶片、射頻晶片、記憶體或片上網路(network-on-chip，NoC)的系統級單晶片(SoC)，但不以此為限。
簡言之，本實施例的晶片封裝結構100b是透過第一晶片120a的第一矽穿孔124以及第二晶片130a的第二矽穿孔134，來達到將晶片組180以及整合式被動元件190異質整合至單一模組內。
圖3是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。請同時參考圖1與圖3，本實施例的晶片封裝結構100c與圖1的晶片封裝結構100a相似，兩者的差異在於：在本實施例中，第一凸塊150的尺寸、第二凸塊160的尺寸以及第三凸塊170的尺寸相同。再者，本實施例的晶片封裝結構100c更包括一第一重配置線路層RLD1。第一重配置線路層RDL1配置於基板110b的第一表面111上，且橋接器140c與第一重配置線路層RLD1位於第一晶片120c與基板110b之間以及第二晶片130c與基板110b之間。更進一步來說，本實施例的橋接器140c是內埋於第一重配置線路層RDL1內，可降低晶片封裝結構100c整體的厚度。第一晶片120c透過第一凸塊150及第一重配置線路層RDL1與基板110b電性連接。再者，本實施例的晶片封裝結構100c還包括一第二重配置線路層RDL2，其中第二晶片130c透過第二凸塊160及第二重配置線路層RDL2與基板110b電性連接。此處，如圖3所示，第一晶片120c與第二晶片130c皆無設置矽穿孔結構。第二重配置線路層RDL2配置於基板110b的第二表面113上，且位於基板110b與焊球175之間。焊球175透過第二重配置線路層RDL2與基板110b電性連接。此外，本實施例的基板110b還包括至少一第一導電通孔116（示意地繪示多個導電通孔116），電性連接第一重配置線路層RDL1與第二重配置線路層RDL2。
在製程上，第一凸塊150、第二凸塊160及第三凸塊170會先形成在第一晶片120c與第二晶片130c上，接著，進行第一晶片120c及第二晶片130c與基板110b及橋接器140c的接合。由於第一凸塊150、第二凸塊160以及第三凸塊170具有相同尺寸，因此第一晶片120c與第二晶片130c與基板110b及橋接器140c組裝時，無須考慮連接的凸塊大小，可具有較高的組裝良率，進而可提升晶片封裝結構100c的結構可靠度。
圖4是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。請同時參考圖3與圖4，本實施例的晶片封裝結構100d與圖3的晶片封裝結構100c相似，兩者的差異在於：在本實施例中，橋接器140d是配置於第一重配置線路層RDL1上。
圖5是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。請同時參考圖3與圖5，本實施例的晶片封裝結構100e與圖3的晶片封裝結構100c相似，兩者的差異在於：在本實施例中，第一重配置線路層RDL1’包括至少一第二導電通孔T（示意地繪示二個導電通孔T），其中第二導電通孔T電性連接橋接器140c與基板110b的接墊112。也就是說，本實施例的基板110b可透過第二導電通孔T與橋接器140c電性連接，可提升設計靈活度。
圖6是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。請同時參考圖4與圖6，本實施例的晶片封裝結構100f與圖4的晶片封裝結構100d相似，兩者的差異在於：第一重配置線路層RDL1’包括至少一第二導電通孔T（示意地繪示二個導電通孔T），其中第二導電通孔T電性連接橋接器140d與基板110b的接墊112。也就是說，本實施例的基板110b可透過第二導電通孔T與橋接器140d電性連接，可提升設計靈活度。
綜上所述，在本發明的晶片封裝結構中，在每個晶片與基板之間的凸塊大小相同，意即第一凸塊與第二凸塊具有相同尺寸，因此可提高晶片在組裝上的良率，進而使得本發明的晶片封裝結構可具有較佳的結構可靠度。再者，第三凸塊的尺寸可依據橋接器的配置位置而與第一凸塊的尺寸可相同或不同。若第三凸塊的尺寸與第一凸塊的尺寸相同，則當第一晶片與第二晶片與基板及橋接器組裝時，無須考慮連接的凸塊大小，可具有較高的組裝良率，進而可提升晶片封裝結構的結構可靠度。此外，第一晶片的性質與第二晶片的性質可不相同，而使本發明的晶片封裝結構達到異質整合的效果。另外，除了第一晶片與第二晶片（例如是兩個邏輯晶片）之外，亦可設置晶片組及整合式被動元件於橋接器上，且透過橋接器及晶片上的矽穿孔來電性連接，以使本發明的晶片封裝結構達到異質整合的效果。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100a、100b、100c、100d、100e、100f:晶片封裝結構 110a、110b:基板 111:第一表面 112、114:接墊 113:第二表面 116:導電通孔 120a、120c:第一晶片 121:第一主動表面 122:第一接墊 124:第一矽穿孔 130a、130c:第二晶片 131:第二主動表面 132:第二接墊 134:第二矽穿孔 140a、140b、140c、140d:橋接器 142a:高分子聚合物層 144a:接墊層 146a:圖案化線路層 148a:導電通孔 150:第一凸塊 160:第二凸塊 170:第三凸塊 175:焊球 180:晶片組 190:整合式被動元件 RDL1、RDL1’:第一重配置線路層 RDL2:第二重配置線路層 T:第二導電通孔
圖1是依照本發明的一實施例的一種晶片封裝結構的剖面示意圖。 圖2是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。 圖3是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。 圖4是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。 圖5是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。 圖6是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。
100a:晶片封裝結構
110a:基板
111:第一表面
112、114:接墊
113:第二表面
120a:第一晶片
121:第一主動表面
122:第一接墊
124:第一矽穿孔
130a:第二晶片
131:第二主動表面
132:第二接墊
134:第二矽穿孔
140a:橋接器
142a:高分子聚合物層
144a:接墊層
146a:圖案化線路層
148a:導電通孔
150:第一凸塊
160:第二凸塊
170:第三凸塊
175:焊球

Claims (11)

  1. 一種晶片封裝結構，包括：一基板，具有彼此相對的一第一表面與一第二表面；一第一晶片，配置於該基板的該第一表面上，且具有朝向該第一表面的一第一主動表面，以及包括配置於該第一主動表面上的多個第一接墊；一第二晶片，配置於該基板的該第一表面上，且具有朝向該第一表面的一第二主動表面，以及包括配置於該第二主動表面上的多個第二接墊；一橋接器，包括一高分子聚合物層以及位於該高分子聚合物層上的一接墊層；多個第一凸塊，配置於該第一晶片與該基板之間，其中該第一晶片透過該些第一凸塊與該基板電性連接；多個第二凸塊，配置於該第二晶片與該基板之間，其中該第二晶片透過該些第二凸塊與該基板電性連接，其中該些第一凸塊與該些第二凸塊具有相同尺寸；多個第三凸塊，配置於該第一晶片與該橋接器之間以及該第二晶片與該橋接器之間，其中該第一晶片與該第二晶片分別透過該些第三凸塊與該橋接器的該接墊層電性連接，該第一晶片包括至少一第一矽穿孔，而該第二晶片包括至少一第二矽穿孔，該第一晶片與該第二晶片位於該橋接器與該基板之間，且該橋接器透過該些第三凸塊與該至少一第一矽穿孔及該至少一第二矽穿孔電性連接；以及 多個焊球，設置於該基板的該第二表面上且與該基板電性連接。
  2. 如請求項1所述的晶片封裝結構，其中該些第三凸塊的尺寸與該些第一凸塊的尺寸相同。
  3. 如請求項1所述的晶片封裝結構，其中該些第三凸塊的尺寸與該些第一凸塊的尺寸不同。
  4. 如請求項1所述的晶片封裝結構，其中該橋接器於該基板上的正投影部分重疊於該第一晶片與該第二晶片於該基板上的正投影。
  5. 如請求項1所述的晶片封裝結構，更包括：一第一重配置線路層，配置於該基板的該第一表面上，且位於該第一晶片與該基板之間以及該第二晶片與該基板之間，其中該第一晶片透過該些第一凸塊及該第一重配置線路層與該基板電性連接。
  6. 如請求項5所述的晶片封裝結構，更包括：一第二重配置線路層，配置於該基板的該第二表面上，且位於該基板與該些焊球之間，該些焊球透過該第二重配置線路層與該基板電性連接，其中該基板包括至少一導電通孔，電性連接該第一重配置線路層與該第二重配置線路層，而該第二晶片透過該些第二凸塊及該第二重配置線路層與該基板電性連接。
  7. 如請求項5所述的晶片封裝結構，更包括：一晶片組，配置於該橋接器上，且透過該橋接器及該些第三凸塊與該第一晶片的該至少一第一矽穿孔電性連接。
  8. 如請求項5所述的晶片封裝結構，更包括： 一整合式被動元件，配置於該橋接器上，且透過該橋接器及該些第三凸塊與該第二晶片的該至少一第二矽穿孔電性連接。
  9. 一種晶片封裝結構，包括：一基板，具有彼此相對的一第一表面與一第二表面；一第一晶片，配置於該基板的該第一表面上，且具有朝向該第一表面的一第一主動表面，以及包括配置於該第一主動表面上的多個第一接墊；一第二晶片，配置於該基板的該第一表面上，且具有朝向該第一表面的一第二主動表面，以及包括配置於該第二主動表面上的多個第二接墊；一橋接器，包括一高分子聚合物層以及位於該高分子聚合物層上的一接墊層；多個第一凸塊，配置於該第一晶片與該基板之間，其中該第一晶片透過該些第一凸塊與該基板電性連接；多個第二凸塊，配置於該第二晶片與該基板之間，其中該第二晶片透過該些第二凸塊與該基板電性連接，其中該些第一凸塊與該些第二凸塊具有相同尺寸；多個第三凸塊，配置於該第一晶片與該橋接器之間以及該第二晶片與該橋接器之間，其中該第一晶片與該第二晶片分別透過該些第三凸塊與該橋接器的該接墊層電性連接；多個焊球，設置於該基板的該第二表面上且與該基板電性連接；以及一第一重配置線路層，配置於該基板的該第一表面上，且該橋接器與該第一重配置線路層位於該第一晶片與該基板之間以及 該第二晶片與該基板之間，其中該第一晶片透過該些第一凸塊及該第一重配置線路層與該基板電性連接，該第一重配置線路層包括至少一導電通孔，電性連接該橋接器與該基板。
  10. 如請求項9所述的晶片封裝結構，更包括：一第二重配置線路層，配置於該基板的該第二表面上，且位於該基板與該些焊球之間，該些焊球透過該第二重配置線路層與該基板電性連接，其中該基板包括至少一第一導電通孔，電性連接該第一重配置線路層與該第二重配置線路層，而該第二晶片透過該些第二凸塊及該第二重配置線路層與該基板電性連接。
  11. 如請求項9所述的晶片封裝結構，其中該橋接器內埋於該第一重配置線路層或者是配置於該第一重配置線路層上。
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