Nothing Special   »   [go: up one dir, main page]

TWI721898B - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

Info

Publication number
TWI721898B
TWI721898B TW109118412A TW109118412A TWI721898B TW I721898 B TWI721898 B TW I721898B TW 109118412 A TW109118412 A TW 109118412A TW 109118412 A TW109118412 A TW 109118412A TW I721898 B TWI721898 B TW I721898B
Authority
TW
Taiwan
Prior art keywords
package structure
semiconductor package
thermal interface
bonding layer
interface material
Prior art date
Application number
TW109118412A
Other languages
English (en)
Other versions
TW202101617A (zh
Inventor
謝亞叡
許家豪
陳泰宇
許耀邦
Original Assignee
聯發科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯發科技股份有限公司 filed Critical 聯發科技股份有限公司
Publication of TW202101617A publication Critical patent/TW202101617A/zh
Application granted granted Critical
Publication of TWI721898B publication Critical patent/TWI721898B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/0566—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/29191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

提供了一種半導體封裝結構。半導體封裝結構包括：基板，半導體裸晶，成型材料，第一接合層和熱接口材料。半導體裸晶被設置在基板的上方。成型材料環繞半導體裸晶。第一接合層被設置在半導體裸晶的上方。熱接口材料被設置在成型材料的上方。

Description

半導體封裝結構
本發明涉及一種半導體封裝結構，尤其涉及一種具有熱接口材料（thermal interface material）的半導體封裝結構。
半導體封裝結構不僅能夠給半導體裸晶（semiconductor die）提供免受環境污染物侵害的保護，而且還能夠在封裝於其中的半導體裸晶與諸如印刷電路板（printed circuit board，PCB）的基板之間提供電連接。
在半導體裸晶的操作期間會產生熱量。如果沒有充分除去熱量，則升高的溫度會損壞半導體組件，並會導致熱應力和半導體封裝結構的彎曲（warpage）。
需要將散熱裝置（heat dissipation device）設置在半導體封裝結構中。散熱器/散熱片（heatsink）通常用於散發熱量。熱接口材料被設置在半導體裸晶和散熱器之間，以促進熱量從半導體裸晶傳遞到散熱器。然而，儘管半導體封裝結構中的現有散熱裝置通常能夠滿足要求，但是它們並不是在各個方面都令人滿意，因此，需要進一步的改進以提高散熱效率。
本發明提供了一種半導體封裝結構。半導體封裝結構的示例性實施例包括：基板，半導體裸晶，成型材料，第一接合層和熱接口材料。半導體裸晶被設置在基板的上方。成型材料環繞半導體裸晶。第一接合層被設置在半導體裸晶的上方。熱接口材料被設置在成型材料的上方。
在一些實施例中，該半導體封裝結構還包括：第一散熱器，被設置在該第一接合層的上方。
在一些實施例中，該熱接口材料連接該成型材料和該第一散熱器。
在一些實施例中，該熱接口材料是粘合劑。
在一些實施例中，該熱接口材料環繞該第一接合層。
在一些實施例中，該熱接口材料和該第一接合層被間隙間隔開。
在一些實施例中，該半導體封裝結構還包括：金屬層，被設置在該第一接合層和該半導體裸晶之間。
在一些實施例中，該熱接口材料具有至少一個凹口。
在一些實施例中，該熱接口材料被至少一個缺口切斷。
在一些實施例中，該熱接口材料部分地環繞該第一接合層。
在一些實施例中，該半導體封裝結構還包括：導電元件，被設置在該半導體裸晶和該基板之間。
在一些實施例中，該半導體封裝結構還包括：被設置在該基板下方的第二散熱器，其中，該第二散熱器透過第二接合層接合至該基板。
在一些實施例中，該第二散熱器是在接合該第一散熱器之前被接合的，以及，該第一接合層的熔點低於該第二接合層的熔點。
在一些實施例中，該第一接合層包括SnBi，SnBiAg或其組合。
在一些實施例中，該熱接口材料比該金屬層厚並且比該接合層厚。
在一些實施例中，該熱接口材料的側壁與該成型材料的側壁對準。
本發明內容並非旨在限定本發明，以及，本發明由申請專利範圍限定。在下面的詳細描述中描述其它實施例和優點。
以下描述為本發明實施的較佳實施例。以下實施例僅用來例舉闡釋本發明的技術特徵，並非用來限制本發明的範疇。在通篇說明書及申請專利範圍當中使用了某些詞彙來指稱特定的組件。所屬技術領域中具有通常知識者應可理解，製造商可能會用不同的名詞來稱呼同樣的組件。本說明書及申請專利範圍並不以名稱的差異來作為區別組件的方式，而係以組件在功能上的差異來作為區別的基準。本發明的範圍應當參考后附的申請專利範圍來確定。在以下描述和申請專利範圍當中所提及的術語“包含”和“包括”為開放式用語，故應解釋成“包含，但不限定於…”的意思。此外，術語“耦接”意指間接或直接的電氣連接。因此，若文中描述一個裝置耦接至另一裝置，則代表該裝置可直接電氣連接於該另一裝置，或者透過其它裝置或連接手段間接地電氣連接至該另一裝置。
參考特定實施例並且參考某些附圖描述了本發明，但是本發明不限於此，而是僅由申請專利範圍限制。所描述的附圖僅是示意性的而非限制性的。在附圖中，出於說明的目的，一些元件的尺寸可能被放大且未按比例繪製。在本發明的實踐中，尺寸和相對尺寸不對應於實際尺寸。文中所用術語“基本”或“大致”係指在可接受的範圍內，所屬技術領域中具有通常知識者能夠解決所要解決的技術問題，基本達到所要達到的技術效果。舉例而言，“基本等於”係指在不影響結果正確性時，所屬技術領域中具有通常知識者能夠接受的與“完全等於”有一定誤差的方式。
第1圖是根據本發明一些實施例的半導體封裝結構100的截面圖。附加的特徵可以被添加至半導體封裝結構100。對於不同的實施例，可以替換或消除以下描述的一些特徵。為了簡化該圖，在第1圖中僅示出了半導體封裝結構100的一部分。
如第1圖所示，根據一些實施例，基板（substrate）102被提供。基板102可以是無核芯/核芯基板（coreless/core substrate）或印刷電路板（PCB）。基板102可以由聚丙烯（polypropylene，PP），聚酰亞胺（Polyimide），BT/環氧樹脂（BT/Epoxy），預浸料（Prepreg），ABF，陶瓷材料（ceramic material）或其它合適的材料形成。任何期望的半導體元件（element）可以被形成在基板102之中和之上（in and on）。然而，為了簡化附圖，僅示出了平坦的（flat）基板102。
半導體封裝結構100包括半導體裸晶106，半導體裸晶106被設置在基板102的上方（over）。為了簡化起見，根據一些實施例，第1圖僅示出了一個半導體裸晶106，但本發明並不限於此。例如，在一些實施例中，可以將多個半導體裸晶106設置在基板102的上方且該多個半導體裸晶被並排（side-by-side）佈置。在一些實施例中，半導體裸晶106是主動裝置（active device）。例如，半導體裸晶106是片上系統（system-on-chip，SOC）裸晶，其可以包括微控制器（microcontroller，MCU），微處理器（microprocessor，MPU），電源管理集成電路（power management integrated circuit，PMIC），全球定位系統（global positioning system，GPS）裝置，或射頻（radio frequency，RF）裝置等或其任意組合。可選地，半導體裸晶106可以是類比裸晶，其可以包括中央處理單元（central processing unit，CPU），圖形處理單元（graphics processing unit，GPU），動態隨機存取記憶體（dynamic random access memory，DRAM）控制器等或其任意組合。在一些其它實施例中，一個或多個被動裝置（諸如電阻器，電容器，電感器等或其組合）也可以被接合至（bonded onto）基板102上。
根據一些實施例，半導體封裝結構100包括：環繞（surrounding）半導體裸晶106的成型材料（molding material）108。成型材料108鄰接（adjoin）半導體裸晶106的側壁。儘管第1圖的示例使得半導體裸晶106的上表面被露出，但是，在一些實施例中，半導體裸晶106的上表面也可以被成型材料108覆蓋，本發明對此不做限制。
在一些實施例中，成型材料108包括非導電材料，諸如環氧樹脂，樹脂，可成型聚合物或另一種合適的成型材料。在一些實施例中，成型材料108被作為大量液體（substantial liquid）應用，然後通過化學反應被固化。在一些其它實施例中，成型材料108是作為凝膠或可延展的固體應用的紫外線（an ultraviolet，UV）或熱固化的聚合物，然後通過紫外線或熱固化工藝來固化。可以用模具（未示出）來固化成型材料108。
如第1圖所示，根據一些實施例，半導體裸晶106和成型材料108通過導電元件104接合至基板102上。在一些實施例中，導電元件104包括導電球結構，導電柱結構或導電膠結構（conductive paste structures），其在接合工藝（bonding process）中被安裝在基板102上並電耦接至基板102。例如，導電元件104可以是觸點柵格陣列（land grid array，LGA），球形柵格陣列（ball grid array，BGA）等或它們的組合。
如第1圖所示，根據一些實施例，半導體封裝結構100包括散熱器（heatsink）122，散熱器122通過熱接口材料（thermal interface material）120接合至半導體裸晶106。散熱器122可以由Cu，Al等或其組合製成。熱接口材料120可包括聚合物，例如，該聚合物為粘合劑（adhesive）。例如，熱接口材料120可以是矽酮粘合劑，諸如來自Dow-Corning的SE4450環氧樹脂。在其它示例中，熱接口材料120還可以包括陶瓷材料，例如晶體氧化物，氮化物或碳化物材料。
然而，在一些實施例中，當僅使用熱接口材料120連接散熱器122和半導體裸晶106時，會發生副作用（side effects）。通常，具有高粘度的熱接口材料120具有低導熱率。因此，熱接口材料120是半導體裸晶106和散熱器122之間的熱瓶頸（thermal bottleneck）。因此，本發明提供了解決上述問題的另一實施例。
第2圖是根據本發明的一些其它實施例的半導體封裝結構200的截面圖。應當注意，半導體封裝結構200包括與第1圖所示的半導體封裝結構100相同或相似的組件，為了簡單起見，將不再詳細討論那些組件。與第1圖（僅通過熱接口材料120將散熱器122接合至半導體裸晶106）的實施例相比，以下實施例將用接合層（bonding layer）代替熱接口材料120的一部分，以提高散熱效率。
可以將附加特徵添加到半導體封裝結構200。對於不同的實施例，可以替換或消除以下描述的一些特徵。為了簡化該圖，在第2圖中僅示出了半導體封裝結構200的一部分。
如第2圖所示，根據一些實施例，可選的金屬層（metal layer）124被設置（is disposed on）在半導體裸晶106上，以提供用於在其上形成接合層的表面。例如，通過背面金屬化（backside metallization，BSM）技術，在半導體裸晶106上形成金屬層124。在一些實施例中，金屬層124可通過化學氣相沉積，濺射沉積，電鍍等或其組合形成。金屬層124可以包括金，銀，鉻，鈦，鎢，釩，鎳等，其合金或它們的組合。金屬層124還可包括不銹鋼（backside metallization，SUS）材料。金屬層124可以是單層或多層。
儘管如圖所示，半導體裸晶106與成型材料108共平面（coplanar），但是本發明不限於此。例如，在一些實施例中，成型材料108是在形成金屬層124之後形成的，以及，成型材料108也環繞金屬層124。在這些實施例中，成型材料108與金屬層124共平面。
如第2圖所示，根據一些實施例，接合層126被設置在金屬層124上。接合層126可以包括金屬或焊接材料（metal or solder material）。例如，接合層126可以是鉛，錫，銦，銀，銅等，其合金或它們的組合。由於接合層126具有比熱接口材料120更好的導熱率，例如是熱接口材料120的導熱率的10倍，因此，通過設置接合層126能夠提高散熱效率。
然而，如果只有接合層126被用來將散熱器122接合至半導體裸晶106，則應力會很高。在這種情況下，在諸如表面安裝技術（surface mount technology，SMT）的順序工藝中，接合層126是易碎的，從而造成產量損失。因此，根據本發明的半導體封裝結構200包括熱接口材料120和接合層126這兩者，從而在不增加應力的情況下提高了散熱效率，這對於大功率應用是優選的。因此，熱性能、可製造性和可靠性能夠被同時提高。
如第2圖所示，在一些實施例中，熱接口材料120位於成型材料108的上方，以及，金屬層124和接合層126位於半導體裸晶106的上方。根據一些實施例，散熱器122通過熱接口材料120連接至成型材料108，以及，散熱器122通過金屬層124和接合層126連接至半導體裸晶106。熱接口材料120被設置在成型材料108的邊緣（edge）上。特別地，熱接口材料120的側壁與成型材料108的側壁對準（align）。
在一些實施例中，熱接口材料120與金屬層124、接合層126間隔開一間隙（gap），以防止由熱接口材料120與金屬層124、接合層126的熱膨脹係數（CTE）的不同引起的問題。因此，半導體封裝結構的可靠性能夠被提高。例如，熱接口材料120與金屬層124、接合層126之間間隔開的該間隙環繞金屬層124、接合層126。
在一些實施例中，熱接口材料120比金屬層124厚並且比接合層126厚，以提供用於在其上接合散熱器122的平坦表面（planar surface）。可選地，如上所述，在一些其它實施例中（例如，成型材料108在設置金屬層124之後形成的實施例中），成型材料108與金屬層124共平面。在這些實施例中，熱接口材料120的厚度基本等於接合層126的厚度，以提供用於將散熱器122接合在其上的平坦平面。
第3A圖至第3B圖是根據本發明一些實施例的半導體封裝結構的俯視圖（plan view）。應該注意的是，第3A圖至第3B圖是從第2圖所示的半導體封裝結構200的頂部看的俯視圖，為簡潔起見，省略了一些組件。
如第3A圖所示，根據一些實施例，熱接口材料120環繞接合層126。儘管未示出，但是熱接口材料120也環繞被設置在接合層126下方的金屬層124（參考第2圖）。熱接口材料120被設置在成型材料108的邊緣上。熱接口材料120的側壁可以與成型材料108的側壁對準。
在一些實施例中，熱接口材料120與金屬層124、接合層126間隔開一間隙，以防止由熱接口材料120與金屬層124、接合層126的熱膨脹係數（CTE）的不同引起的問題。因此，可以提高半導體封裝結構的可靠性。
在第3A圖所示的實施例中，熱接口材料120完全圍繞接合層126，或者，完全圍繞接合層126和金屬層124。例如，第3A圖示出了成型材料120呈類“回”字形的結構示意圖，但本發明并不限於此。根據一些實施例，熱接口材料120可以部分地環繞（partially surrounds）接合層126，如第3B圖所示。儘管未示出，但是在一些實施例中，熱接口材料120也可以部分地環繞被設置在接合層126下方的金屬層124。換句話說，在一些實施例中，熱接口材料120被缺口（gap）132切斷（cut off）。缺口132可以釋放在製造過程中產生的氣體。因此，半導體封裝結構的可靠性能夠被進一步提高。
儘管在第3B圖中示出了僅一個缺口132，但本發明不限於此。例如，熱接口材料120可以被類似於缺口132的多個缺口切斷。特別地，熱接口材料120可以包括多個分開/分離/獨立的部分（separate sections）。
在一些實施例中，代替被缺口132切斷，熱接口材料120可具有凹口（notch）（未示出）以釋放氣體。在其它實施例中，熱接口材料120被一個或多個缺口132和/或一個或多個凹口切斷。在本發明實施例中，熱接口材料120具有至少一個缺口/凹口，其中，缺口132和所述凹口的設置均是為了釋放製造過程中產生的氣體，以進一步提高半導體封裝結構的可靠性。
第4圖是根據本發明一些其它實施例的半導體封裝結構300的截面圖。應當注意，半導體封裝結構300包括與第2圖所示的半導體封裝結構200相同或相似的組件，為了簡單起見，將不再詳細討論那些組件。與第2圖（熱接口材料120被設置在成型材料108的邊緣上）的實施例相比，熱接口材料120被設置在成型材料108的外圍（periphery）上。特別地，熱接口材料120的側壁在成型材料108的側壁的內側/裡面（inside）。或者說，熱接口材料120的外側壁不與成型材料108的外側壁對準（第2圖示出了對準的示例）。例如，熱接口材料120的外側壁比成型材料108的外側壁更靠近裡面。
第5A圖至第5C圖是根據本發明一些實施例的半導體封裝結構的俯視圖。應該注意的是，第5A圖至第5C圖是從第4圖所示的半導體封裝結構300的頂部看的俯視圖，為了簡潔起見，一些組件被省略。
如第5A圖所示，根據一些實施例，熱接口材料120環繞接合層126。儘管未示出，但是熱接口材料120也可以環繞被設置在接合層126下方的金屬層124（參考第4圖）。熱接口材料120可以被設置在成型材料108的外圍（periphery）上。
在一些實施例中，熱接口材料120與金屬層124、接合層126通過間隙間隔開，以防止由熱接口材料120與金屬層124、接合層126的熱膨脹係數（CTE）的不同引起的問題。因此，半導體封裝結構的可靠性能夠被提高。
如第5B圖所示，根據一些實施例，熱接口材料120部分地環繞接合層126。儘管未示出，但是在一些實施例中，熱接口材料120也可以部分地環繞被設置在接合層126下方的金屬層124。換句話說，在一些實施例中，熱接口材料120被缺口132切斷。缺口132可以釋放在製造過程中產生的氣體。因此，可以進一步提高半導體封裝結構的可靠性。
儘管在第5B圖中示出了僅一個缺口132，但是本發明不限於此。例如，熱接口材料120可以被多個缺口切斷，如第5C圖所示。特別地，熱接口材料120可以包括多個獨立的部分（separate sections）。
在一些實施方式中，代替被缺口切斷，熱接口材料120具有凹口（未示出）以釋放氣體。在其它實施例中，熱接口材料120被一個或多個缺口132和/或一個或多個凹口切斷。
第6圖是根據本發明一些其它實施例的半導體封裝結構400的截面圖。應當注意，半導體封裝結構400包括與半導體封裝結構200相同或相似的部件，為了簡單起見，將不再詳細討論那些部件。與第2圖的（散熱器122被設置在基板102的上方）實施例相比，以下實施例還提供了另一散熱器，該另一散熱器被設置在基板102的下方，以進一步提高散熱效率。
如第6圖所示，根據一些實施例，半導體封裝結構400包括：被設置在基板102的相對側（opposite sides）上的散熱器122和散熱器130。散熱器130通過接合層128接合到至基板102。接合層128可以包括金屬或焊接材料。例如，接合層128可以是鉛，錫，銦，銀，銅等，其合金或它們的組合。儘管僅示出了兩個散熱器（散熱器122和散熱器130），但是根據需要，本發明可以包括兩個以上的散熱器。
在一實施例中，散熱器130是在接合散熱器122之前被接合的。在該實施例中，如果接合散熱器122時的溫度高於或基本等於接合層128的熔點（opposite sides），則在諸如回流（reflow）的過程中，接合層128將熔化並導致散熱器130掉落。就這一點而言，根據一些實施例，具有比接合層128的熔點低的接合層126（接合層126的熔點低於接合層128的熔點）能夠防止該問題。例如，接合層126可以包括SnBi，SnBiAg等或其組合。
類似地，可以基於工藝順序來調整接合層的組成。例如，如果散熱器122是在接合散熱器130之前被接合的，則用於接合散熱器130的接合層128的熔點低於用於接合散熱器122的接合層126的熔點。因此，半導體封裝結構400的可靠性能夠被提高。
綜上，本發明提供了一種半導體封裝結構，其包括用於將散熱器接合至基板的接合層和熱接口材料，從而，能夠在不增加應力的情況下提高散熱效率。因此，半導體封裝結構的熱性能，可製造性和可靠性能夠被同時提高。
此外，根據一些實施例，熱接口材料和接合層通過間隙間隔開以防止CTE不匹配。另外，根據一些實施例，被一個或多個缺口切斷的熱接口材料和/或具有一個或多個凹口的熱接口材料（熱接口材料部分圍繞接合層126，或者，部分圍繞接合層126和金屬層124）可以釋放在製造過程中產生的氣體。
此外，在一些實施例中，半導體封裝結構具有位於相對側上的多個散熱器，以進一步提高散熱效率。在將一散熱器接合至基板之後將另一個散熱器接合至半導體裸晶的實施例中，用於前者的接合層的熔點低於用於後者的接合層的熔點是優選的。因此，在工藝期間能夠減少散熱器掉落的風險，從而提高了半導體封裝結構的可靠性。
可以對本發明的實施例做出許多變化和/或修改。根據本發明的一些實施例的半導體封裝結構可以用於形成三維（three-dimensional，3D）封裝，2.5D封裝，扇出式封裝或另一種合適的封裝。
雖然已經對本發明實施例及其優點進行了詳細說明，但應當理解的係，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更，例如，可以通過結合不同實施例的若干部分來得出新的實施例。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。所屬技術領域中具有通常知識者皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。
100、200、300、400:半導體封裝結構 122、130:散熱器 120:熱接口材料 108:成型材料 104:導電元件 106:半導體裸晶 102:基板 124:金屬層 126、128:接合層 132:缺口
通過閱讀後續的詳細描述和實施例可以更全面地理解本發明，該實施例參照附圖給出。 第1圖是根據本發明一些實施例的半導體封裝結構的截面圖。 第2圖是根據本發明一些其它實施例的半導體封裝結構的截面圖。 第3A圖至第3B圖是根據本發明一些實施例的半導體封裝結構的俯視圖。 第4圖是根據本發明一些其它實施例的半導體封裝結構的截面圖。 第5A圖至第5C圖是根據本發明一些實施例的半導體封裝結構的俯視圖。 第6圖是根據本發明一些其它實施例的半導體封裝結構的截面圖。
在下面的詳細描述中，為了說明的目的，闡述了許多具體細節，以便所屬技術領域中具有通常知識者能夠更透徹地理解本發明實施例。然而，顯而易見的是，可以在沒有這些具體細節的情況下實施一個或複數個實施例，不同的實施例或不同實施例中披露的不同特徵可根據需求相結合，而並不應當僅限於附圖所列舉的實施例。
200:半導體封裝結構
122:散熱器
120:熱接口材料
108:成型材料
104:導電元件
106:半導體裸晶
102:基板
124:金屬層
126:接合層

Claims (14)

  1. 一種半導體封裝結構，包括：基板；半導體裸晶，被設置在該基板的上方；環繞該半導體裸晶的成型材料；第一接合層，被設置在該半導體裸晶的上方；以及，熱接口材料，被設置在該成型材料的上方，其中，該熱接口材料和該第一接合層間隔開一間隙。
  2. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該半導體封裝結構還包括：第一散熱器，被設置在該第一接合層的上方。
  3. 根據申請專利範圍第2項所述的半導體封裝結構，其中，該熱接口材料連接該成型材料和該第一散熱器。
  4. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該熱接口材料是粘合劑。
  5. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該熱接口材料環繞該第一接合層。
  6. 根據申請專利範圍第1項或第2項所述的半導體封裝結構，其中，該半導體封裝結構還包括：金屬層，被設置在該第一接合層和該半導體裸晶之間。
  7. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該熱接口材料具有至少一個凹口；或者，該熱接口材料被至少一個缺口切斷。
  8. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該熱接口材料部分地環繞該第一接合層。
  9. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該半導體封裝結構還包括：導電元件，被設置在該半導體裸晶和該基板之間。
  10. 根據申請專利範圍第2項所述的半導體封裝結構，其中，該半導體封裝結構還包括：被設置在該基板下方的第二散熱器，其中，該第二散熱器透過第二接合層接合至該基板。
  11. 根據申請專利範圍第10項所述的半導體封裝結構，其中，該第二散熱器是在接合該第一散熱器之前被接合的，以及，該第一接合層的熔點低於該第二接合層的熔點。
  12. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該第一接合層包括SnBi，SnBiAg或其組合。
  13. 根據申請專利範圍第6項所述的半導體封裝結構，其中，該熱接口材料比該金屬層厚並且比該接合層厚。
  14. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該熱接口材料的側壁與該成型材料的側壁對準。
TW109118412A 2019-06-14 2020-06-02 半導體封裝結構 TWI721898B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201962861379P 2019-06-14 2019-06-14
US62/861,379 2019-06-14
US202062985371P 2020-03-05 2020-03-05
US62/985,371 2020-03-05
US16/881,206 US11621211B2 (en) 2019-06-14 2020-05-22 Semiconductor package structure
US16/881,206 2020-05-22

Publications (2)

Publication Number Publication Date
TW202101617A TW202101617A (zh) 2021-01-01
TWI721898B true TWI721898B (zh) 2021-03-11

Family

ID=71092245

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109118412A TWI721898B (zh) 2019-06-14 2020-06-02 半導體封裝結構

Country Status (4)

Country Link
US (1) US11621211B2 (zh)
EP (1) EP3751603B1 (zh)
CN (1) CN112086414A (zh)
TW (1) TWI721898B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3138733A1 (fr) * 2022-08-03 2024-02-09 Stmicroelectronics (Grenoble 2) Sas Boîtier de circuit integre

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200606198A (en) * 2004-05-11 2006-02-16 Ibm Thermal interface adhesive and rework
TW200814255A (en) * 2006-06-02 2008-03-16 Sony Corp Semiconductor device having high cooling efficiency and method for manufacturing the same
TW200816423A (en) * 2006-06-16 2008-04-01 Sony Corp Semiconductor device and method for manufacturing the same
TW201507077A (zh) * 2013-03-26 2015-02-16 Tanaka Precious Metal Ind 半導體裝置及散熱機構
TW201820468A (zh) * 2016-08-31 2018-06-01 華為技術有限公司 半導體裝置及其製造方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2914342B2 (ja) 1997-03-28 1999-06-28 日本電気株式会社 集積回路装置の冷却構造
US5909056A (en) * 1997-06-03 1999-06-01 Lsi Logic Corporation High performance heat spreader for flip chip packages
JP2000114413A (ja) * 1998-09-29 2000-04-21 Sony Corp 半導体装置、その製造方法および部品の実装方法
AU1348901A (en) * 1999-10-28 2001-05-08 P1 Diamond, Inc. Improved diamond thermal management components
KR100446290B1 (ko) * 2001-11-03 2004-09-01 삼성전자주식회사 댐을 포함하는 반도체 패키지 및 그 제조방법
US6787899B2 (en) * 2002-03-12 2004-09-07 Intel Corporation Electronic assemblies with solidified thixotropic thermal interface material
US6767765B2 (en) 2002-03-27 2004-07-27 Intel Corporation Methods and apparatus for disposing a thermal interface material between a heat source and a heat dissipation device
US7408787B2 (en) * 2003-07-30 2008-08-05 Intel Corporation Phase change thermal interface materials including polyester resin
US7015577B2 (en) * 2004-07-21 2006-03-21 Advanced Semiconductor Engineering, Inc. Flip chip package capable of measuring bond line thickness of thermal interface material
US7755184B2 (en) 2004-12-03 2010-07-13 Chris Macris Liquid metal thermal interface material system
US7999369B2 (en) 2006-08-29 2011-08-16 Denso Corporation Power electronic package having two substrates with multiple semiconductor chips and electronic components
JP2010103244A (ja) 2008-10-22 2010-05-06 Sony Corp 半導体装置及びその製造方法
US8232636B2 (en) * 2010-01-26 2012-07-31 International Business Machines Corporation Reliability enhancement of metal thermal interface
WO2011092859A1 (ja) 2010-02-01 2011-08-04 トヨタ自動車株式会社 半導体装置の製造方法および半導体装置
US8804331B2 (en) * 2011-12-02 2014-08-12 Ati Technologies Ulc Portable computing device with thermal management
US9041192B2 (en) * 2012-08-29 2015-05-26 Broadcom Corporation Hybrid thermal interface material for IC packages with integrated heat spreader
FR3011067B1 (fr) * 2013-09-23 2016-06-24 Commissariat Energie Atomique Appareil comportant un composant fonctionnel susceptible d'etre en surcharge thermique lors de son fonctionnement et un systeme de refroidissement du composant
US9287233B2 (en) 2013-12-02 2016-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Adhesive pattern for advance package reliability improvement
US20150170989A1 (en) * 2013-12-16 2015-06-18 Hemanth K. Dhavaleswarapu Three-dimensional (3d) integrated heat spreader for multichip packages
US10269682B2 (en) 2015-10-09 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US10049896B2 (en) * 2015-12-09 2018-08-14 International Business Machines Corporation Lid attach optimization to limit electronic package warpage
EP3403279A4 (en) * 2016-01-11 2019-09-11 INTEL Corporation MULTICHIP HOUSING WITH MULTIPLE THERMAL INTERMEDIATES
US9918407B2 (en) * 2016-08-02 2018-03-13 Qualcomm Incorporated Multi-layer heat dissipating device comprising heat storage capabilities, for an electronic device
CN109148397B (zh) 2017-06-16 2023-02-28 日月光半导体制造股份有限公司 半导体装置封装
US10319609B2 (en) 2017-06-21 2019-06-11 International Business Machines Corporation Adhesive-bonded thermal interface structures
US10483187B2 (en) * 2017-06-30 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Heat spreading device and method
US10431517B2 (en) * 2017-08-25 2019-10-01 Advanced Micro Devices, Inc. Arrangement and thermal management of 3D stacked dies
US11817364B2 (en) 2018-06-25 2023-11-14 Intel Corporation BGA STIM package architecture for high performance systems
DE102018216593A1 (de) 2018-09-27 2020-04-02 Robert Bosch Gmbh Leistungshalbleitermodul
US11088109B2 (en) 2018-11-21 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with multi-thermal interface materials and methods of fabricating the same
CN209029362U (zh) * 2018-11-23 2019-06-25 北京比特大陆科技有限公司 芯片散热结构、芯片结构、电路板和超算设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200606198A (en) * 2004-05-11 2006-02-16 Ibm Thermal interface adhesive and rework
TW200814255A (en) * 2006-06-02 2008-03-16 Sony Corp Semiconductor device having high cooling efficiency and method for manufacturing the same
TW200816423A (en) * 2006-06-16 2008-04-01 Sony Corp Semiconductor device and method for manufacturing the same
TW201507077A (zh) * 2013-03-26 2015-02-16 Tanaka Precious Metal Ind 半導體裝置及散熱機構
TW201820468A (zh) * 2016-08-31 2018-06-01 華為技術有限公司 半導體裝置及其製造方法

Also Published As

Publication number Publication date
US11621211B2 (en) 2023-04-04
EP3751603B1 (en) 2024-10-09
EP3751603A3 (en) 2021-01-06
US20200395267A1 (en) 2020-12-17
CN112086414A (zh) 2020-12-15
TW202101617A (zh) 2021-01-01
EP3751603A2 (en) 2020-12-16

Similar Documents

Publication Publication Date Title
US7138706B2 (en) Semiconductor device and method for manufacturing the same
US20180174984A1 (en) Packaging Devices and Methods for Semiconductor Devices
US7843058B2 (en) Flip chip packages with spacers separating heat sinks and substrates
JP4493121B2 (ja) 半導体素子および半導体チップのパッケージ方法
JPH0758254A (ja) マルチチップモジュール及びその製造方法
JP2008294388A (ja) ウェハレベルのシステムインパッケージ及びその製造方法
TW201415587A (zh) 半導體裝置的熱能管理結構及其製造方法
JP2016063178A (ja) 半導体装置及びその製造方法
WO2022057822A1 (zh) 一种散热封装结构及其制备方法、以及电子器件
JP2004253738A (ja) パッケージ基板及びフリップチップ型半導体装置
TWI659509B (zh) 電子封裝件及其製法
JP2000077576A (ja) 半導体装置及びその製造方法
TW202243151A (zh) 封裝結構及其形成方法
TWI733142B (zh) 電子封裝件
JP2008537355A (ja) 金属薄片を利用した受動素子及び半導体パッケージの製造方法
TWI830115B (zh) 封裝結構及其製造方法
TWI721898B (zh) 半導體封裝結構
US20220223542A1 (en) Semiconductor device and manufacturing method thereof
TWI536515B (zh) 具有散熱結構之半導體封裝元件及其封裝方法
TWI269414B (en) Package substrate with improved structure for thermal dissipation and electronic device using the same
WO2023241304A1 (zh) 芯片封装方法及芯片
US20100283143A1 (en) Die Exposed Chip Package
US20220359322A1 (en) Semiconductor package and method forming the same
TW201342542A (zh) 半導體封裝結構及其製造方法
TWI557852B (zh) 系統級封裝模組及其製造方法