TWI718503B - Image display method and image display system - Google Patents

Abstract

An image display method includes setting a plurality of frame rate intervals and a plurality of backlight driving signal adjustment modes, acquiring a data clock signal, detecting a first frame rate of the data clock signal, adjusting a first power distribution of a backlight driving signal according to a first backlight driving signal adjustment mode of the plurality of backlight driving signal adjustment modes when the first frame rate falls into a first frame rate interval of the plurality of frame rate intervals, and displaying an image according to at least data clock signal and the backlight driving signal.

Description

Image display method and image display system

The invention discloses an image display method and an image display system, in particular to an image display method and an image display system that reduce image flicker and maintain brightness stability.

Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED) display devices have been widely used in multimedia players because of their light and thin appearance, power saving, and non-radiation. , Mobile phones, personal digital assistants, computer monitors, or flat-screen TVs and other electronic products.

Nowadays, many advanced monitors are often used in video games, or used to play movies. Whether it is a video game or a movie image, there are many moving objects. Therefore, in order to provide users with a better quality of audio and video experience, advanced displays have the function of Dynamic Accuracy (DyAc). The dynamic precision function can further improve the clarity of the dynamic display image, which is especially helpful for images that will cause severe vibration in the game. In addition, advanced displays also have the function of dynamically refreshing the frame rate (Free Sync). The dynamic refresh frame rate function can drive the screen to display images by dynamically adjusting the frame rate according to the image data performed by the game console or the graphics card. In other words, when the screen receives image data whose frame rate changes over time (such as 30~240 Hz), the image can be displayed directly.

However, after the monitor turns on the Free Sync function, the frame rate will change over time. After the monitor turns on the DyAc function, when the frame rate is lower than 100 Hz, the human eye can easily detect the flicker of the image. Elephant. Also, because the frame rate under the Free Sync function will change over time, the image brightness may also be unstable. Therefore, when the current displays enable Free Sync and DyAc functions at the same time, the quality of the user's audiovisual experience will be reduced due to image flickering and unstable brightness at lower frame rates.

An embodiment of the present invention provides an image display method. The image display method includes setting a plurality of frame rate intervals and a plurality of backlight drive signal adjustment modes, obtaining a data clock signal, and detecting the first frame rate of the data clock signal. When the first frame rate falls within the frame rate interval In the first frame rate interval, according to the first backlight driving signal adjustment mode among the backlight driving signal adjustment modes, the first energy distribution of the backlight driving signal is adjusted, and the image is displayed according to at least the data clock signal and the backlight driving signal.

Another embodiment of the present invention provides an image display system. The image display system includes a display panel, a driving circuit, a processor, a backlight device, and a memory. The display panel includes a plurality of pixels for displaying images. The driving circuit is coupled to the display panel for driving the pixels. The processor is coupled to the driving circuit for controlling the driving circuit. The backlight device is coupled to the processor for generating a backlight source. The memory is coupled to the processor for storing data of a plurality of frame rate intervals and a plurality of backlight driving signal adjustment modes. After the processor obtains the data clock signal of the signal source, it detects the first frame rate of the data clock signal. When the first frame rate falls within the first frame rate interval of the frame rate intervals, the processor adjusts the first backlight drive signal adjustment mode according to the first backlight drive signal adjustment mode among the backlight drive signal adjustment modes stored in the memory. One energy distribution. The backlight device generates a backlight source according to the backlight driving signal. The driving circuit drives the pixels in the display panel to display images according to at least the data clock signal and the backlight driving signal.

100: Image display system

10: Display panel

P: pixel

11: Drive circuit

12: processor

13: Backlight device

14: Memory

15: signal source

R1: First frame rate

R2: second frame rate

DLK: Data clock signal

BL: backlight drive signal

S1: The first square wave

S2: second square wave

F1 and FQ: Frame

E11, E12, E13, E21, E22 and E23: energy

Freq1: the first frequency

Freq2: second frequency

H1: first height

W1: first width

H2: second height

W2: second width

S501 to S505: steps

Figure 1 is a block diagram of an embodiment of the image display system of the present invention.

Fig. 2 is a schematic diagram of the first relationship between the data clock signal and the backlight driving signal in the image display system of Fig. 1.

Fig. 3 is a schematic diagram of the second relationship between the data clock signal and the backlight driving signal in the image display system of Fig. 1.

Figure 4 is a schematic diagram of the third relationship between the data clock signal and the backlight driving signal in the image display system of Figure 1.

Fig. 5 is a flowchart of the image display method executed by the image display system of Fig. 1.

FIG. 1 is a block diagram of an embodiment of the image display system 100 of the present invention. The display system 100 includes a display panel 10, a driving circuit 11, a processor 12, a backlight device 13 and a memory 14. The display panel 10 may be any type of display panel, such as a liquid crystal display (LCD) display panel or an organic light emitting diode (OLED) display panel. The display panel 10 includes a plurality of pixels P for displaying images. The pixels P can be arranged in a pixel array to display a rectangular image. The driving circuit 11 is coupled to the display panel 10 for driving the pixels P. The driving circuit 11 may include any circuit elements for driving the pixels P, for example, may include a gate driving circuit and a data driving circuit. The gate driving circuit can control the control terminals of the pixels P one by one with the gate voltage, thereby controlling the on or off state of the pixels P. The data driving circuit can transmit the data voltage to the pixels P line by line, so that the pixels P display different colors and grayscale values. The processor 12 is coupled to the driving circuit 11 for controlling the driving circuit 11. The processor 12 may be a processing chip (Scaler) in the image display system 100, or may be a microprocessor with logic processing capabilities. The processor 12 may also store multiple sets of timing control parameters (Timing Control Parameters). In addition, the processor 12 may also integrate a timing controller (Timing Controller) to control various timings of the driving circuit 11. Order to scan the pixels P. The backlight device 13 is coupled to the processor 12 for generating a backlight light source. The backlight device 13 can be any device composed of controllable light-emitting bodies. For example, the backlight device 13 can be a Light-Emitting Diode Array, an incandescent bulb, an Electroluminescent Panel (ELP), or a cold cathode. Fluorescent lamps (Cold Cathode Fluorescent Lamp, CCFL) and other devices. The memory 14 is coupled to the processor 12 for storing data of a plurality of frame rate intervals and a plurality of backlight driving signal adjustment modes. In the image display system 100, the processor 12 can receive the data clock signal from the signal source 15. The definition of the data clock signal of the signal source 15 can be an image data clock signal generated by a display card of an external computer, or an image data clock signal generated by an audio-visual player (such as a DVD Player).

In the image display system 100, after the processor 12 obtains the data clock signal of the signal source 15, it can detect the first frame rate of the data clock signal. When the first frame rate falls within the first frame rate interval of the frame rate intervals, the processor can adjust the backlight drive according to the first backlight drive signal adjustment mode among the backlight drive signal adjustment modes stored in the memory 14 The first energy distribution of the signal. The backlight device 13 can generate a backlight light source according to a backlight driving signal. The driving circuit 11 drives the pixels P in the display panel 10 to display images according to at least the data clock signal and the backlight driving signal. In addition, the image display system 100 has a function of dynamically refreshing the frame rate (Free Sync), so the first frame rate of the data clock signal will vary with time, and the variation range may be 30 to 240 hertz (Hz). The data of the plurality of frame rate intervals and the plurality of backlight driving signal adjustment modes stored in the memory 14 can be shown in the following table T1.

表T1

Table T1

However, the data listed in Table T1 are only parameters used in an embodiment of the image display system 100 and are not limited to the present invention. Any reasonable changes to the frame rate interval and the backlight driving signal adjustment mode belong to the scope of the present invention. The details of the various adjustment modes of the backlight driving signal will be described later.

40Hz」的區間。因此，處理器12會利用三倍幀率之背光驅動訊號BL的頻率驅動背光裝置13。如第2圖所示，處理器12會將第一幀F1區間內的背光驅動訊號BL的頻率設定為三倍的第一幀率R1，意即為40Hz×3=120Hz(於第2圖中稱為第一頻率Freq1)。換句話說，背光驅動訊號BL在第一幀F1區間內具有三個第一方波S1，其能量為E11、E12及E13。於此，方波的能量定義為其波形的積分面積。因此，雖然資料時脈訊號DLK第一幀率R1(40Hz)較低，然而，因背光驅動訊號BL的第一頻率Freq1被設定為120Hz。因此，就算影像顯示系統100開啟了動態精準(Dynamic Accuracy，DyAc)的功能，也不會發生影像閃爍的現象。如前述提及，影像顯示系統100具有Free Sync的功能，因此資料時脈訊號DLK的第一幀率R1會隨時間變化，其變化範圍可為30~240赫茲(Hz)。例如，處理器12經過Q個幀的時間後(Q為正整數)，偵測到資料時脈訊號DLK由第一幀率R1變化為第二幀率R2，如75Hz。處理器12會依據第二幀率R2，利用表T1判斷第二幀率R2落入第二幀率區間。於此，第二幀率R2落入「40Hz<FR

99Hz」的幀率區間。因此，處理器12會利用二倍幀率之背光驅動訊 號BL的頻率驅動背光裝置13。如第2圖所示，處理器12會將第Q幀FQ區間內的背光驅動訊號BL的頻率設定為二倍的第二幀率R2，意即為75Hz×2=150Hz(於第2圖中稱為第二頻率Freq2)。因此，影像閃爍的現象也可以避免。換句話說，因為人眼對於低於100Hz的幀率影像會覺得有影像閃爍的不適感，因此，影像顯示系統100的設計目的在於依據目前資料時脈訊號DLK的幀率，動態地調整背光驅動訊號BL的頻率。並且，也因為背光驅動訊號BL的頻率(如第一頻率Freq1=120Hz，第二頻率Freq2=150Hz)大於100Hz，故可緩和影像閃爍的程度。 FIG. 2 is a schematic diagram of the first relationship between the data clock signal DLK and the backlight driving signal BL in the image display system 100. The adjustment method of the backlight drive signal BL in Figure 2 can correspond to Table T1. In other words, the frequency of the backlight driving signal BL in FIG. 2 can be adjusted according to the data in the correspondence table T1. The details are as follows. The X axis in Figure 2 is the time axis. First, the processor 12 detects the first frame rate R1 of the data clock signal DLK generated by the signal source 15, for example, the first frame rate R1 is 40 Hz. When the first frame rate R1 is 40Hz, the first frame rate R1 will fall into the "FR

40Hz" interval. Therefore, the processor 12 drives the backlight device 13 by using the frequency of the backlight driving signal BL of three times the frame rate. As shown in Figure 2, the processor 12 sets the frequency of the backlight drive signal BL in the first frame F1 interval to three times the first frame rate R1, which means 40Hz×3=120Hz (in Figure 2 Called the first frequency Freq1). In other words, the backlight driving signal BL has three first square waves S1 in the interval of the first frame F1, the energy of which is E11, E12, and E13. Here, the energy of a square wave is defined as the integral area of its waveform. Therefore, although the first frame rate R1 (40 Hz) of the data clock signal DLK is relatively low, the first frequency Freq1 of the backlight driving signal BL is set to 120 Hz. Therefore, even if the dynamic accuracy (DyAc) function is turned on in the image display system 100, the image flicker will not occur. As mentioned above, the image display system 100 has the function of Free Sync, so the first frame rate R1 of the data clock signal DLK will vary with time, and the variation range can be 30-240 hertz (Hz). For example, after Q frames of time (Q is a positive integer), the processor 12 detects that the data clock signal DLK changes from the first frame rate R1 to the second frame rate R2, such as 75 Hz. The processor 12 uses the table T1 to determine that the second frame rate R2 falls within the second frame rate interval according to the second frame rate R2. Here, the second frame rate R2 falls into "40Hz<FR

99Hz" frame rate interval. Therefore, the processor 12 drives the backlight device 13 by using the frequency of the backlight driving signal BL of twice the frame rate. As shown in Figure 2, the processor 12 sets the frequency of the backlight drive signal BL in the Q-th frame FQ interval to twice the second frame rate R2, which means 75Hz×2=150Hz (in Figure 2 Called the second frequency Freq2). Therefore, the phenomenon of image flickering can be avoided. In other words, because human eyes feel uncomfortable with image flickering for images with a frame rate lower than 100Hz, the image display system 100 is designed to dynamically adjust the backlight drive according to the frame rate of the current data clock signal DLK. The frequency of the signal BL. Moreover, because the frequency of the backlight driving signal BL (for example, the first frequency Freq1=120 Hz, the second frequency Freq2=150 Hz) is greater than 100 Hz, the degree of image flicker can be alleviated.

40Hz」的幀率區間，N=3。第一幀率R1若在「40Hz<FR

99Hz」的幀率區間，N=2。第一幀率R1若在「FR

100Hz」的幀率區間，N=1。資料時脈訊號DLK依據資料時脈訊號DLK在第二幀率R2的調整模式是類似的，說明已於前文中提及，故於此不再贅述。 In other words, as far as the data clock signal DLK is at the first frame rate R1, the processor 12 can adjust the first backlight driving signal according to the first backlight driving signal adjustment mode stored in the memory 14 (Table T1) , Adjust the first frequency Freq1 of the backlight driving signal BL. The method of adjusting the first frequency Freq1 may be to adjust the first frequency Freq1 of the backlight driving signal BL to N times the first frame rate R1 of the data clock signal DLK, and N is a positive integer. Moreover, if the first frame rate R1 of the data clock signal DLK increases, the processor 12 can decrease the value of N. As shown in Table T1, if the first frame rate R1 is in the "FR

40Hz" frame rate interval, N=3. If the first frame rate R1 is at "40Hz<FR

"99Hz" frame rate interval, N=2. If the first frame rate R1 is in "FR

100Hz" frame rate interval, N=1. The adjustment mode of the data clock signal DLK in the second frame rate R2 according to the data clock signal DLK is similar, and the description has been mentioned in the foregoing, so it will not be repeated here.

E21+E22。背光驅動訊號BL在資料時脈訊號DLK之所有幀中的能量相近，可以保持影像亮度的穩定性，進而提升使用者的影音體驗品質。 However, in addition to adjusting the frequency of the backlight driving signal BL, the image display system 100 can also adjust the waveform of the backlight driving signal BL. The processor 12 can adjust the first energy distribution of the backlight driving signal BL according to the first backlight driving signal adjustment mode stored in the memory 14. For example, the first frequency Freq1 of the backlight driving signal BL in the interval of the first frame F1 is set to three times the first frame rate R1. The processor 12 can adjust the energies E11, E12, and E13 of the plurality of first square waves S1 of the backlight driving signal BL in the interval of the first frame F1. Similarly, the second frequency Freq2 of the backlight driving signal BL in the Q-th frame FQ interval is set to twice the second frame rate R2. The processor 12 can adjust the energy E21 and E22 of the plurality of second square waves S2 in the Q-th frame FQ interval of the backlight driving signal BL. By analogy, the image display system 100 can redistribute the energy of the backlight driving signal BL in each frame by adjusting the waveform of the backlight driving signal BL, so that the backlight driving signal BL is in all frames of the data clock signal DLK. Similar energy, such as E11+E12+E13

E21+E22. The energy of the backlight drive signal BL in all the frames of the data clock signal DLK is similar, which can maintain the stability of the image brightness, thereby improving the quality of the user's audiovisual experience.

40Hz」的區間。因此，處理器12會利用三倍幀率之背光驅動訊號BL的頻率驅動背光裝置13。因此，第一幀F1區間內的背光驅動訊號BL的第一頻率Freq1可設定為三倍的第一幀率R1，意即為40Hz×3=120Hz。處理器12偵測訊號源15產生的資料時脈訊號DLK的第二幀率R2，如第二幀率R2為100Hz。當第二幀率R2為100Hz時，第二幀率R2會落入表T1中之「FR

100Hz」的區間。因此，處理器12會利用一倍幀率之背光驅動訊號BL的頻率驅動背光裝置13。因此，第Q幀FQ區間內的背光驅動訊號BL的第二頻率Freq2可設定為一倍的第二幀率R2，意即為100Hz。並且，背光驅動訊號BL包含至少一個方波。處理器12可調整背光驅動訊號BL之至少一個方波的高度及/或寬度。例如，在第一幀F1區間內的背光驅動訊號BL包含三個第一方波S1。處理器12可以調整每一個第一方波S1的第一高度H1及/或第一寬度W1。如前述提及，方波的能量定義為其波形的積分面積。因此，具有第一高度H1及第一寬度W1的第一方波S1，其能量E11=W1×H1，依此類推。處理器12可調整背光驅動訊號BL在第一幀F1區間內之能量E11、E12及E13的分佈。類似地，在第Q幀FQ區間內的背光驅動訊號BL包含一個第二方波S2。處理器12可以調整第二方波S2的第二高度H2及/或第二寬度W2。因此，具有第二高度H2及第二寬度W2的第二方波S2，其能量E21=W2×H2。處理器12可調整背光驅動訊號BL在第Q幀FQ區 間內之能量E21的分佈。 FIG. 3 is a schematic diagram of the second relationship between the data clock signal DLK and the backlight driving signal BL in the image display system 100. The X axis in Figure 3 is the time axis. Similarly, the processor 12 detects the first frame rate R1 of the data clock signal DLK generated by the signal source 15, for example, the first frame rate R1 is 40 Hz. When the first frame rate R1 is 40Hz, the first frame rate R1 will fall into the "FR

40Hz" interval. Therefore, the processor 12 drives the backlight device 13 by using the frequency of the backlight driving signal BL of three times the frame rate. Therefore, the first frequency Freq1 of the backlight driving signal BL in the interval of the first frame F1 can be set to three times the first frame rate R1, which means 40 Hz×3=120 Hz. The processor 12 detects the second frame rate R2 of the data clock signal DLK generated by the signal source 15, for example, the second frame rate R2 is 100 Hz. When the second frame rate R2 is 100Hz, the second frame rate R2 will fall into the "FR

100Hz" interval. Therefore, the processor 12 drives the backlight device 13 by using the frequency of the backlight driving signal BL at one frame rate. Therefore, the second frequency Freq2 of the backlight driving signal BL in the Q-th frame FQ interval can be set to double the second frame rate R2, which means 100 Hz. In addition, the backlight driving signal BL includes at least one square wave. The processor 12 can adjust the height and/or width of at least one square wave of the backlight driving signal BL. For example, the backlight driving signal BL in the interval of the first frame F1 includes three first square waves S1. The processor 12 can adjust the first height H1 and/or the first width W1 of each first square wave S1. As mentioned earlier, the energy of a square wave is defined as the integral area of its waveform. Therefore, the first square wave S1 with the first height H1 and the first width W1 has an energy E11=W1×H1, and so on. The processor 12 can adjust the distribution of the energy E11, E12, and E13 of the backlight driving signal BL in the interval of the first frame F1. Similarly, the backlight driving signal BL in the Q-th frame FQ interval includes a second square wave S2. The processor 12 can adjust the second height H2 and/or the second width W2 of the second square wave S2. Therefore, the energy of the second square wave S2 with the second height H2 and the second width W2 is E21=W2×H2. The processor 12 can adjust the distribution of the energy E21 of the backlight driving signal BL in the Q-th frame FQ interval.

E12

E13。如此，對於第一幀F1區間內的影像而言，影像亮度的穩定性將更高。 Moreover, as mentioned above, the processor 12 adjusts the energy distribution of the backlight driving signal BL so that the energy of the backlight driving signal BL in all frames of the data clock signal DLK is similar, so as to maintain the stability of the image brightness. Therefore, in Figure 3, when the first frame rate R1 (40 Hz) is less than the second frame rate R2 (100 Hz), the energy of each first square wave S1 of the backlight drive signal BL can be set to be slightly smaller than that of the backlight drive signal BL. The energy of each second square wave S2 is such that the energy in the F1 interval of the first frame with a larger number of square waves is balanced with the energy in the Qth frame FQ interval with a smaller number of square waves. Conversely, when the first frame rate R1 is greater than the second frame rate R2, the energy of each first square wave S1 of the backlight driving signal BL can be set to be slightly larger than each second square wave S2 of the backlight driving signal under the second energy distribution. energy. Furthermore, the image display system 100 can also set the energies of the multiple first square waves S1 to be approximately equal, which means E11

E12

E13. In this way, for the image in the F1 interval of the first frame, the stability of the image brightness will be higher.

E21+E22)。背光驅動訊號BL的波形之能量調整方式也可以進一步地將多個方波的能量設定為趨近相等，如能量設定為E11

E12

E13。任何能增加影像亮度穩定性之背光驅動訊號的能量調整模式都屬於本發明所揭露的範疇。 In the image display system 100, the method of adjusting the energy distribution of the backlight driving signal BL includes adjusting the frequency of the backlight driving signal BL and/or adjusting the waveform (length/width of the square wave) of the backlight driving signal BL. Increasing the frequency of the backlight driving signal BL can prevent human eyes from seeing flickering images. Adjusting the waveform (length/width of the square wave) of the backlight driving signal BL can make the energy of the backlight driving signal BL in all the frames of the data clock signal DLK similar, while maintaining the stability of the image brightness. However, the energy adjustment method of the waveform of the backlight driving signal BL is not limited to frame-to-frame energy adjustment (for example, the energy in the figure 2 can be set to E11+E12+E13

E21+E22). The energy adjustment method of the waveform of the backlight driving signal BL can also further set the energy of multiple square waves to be approximately equal, for example, the energy is set to E11

E12

E13. Any energy adjustment mode of the backlight driving signal that can increase the stability of the image brightness falls within the scope of the present invention.

40Hz」的區間。因此，處理器12會利用三倍幀率之背光驅動訊號BL的頻率驅動背光裝置13。因此，第一幀F1區間內的背光驅動訊號BL的第一頻率Freq1可設定為三倍的第一幀率R1，意即為40Hz×3=120Hz。處理器12偵測訊號源15產生的資料時脈訊號DLK的第二幀率R2，如第二幀率R2為120Hz。當第二幀率R2為120Hz時，第二幀率R2會落入表T1中之「FR

100Hz」的區間。因此，處理器12會利用一倍幀率之背光驅動訊號BL的頻率驅動背光裝置13。因此，第Q幀FQ區間內的背光驅動訊號BL的第二頻率Freq2可設定為一倍的第二幀率R2，意即為120Hz。在第4圖中，由於第二幀率R2為三倍的第一幀率R1(120Hz是40Hz的三倍)，故背光驅動訊號BL依據表T1調整後，其第一頻率Freq1與第二頻率Freq2恰為相同，為120Hz。換句話說，在某些條件下，背光驅動訊號BL的頻率可以維持常數(如120Hz)，處理器12只要調整調整背光驅動訊號BL的波形(方波的長度/寬度)即可。並且，處理器12調整每一個第一方波S1的寬度W1及/或高度H1，調整每一個第二方波S2的寬度W2及/或高度H2的方式，以及將能量E11、E12、E13、E21、E22及E23的分配的模式已於前文中描述，故於此將不再贅述。 FIG. 4 is a schematic diagram of the third relationship between the data clock signal DLK and the backlight driving signal BL in the image display system 100. The X axis in Figure 4 is the time axis. Similarly, the processor 12 detects the first frame rate R1 of the data clock signal DLK generated by the signal source 15, for example, the first frame rate R1 is 40 Hz. When the first frame rate R1 is 40Hz, the first frame rate R1 will fall into the "FR

40Hz" interval. Therefore, the processor 12 drives the backlight device 13 by using the frequency of the backlight driving signal BL of three times the frame rate. Therefore, the first frequency Freq1 of the backlight driving signal BL in the interval of the first frame F1 can be set to three times the first frame rate R1, which means 40 Hz×3=120 Hz. The processor 12 detects the second frame rate R2 of the data clock signal DLK generated by the signal source 15, for example, the second frame rate R2 is 120 Hz. When the second frame rate R2 is 120Hz, the second frame rate R2 will fall into the "FR

100Hz" interval. Therefore, the processor 12 drives the backlight device 13 by using the frequency of the backlight driving signal BL at one frame rate. Therefore, the second frequency Freq2 of the backlight driving signal BL in the Q-th frame FQ interval can be set to double the second frame rate R2, which means 120 Hz. In Figure 4, since the second frame rate R2 is three times the first frame rate R1 (120Hz is three times 40Hz), the backlight driving signal BL is adjusted according to the table T1, the first frequency Freq1 and the second frequency Freq2 is exactly the same, which is 120 Hz. In other words, under certain conditions, the frequency of the backlight driving signal BL can be maintained constant (for example, 120 Hz), and the processor 12 only needs to adjust the waveform (length/width of the square wave) of the backlight driving signal BL. In addition, the processor 12 adjusts the width W1 and/or height H1 of each first square wave S1, adjusts the width W2 and/or height H2 of each second square wave S2, and adjusts the energy E11, E12, E13, The allocation modes of E21, E22, and E23 have been described above, so they will not be repeated here.

In addition, the method of adjusting the energy distribution of the backlight driving signal BL in the present invention is not limited to the modes shown in FIGS. 2 to 4. For example, in Figure 2, the energy distribution of the first square wave S1 and the second square wave S2 of the backlight driving signal BL can be adjusted reasonably. For example, the backlight driving signal BL can set a first square wave S1 with energy E13 in the Blanking Interval of the first frame F1. The backlight driving signal BL can set a first square wave S1 with energy E11 and a first square wave S1 with energy E12 in an "arbitrary" period within the Active Interval of the first frame F1. In other words, the intervals of the first square waves S1 of the backlight driving signal BL in the first frame F1 can be different. In addition, the backlight driving signal BL can set a second square wave S2 with energy E22 in the blank interval of the Q-th frame FQ. The backlight drive signal BL can be in the Qth frame A second square wave S2 with energy E21 is set for an "arbitrary" time period in the active interval of FQ. Any method for reasonably adjusting the energy distribution of the backlight driving signal BL belongs to the scope of the present invention.

In the image display system 100, the processor 12 adjusts the energy distribution of the backlight driving signal BL to prevent the human eye from seeing the flickering image and maintain the stability of the image brightness. However, the way the image display system 100 optimizes the image is not limited to this. For example, in the image display system 100, the memory 14 may additionally store a plurality of liquid crystal acceleration drive modes (Over Drive Modes, OD Modes). When the first frame rate R1 falls within the first frame rate interval of the frame rate intervals, the processor 12 can adjust the liquid crystal pixel driving voltage according to one of the liquid crystal acceleration driving modes. When the image display system 100 introduces a plurality of liquid crystal acceleration driving modes, the table T2 of the memory 14 may include data of a plurality of liquid crystal acceleration driving modes, data of a plurality of frame rate intervals, and data of a plurality of backlight driving signal adjustment modes. As follows.

40Hz的幀率區間)，表示訊號源15產生的影像為低速(Slow Motion)或是靜態的影像，例如文書處理的畫面。影像疊影不明顯。因此，液晶加速驅動模式可設定為「弱」模式， 處理器12無須利用很大的液晶畫素驅動電壓驅動顯示面板10。當資料時脈訊號DLK的第一幀率R1很高時(如落在FR

100Hz的幀率區間)，表示訊號源15產生的影像為高速(High Motion)或是動態的影像，例如影音遊戲的畫面。會產生嚴重的影像疊影。因此，液晶加速驅動模式可設定為「強」模式，處理器12利用較大的液晶畫素驅動電壓驅動顯示面板10，以降低影像疊影的現象。因此，處理器12在調整背光驅動訊號BL之能量分佈並引入多個液晶加速驅動模式後，可以同時避免人眼看到閃爍的影像、保持影像亮度的穩定性以及降低影像疊影的現象。因此，影像顯示系統100可大幅度地增加使用者的影音體驗品質。 The image display system 100 can introduce multiple liquid crystal acceleration driving modes to adjust the driving voltage of the liquid crystal pixels. The stronger the driving voltage of the liquid crystal pixel, the shorter the time for the liquid crystal molecules in the pixel to be in the transient state. Therefore, when the first frame rate R1 of the data clock signal DLK is not high (such as falling on FR

The frame rate interval of 40 Hz) indicates that the image generated by the signal source 15 is a slow motion or static image, such as a word processing image. The image overlap is not obvious. Therefore, the liquid crystal acceleration driving mode can be set to the "weak" mode, and the processor 12 does not need to use a large liquid crystal pixel driving voltage to drive the display panel 10. When the first frame rate R1 of the data clock signal DLK is very high (such as falling on FR

The frame rate interval of 100 Hz) indicates that the image generated by the signal source 15 is a high-speed (High Motion) or dynamic image, such as a video game screen. Will produce serious image duplication. Therefore, the liquid crystal acceleration driving mode can be set to a "strong" mode, and the processor 12 uses a larger liquid crystal pixel driving voltage to drive the display panel 10 to reduce the phenomenon of image overlap. Therefore, after the processor 12 adjusts the energy distribution of the backlight driving signal BL and introduces multiple liquid crystal acceleration driving modes, it can simultaneously prevent the human eye from seeing the flickering image, maintain the stability of the image brightness, and reduce the phenomenon of image overlap. Therefore, the image display system 100 can greatly increase the quality of the user's audiovisual experience.

FIG. 5 is a flowchart of the image display method executed by the image display system 100. The flow of the image display method includes step S501 to step S505. Any reasonable technical modification belongs to the scope disclosed in the present invention. Steps S501 to S505 are described below.

Step S501: Set a plurality of frame rate intervals and a plurality of backlight drive signal adjustment modes; Step S502: Obtain the data clock signal DLK; Step S503: Detect the first frame rate R1 of the data clock signal DLK; Step S504: When the first frame rate When a frame rate R1 falls within the first frame rate interval of the frame rate intervals, adjust the first energy distribution of the backlight drive signal BL according to the first backlight drive signal adjustment mode among the backlight drive signal adjustment modes; step S505 : Display images based on at least the data clock signal DLK and the backlight drive signal BL.

The details of step S501 to step S505 have been described in detail in the foregoing, so they will not be repeated here. By adjusting the backlight driving signal, the image display system 100 can prevent the human eye from seeing the flickering image and maintain the stability of the image brightness. In other words, even if the image display system 100 is performing the function of Free Sync, no matter how the frame rate of the data clock signal changes, the frequency of the backlight driving signal can be raised above a certain threshold (such as greater than 100 Hz), so it can be avoided The human eye sees the flickering image. Therefore, the image display system 100 can increase the quality of the user's audio and video experience.

In summary, the present invention describes an image display method and image display system. The image display system can dynamically adjust the frequency of the backlight driving signal according to the variability of the frame rate of the data clock signal. Especially when the frame rate of the data clock signal is very low, the image display system can increase the frequency of the backlight driving signal to prevent the human eye from perceiving the flickering image. Moreover, the image display system can also fine-tune the height and/or width of each square wave in the backlight driving signal to optimize the energy distribution of the backlight driving signal in all frames, so that the stability of the image brightness can be maintained. In addition, the image display system can also introduce multiple liquid crystal acceleration drive modes to reduce the phenomenon of image overlap. Therefore, the image display system of the present invention can prevent the human eyes from seeing the flickering image, maintain the stability of the image brightness, and reduce the image overlap, so it can greatly increase the quality of the user's audiovisual experience.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should fall within the scope of the present invention.

R1: First frame rate

R2: second frame rate

DLK: Data clock signal

BL: backlight drive signal

S1: The first square wave

S2: second square wave

F1 and FQ: Frame

E11, E12, E13, E21 and E22: energy

Freq1: the first frequency

Freq2: second frequency

Claims (17)

An image display method, including: setting a plurality of frame rate intervals and a plurality of backlight driving signal adjustment modes; obtaining a data clock signal; detecting a first frame rate of the data clock signal; when the first frame rate falls When entering a first frame rate interval of one of the frame rate intervals, adjust a first energy distribution of a backlight drive signal according to one of the backlight drive signal adjustment modes in the first backlight drive signal adjustment mode; detect the data The clock signal changes from the first frame rate to a second frame rate; when the second frame rate falls within a second frame rate interval of the frame rate intervals, one of the backlight driving signal adjustment modes The second backlight drive signal adjustment mode adjusts a second energy distribution of the backlight drive signal; and displays an image based on at least the data clock signal and the backlight drive signal; wherein the backlight drive signal is within the range of the data clock signal The energy in all frames is similar. The method according to claim 1, wherein the first frame rate of the data clock signal changes with time. The method according to claim 1, wherein when the first frame rate is greater than the second frame rate, a first square wave energy of the backlight driving signal in the first energy distribution is greater than that of the backlight driving signal in the first energy distribution A second square wave energy under the second energy distribution. The method according to claim 1, wherein when the first frame rate is less than the second frame rate, a first square wave energy of the backlight driving signal in the first energy distribution is less than that of the backlight driving signal in the first energy distribution. A second square wave energy under the second energy distribution. The method according to claim 1, wherein the backlight driving signal includes at least one first square wave, and the second backlight driving signal is adjusted according to the first backlight driving signal adjustment mode among the backlight driving signal adjustment modes An energy distribution is to adjust a first height and/or a first width of the at least one first square wave of the backlight driving signal according to the first backlight driving signal adjustment mode in the backlight driving signal adjustment modes . An image display method, including: setting a plurality of frame rate intervals and a plurality of backlight driving signal adjustment modes; obtaining a data clock signal; detecting a first frame rate of the data clock signal; when the first frame rate falls When entering a first frame rate interval of one of the frame rate intervals, adjust a first frequency of the backlight drive signal according to the first backlight drive signal adjustment mode in the backlight drive signal adjustment modes to adjust the backlight drive A first energy distribution of the signal; and displaying an image based on at least the data clock signal and the backlight driving signal. The method according to claim 6, wherein adjusting the first frequency of the backlight driving signal according to the first backlight driving signal adjustment mode among the backlight driving signal adjustment modes is based on the backlight driving signal adjustment modes In the first backlight driving signal adjustment mode, the first frequency of the backlight driving signal is adjusted to N times the first frame rate of the data clock signal, and N is a positive integer. The method according to claim 7, wherein if the first frame rate of the data clock signal increases, a value of the N decreases. The method according to claim 1, wherein the backlight driving signal includes at least one first square wave, and the second backlight driving signal is adjusted according to the first backlight driving signal adjustment mode among the backlight driving signal adjustment modes An energy distribution is to adjust a first frequency of the backlight driving signal and a first height of the at least one first square wave according to the first backlight driving signal adjustment mode of the backlight driving signal adjustment modes and/ Or a first width. An image display system includes: a display panel including a plurality of pixels for displaying an image; a driving circuit coupled to the display panel for driving the pixels; and a processor coupled to the A driving circuit for controlling the driving circuit; a backlight device, coupled to the processor, for generating a backlight light source; and a memory, coupled to the processor, for storing a plurality of frame rate intervals and a plurality of numbers Data of a backlight driving signal adjustment mode; wherein the processor detects a first frame rate of the data clock signal after obtaining a data clock signal of a signal source, when the first frame rate falls into the frames When the first frame rate interval is one of the rate intervals, the processor adjusts a first energy distribution of a backlight drive signal according to one of the backlight drive signal adjustment modes stored in the memory. The backlight device generates the backlight light source according to the backlight driving signal, and the driving circuit drives the pixels in the display panel to display images according to at least the data clock signal and the backlight driving signal; and the processor detects The data clock signal changes from the first frame rate to a second frame rate, and when the second frame rate falls within a second frame rate interval of one of the frame rate intervals, the processor depends on the data stored in the memory One of the backlight drive signal adjustment modes, the second backlight drive signal adjustment mode, adjusts a second energy distribution of the backlight drive signal, and the backlight drive signal is at the data clock signal The energies in all frames are similar. The system according to claim 10, wherein the first frame rate of the data clock signal changes with time. The system according to claim 10, wherein when the first frame rate is greater than the second frame rate, a first square wave energy of the backlight driving signal in the first energy distribution is greater than that of the backlight driving signal in the first energy distribution. A second square wave energy under the second energy distribution. The system according to claim 10, wherein when the first frame rate is less than the second frame rate, a first square wave energy of the backlight driving signal in the first energy distribution is less than that of the backlight driving signal in the first energy distribution. A second square wave energy under the second energy distribution. The system according to claim 10, wherein the backlight driving signal includes at least one first square wave, and the processor is based on the first backlight driving signal adjustment mode among the backlight driving signal adjustment modes stored in the memory, and Adjusting a first height and/or a first width of the at least one first square wave of the backlight driving signal. An image display system includes: a display panel including a plurality of pixels for displaying an image; a driving circuit coupled to the display panel for driving the pixels; and a processor coupled to the A driving circuit for controlling the driving circuit; a backlight device, coupled to the processor, for generating a backlight light source; and a memory, coupled to the processor, for storing a plurality of frame rate intervals and a plurality of numbers Backlight drive signal Data of the adjustment mode; wherein the processor obtains a data clock signal of a signal source, and detects a first frame rate of the data clock signal when the first frame rate falls within one of the frame rate intervals In the first frame rate interval, the processor adjusts a first energy distribution of a backlight driving signal according to one of the backlight driving signal adjustment modes stored in the memory, and the backlight device according to The backlight driving signal generates the backlight light source, the driving circuit drives the pixels in the display panel to display images according to at least the data clock signal and the backlight driving signal; and the processor according to the memory stored in the The first backlight driving signal adjustment mode among the backlight driving signal adjustment modes adjusts a first frequency of the backlight driving signal. The system according to claim 15, wherein the processor adjusts the first frequency of the backlight driving signal to the value of the data clock signal according to the first backlight driving signal adjustment mode among the backlight driving signal adjustment modes N times the first frame rate, and N is a positive integer. The system according to claim 16, wherein if the first frame rate of the data clock signal increases, the processor decreases a value of N.

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