TWI792967B - Memory device and word line driver thereof - Google Patents

Abstract

A memory device and a word line driver thereof are provided. The word line driver includes a first word line signal generator, a second word line driver includes a first word line signal generator, a first voltage generator and a second voltage generator. The first word line signal generator selects one of a first voltage and a second voltage to generate a first word line signal according a control signal. The second word line signal generator selects one of a fourth voltage and a fifth voltage to generate a second word line signal according the control signal. The first voltage generator provides the second voltage, and the second voltage generator provides the fourth voltage, where the first voltage generator is independent to the second voltage generator.

Description

Memory device and its word line driver

The present invention relates to a memory device and a word line driver, and in particular to a memory device and a word line driver capable of erasing memory cells on a selected word line.

Today, with the increasing popularity of electronic products, it is an important issue to provide high-efficiency data storage media in electronic products.

In today's flash memory, when data needs to be updated, the memory cells need to be erased first, and then can be completed through programming. Due to the limitations of the architecture, when erasing the memory cells in the flash memory, it is often necessary to erase the memory cells of an entire block, and it is impossible to perform data erasure on a small number of memory cells. . As a result, many inconveniences are often caused when updating data. For example, when performing artificial intelligence algorithm calculations, small-sized data update actions often occur. Therefore, the feature of only block erasing causes the usage efficiency of the flash memory to be significantly reduced.

The invention provides a stacked memory device and its word line driver, which can execute erasing action on the memory cell on the selected word line.

The word line driver of the present invention includes a first word line signal generation circuit, a second word line signal generation circuit, a first voltage generator and a second voltage generator. The first word line signal generating circuit is used for driving the first word line, and generates the first word line signal by selecting one of the first voltage and the second voltage according to the control signal. The second word line signal generating circuit is used to drive a second word line, and select one of the third voltage and the fourth voltage according to the control signal to generate the second word line signal. The first voltage generator is coupled to the first word line signal generating circuit for providing the second voltage. The second voltage generator is coupled to the second word line signal generating circuit for providing a fourth voltage. Wherein the first voltage generator and the second voltage generator are independent of each other.

According to an embodiment of the present invention, the word line driver further includes a third voltage generator and a fourth voltage generator. The third voltage generator is coupled to the first word line signal generating circuit for providing the first voltage. The fourth voltage generator is coupled to the second word line signal generating circuit for providing the third voltage.

The stacked memory device of the present invention includes a word line driver, a first memory cell array and a second memory cell array. The first memory cell array and the second memory cell array are respectively coupled to a plurality of first word lines and a plurality of second word lines. The word line driver includes a plurality of first word line signal generation circuits, a plurality of second word line signal generation circuits, a first voltage generator and a second voltage generator. First word line signal generation The circuit is used to respectively drive the first word line, and select one of the first voltage and the second voltage according to a plurality of first control signals to generate the first word line signal. The second word line signal generating circuit is used for driving the second word line respectively, and generates the second word line signal by selecting one of the third voltage and the fourth voltage according to a plurality of second control signals. A voltage generator is coupled to the first word line signal generating circuit for providing the second voltage. The second voltage generator is coupled to the second word line signal generating circuit for providing the fourth voltage, wherein the first voltage generator and the second voltage generator are independent of each other.

Based on the above, the word line driver of the present invention can provide mutually independent word line voltages for different word lines through different word line signal generating circuits. In this way, memory cells corresponding to different word lines in the memory device can be erased independently. That is to say, the erasing operation of the memory device in the embodiment of the present invention does not need to be performed on the entire memory cell array, but can be performed on a local memory cell on a selected word line, thereby effectively improving the performance of the memory device. data access performance.

100, 310: word line driver

110, 120, 3111~311M, 3121~312M, 10111~10113: word line signal generation circuit

131~134, 3131~3134, 10131~10134: voltage generator

300: stacked memory device

BLT: bit line switch

CSL: common source line

GBL: common bit line

HV, LV: operating voltage

S1~S4: select signal

MCS: selected memory cell

MP1, MN1, MN2: Transistor

PG, PG[1]~PG[M]: control signal

PG[1]B~PG[M]B: reverse signal

SBLT: selected bit line switch

SLT: Source Line Switch

SLT1, SLT2: memory cell array

SSLT: Select Source Line Switch

V1, V2, V3, V4: Voltage

WL1, WL2, WL11~WL1M, WL21~WL2M: word line

WLS1, WLS2: word line signal

FIG. 1 is a schematic diagram of a word line driver according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of an implementation of the word line signal generating circuits 110 and 120 in the embodiment of FIG. 1 of the present invention.

FIG. 3 is a schematic diagram of a stacked memory device according to an embodiment of the present invention.

FIG. 4 shows a diagram of the read operation of the stacked memory device according to the embodiment of the present invention. intention.

FIG. 5 is a schematic diagram of programming operations of the stacked memory device according to the embodiment of the present invention.

FIG. 6 is a schematic diagram of a block erase operation of the stacked memory device according to an embodiment of the present invention.

7 is a schematic diagram of a selected word line erase operation of the stacked memory device according to the embodiment of the present invention.

FIG. 8 and FIG. 9 are schematic diagrams respectively showing the erase mode of one or more memory cells in the erase operation of the selected word line according to the embodiment of the present invention.

FIG. 10 is a schematic diagram of an arbitrary bit line erase operation of the memory device according to an embodiment of the present invention.

Please refer to FIG. 1 , which is a schematic diagram of a word line driver according to an embodiment of the present invention. The word line driver 100 includes word line signal generation circuits 110 , 120 and voltage generators 131 - 134 . The word line signal generating circuit 110 is used to drive the word line WL1. The word line signal generating circuit 110 can generate the word line signal WLS1 on the word line WL1 according to the control signal PG. The word line signal generating circuit 110 receives the voltages V1 and V2, and the word line signal generating circuit 110 generates the word line signal WLS1 according to one of the voltages V1 and V2 according to the control signal PG. In addition, the word line signal generation circuit 120 is used to drive the word line WL2. The word line signal generation circuit 120 can generate words on the word line WL2 according to the control signal PG Line signal WLS2. The word line signal generating circuit 120 receives the voltages V3 and V4, and the word line signal generating circuit 120 generates the word line signal WLS2 according to one of the voltages V3 and V4 according to the control signal PG.

The voltage generators 131 and 132 are coupled to the word line signal generating circuit 110 . The voltage generators 131 and 132 are used to generate voltages V1 and V2 respectively. Wherein, the voltage generators 131 and 132 can respectively adjust the voltage values of the voltages V1 and V2 corresponding to different types of access operations performed by the memory device. Similarly, the voltage generators 133 and 134 are coupled to the word line signal generating circuit 120 . The voltage generators 133 and 134 are used to generate the voltages V3 and V4 respectively, and can adjust the voltage values of the voltages V3 and V4 corresponding to different types of access operations performed by the memory device.

It should be noted that the voltage value of the voltage V1 generated by the voltage generator 131 and the voltage value of the voltage V3 generated by the voltage generator 133 may be independent of each other. The voltage value of the voltage V2 generated by the voltage generator 132 and the voltage value of the voltage V4 generated by the voltage generator 134 may also be independent of each other.

In this embodiment, the word line WL1 is disposed in the memory cell array SLT1, and the word line WL2 may be disposed in another memory cell array SLT2. Of course, there may be other word lines in the memory cell array SLT1 and the memory cell array SLT2. FIG. 1 is only an example for illustration, and there is no fixed limit to the number of word lines in a single memory cell array SLT1 and SLT2.

Please note here that the voltage values based on the word line signals WLS1 and WLS2 on the single word lines WL1 and WL2 can be independently set. Therefore, the present In the illustrated embodiment, the erasing operation can be performed on one or more memory cells on any word line (eg, word line WL1 or WL2 ) in the memory cell arrays SLT1 and SLT2 . And increase the degree of freedom of data writing in the memory cell in the memory device, and improve the efficiency of data access.

Please refer to FIG. 2 below. FIG. 2 is a schematic diagram of an implementation of the word line signal generating circuits 110 and 120 in the embodiment of FIG. 1 of the present invention. The word line signal generating circuit 110 includes transistors MP1, MN1 and MN2. The first end of the transistor MP1 receives the voltage V1; the control end of the transistor MP1 receives the control signal PG; the second end of the transistor MP1 is coupled to the word line WL1 for providing the word line signal WLS1. The first end of the transistor MN1 is coupled to the second end of the transistor MP1; the control end of the transistor MN1 receives the control signal PG; the second end of the transistor MN1 receives the voltage V2. In addition, the first terminal of the transistor MN2 receives the voltage V1; the control terminal of the transistor MN2 receives the reverse signal PGB of the control signal PG; the second terminal of the transistor MN2 is coupled to the word line WL1.

The word line signal generating circuit 120 includes transistors MP2, MN3 and MN4. The circuit architecture of the word line signal generating circuit 120 is the same as that of the word line signal generating circuit 110 , and will not be repeated here.

In this embodiment, the transistors MP1 and MP2 are P-type transistors, and the transistors MN1 - MN4 are N-type transistors.

Regarding the actions of the word line signal generating circuits 110 and 120, taking the word line signal generating circuit 110 as an example, when the voltage V1 has a relatively high voltage value, and when the control signal PG is at a logic low level, the transistor MP1 can be turned on and deliver voltage V1 to generate word line signal WLS1 (transistor MN1 is turned off at this time). When the voltage V1 has a relatively low voltage value, and when the control signal PG is at a logic low level, the transistor MN2 can be turned on and transmit the voltage V1 to generate the word line signal WLS1. In addition, when the logic level of the control signal PG is high, both the transistors MP1 and MN2 can be turned off, and the transistor MN1 can be turned on to transmit the voltage V2 to generate the word line signal WLS1. In this embodiment, the voltage value of the voltage V2 may be equal to or lower than the voltage value of the voltage V1.

On the other hand, the transistors MP1, MN1, and MN2 can be formed on a substrate with three well regions. In this embodiment, the transistor MP1 can be formed on the N-type well region NW, and the transistors MN1 and MN2 can be formed on the On the PWI of the P-type well area. In this way, the word line signal generating circuits 110 and 120 can provide negative voltages V2 and V4 to generate word line signals WLS1 and WLS2 respectively.

Please refer to FIG. 3 below. FIG. 3 is a schematic diagram of a stacked memory device according to an embodiment of the present invention. The stacked memory device 300 includes a word line driver 310 and memory cell arrays SLT1, SLT2. The word line driver 310 includes word line signal generating circuits 3111~311M, 3121~312M and voltage generators 3131~3134. The word line signal generating circuits 3111˜311M are respectively coupled to the word lines WL11˜WL1M, and the word line signal generating circuits 3121˜312M are respectively coupled to the word lines WL21˜WL2M. The word lines WL11˜WL1M are coupled to the memory cell array SLT1, and the word lines WL21˜WL2M are coupled to the memory cell array SLT2.

On the other hand, the word line signal generation circuits 3111~311M respectively receive the control signals PG[1]~PG[M], and respectively receive the inverses of the control signals PG[1]~PG[M]. To signal PG[1]B~PG[M]B. The word line signal generation circuits 3111~311M select one of the voltages V1 and V2 according to the control signals PG[1]~PG[M] and their reverse signals PG[1]B~PG[M]B to generate The corresponding data access operation is performed on the memory cell array SLT1 by using the word line signals respectively driving the word lines WL11˜WL1M. The word line signal generating circuits 3121~312M respectively receive the control signals PG[1]~PG[M], and respectively receive the inverse signals PG[1]B~PG[M] of the control signals PG[1]~PG[M]. ] B. The word line signal generating circuits 3121~312M select one of the voltages V3 and V4 according to the control signals PG[1]~PG[M] and their inverse signals PG[1]B~PG[M]B to generate The corresponding data access operation is performed on the memory cell array SLT2 by using the word line signals respectively driving the word lines WL21˜WL2M.

The voltage generators 3131-3134 may be voltage shifters, and receive selection signals S1-S4 respectively. Taking the voltage generator 3131 as an example, the voltage generator 3131 can determine the voltage value of the generated voltage V1 according to the logic level of the selection signal S1 . For example, the voltage generator 3131 may receive the operating voltage HV having a relatively high voltage value and the operating voltage LV having a relatively low voltage value. When the selection signal S1 is at a high logic level, the voltage generator 3131 can generate a voltage V1 having the same voltage value (relatively high voltage value) as the operating voltage HV. In contrast, when the selection signal S1 is at a low logic level , the voltage generator 3131 can generate the voltage V1 having the same voltage value (relatively low voltage value) as the operating voltage LV.

Referring to FIG. 4 , FIG. 4 is a schematic diagram of the read operation of the stacked memory device according to the embodiment of the present invention. Take the hardware architecture of the stacked memory device 300 in FIG. 3 as an example. In FIG. 4, in the read operation, the voltage generators 3131, 3132 The voltages V1 and V2 are generated with the same voltage value, such as 0 volts, and the voltage generator 3133 generates a voltage V3 with a read voltage value, such as 7.5 volts. The voltage generator 3134 generates a voltage V4 such as 0V.

In addition, the control signals PG[1]~PG[3] can be logic levels 0, 1, 1 respectively, and the reverse signals PG[1]B~PG[3]B can be logic levels 1, 0 respectively. , 0. According to the voltage values of voltages V1~V4, control signals PG[1]~PG[3] and their reverse signals PG[1]B~PG[3]B, word line signal generation circuits 3111~3113 can generate The word line signal of 0 volts is used to drive the word lines WL11˜WL13, and the word line signal generating circuits 3121˜3123 can generate word line signals of 7.5, 0, and 0 volts respectively to drive the word lines WL21˜WL23. In this way, the word line WL21 is the selected word line, and the remaining word lines WL11˜WL13, WL22 and WL23 are the unselected word lines.

Please refer to FIG. 5 below. FIG. 5 is a schematic diagram of programming operations of a stacked memory device according to an embodiment of the present invention. Also take the hardware architecture of the stacked memory device 300 in FIG. 3 as an example. In FIG. 5, in the stylized action, the voltage generators 3131, 3132 generate voltages V1 and V2 with the same voltage value, for example, 0 volts, and the voltage generator 3133 generates a voltage V3 with a stylized voltage value, the stylized voltage The value is for example 13 volts. The voltage generator 3134 generates a voltage V4 such as 0V.

In addition, the control signals PG[1]~PG[3] can be logic levels 0, 1, 1 respectively, and the reverse signals PG[1]B~PG[3]B can be logic levels 1, 0 respectively. , 0. According to the voltage value of voltage V1~V4, control signal PG[1]~PG[3] and its reverse signal PG[1]B~PG[3]B, word line signal generation circuits 3111~3113 can generate word line signals of 0 volts to drive word line WL11~WL13, word line signal generation circuits 3121~3123 Then word line signals of 13, 0, and 0 volts can be generated to drive the word lines WL21 - WL23 . In this way, the word line WL21 is the selected word line, and the remaining word lines WL11˜WL13, WL22 and WL23 are the unselected word lines.

Please refer to FIG. 6 below. FIG. 6 is a schematic diagram of the block erase operation of the stacked memory device according to the embodiment of the present invention. Also take the hardware architecture of the stacked memory device 300 in FIG. 3 as an example. In FIG. 6 , in the block erase operation, the voltage generator 3131 generates a voltage V1 with a voltage value of, for example, 5 volts, and the voltage generator 3132 generates a voltage V2 with a voltage value of, for example, −8 volts. The voltage generator 3133 generates a voltage V3 having an erase voltage value, such as -8 volts. The voltage generator 3134 also generates a voltage V4 of the erase voltage value.

In addition, the control signals PG[1]~PG[3] can be logic levels 0, 0, and 0 respectively, and the reverse signals PG[1]B~PG[3]B can be logic levels 1, 1 respectively. ,1. According to the voltage values of voltages V1~V4, control signals PG[1]~PG[3] and their reverse signals PG[1]B~PG[3]B, word line signal generation circuits 3111~3113 can generate The word line signal of 5 volts is used to drive the word lines WL11 ˜ WL13 , and the word line signal generation circuits 3121 ˜ 3123 can generate word line signals of -8 volts to drive the word lines WL21 ˜ WL23 . In this way, the word lines WL21˜W23 are the selected word lines, and the remaining word lines WL11˜WL13 are the unselected word lines. That is to say, all the memory cells in the memory cell array SLT2 can be selected to be erased, and the memory cell array All memory cells in column SLT1 are inhibited and not erased.

Please refer to FIG. 7 below. FIG. 7 is a schematic diagram of a selected word line erase operation of the stacked memory device according to an embodiment of the present invention. Also take the hardware architecture of the stacked memory device 300 in FIG. 3 as an example. In FIG. 7 , in the erase operation of the selected word line, the voltage generator 3131 generates a voltage V1 with a voltage value of, for example, 5 volts, and the voltage generator 3132 generates a voltage value of, for example, a voltage V2 of 5 volts. The voltage generator 3133 generates a voltage V3 of, for example, 5 volts. The voltage generator 3134 generates a voltage V4 of an erasing voltage value, such as -8 volts.

In addition, the control signals PG[1]~PG[3] can be logic levels 0, 1, and 0 respectively, and the reverse signals PG[1]B~PG[3]B can be logic levels 1, 0 respectively. ,1. According to the voltage values of the voltages V1~V4, the control signals PG[1]~PG[3] and their reverse signals PG[1]B~PG[3]B, the word line signal generating circuits 3111~3113 can generate The word line signals of 5, 3, and 5 volts are used to drive the word lines WL11~WL13, and the word line signal generating circuits 3121~3123 can generate word line signals of 5, -8, and 5 volts respectively to drive the words Lines WL21~WL23. In this way, only the word line WL22 can be the selected word line, and the rest of the word lines WL11˜WL13, W21, W23 are not selected word lines. That is to say, only the memory cell corresponding to the single word line WL22 can be erased, and the rest of the memory cells can be masked but not erased.

That is to say, in this embodiment, by setting one of the control signals PG[1]~PG[3] to logic level 1, and working with the voltage generator 3132 or 3134 to provide the erasing voltage value, it can be selected The word line on which the erase operation is to be performed, and the erase operation is performed on all or part of the memory cells on the single word line.

It is worth mentioning that in this embodiment, the word line signal generating circuit 3112 transmits the voltage V2 by turning on the lower N-type transistor to generate the word line signal for driving the word line WL22. Based on the body effect of the N-type transistor, the word line signal generated by the word line signal generating circuit 3112 can be slightly lower than the voltage V2, and can be equal to 3 volts.

Please refer to FIG. 8 and FIG. 9 below. FIG. 8 and FIG. 9 respectively illustrate a schematic view of an erasing manner of one or more memory cells in the selected word line erasing operation according to an embodiment of the present invention. In FIG. 8, corresponding to the embodiment of FIG. 7, when the word line WL21 is set as the selected word line, by making the source line switch SLT and the bit line switch BLT all be turned on, the word line WL21 can be turned on. All memory cells in are erased. In this embodiment, the word line signal on the word line WL21 is, for example, -8 volts, and the word line signals on the other unselected word lines WL11 , WL12 and WL22 are, for example, 5 volts. In addition, in this embodiment, the source line switch SLT is coupled between the source end of the memory cell and the common source line CSL, and the bit line switch BLT is coupled between the bit line end of the memory cell and the common bit line. GBL room. When performing the erase operation, the voltage on the common bit line GBL is, for example, 5-8 volts.

In this embodiment, the memory cell arrays corresponding to the word lines WL11 and WL12 and the memory cell arrays corresponding to the word lines WL21 and WL22 are all three-dimensional stacked AND flash memory cell arrays.

In FIG. 9, also corresponding to the embodiment of FIG. 7, when the word line WL21 is set as the selected word line, and only the selected memory cell MCS is to be erased, the corresponding selected memory cell The selected source line switch SSLT of the MCS is broken open, and make other source line switches SLT be turned on, make the selected bit line switch SBLT corresponding to the selected memory cell MCS be turned on, and make other bit line switches BLT be turned off, then the selected The memory cell MCS is erased. That is to say, any one or more memory cells on the selected word line can be selected to perform the erasing operation by adjusting the on or off state of the source line switch and the bit line switch.

In this embodiment, the word line signal on the word line WL21 is, for example, -8 volts, and the word line signals on the other unselected word lines WL11 , WL12 and WL22 are, for example, 5 volts. In addition, in this embodiment, the source line switch SLT is coupled between the source end of the memory cell and the common source line CSL, and the bit line switch BLT is coupled between the bit line end of the memory cell and the common bit line. GBL room. When performing the erase operation, the voltage on the common bit line GBL is, for example, 5-8 volts.

Please refer to FIG. 10 below. FIG. 10 is a schematic diagram of an arbitrary bit line erase operation of the memory device according to an embodiment of the present invention. In FIG. 10 , in any selected word line erase operation, the voltage generator 10131 generates a voltage V1 with a voltage value of, for example, 5 volts, and the voltage generator 10132 generates a voltage value of, for example, a voltage V2 of 5 volts. The voltage generator 10133 generates a voltage V3 of, for example, 5 volts, and the voltage generator 10134 generates a voltage V4 of an erasing voltage value, such as -8 volts.

In addition, the control signals PG[1]~PG[3] can be logic levels 0, 1, 1 respectively, and the reverse signals PG[1]B~PG[3]B can be logic levels 1, 0 respectively. , 0. According to the voltage values of voltages V1~V4, control signals PG[1]~PG[3] and their reverse signals PG[1]B~PG[3]B, word line signal generation circuits 10111~10113 can generate 5, 3, 3 volt word line signal to drive word line WL11~WL13, word line signal The signal generation circuits 10121-10123 can generate word-line signals of 5, -8, -8 volts respectively to drive the word-lines WL21-WL23. In this way, the word lines WL22 and WL23 are all selected word lines, and the rest of the word lines WL11˜WL13 and W21 are unselected word lines.

According to the above description, it can be known that in this embodiment, any one or more word lines can be selected so that the corresponding memory cells can be erased, and the remaining memory cells can be masked but not erase.

To sum up, the word line signal generating circuit of the present invention can generate word line signals on different word lines according to mutually independent voltages. By adjusting the voltage value of each word line signal, during the erase operation, the erase operation can be performed on a selected word line or memory cells on multiple word lines, effectively improving the freedom of data writing in memory devices Speed, improve the data access performance of the memory device.

100: word line driver

110, 120: word line signal generation circuit

131~134: Voltage generator

PG: control signal

SLT1, SLT2: memory cell array

V1, V2, V3, V4: Voltage

WL1, WL2: word line

WLS1, WLS2: word line signal

Claims (19)

A word line driver, comprising: a first word line signal generating circuit, used to drive a first word line, select one of a first voltage and a second voltage according to a control signal to generate a The first word line signal; and a second word line signal generating circuit, used to drive a second word line, according to the control signal to select one of a third voltage and a fourth voltage to generate a second word line signal; a first voltage generator coupled to the first word line signal generating circuit for providing the second voltage; and a second voltage generator coupled to the second word line a signal generating circuit for providing the fourth voltage, wherein the first voltage generator and the second voltage generator are independent of each other, wherein the first word line signal generating circuit and the second word line signal generating circuit Each of them includes: a first transistor with a first terminal receiving the first voltage or the third voltage, a control terminal of the first transistor receiving the control signal, and a second terminal of the first transistor coupled to To the corresponding word line; a second transistor, with a first terminal coupled to the second terminal of the first transistor, the control terminal of the second transistor receives the control signal, the second transistor of the second transistor Two terminals receive the second voltage or the fourth voltage; and a third transistor having a first terminal coupled to the first transistor of the first transistor terminal, the control terminal of the third transistor receives the reverse signal of the control signal, and the second terminal of the third transistor is coupled to the second terminal of the first transistor. The word line driver as claimed in claim 1, further comprising: a third voltage generator coupled to the first word line signal generating circuit for providing the first voltage; and a fourth voltage generator, coupled to the second word line signal generation circuit for providing the third voltage. The word line driver as claimed in item 2, wherein each of the third voltage generator and the fourth voltage generator is a voltage shifter, and the third voltage generator is based on a first selection signal The logic level is used to determine the voltage value of the first voltage, and the fourth voltage generator determines the voltage value of the third voltage according to the logic level of a second selection signal. The word line driver as claimed in item 1, wherein in a read operation, the voltage value of the first voltage is the same as that of the second voltage, and the first word line signal generating circuit generates the first word line signal to make the first word line an unselected word line; the third voltage is a read voltage value, the fourth voltage is the same as the first voltage, and the second word line signal generation circuit Make the second word line signal equal to the read voltage value to make the second word line a selected word line, or make the second word line signal equal to the fourth voltage to make the second word line for unselected character lines. The word line driver according to claim 1, wherein in a programming operation, the first voltage and the second voltage have the same voltage value, and the first word line signal generating circuit generates the first word line signal to make the first word line an unselected word element line; the third voltage is a programmed voltage value, the fourth voltage is the same as the voltage value of the first voltage, and the second word line signal generating circuit makes the second word line signal equal to the programmed voltage value to make the second wordline a selected wordline, or make the second wordline signal equal to the fourth voltage to make the second wordline an unselected wordline. The word line driver as claimed in item 1, wherein in a block erase operation, the first voltage is greater than the second voltage, and the first word line signal generation circuit makes the first word line signal equal to The first voltage makes the first word line an unselected word line; the third voltage is equal to an erasing voltage value, and the second word line signal generating circuit makes the second word line signal equal to the erase The voltage value is divided to make the second word line a selected word line. The word line driver according to claim 1, wherein in a selected word line erase operation, the first voltage is equal to the second voltage, and the first word line signal generating circuit generates the word line signal according to the second voltage the first word line signal, and make the first word line a masked word line; the second word line signal generating circuit makes the second word line signal equal to an erasing voltage value so that the first word line signal The second character line is the selected character line. The word line driver as claimed in claim 7, wherein the erase voltage value is less than zero. The word line driver as claimed in claim 1, wherein the first transistor is a P-type transistor, and the second transistor and the third transistor are N-type transistors. The word line driver as claimed in item 9, wherein the first transistor is disposed on the N-type well region, and the second transistor and the third transistor are disposed on the P-type well region. The word line driver as claimed in item 1, wherein each of the first voltage generator and the second voltage generator is a voltage shifter, and the first voltage generator is based on a first selection signal The logic level is used to determine the voltage value of the second voltage, and the second voltage generator determines the voltage value of the fourth voltage according to a logic level of a second selection signal. The word line driver as claimed in claim 1, wherein the first word line signal generation circuit and the second word line signal generation circuit are both disposed on a Mitsui substrate. A stacked memory device, comprising: a word line driver, including: a plurality of first word line signal generating circuits, used to respectively drive a plurality of first word lines, and select a word line according to a plurality of first control signals One of the first voltage and a second voltage is used to generate the first word line signals; a plurality of second word line signal generating circuits are used to respectively drive a plurality of second word lines, according to the plurality of first word line signals Two control signals are used to select one of a third voltage and a fourth voltage to generate the second word line signals; a first voltage generator, coupled to the first word line signal generating circuits, is used for to provide the second voltage; and a second voltage generator coupled to the second word line signal generating circuits to provide the fourth voltage, wherein the first voltage generator and the second voltage generator are independent; and a first memory A cell array, coupled to the first word lines; and a second memory cell array, coupled to the second word lines, wherein the first word line signal generating circuits are connected to the second word lines Each of the signal generating circuits includes: a first transistor having a first terminal receiving the first voltage or the third voltage, and a control terminal of the first transistor receiving one of the first control signals or For one of the second control signals, the second end of the first transistor is coupled to the corresponding word line; a second transistor has a first end coupled to the second end of the first transistor. terminal, the control terminal of the second transistor receives one of the first control signals or one of the second control signals, and the second terminal of the second transistor receives the second voltage or the first Four voltages; and a third transistor having a first end coupled to the first end of the first transistor, the control end of the third transistor receiving one of the first control signals or the first control signals For an inverse signal of one of the two control signals, the second terminal of the third transistor is coupled to the second terminal of the first transistor. The stacked memory device as claimed in claim 13, wherein the first memory cell array and the second memory cell array are three-dimensional flash memory cell arrays. The stacked memory device as described in claim 13, further comprising: a third voltage generator coupled to the first word line signal generating circuits for providing the first voltage; and a fourth voltage generator coupled to the second word line signal generating circuits for to provide the third voltage, wherein each of the first voltage generator and the second voltage generator is a first voltage shifter, and the first voltage generator is based on a logic level of a first selection signal To determine the voltage value of the second voltage, the second voltage generator determines the voltage value of the fourth voltage according to the logic level of a second selection signal; the third voltage generator and the fourth voltage generator Each is a second voltage shifter, the third voltage generator determines the voltage value of the first voltage according to the logic level of a third selection signal, and the fourth voltage generator determines the voltage value of the first voltage according to a fourth selection signal to determine the voltage value of the third voltage. The stacked memory device according to claim 13, wherein in a read operation, the first voltage and the second voltage have the same voltage value, and each of the first word line signal generating circuits generates each of the first word line signal so that each of the first word lines is an unselected word line; the third voltage is a read voltage value, the fourth voltage is the same as the voltage value of the first voltage, and each of the second word lines The element line signal generation circuit makes each of the second word line signals equal to the read voltage value so that each of the second word lines is a selected word line, or makes each of the second word line signals equal to the fourth voltage so that each of the second word lines is an unselected word line. The stacked memory device according to claim 13, wherein in a programming operation, the first voltage and the second voltage have the same voltage value, each of the first voltage A word line signal generating circuit generates the first word line signal so that each of the first word lines is an unselected word line; the third voltage is a programming voltage value, and the fourth voltage is the same as the first word line The voltage values of the voltages are the same, each of the second word line signal generating circuits makes each of the second word line signals equal to the programming voltage value so that each of the second word lines is a selected word line, or makes each of the second word line signals The second wordline signal is equal to the fourth voltage so that each of the second wordlines is an unselected wordline. The stacked memory device according to claim 13, wherein in a block erase operation, the first voltage is greater than the second voltage, and each of the first word line signal generating circuits makes the first word line The signal is equal to the first voltage so that each of the first word lines is an unselected word line; the third voltage is equal to an erasing voltage value, and each of the second word line signal generation circuits makes each of the second word lines The line signal is equal to the erase voltage value to make each of the second word lines a selected word line. The stacked memory device according to claim 13, wherein in a selected word line erase operation, the first voltage is equal to the second voltage, and each of the first word line signal generating circuits is based on the second voltage Generate each of the first word line signals, and make each of the first word lines a masked word line; a selected second word line corresponding to a selected word line in the second word line signal generating circuits The second word line signal generating circuit makes the second word line signal of the selected second word line signal generating circuit equal to an erasing voltage value according to the second control signals; the second word line signal generates A plurality of unselected second word line generation circuits not corresponding to the selected word line in the circuit make the second word lines corresponding to the unselected second word line generation circuits according to the second control signals Element lines are masked element lines.

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