TWI792617B - Methods of manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.

Description

Method for manufacturing semiconductor device

Embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. [CROSS-REFERENCE TO RELATED APPLICATIONS]

The entire contents of Korean Patent Application No. 10-2020-0136089 filed on October 20, 2020 at the Korea Intellectual Property Office and entitled "Methods of Manufacturing Semiconductor Device" are incorporated herein by reference. refer to.

Research is ongoing to reduce the size of elements constituting semiconductor devices and to improve the performance of the elements. For example, in dynamic random-access memory (DRAM) devices, research is ongoing to reliably and stably form elements with reduced sizes.

According to an exemplary embodiment, a method of manufacturing a semiconductor device includes: forming a lower structure including a plurality of transistors; forming a conductive layer on the lower structure; forming a first preliminary pad mask pattern on the conductive layer; a wiring mask pattern; forming a pad mask pattern by patterning the first preliminary pad mask pattern while protecting the wiring mask pattern; and using the pad mask pattern and the The wiring mask pattern is used as an etching process of the etching mask to etch the conductive layer to form pad patterns and wiring patterns.

According to an exemplary embodiment, a method of manufacturing a semiconductor device includes: forming a lower structure including a first transistor and a second transistor; forming a conductive layer on the lower structure; forming a first mask on the conductive layer layer; the first mask layer is patterned in a patterning process using a first photolithography process to form a first preliminary pad mask pattern and a wiring mask pattern, and the first photolithography process uses extreme ultraviolet (EUV) light as a first light source; using multiple patterning techniques to form a second preliminary pad mask pattern and a wiring mask protective layer; using the second preliminary pad mask pattern and the wiring mask etching the first preliminary pad mask pattern as an etching process of the etching mask to form a pad mask pattern while protecting the wiring mask pattern; and using the pad mask pattern And the pattern of the wiring mask is used as an etching process of the etching mask to etch the conductive layer to form a pad pattern and a wiring pattern. The pad patterns are electrically connected to the first transistor, and at least some of the wiring patterns are electrically connected to the second transistor. The multiple patterning technique includes performing at least one second photolithography process using deep ultraviolet (DUV) light having a longer wavelength than the extreme ultraviolet (EUV) light as a second light source wavelength, and the multiple patterning technique further includes performing one or more patterning processes, and the patterning process includes performing a deposition process and an etching process without using a photolithography process.

According to an exemplary embodiment, a method of manufacturing a semiconductor device includes: forming a conductive layer on a semiconductor substrate; and patterning the conductive layer to form a pad pattern and a wiring pattern. Patterning the conductive layer includes: performing a first patterning process including a first photolithography process using extreme ultraviolet (EUV) light as a first light source; and performing a second patterning process , the second patterning process includes a second photolithography process using deep ultraviolet (DUV) light as a light source, the deep ultraviolet (DUV) light having a wavelength longer than that of the extreme ultraviolet (EUV) light. The second patterning process is performed after the first patterning process is performed. The pad pattern is formed after performing both the first patterning process and the second patterning process. The wiring pattern is formed by the first patterning process before performing the second patterning process.

1A is a plan view schematically showing an example of a semiconductor device according to an exemplary embodiment, FIG. 1B is a plan view showing a pad pattern 49c shown in FIG. 1A , and FIG. 2A is along the line I-I shown in FIG. 1A. ' and II-II' cross-sectional views, and Figure 2B is a cross-sectional view along the line III-III' shown in Figure 1A.

Referring to FIG. 1A, FIG. 1B, FIG. 2A and FIG. 2B, a semiconductor device 1 according to an exemplary embodiment may include: a lower structure 3 having a plurality of transistors CTR and PTR; a pad pattern 49c and a wiring pattern 49p located in the lower structure 3; and the data storage structure 97, which is electrically connected to the pad pattern 49c on the lower structure 3.

In an exemplary embodiment, the lower structure 3 may include: a semiconductor substrate 5 having a first region MA and a second region PA; a first active region 7a1 located on the semiconductor substrate 5 in the first region MA; a second active region 7a2 , on the semiconductor substrate 5 in the second area PA; the first device isolation region 7s1 on the side surface of the first active region 7a1; and the second device isolation region 7s2 on the side surface of the second active region 7a2.

In the following, for the convenience of description, description will be given around a first active region 7a1 and a second active region 7a2. Also, in the following, even in the case where the description focuses on one component, it is understood that the one component may be provided in plural.

In an exemplary embodiment, the lower structure 3 may further include: one or more gate trenches 12 crossing the first active region 7a1 and extending to the first device isolation region 7s1; a first gate structure 15 disposed on the gate and the first impurity region 9a and the second impurity region 9b are disposed in the first active region 7a1 adjacent to the side surface of the first gate structure 15 . Each of the first gate structures 15 may include: a first gate electrode 17b; a first gate dielectric 17a between the first gate electrode 17b and the first active region 7a1; and a first gate The top cover layer 17c is located on the first gate electrode 17b. The first gate electrode 17b may be formed of a conductive material, and the first gate capping layer 17c may be formed of an insulating material. For example, the first gate electrode 17b may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, graphene, carbon nanotube or a combination thereof. For example, the first gate electrode 17b can be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi , TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO _x , RuO _x , graphene, carbon nanotubes or a combination thereof, but the material is not limited thereto. The first gate electrode 17b may include a single layer or a plurality of layers of the aforementioned materials.

Any one of the first gate structures 15 and the first impurity region 9a and the second impurity region 9b disposed on both sides of the first gate structure 15 can constitute a first transistor CTR. In this case, the first impurity region 9a and the second impurity region 9b may be first source/drain regions.

In an exemplary embodiment, the lower structure 3 may further include: a second gate structure 123 disposed on the second active region 7a2; a peripheral gate capping layer 127 disposed on the second gate structure 123; and a second The source/drain regions 131 are disposed in the second active region 7 a 2 on both sides of the second gate structure 123 . The second gate structure 123 may include a second gate dielectric 124 and a second gate electrode 125 on the second gate dielectric 124 . The second gate electrode 125 may include a first electrode material layer 125a, a second electrode material layer 125b and a third electrode material layer 125c stacked in sequence. For example, the first electrode material layer 125a may include doped silicon (such as polysilicon with N-type conductivity or polysilicon with P-type conductivity), and the second electrode material layer 125b may include a metal-semiconductor compound (such as tungsten silicide), and the third electrode material layer 125c may include metal (such as tungsten). The second gate electrode 125 and the second source/drain region 131 can constitute a second transistor PTR. The peripheral gate capping layer 127 may be formed of an insulating material such as silicon nitride.

In an exemplary embodiment, the first area MA may be a memory cell area in which memory cells storing information are disposed, and the second area PA may be disposed in the same area as the first area. A peripheral area or a peripheral circuit area in the area adjacent to the MA. Hereinafter, in the following description, the first area MA will be referred to as a memory cell area, and the second area PA will be referred to as a peripheral circuit area.

In an exemplary embodiment, the first active area 7a1 may be a cell active area, and the second active area 7a2 may be a peripheral active area. Hereinafter, the first active area 7a1 will be called a cell active area, and the second active area 7a2 will be called a peripheral active area.

In an exemplary embodiment, the first transistor CTR may be a cellular transistor or a cellular switching device, and the second transistor PTR may be a peripheral transistor or a peripheral circuit transistor. Hereinafter, the first transistor CTR will be called a cell transistor, and the second transistor PTR will be called a peripheral transistor. The first gate electrode 17b of the cell transistor CTR can be a cell gate electrode or a word line, and the second gate electrode 125 of the peripheral transistor PTR can be a peripheral gate electrode.

In an exemplary embodiment, the lower structure 3 may further include a buffer insulating layer 20 formed on the cell active region 7a1 and the first device isolation region 7s1.

In an exemplary embodiment, the lower structure 3 may further include a bit line structure 23 and a contact plug 43 . The bit line structure 23 may include a bit line 25 and a bit line capping layer 27 stacked in sequence. Bit line 25 may be formed of a conductive material. The bit line 25 may include a first bit line material layer 25 a , a second bit line material layer 25 b and a third bit line material layer 25 c stacked in sequence. For example, the first bit line material layer 25a may include doped silicon (such as polysilicon with N-type conductivity), and the second bit line material layer 25b may include a metal-semiconductor compound (such as tungsten silicide), And the third bit line material layer 25c may include metal (such as tungsten). The bit line cap layer 27 may include a first bit line cap layer 27 a , a second bit line cap layer 27 b and a third bit line cap layer 27 c stacked in sequence. The bit line capping layer 27 may be formed of an insulating material. Each of the first bitline cap layer 27a, the second bitline cap layer 27b, and the third bitline cap layer 27c may be formed of silicon nitride or a silicon nitride-based insulating material.

In an exemplary embodiment, the bit line 25 may further include a bit line contact portion 25d extending downward from the first bit line material layer 25a and electrically connected to the first impurity region 9a. The bit line 25 may be formed on the buffer insulating layer 20, and the bit line contact portion 25d of the bit line 25 may penetrate through the buffer insulating layer 20 to contact the first impurity region 9a.

In exemplary embodiments, the contact plug 43 may penetrate through the buffer insulating layer 20 and may contact the second impurity region 9b. The contact plug 43 may include doped silicon (eg, polysilicon with N-type conductivity).

In an exemplary embodiment, the lower structure 3 may further include: a bit line spacer 29 that may contact the side surface of the bit line structure 23 and may be formed of an insulating material; and a peripheral gate spacer 129 that may contact the second gate The side surface of the pole structure 123 may be formed of insulating material.

In an exemplary embodiment, the lower structure 3 may further include a partition wall insulating pattern 40 contacting a contact plug 43 between a pair of bit lines 25 adjacent to and parallel to each other. For example, between a pair of adjacent and parallel bit lines 25 , a plurality of contact plugs 43 may be disposed, and the partition wall insulating pattern 40 may be disposed between the plurality of contact plugs 43 .

In an exemplary embodiment, the lower structure 3 may further include an insulating liner 134 covering the peripheral active region 7a2 and the second device isolation region 7s2 and covering the surface of the peripheral gate spacer 129 and the second gate structure. 123 upper surface. The lower structure 3 may further include: a first interlayer insulating layer 137 located on the insulating liner 134 ; and a second interlayer insulating layer 140 located on the first interlayer insulating layer 137 . In an example, a portion of the insulating liner 134 on the upper surface of the second gate structure 123 may contact the second insulating interlayer 140 . The second gate structure 123 may be a peripheral gate structure.

In exemplary embodiments, the first insulating interlayer 137 may be formed of a material different from those of the insulating liner 134 and the second insulating interlayer 140 . For example, the first interlayer insulating layer 137 may be formed of silicon oxide or a silicon oxide-based insulating material, and the insulating liner 134 and the second interlayer insulating layer 140 may be formed of silicon nitride or a silicon nitride-based insulating material.

The pad pattern 49 c can be disposed on the memory cell area MA of the semiconductor substrate 5 , and the wiring pattern 49 p can be disposed on the peripheral circuit area PA of the semiconductor substrate 5 .

The pad pattern 49c and the wiring pattern 49p may be formed of the same conductive material. For example, each of the pad pattern 49 c and the wiring pattern 49 p may include a first conductive material layer 51 and a second conductive material layer 53 on the first conductive material layer 51 . For example, the first conductive material layer 51 may include metal nitride (such as titanium nitride), and the second conductive material layer 53 may include metal (such as tungsten).

In an exemplary embodiment, each of the pad patterns 49c may include: a pad portion 49c1 located on the lower structure 3; and a first plug portion 49c2 extending from the pad portion 49c1 into the lower structure 3 and Electrically connected to the contact plug 43 . Therefore, the pad pattern 49 c can be electrically connected to the cell transistor CTR through the contact plug 43 .

In an exemplary embodiment, at least one of the wiring patterns 49p may include: a wiring portion 49p1 positioned on the lower structure 3; and a second plug portion 49p2 extending from the wiring portion 49p1 into the lower structure 3 and electrically connected To the peripheral transistor PTR. Therefore, at least some of the wiring patterns 49p can be electrically connected to the peripheral transistor PTR.

In an exemplary embodiment, the lower structure 3 may further include: a first metal-semiconductor compound layer 46 electrically connecting the contact plug 43 and the first plug portion 49c2 between the contact plug 43 and the first plug portion 49c2 49c2; and a second metal-semiconductor compound layer 146, electrically connecting the second source/drain region 131 and the second plug portion 49p2 between the second source/drain region 131 and the second plug portion 49p2 .

In an exemplary embodiment, as shown in FIG. 1A, when viewed in a plan view, the bit line 25 may have a line shape extending in the first horizontal direction X, and the first gate electrode 17b (eg, the word line) may have a line shape extending in a second horizontal direction Y perpendicular to the first horizontal direction X. As shown in FIG. 1B , each of the pad patterns 49c may have a first side S1 and a second side S2 opposite to and parallel to each other, and a third side S3 and a fourth side S4 opposite to and parallel to each other. . Each of the pad patterns 49c may have a first side S1, a second side S2, a third side S3, and a fourth side S4, and may include the first side S1, the second side S2, the third side S3, and the fourth side S4. The fourth sides S4 have a circular shape in the area where they meet each other. For example, each of the pad patterns 49c may have edges such as a first side S1, a second side S2, a third side S3, and a fourth side S4 when viewed in a plan view, and may have edges in which S1, S2, S3, and S4 have circular shapes in portions where they are adjacent to each other. In an exemplary embodiment, each of the pad patterns 49c may have an oval shape, a circle shape, or a quadrangular shape in which apex portions are rounded.

In an exemplary embodiment, in each of the pad patterns 49c, the first side S1 and the second side S2 may have a line shape extending in the first diagonal direction D1 when viewed in a plan view. , the first diagonal direction D1 forms an acute angle with respect to the first horizontal direction X, and the third side S3 and the fourth side S4 may have a line shape extending in the second diagonal direction D2, the second diagonal direction D2 forms an obtuse angle with respect to the first horizontal direction X.

In an exemplary embodiment, in the pad pattern 49c, among the pad patterns sequentially arranged in the first diagonal direction D1 when viewed in a plan view, the first side S1 may be on the first diagonal aligned in the direction D1, and the second side S2 may be aligned in the first diagonal direction D1. In an exemplary embodiment, in the pad pattern 49c, in the pad patterns sequentially arranged in the second diagonal direction D2 in plan view, the third side S3 may be in the second diagonal direction D2 aligned, and the fourth side S4 may be aligned in the second diagonal direction D2.

The semiconductor device 1 according to an exemplary embodiment may further include a first insulating pattern 92a filled between the pad patterns 49c and a second insulating pattern 92b filled between the wiring patterns 49p on the lower structure 3 . The first insulating pattern 92a may be filled between the pad portions 49c1 of the pad pattern 49c and extended into the lower structure 3, and the second insulating pattern 92b may be filled between the wiring portions 49p1 of the wiring pattern 49p and extended to the lower structure. 3 in. The lower surface of each of the first insulating pattern 92a and the second insulating pattern 92b may be provided at a lower level than that of each of the pad portion 49c1 and the wiring portion 49p1, for example, of the semiconductor substrate 5. The distance between the bottom and the lower surface of each of the first insulating pattern 92a and the second insulating pattern 92b may be smaller than the corresponding distance between the bottom of the semiconductor substrate 5 and the lower surface of the pad portion 49c1 and the lower surface of the wiring portion 49p1. the distance between them.

In an exemplary embodiment, data storage structure 97 may be a capacitor that stores information in a DRAM device. For example, the data storage structure 97 may include: a first electrode 97a electrically connected to the pad pattern 49c on the pad pattern 49c; a second electrode 97c covering the first electrode 97a; and a dielectric layer 97b disposed on the pad pattern 49c. Between the first electrode 97a and the second electrode 97c. Dielectric layer 97b may be the dielectric layer of a capacitor that stores information in a DRAM device.

In another embodiment, the data storage structure 97 may be able to be stored in a non-volatile memory device (such as a magnetoresistive random-access memory (MRAM) device or a variable resistance memory device) A data storage structure that stores information.

The semiconductor device 1 according to an exemplary embodiment may further include an etch stop insulating layer 94 on the first and second insulating patterns 92a and 92b and the wiring pattern 49p.

The semiconductor device 1 according to an exemplary embodiment may further include an upper insulating layer 99 covering the wiring pattern 49 p on the etch stop insulating layer 94 on the second area PA of the semiconductor substrate 5 .

Next, another example of the semiconductor device according to the exemplary embodiment will be explained with reference to FIGS. 3 , 4A, and 4B. FIG. 3 is a schematic plan view illustrating another example of a semiconductor device according to an exemplary embodiment. 4A is a cross-sectional view along lines IV-IV' and V-V' shown in FIG. 3 , and FIG. 4B is a cross-sectional view along line VI-VI' shown in FIG. 3 .

Referring to FIGS. 3 , 4A and 4B , a semiconductor device 200 according to an exemplary embodiment may include a lower structure 203 , a pad pattern 260 c , a wiring pattern 260 p and a data storage structure 280 . The semiconductor device 200 according to an exemplary embodiment may further include first insulating patterns 262a filled between the pad patterns 260c and second insulating patterns 262b filled between the wiring patterns 260p.

The lower structure 203 may include a semiconductor substrate 205, and the semiconductor substrate 205 includes a memory cell area MA' and a peripheral circuit area PA'. The lower structure 203 may further include a plurality of first conductive lines 220 disposed on the memory cell area MA', a channel layer 230c, a lower source/drain region 230s, an upper source/drain region 230d, and a cell gate pole electrode 240 and cell gate dielectric 250.

The channel layer 230c, the lower source/drain region 230s, the upper source/drain region 230d, the cell gate electrode 240 and the cell gate dielectric 250 can form a vertical channel transistor CTR'. In this case, the vertical channel transistor CTR' can also be called a cell transistor. The vertical channel transistor CTR′ may refer to a structure in which the channel length of each of the channel layers 230 c extends in the vertical direction Z from the semiconductor substrate 205 .

On the peripheral circuit area PA', the lower structure 203 may further include: a peripheral active region 307a, disposed on the semiconductor substrate 205; a peripheral device isolation region 307s, located on the side surface of the peripheral active region 307a; a peripheral gate structure 323, disposed on the peripheral active region 307a; peripheral source/drain regions 331 disposed in the peripheral active region 307a on both sides of the peripheral gate structure 323; and peripheral gate spacers 329 on the sides of the peripheral gate structure 323 On the surface.

The perimeter gate structure 323 may include: a perimeter gate dielectric 324 ; a perimeter gate electrode 325 on the perimeter gate dielectric 324 ; and a perimeter gate capping layer 327 on the perimeter gate electrode 325 . The perimeter gate capping layer 327 may be formed of an insulating material. The peripheral gate electrode 325 and the peripheral source/drain region 331 can constitute a peripheral transistor PTR′.

In the peripheral circuit area PA′, the lower structure 203 may further include a lower insulating layer 340 covering the peripheral transistor PTR′.

In the memory cell area MA′, the lower structure 203 may further include a lower insulating layer 212 disposed on the semiconductor substrate 205 . The plurality of first conductive lines 220 may be spaced apart from each other in the first horizontal direction X and extend in the second horizontal direction Y on the lower insulating layer 212 .

On the memory cell area MA′, the lower structure 203 may further include a plurality of first lower insulating patterns 222 filling the plurality of first lower insulating patterns 222 on the lower insulating layer 212 . spaces between conductive lines 220 . The plurality of first lower insulating patterns 222 may extend in the second horizontal direction Y, and upper surfaces of the plurality of first lower insulating patterns 222 may be disposed in contact with the plurality of first conductive lines 220 . on the same level as the upper surface. According to an exemplary embodiment, the plurality of first conductive lines 220 may be used as bit lines of the semiconductor device 200 .

In an exemplary embodiment, the plurality of first conductive lines 220 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the plurality of first conductive lines 220 may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, _IrOx , _RuOx or a combination thereof, but not limited thereto. The plurality of first conductive lines 220 may include a single layer or multiple layers of the aforementioned materials. In an exemplary embodiment, the plurality of first conductive lines 220 may include two-dimensional (Two-Dimensional, 2D) semiconductor materials (such as graphene, carbon nanotubes or combinations thereof).

The channel layer 230c may be arranged in a matrix to be spaced apart from each other in the first horizontal direction X and the second horizontal direction Y on the plurality of first conductive lines 220 . The lower source/drain region 230s, the channel layer 230c and the upper source/drain region 230d can be stacked in sequence. In an exemplary embodiment, one channel layer 230c and the lower source/drain region 230s and upper source/drain region 230d disposed under/on the one channel layer 230c may have The first width has a first height in the vertical direction Z, and the first height may be greater than the first width. For example, the first height may be about 2 to about 10 times the first width, but is not limited thereto.

In exemplary embodiments, the channel layer 230c may include an oxide semiconductor. For example, the oxide semiconductor may include In _x Ga _y Zn _z O, In _x Ga _y S _z O, In x Sn _y Zn _z O, In _x Zn _y O, Zn _x O, Zn _{x Sn y} O, Zn _x O _y N, Zr _x Zn _y Sn _z O, Sn _x O, Hf _x In _y Zn _z O, Ga _x Zn _y Sn _z O, Al _x Zn _y Sn _z O, Yb _x Ga _y Zn _z O, In _x Ga _y O or a combination thereof. The channel layer 230c may include a single layer or a plurality of layers of an oxide semiconductor. In some examples, the channel layer 230c may have a bandgap energy greater than that of silicon. For example, the channel layer 230c may have a bandgap energy of about 1.5 eV to about 5.6 eV. For example, when the channel layer 230c has a bandgap energy of about 2.0 eV to about 4.0 eV, the channel layer 230c may have the best channel performance. For example, the channel layer 230c may be polycrystalline or amorphous, but not limited thereto.

In an exemplary embodiment, the channel layer 230c may include a 2D semiconductor material such as graphene, carbon nanotubes, or a combination thereof. In an exemplary embodiment, the channel layer 230c may include a semiconductor material such as silicon or the like.

In the following, description will be provided focusing on one channel layer 230 c and one cell gate electrode 240 .

The cell gate electrode 240 may extend in the first horizontal direction X on both sidewalls of the channel layer 230c. The cell gate electrode 240 may include: a first sub-gate electrode 240P1 facing a first sidewall of the channel layer 230c; and a second sub-gate electrode 240P2 facing a second sidewall of the channel layer 230c opposite to the first sidewall. side wall. Since one channel layer 230c is disposed between the first sub-gate electrode 240P1 and the second sub-gate electrode 240P2, the semiconductor device 200 according to an exemplary embodiment may have a dual gate transistor structure. However, the embodiment is not limited thereto, and the second sub-gate electrode 240P2 is omitted and only the first sub-gate electrode 240P1 facing the first sidewall of the channel layer 230c may also be formed to implement a single gate transistor structure.

The cell gate electrode 240 may comprise doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. For example, the cell gate electrode 240 can be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi , TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO _x , RuO _x or a combination thereof, but the material is not limited thereto.

The cell gate dielectric 250 may surround the sidewalls of the channel layer 230c and may be interposed between the channel layer 230c and the cell gate electrode 240 . For example, as shown in FIG. 3, the entire sidewall of the channel layer 230c may be surrounded by the cell gate dielectric 250, and a portion of the sidewall of the cell gate electrode 240 may contact the cell gate dielectric 250. . In other embodiments, the cell gate dielectric 250 extends in the extension direction of the cell gate electrode 240 (for example, in the first horizontal direction X), and only faces the cell gate in the sidewall of the channel layer 230c. Two sidewalls of the cell gate electrode 240 may contact the cell gate dielectric 250 .

In an exemplary embodiment, the cell gate dielectric 250 may be formed of a silicon oxide film, a silicon oxynitride film, a high dielectric film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high dielectric film can be formed of metal oxide or metal oxynitride. For example, the high dielectric film that can be used as the cell gate dielectric 250 can be formed of HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ , Al ₂ O ₃ or combinations thereof, but is not limited to this.

On the memory cell area MA′, the lower structure 203 may further include a plurality of second lower insulating patterns 232 disposed on the plurality of first lower insulating patterns 222 . The second lower insulating patterns 232 may extend in the second horizontal direction Y, and the channel layer 230c may be disposed between adjacent two second lower insulating patterns 232 among the plurality of second lower insulating patterns 232 .

On the memory cell area MA', the lower structure 203 may further include a first buried layer 234 and a second buried layer 236, and the first buried layer 234 and the second buried layer 236 are formed on two adjacent second lower insulating patterns. 232 are disposed in the space between two adjacent channel layers 230c. The first burying layer 234 is disposed on the bottom of the space between the two adjacent channel layers 230c, and the second burying layer 236 may be formed to fill between the two adjacent channel layers 230c on the first burying layer 234. the rest of the space between. The upper surface of the second buried layer 236 is disposed at the same level as the upper surface of the upper source/drain region 230 d , and the second buried layer 236 may cover the upper surface of the cell gate electrode 240 . Unlike this, the plurality of second lower insulating patterns 232 may be formed as a material layer continuous with the plurality of first lower insulating patterns 222 , or the second burying layer 236 may be formed as a layer of material adjacent to the first burying layer. 234 consecutive layers of material.

The pad pattern 260c disposed on the memory cell area MA' and the wiring pattern 260p disposed on the peripheral circuit area PA' may be formed of the same material. The pad pattern 260c can be disposed on the upper source/drain region 230d, and can be electrically connected to the upper source/drain region 230d. The pad patterns 260c may vertically overlap the channel layer 230c respectively, and may be arranged in a matrix to be spaced apart in the first horizontal direction X and the second horizontal direction Y. Referring to FIG. The pad pattern 260c and the wiring pattern 260p can be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN , TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO _x , RuO _x or a combination thereof, but not limited thereto.

For example, each of the pad pattern 260c and the wiring pattern 260p may include a first conductive material layer 259a and a second conductive material layer 259b on the first conductive material layer 259a. In another example, the contact pattern may be disposed between the upper source/drain region 230d and the pad pattern 260c. For example, in FIG. 4A, the portion indicated by reference numeral 259a may be referred to as a contact pattern, and the portion indicated by reference numeral 259b may be referred to as a pad pattern.

At least one of the wiring patterns 260p may include: a wiring portion 260p1 located on the lower structure 203 ; and a plug portion 260p2 extending from the wiring portion 260p1 into the lower structure 203 and electrically connected to the peripheral transistor PTR′.

In an exemplary embodiment, the lower structure 203 may further include a metal-semiconductor compound layer 346, and the metal-semiconductor compound layer 346 is electrically connected to the peripheral source/drain region 331 and the plug portion 260p2. Pole region 331 and plug portion 260p2.

Each of the pad patterns 260c may have a first side S1 and a second side S2 opposite to and parallel to each other, and a third side S3 and a fourth side S4 opposite to and parallel to each other. Each of the pad patterns 260c has a first side S1, a second side S2, a third side S3, and a fourth side S4, and wherein the first side S1, the second side S2, the third side S3, and the fourth side The sides S4 may have a circular shape in the area where they meet each other. For example, each of the pad patterns 260c has edges such as a first side S1, a second side S2, a third side S3, and a fourth side S4 when viewed in a plan view, and the edge S1 may be among them. , S2, S3, and S4 have circular shapes in portions where they are adjacent to each other. In an exemplary embodiment, each of the pad patterns 260c may have an oval shape, a circle shape, or a quadrilateral shape with a round apex.

In an exemplary embodiment, in each of the pad patterns 260c, the first side S1 and the second side S2 may have a line extending in a first diagonal direction D1' when viewed in a plan view. shape, the first diagonal direction D1' forms an acute angle with respect to the first horizontal direction X, and the third side S3 and the fourth side S4 may have a line shape extending in the second diagonal direction D2', the second pair The angular direction D2' forms an obtuse angle with respect to the first horizontal direction X. In an exemplary embodiment, in the pad pattern 260c, among the pad patterns sequentially arranged in the first diagonal direction D1' in plan view, the first side S1 may be in the first diagonal direction D1. ', and the second side S2 may be aligned in the first diagonal direction D1'.

In an exemplary embodiment, in the pad pattern 260c, in the pad patterns sequentially arranged in the second diagonal direction D2' in plan view, the third side S3 may be in the second diagonal direction D2. ', and the fourth side S4 may be aligned in the second diagonal direction D2'.

On the memory cell area MA′, the first insulating pattern 262 a may surround sidewalls of the pad pattern 260 c on the plurality of second lower insulating patterns 232 and the second buried layer 236 .

On the memory cell area MA', the etch stop layer 270 may be disposed on the first insulating pattern 262a, and on the peripheral circuit area PA', the etch stop layer 270 may be disposed on the second insulating pattern 262b and the wiring pattern 260p. . On the memory cell area MA′, the data storage structure 280 can be disposed on the etch stop layer 270 .

In an exemplary embodiment, the data storage structure 280 may be a capacitor that stores information in a DRAM. For example, the data storage structure 280 may include a first electrode 282 , a dielectric layer 284 and a second electrode 286 . The first electrode 282 can penetrate through the etch stop layer 270 and be electrically connected to the upper surface of the pad pattern 260c. The first electrode 282 may be formed in a columnar shape extending in the vertical direction Z, but is not limited thereto. In an exemplary embodiment, the first electrodes 282 may be disposed to overlap the pad patterns 260c in a vertical direction and may be arranged in a matrix to be spaced apart in a first horizontal direction X and a second horizontal direction Y. Referring to FIG.

In another embodiment, the data storage structure 280 may be a data storage structure capable of storing information in a non-volatile memory device such as an MRAM device or a variable resistance memory device.

Next, an exemplary embodiment of a method of manufacturing a semiconductor device according to an exemplary embodiment will be explained with reference to FIG. 5A . FIG. 5A is a flowchart schematically illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.

Referring to FIG. 5A , a lower structure including a plurality of transistors may be formed ( S10 ). For example, the substructure may be the substructure 3 explained with reference to FIGS. 1A to 2B . In another example, the lower structure may be the lower structure 203 described with reference to FIGS. 3-4B .

Next, a conductive layer may be formed on the lower structure ( S20 ). For example, the conductive layer may be formed of the same material as the pad pattern 49c and the wiring pattern 49p explained with reference to FIGS. 1A to 2B . In another example, the conductive layer may be formed of the same material as the pad pattern 260c and the wiring pattern 260p described with reference to FIGS. 3 to 4B .

Subsequently, the conductive layer may be patterned to form pad patterns and wiring patterns ( S30 ). A patterning process may be used to form the pad pattern and the wiring pattern. The patterning process includes performing a first patterning process and a second patterning process respectively. The first patterning process includes using extreme ultraviolet (extreme ultraviolet) , EUV) light as a light source, the second patterning process includes a second photolithography process in which deep ultraviolet (deep ultraviolet, DUV) light having a wavelength longer than that of EUV light is used as a light source. film process.

For example, the pad pattern and the wiring pattern may be the pad pattern 49c and the wiring pattern 49p described with reference to FIGS. 1A to 2B . In another example, the pad pattern and the wiring pattern may be the pad pattern 260c and the wiring pattern 260p described with reference to FIGS. 3 to 4B .

Next, referring to FIG. 5B , operation S30 will be explained in detail. FIG. 5B is a process flow diagram of a stage in operation S30 illustrated in FIG. 5A .

Referring to FIG. 5B, a first mask layer can be formed (S35), and the first mask layer can be patterned using a first patterning process to form a first preliminary pad mask pattern and a wiring mask pattern (S45). Using multiple patterning techniques including a second patterning process to form the second preliminary pad mask pattern and the wiring mask protection layer (S55), the second preliminary pad mask pattern and the wiring mask protection layer can be used as The etch process of etching the mask to etch the first preliminary pad mask pattern to form the pad mask pattern while protecting the wiring mask pattern (S65), and the pad mask pattern and the wiring mask pattern can be used The conductive layer is etched as an etching process of etching a mask to form a pad pattern and a wiring pattern ( S75 ). Accordingly, a pad pattern and a wiring pattern as illustrated in FIG. 5A can be formed. Accordingly, operation S30 set forth in FIG. 5A may include operations S35, S45, S55, S65, and S75 set forth with reference to FIG. 5B.

Next, an exemplary embodiment of a method of manufacturing a semiconductor device according to an exemplary embodiment will be explained mainly with reference to FIGS. 6A to 19B . 6A to 19B are cross-sectional views of stages in a method of manufacturing a semiconductor device according to example embodiments. 6A, 8A, 10A, 11A, 12A, 13A, 14A, 16, 17A, 18, and 19A illustrate a sequence of stages in a method of manufacturing a semiconductor device according to an exemplary embodiment. Follow the cross-sectional views of lines II' and II-II' shown in FIG. 1A. 6B, FIG. 8B, FIG. 10B, FIG. 11B, FIG. 12B, FIG. 13B, FIG. 14B, FIG. 17B and FIG. 19B show stages along the line shown in FIG. Sectional view of III-III'. 7 , 9A, 9B and 15 illustrate plan views of stages in a method of manufacturing a semiconductor device according to example embodiments.

Referring to FIG. 1A , FIG. 5A , FIG. 5B , FIG. 6A and FIG. 6B , a lower structure 3 including a plurality of transistors CTR and PTR may be formed (see S10 in FIG. 5A ). As shown in FIG. 5A , the lower structure 3 may be the lower structure 3 explained with reference to FIGS. 1A to 2B , but the embodiment is not limited thereto. For example, the lower structure 3 can be replaced by the lower structure 203 explained with reference to FIGS. 3 to 4B .

A conductive layer 49 may be formed (see S20 in FIG. 5A ). In an exemplary embodiment, forming the conductive layer 49 may include: forming the first opening 45a exposing the upper surface of the contact plug 43 on the memory cell area MA by etching a part of the lower structure 3 and forming the first opening 45a on the peripheral circuit. A second opening 45b exposing the second source/drain region 131 on the area PA; and a conductive material layer formed to cover the upper surface of the lower structure 3 while filling the first opening 45a and the second opening 45b. The conductive layer 49 may include a first conductive material layer 51 and a second conductive material layer 53 formed in sequence.

In an exemplary embodiment, after forming the first opening 45a and the second opening 45b, and before forming the conductive material layer filling the first opening 45a and the second opening 45b, exposed portions of the contact plug 43 may be formed. A first metal-semiconductor compound layer 46 and a second metal-semiconductor compound layer 146 are formed on the surface and the exposed surface of the second source/drain region 131 . For example, the first metal-semiconductor compound layer 46 and the second metal-semiconductor compound layer 146 may include the same material, such as metal silicide (eg, TiSi, CoSi, WSi, TaSi, NiSi, MoSi, or the like).

A lower layer 56 may be formed on the conductive layer 49 . The lower layer 56 may be formed of a material having etch selectivity with respect to the conductive layer 49 . For example, the lower layer 56 may be formed of an amorphous carbon layer, a polysilicon layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or a combination thereof, but the material is not limited thereto. The lower layer 56 may be formed from a single layer or multiple layers of the aforementioned materials.

A first mask layer 59 may be formed (S35 in FIG. 5B). The first mask layer 59 may be formed on the lower layer 56 . The first mask layer 59 may be formed of an amorphous carbon layer, a polysilicon layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or a combination thereof, but the configuration is not limited thereto. The first mask layer 59 may be formed from a single layer or multiple layers of the aforementioned materials.

In an exemplary embodiment, a portion of the first mask layer 59 and a portion of the lower layer 56 that are adjacent to each other may be formed of different materials.

1A, FIG. 5B, FIG. 7, FIG. 8A and FIG. 8B, the first mask layer (59 in FIG. 6A and FIG. 6B) can be patterned using a first patterning process (see S45 in FIG. 5B), To form a first preliminary pad mask pattern 59a and a wiring mask pattern 59b. Therefore, forming the first preliminary pad mask pattern 59a and the wiring mask pattern 59b may include: forming the first mask layer 59 on the conductive layer 49; and using a first patterning process using a first photolithography process to The first mask layer ( 59 in FIGS. 6A and 6B ) is patterned, and EUV light is used as a light source in the first photolithography process.

The first patterning process may include a first photolithography process using EUV light as a light source, as described in operation S30 in FIGS. 5A and 5B . In an exemplary embodiment, the EUV light may have a wavelength between about 4 nm and about 124 nm (eg, about 4 nm to about 20 nm). For example, EUV light may have a wavelength of about 13.5 nanometers. The first photolithography process can use a reflective EUV mask that reflects extreme ultraviolet rays.

For example, as shown in FIG. 7, at least one of the wiring mask patterns 59b has a first line shape extending in the first horizontal direction X, and each of the first preliminary pad mask patterns 59a Or may have a second line shape extending in a first diagonal direction D1 forming an acute angle or an obtuse angle with respect to the first horizontal direction.

For example, the wiring mask pattern 59b may include a wiring mask pattern having a line shape extending in the first horizontal direction X or a wiring mask pattern having a line shape extending in the second horizontal direction Y perpendicular to the first horizontal direction X. Wiring mask pattern. For example, if the first horizontal direction is defined as the direction represented by “X” in FIG. 7 , the first diagonal direction D1 may form an acute angle with respect to the first horizontal direction X. Referring to FIG. In another example, if the first horizontal direction is defined as a direction opposite to the direction indicated by 'X' in FIG. 7 , the first diagonal direction D1 may form an obtuse angle with respect to the first horizontal direction.

Referring to FIG. 1A , FIG. 9A , FIG. 9B , FIG. 10A and FIG. 10B , a second mask layer 62 covering the first preliminary pad mask pattern 59 a and the wiring mask pattern 59 b may be formed on the lower layer 56 . The second mask layer 62 may include a first material layer 64a and a second material layer 64b on the first material layer 64a. The first material layer 64a and the second material layer 64b may be formed of different materials. For example, the first material layer 64a and the second material layer 64b may be formed of different layers, for example, the first material layer 64a and the second material layer 64b may independently include an amorphous carbon layer, a polysilicon layer, a silicon oxide layer, A silicon nitride layer, a silicon oxynitride layer and/or a spin on hardmask (SOH) material layer.

An upper layer 67 may be formed on the second mask layer 62 . The upper layer 67 may include a first upper material layer 69a and a second upper material layer 69b on the first upper material layer 69a. The first upper material layer 69a and the second upper material layer 69b may be formed of different materials. For example, the first upper material layer 69a and the second upper material layer 69b may be formed of different layers, for example, the first upper material layer 69a and the second upper material layer 69b may independently include an amorphous carbon layer, a polysilicon layer, A silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and/or a spin-on-hard-mask (SOH) material layer.

A cap mask layer 72 may be formed on the upper layer 67 . The cap mask layer 72 can be formed of, for example, an amorphous carbon layer, a polysilicon layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or a combination thereof, but the configuration is not limited thereto. The roof mask layer 72 may be formed from a single layer or multiple layers of the aforementioned materials.

1A, 9A, 9B, 11A and 11B, a second photolithography process may be used to pattern the top cover mask layer (72 in FIGS. 10A and 10B) to form a top cover mask pattern 72a and the protective mask pattern 72b, in the second photolithography process, DUV light having a wavelength longer than that of EUV light is used as a light source.

In an exemplary embodiment, the DUV light may be an Argon Fluoride (ArF) excimer laser having a wavelength of about 193 nm, but is not limited thereto, and may have a wavelength of about 436 nm g-line, i-line (365 nm) with a wavelength of about 365 nm, or a KrF laser with a wavelength of about 248 nm. In an exemplary embodiment, the second photolithography process may use a transmission type photomask. In an exemplary embodiment, the second photolithography process may be a photolithography process using an immersion ArF exposure apparatus.

In an exemplary embodiment, each of the top cover mask patterns 72a may have a line shape extending in a second diagonal direction D2 forming an obtuse angle with respect to the first horizontal direction X. . The second diagonal direction D2 may intersect the first diagonal direction D1. Therefore, the cap mask pattern 72a may intersect with the first preliminary pad mask pattern 59a.

The protective mask pattern 72b may have a plate shape covering the wiring mask pattern 59b. For example, the protective mask pattern 72b can cover the entire space between the wiring mask pattern 59b and the wiring mask pattern 59b.

Each of the first preliminary pad mask patterns 59a may be formed to have a first width, and each of the cap mask patterns 72a may be formed to have a second width greater than the first width. The first preliminary pad mask patterns 59a may be spaced apart by a first interval, and the cap mask patterns 72a may be spaced apart by a second interval greater than the first interval.

The first liner 77 covering the top cover mask pattern 72a and the protection mask pattern 72b may be formed on the upper layer 67 with a substantially uniform thickness. The first liner layer 77 can be formed by an atomic layer deposition process. For example, the first lining layer 77 can be formed of silicon oxide.

An upper capping layer 80 overlapping the protective mask pattern 72 b may be formed on the first liner 77 . The upper cap layer 80 may not overlap the cap mask pattern 72a. The upper capping layer 80 can be a photoresist layer.

1A, FIG. 12A and FIG. 12B, the first lining layer (77 in FIG. 77) remaining on the side surface of the cap mask pattern (72a in FIG. 11A). The upper cap layer ( 80 in FIG. 11B ) and the cap mask pattern ( 72a in FIG. 11A ) can be removed.

In order to form the first upper pattern 67a and the upper protective layer 67b, the upper layer 67 is etched using an etching process using the first liner layer (77 in FIG. 11A ) as an etching mask, and additionally, the first liner layer ( 77) in FIG. 11B and the protective mask pattern 72b. The upper protective layer 67b may be formed under the protective mask pattern 72b.

Referring to FIG. 1A , FIG. 13A and FIG. 13B , a second liner layer 83 covering the first upper pattern 67 a and the upper protective layer 67 b may be formed on the second mask layer 62 with a substantially uniform thickness. The second liner layer 83 can be formed by an atomic layer deposition process. For example, the second liner 83 can be formed of silicon oxide.

Referring to FIGS. 1A , 14A, and 14B, a gap-fill pattern 86 may be formed on the second liner ( 83 in FIG. 13A ) between the first upper patterns ( 67 a in FIG. 13A ). The lower and side surfaces of each of the gap-fill patterns 86 may contact the second liner ( 83 in FIG. 13A ).

By performing a planarization process, the upper surface of the second liner layer (83 in FIG. 13A and FIG. 13B ) disposed on the first upper pattern (67a in FIG. 13A ) and the upper protective layer (in FIG. 13B ) can be removed. 67b), and in addition, the thickness of the first upper pattern (67a in FIG. 13A ) and the thickness of the upper protective layer (67b in FIG. 13B ) can be reduced. In an example, the planarization process may include an etch back process. Accordingly, the first upper pattern 67a' having a reduced thickness, the upper protective layer 67b' having a reduced thickness, and the second liner 83' having a reduced thickness may be formed.

1A, 15 and 16, in order to form the second liner pattern 83' remaining under the gap-fill pattern 86, the second liner layer (83 in FIG. '). The sequentially stacked second liner pattern 83 ′ and gap-fill pattern 86 may be defined as a second upper pattern 88 .

The second upper pattern 88 having a reduced thickness and the first upper pattern 67a' may have parallel line shapes. The first upper patterns 67 a ′ having a reduced thickness may be alternately and repeatedly arranged with the second upper patterns 88 .

Referring to FIG. 1A, FIG. 5B, FIG. 15, FIG. 17A and FIG. 17B, in order to form the second preliminary pad mask pattern 62a and the wiring mask protective layer 62b, the second mask layer can be etched by an etching process (FIG. 16 and 62 in FIG. 14B), in the etching process, use the first upper pattern (67a' in FIG. 16) with reduced thickness, the second upper pattern (88 in FIG. 16) and the upper The protective layer (67b' in Figure 14B) acts as an etch mask. While etching the second mask layer (62 in FIGS. 16 and 14B), the first upper pattern (67a' in FIG. 16), the second upper pattern (67a' in FIG. 88 in 16) and an upper protective layer (67b' in FIG. 14B) with a reduced thickness.

In an exemplary embodiment, the second preliminary pad mask pattern 62 a and the wiring mask protection layer 62 b may be formed using a multiple patterning technique including a second patterning process (see S55 in FIG. 5B ). In an exemplary embodiment, the second patterning process uses a second photolithography process in which DUV light having a wavelength longer than that of EUV light explained with reference to FIGS. 11A and 11B is used. As a light source, the top cover mask layer ( 72 in FIGS. 10A and 10B ) is thereby patterned.

In an exemplary embodiment, the multiple patterning technique may include performing a patterning process including performing at least one second photolithography process using DUV light as a light source. In an exemplary embodiment, the multiple patterning technique may include performing one or at least two patterning processes including performing a deposition process and an etching process without using a photolithography process.

For example, in a multiple patterning technique, a single patterning process including a deposition process and an etching process may include the formation of a cap mask layer as described in FIGS. 10A and 10B ( 72) deposition process and etching of the top cover mask layer (72 in FIG. 10A and FIG. 10B) as shown in FIG. 9A, FIG. 9B, FIG. 11A and FIG. 11B to form the top cover mask pattern 72a and the protective mask pattern 72b etching process.

In multiple patterning techniques, a single patterning process including a deposition process and an etching process without using a photolithography process may include the formation of the first liner (FIG. 11A ) as described in FIGS. 11A and 11B and 77 in FIG. 11B) and etching of the first liner (77 in FIG. 11A ) as described in FIGS. 12A and 12B to form the remaining top layer of the first liner (77 in FIG. Etching process of portions on side surfaces of the mask pattern (72a in FIG. 11A).

In the multiple patterning technique, another patterning process that is performed once and includes a deposition process and an etching process may include the deposition process for forming the second liner 83 as described in FIGS. 13A and 3B and as shown in FIG. The etching process of etching the second liner layer ( 83 ′ in FIG. 14A ) to form the second liner pattern 83 ′ remaining under the gap-fill pattern 86 described in FIG. 16 .

Therefore, in order to form the second preliminary pad mask pattern 62a and the wiring mask protection layer 62b, a multiple patterning technique including performing a patterning process including a deposition process and an etching process once or at least twice may be used, whereby the first The second mask layer 62 is patterned. The thickness of each of the second preliminary pad mask pattern 62 a and the wiring mask protection layer 62 b may be smaller than the thickness of the second mask layer ( 62 in FIGS. 16 and 14B ).

At least one of the wiring mask patterns 59b may have a shape of a first line extending in the first horizontal direction X, and each of the first preliminary pad mask patterns 59a may have a shape of a first diagonal line extending in the first horizontal direction X. In the shape of the second line extending in the direction D1, the first diagonal direction D1 forms an acute angle or an obtuse angle with respect to the first horizontal direction X, and each of the second preliminary pad mask patterns 62a may have The shape of the third line extending in the second diagonal direction D2 where the diagonal direction D1 intersects. The first horizontal direction X, the first diagonal direction D1 and the second diagonal direction D2 may be parallel to any plane of the lower structure 3 . A plane of the lower structure 3 can be the upper surface of the semiconductor substrate 5 , the lower surface of the semiconductor substrate 5 , the upper surface of the bit line 25 or the upper surface of the lower structure 3 .

Referring to FIG. 1A, FIG. 5B and FIG. 18, in order to form the pad mask pattern 59a' while protecting the wiring mask pattern (59b in FIG. 17B), a second preliminary pad mask pattern (in FIG. 62a) and the wiring mask protective layer (62b in FIG. 17B) are used as an etching process for etching the mask to etch the first preliminary pad mask pattern (59a in FIG. 17A) (S65 in FIG. 5B). Accordingly, the first preliminary pad mask pattern ( 59 a of FIG. 17A ) having a line shape may be formed into a pad mask pattern 59 a ′ having a dot shape.

Subsequently, the second preliminary pad mask pattern ( 62 a in FIG. 17A ) and the wiring mask protection layer ( 62 b in FIG. 17B ) may be removed. Therefore, as shown in FIG. 8B , the pad mask pattern 59 a ′ can be formed while protecting the wiring mask pattern ( 59 b of FIG. 8B ).

1A, FIG. 5B, FIG. 19A and FIG. 19B, in order to form the pad pattern 49c and the wiring pattern 49p, it can be etched using an etching process in which the pad mask pattern 59a' and the wiring mask pattern 59b are used as the etching mask. Conductive layer 49 (S75 in FIG. 5B). The etching process using the pad mask pattern 59 a ′ and the wiring mask pattern 59 b as an etching mask may include sequentially etching the lower layer 56 and the conductive layer 49 .

In an exemplary embodiment, after performing an etching process using the pad mask pattern 59a' and the wiring mask pattern 59b as an etching mask, or using the pad mask pattern 59a' and the wiring mask pattern 59b as During the etching process of the etching mask, the pad mask pattern 59a' and the wiring mask pattern 59b may be removed.

For example, the lower layer 56 may be etched using the pad mask pattern 59a' and the wiring mask pattern 59b as an etching mask, so that the lower pad mask pattern 56a and 56a remaining under the pad mask pattern 59a' are formed. The lower wiring mask pattern 56b below the wiring mask pattern 59b remains, and the conductive layer 49 may be exposed. Subsequently, the exposed conductive layer 49 may be etched to form a pad pattern 49c remaining under the lower pad mask pattern 56a and a wiring pattern 49p remaining under the lower wiring mask pattern 56b, and to form a pattern extending to the lower portion. Groove 90 in structure 3. Accordingly, the pad pattern 49c and the wiring pattern 49p described with reference to FIGS. 2A and 2B can be formed.

In an exemplary embodiment, while etching the lower layer 56, the pad mask pattern 59a' and the wiring mask pattern 59b may be etched and removed.

Referring again to FIGS. 1A , 1B, 2A, and 2B, a first insulating pattern 92 a and a second insulating pattern 92 b filling the groove 90 may be formed. The lower pad mask pattern 56a and the lower wiring mask pattern 56b may be removed while the first insulating pattern 92a and the second insulating pattern 92b are formed.

An etch stop insulating layer 94 may be formed on the pad pattern 49c, the wiring pattern 49p, and the first and second insulating patterns 92a and 92b. A data storage structure 97 may be formed on the memory cell area MA. When forming the data storage structure 97, the first electrode 97a can be formed to penetrate through the etch stop insulating layer 94 and electrically connected to the pad pattern 49c, and a dielectric layer 97b can be formed to conformally cover the first electrode 97a. , and a second electrode 97c may be formed to cover the dielectric layer 97b. A data storage structure 97 may be formed on the pad pattern 49c and the first insulating pattern 92a. An upper insulating layer 99 may be formed on the etch stop insulating layer 94 in the peripheral circuit area PA.

The method of manufacturing a semiconductor device according to the above-described embodiments may include: forming a conductive layer ( 49 in FIGS. 6A and 6B ) on a semiconductor substrate ( 5 in FIGS. 6A and 6B ); and using the method described with reference to FIGS. 6A to 19B The conductive layer ( 49 in FIGS. 6A and 6B ) is patterned to form a pad pattern ( 49 c in FIG. 19A ) and a wiring pattern ( 49 p in FIG. 19B ). For example, patterning the conductive layer ( 49 in FIGS. 6A and 6B ) may include respectively performing a first patterning process including a first photolithography process using extreme ultraviolet ( EUV) light as a light source, as described with reference to FIGS. 1A, 5B, 7, 8A and 8B; and performing a second patterning process including a second photolithography process, in which, Deep ultraviolet (DUV) light having a wavelength longer than that of extreme ultraviolet (EUV) light is used as a light source, as described with reference to FIGS. 1A , 9A, 9B, 11A, and 11B. In this case, the second patterning process may be performed after the first patterning process is performed.

By way of summary and review, exemplary embodiments provide a semiconductor device in which compactness and reliability can be improved and a method of manufacturing the semiconductor device. As described above, according to exemplary embodiments, there may be provided a method of manufacturing a semiconductor device including a dot-shaped pad pattern and a line-shaped wiring pattern formed at the same height level, and a semiconductor device manufactured by the method.

That is, in an exemplary embodiment, a first photolithography process using EUV light as a light source and a second photolithography process using DUV light (having a wavelength longer than that of EUV light) as a light source may be used to form A dot-shaped pad pattern, and a linear wiring pattern can be formed by the first photolithography process using EUV light as a light source without using the second photolithography process using DUV light as a light source. In this way, since the dot-shaped pad pattern and the linear wiring pattern formed at the same height level can be stably and reliably formed, a semiconductor device with improved integration and reliability can be provided.

Exemplary embodiments have been disclosed herein, and although specific language has been employed, it has been used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to those skilled in the art to whom this application is filed that features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments. features, properties and/or elements are used in combination unless otherwise specifically stated. Accordingly, those of ordinary skill in the art will understand that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the appended claims.

1, 200: semiconductor device 3. 203: Substructure 5. 205: Semiconductor substrate 7a1: The first active area/cell active area 7a2: Second Active Area/Peripheral Active Area 7s1: First Device Quarantine 7s2: Second device isolation area 9a: the first impurity region 9b: the second impurity region 12: Gate trench 15: The first gate structure 17a: First gate dielectric 17b: the first gate electrode 17c: The first gate top cover layer 20: buffer insulation layer 23: Bit line structure 25: bit line 25a: The first bit line material layer 25b: Second bit line material layer 25c: The third bit line material layer 25d: bit line contact part 27: bit line top cover layer 27a: The first bit line capping layer 27b: Second bit line cap layer 27c: The top layer of the third bit line 29: Bit line spacer 40: Partition wall insulation pattern 43: contact plug 45a: First opening 45b: Second opening 46: The first metal-semiconductor compound layer 49: Conductive layer 49c, 260c: pad pattern 49c1: pad part 49c2: first plug part 49p, 260p: wiring pattern 49p1, 260p1: wiring part 49p2: Second plug part 51: the first conductive material layer 53: second conductive material layer 56: lower layer 56a: Lower pad mask pattern 56b: Lower wiring mask pattern 59: The first mask layer 59a: First preliminary pad mask pattern 59a': pad mask pattern 59b: Wiring mask pattern 62:Second mask layer 62a: Second preliminary pad mask pattern 62b: Wiring screen protection layer 64a: first layer of material 64b: second material layer 67: upper layer 67a, 67a': first upper pattern 67b, 67b': upper protective layer 69a: first upper layer of material 69b: Second upper layer of material 72: top cover curtain layer 72a: Roof mask pattern 72b: Protective mask pattern 77: The first lining 80: upper roof layer 83: Second lining 83': Second Pad Pattern 86:Gap fill pattern 88:Second upper pattern 90: Groove 92a, 262a: first insulating pattern 92b, 262b: second insulating pattern 94: etch stop insulating layer 97, 280: Data storage structure 97a: first electrode 97b, 284: dielectric layer 97c: second electrode 99: Upper insulating layer 123:Second gate structure 124: Second gate dielectric 125: the second gate electrode 125a: the first electrode material layer 125b: second electrode material layer 125c: the third electrode material layer 127:Peripheral gate top cover layer 129:Perimeter gate spacer 131: the second source/drain region 134: insulating liner 137: The first interlayer insulating layer 140: The second interlayer insulating layer 146: second metal-semiconductor compound layer 212, 340: lower insulating layer 220: The first conductive thread 222: The first lower insulation pattern 230c: channel layer 230d: Upper source/drain region 230s: Lower source/drain region 232: second lower insulation pattern 234: The first buried layer 236: Second buried layer 240: cell gate electrode 240P1: The first sub-gate electrode 240P2: The second sub-gate electrode 250: Cell Gate Dielectric 259a: First layer of conductive material/reference number 259b: Second layer of conductive material/reference number 260p2: plug part 270: etch stop layer 282: first electrode 286: second electrode 307a: Surrounding active area 307s: Peripheral device isolation area 323:Peripheral gate structure 324:Peripheral gate dielectric 325: Peripheral gate electrode 327:Peripheral gate cap layer 329:Perimeter gate spacer 331: Peripheral source/drain area 346: metal-semiconductor compound layer CTR: cell transistor/first transistor/transistor CTR': vertical channel transistor D1, D1': the first diagonal direction D2, D2': the second diagonal direction MA: first area/memory cell area MA': memory cell area PA: Second Area/Peripheral Circuit Area PA': Peripheral circuit area I-I', II-II', III-III', IV-IV', V-V', VI-VI': line PTR: Transistor/Second Transistor/Peripheral Transistor PTR': peripheral transistor S1: First side/edge S2: Second side/edge S3: third side/edge S4: Fourth side/edge S10, S20, S30, S35, S45, S55, S65, S75: Operation X: the first horizontal direction Y: the second horizontal direction Z: vertical direction

Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which: FIG. 1A is a schematic plan view of a semiconductor device according to an exemplary embodiment. FIG. 1B is a plan view showing some components shown in FIG. 1A. FIG. 2A is a schematic cross-sectional view along lines II' and II-II' shown in FIG. 1A . FIG. 2B is a schematic cross-sectional view along line III-III' shown in FIG. 1A. 3 is a schematic plan view of another example of a semiconductor device according to an exemplary embodiment. FIG. 4A is a schematic cross-sectional view along lines IV-IV' and V-V' shown in FIG. 3 . FIG. 4B is a schematic cross-sectional view along line VI-VI' shown in FIG. 3 . 5A and 5B are process flow diagrams of a method of manufacturing a semiconductor device according to example embodiments. 6A to 19B are cross-sectional views of stages in a method of manufacturing a semiconductor device according to example embodiments.

S10, S20, S30: Operation

Claims (10)

A method of manufacturing a semiconductor device, the method comprising: forming a substructure comprising a plurality of transistors; forming a conductive layer on the lower structure; forming a first preliminary pad mask pattern and a wiring mask pattern on the conductive layer; forming a pad mask pattern by patterning the first preliminary pad mask pattern while protecting the wiring mask pattern; and The conductive layer is etched using the pad mask pattern and the wiring mask pattern as an etching mask to form a pad pattern and a wiring pattern. The method according to claim 1, wherein forming the first preliminary pad mask pattern and the wiring mask pattern comprises: forming a first mask layer on the conductive layer; and The first mask layer is patterned in a first patterning process using extreme ultraviolet (EUV) light as a light source. The method of claim 2, wherein forming the pad mask pattern by patterning the first preliminary pad mask pattern while protecting the wiring mask pattern comprises: forming a second mask layer covering the wiring mask pattern and the first preliminary pad mask pattern on the conductive layer; patterning the second mask layer using a multiple patterning technique, the multiple patterning technique comprising performing one or more deposition processes and etching processes to form a second preliminary pad mask pattern and a wiring mask protective layer; as well as Using the second preliminary pad mask pattern and the wiring mask protection layer as an etching mask to etch the first preliminary pad mask pattern to form the wiring mask pattern while protecting the wiring mask pattern. pad mask pattern, wherein at least one of the wiring mask patterns has a first line shape extending in a first horizontal direction, wherein each of the first preliminary pad mask patterns has a second line shape extending in a first diagonal direction forming an acute angle with respect to the first horizontal direction or obtuse angles, wherein each of the second preliminary pad mask patterns has a third line shape extending in a second diagonal direction intersecting the first diagonal direction, and Wherein the first horizontal direction, the first diagonal direction and the second diagonal direction are parallel to the upper surface of the lower structure. The method of claim 3, wherein patterning the second mask layer using the multiple patterning technique comprises: forming an upper layer on the second mask layer; forming a roof mask layer on the upper layer; and patterning the cap mask layer using a second photolithography process comprising using deep ultraviolet (DUV) light as a light source to form a cap mask pattern and a protective mask pattern, so said deep ultraviolet light has a wavelength longer than that of said extreme ultraviolet light, wherein the protective mask pattern overlaps the wiring mask pattern, wherein each of the cap mask patterns has a fourth line shape extending in the second diagonal direction, wherein a width of each of the cap mask patterns is greater than a width of each of the first preliminary pad mask patterns, and Wherein the distance between the cap mask patterns adjacent to each other is greater than the distance between the first preliminary pad mask patterns adjacent to each other. The method of claim 4, wherein patterning the second mask layer using the multiple patterning technique further comprises: forming a first liner layer covering the roof mask pattern and the protective mask pattern with a uniform thickness on the upper layer; forming an upper cap layer on the first liner layer, the upper cap layer overlapping the protective mask pattern while exposing a portion of the first liner layer; anisotropically etching the exposed portion of the first liner to form a portion of the first liner remaining on a side surface of the cap mask pattern; removing the upper roof layer and the roof mask pattern; The upper layer is etched using the portion of the first liner layer as an etch mask and the portion of the first liner layer and the protective mask pattern are removed such that forming an upper protection layer below to form a first upper pattern and the upper protection layer; forming a second liner layer covering the first upper pattern and the upper protective layer with a uniform thickness on the second mask layer; forming gap-fill patterns on the second liner between the first upper patterns; performing a planarization process to remove a portion of the second liner layer disposed on the upper surface of the first upper pattern and the upper surface of the upper protective layer; anisotropically etching the second liner to form a second liner pattern remaining under the gap-fill pattern, the second liner pattern and the gap-fill pattern stacked in sequence are defined as a first two upper patterns; and Etching the second mask layer using the first upper pattern, the second upper pattern and the upper protection layer as an etching mask to form the second preliminary pad mask pattern and the wiring Mask protection layer. The method as recited in claim 1, wherein: The lower structure further includes a semiconductor substrate having a memory cell area and a peripheral circuit area adjacent to the memory cell area, The plurality of transistors include cell transistors formed on the semiconductor substrate in the memory cell region and peripheral transistors formed on the semiconductor substrate in the peripheral circuit region, the pad pattern is electrically connected to the cell transistor, and At least some of the wiring patterns are electrically connected to the peripheral transistors, wherein: The lower structure further includes bit lines and contact plugs, Each of the cellular transistors includes: a cell gate electrode formed in a cell gate trench intersecting the cell active region; a cell gate dielectric formed between the cell gate electrode and the cell active region; and a first impurity region and a second impurity region are formed in the cell active region on both sides of the cell gate electrode, each of the bit lines is electrically connected to the first impurity region of each of the cell transistors, and Each of the contact plugs is electrically connected to the second impurity region of each of the cell transistors. The method as recited in claim 6, wherein: The lower structure further includes bit lines, Each of the cellular transistors includes: The lower source/drain region, the channel layer and the upper source/drain region are sequentially arranged in the vertical direction; a cell gate electrode on a side surface of the channel layer; and a cell gate dielectric between the cell gate electrode and the channel layer, and The pad pattern is electrically connected to the upper source/drain region of the cell transistor. A method of manufacturing a semiconductor device, the method comprising: forming a lower structure including a first transistor and a second transistor; forming a conductive layer on the lower structure; forming a first mask layer on the conductive layer; The first mask layer is patterned using a first photolithography process to form a first preliminary pad mask pattern and a wiring mask pattern, the first photolithography process including using extreme ultraviolet (EUV) light as first light source; Forming a second preliminary pad mask pattern and wiring mask protective layer using multiple patterning techniques; Etching the first preliminary pad mask pattern using the second preliminary pad mask pattern and the wiring mask protective layer as an etching mask to form pads while protecting the wiring mask pattern the mask pattern; and using the pad mask pattern and the wiring mask pattern as an etching mask to etch the conductive layer to form a pad pattern and a wiring pattern, wherein the pad pattern is electrically connected to the first transistor, wherein at least some of the wiring patterns are electrically connected to the second transistor, wherein said multiple patterning technique comprises performing at least one second photolithography process using deep ultraviolet (DUV) light as a second light source, said deep ultraviolet (DUV) light having a wavelength longer than that of said extreme ultraviolet light ,and The multiple patterning technique further includes performing one or more patterning processes, and the patterning process includes performing a deposition process and an etching process without using a photolithography process. A method of manufacturing a semiconductor device, the method comprising: forming a conductive layer on the semiconductor substrate; and patterning the conductive layer to form pad patterns and wiring patterns, Wherein patterning the conductive layer includes: performing a first patterning process comprising a first photolithography process using extreme ultraviolet (EUV) light as a first light source; and performing a second patterning process, the second patterning process including a second photolithography process using deep ultraviolet (DUV) light as a second light source, the deep ultraviolet (DUV) light having a higher long wavelength wavelength, wherein the second patterning process is performed after the first patterning process is performed, wherein the pad pattern is formed after performing both the first patterning process and the second patterning process, and Wherein the wiring pattern is formed by the first patterning process before implementing the second patterning process. The method as described in claim 9, further comprising forming a data storage structure electrically connected to the pad pattern on the pad pattern, so that the data storage structure stores information in a volatile memory device or in non-volatile memory devices.

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