TWI792239B - Method of manufacturing gate dielectrid layer - Google Patents

Abstract

A method of manufacturing a gate dielectric layer including the following steps is provided. A substrate is provided. The substrate includes a low voltage device region and a non-low voltage device region. A block layer is formed on the substrate. The block layer covers the substrate in the low voltage device region and exposes the substrate in non-low voltage device region. After the block layer is formed, a first dielectric layer is formed on the substrate in the non-low voltage device region by an oxidation process. The block layer is removed to expose the substrate in the low voltage device region. A second dielectric layer is formed on the substrate in the low voltage device region.

Description

Fabrication method of gate dielectric layer

The present invention relates to a semiconductor manufacturing process, and in particular to a method for manufacturing a gate dielectric layer.

At present, the formation method of the gate dielectric layer in the non-low voltage component area (such as the medium voltage component area or the high voltage component area) first forms the dielectric layer in the non-low voltage component area and the low voltage component area at the same time, and then removes the low voltage component area The dielectric layer in the non-low voltage device area is formed as the gate dielectric layer.

The gate dielectric layer in the non-low voltage device region usually has a thicker thickness, so in the oxidation process used to form the gate dielectric layer in the non-low voltage device region, a thicker dielectric layer will be formed in the low voltage device region, while The active region in the low-voltage device region produces a relatively large corner rounding effect, thereby reducing the flat area of the active region in the low-voltage device region. In addition, when the thicker dielectric layer in the low-voltage device region is subsequently removed, due to the large amount of etching, a deep recess (divot) will be formed on the isolation structure near the low-voltage device region, thereby making the isolation structure The depressions of have a large variation.

In this way, since the flat area of the active region of the low-voltage device region becomes smaller and the depressions on the isolation structure near the low-voltage device region have greater variation, the electrical performance of the low-voltage device will be deteriorated.

The invention provides a method for manufacturing a gate dielectric layer, which can improve the electrical performance of low-voltage components.

The invention provides a method for manufacturing a gate dielectric layer, which includes the following steps. Provide the base. The base includes a low-voltage component area and a non-low-voltage component area. A barrier layer is formed on the substrate. The blocking layer covers the substrate in the low voltage device area and exposes the substrate in the non-low voltage device area. After forming the blocking layer, a first dielectric layer is formed on the substrate in the non-low voltage device region by an oxidation process. The barrier layer is removed to expose the substrate in the low voltage device area. A second dielectric layer is formed on the substrate in the low voltage element region.

According to an embodiment of the present invention, in the method for manufacturing the gate dielectric layer, the barrier layer may be a single-layer structure.

According to an embodiment of the present invention, in the method for manufacturing the gate dielectric layer, the barrier layer may be a multi-layer structure.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the gate dielectric layer, the forming method of the barrier layer may include the following steps. A barrier material layer is formed on the substrate. A patterned mask layer is formed on the barrier material layer. The patterned mask layer covers the barrier material layer in the low voltage device area and exposes the barrier material layer in the non-low voltage device area. Using the patterned mask layer as a mask, the barrier material layer in the non-low voltage device area is removed to form a barrier layer on the substrate.

According to an embodiment of the present invention, in the method for manufacturing the gate dielectric layer, the barrier material layer may be an oxide material layer.

According to an embodiment of the present invention, in the method for manufacturing the gate dielectric layer, the method for forming the barrier material layer may include the following steps. A first oxide material layer is formed on the substrate. A second oxide material layer is formed on the first oxide material layer.

According to an embodiment of the present invention, in the method for manufacturing the gate dielectric layer, the method for forming the barrier material layer may further include the following steps. A nitride material layer is formed on the second oxide material layer.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the gate dielectric layer, the forming method of the barrier layer may include the following steps. A layer of oxide material is formed on the substrate. A nitride material layer is formed on the oxide material layer.

According to an embodiment of the present invention, in the method for manufacturing the gate dielectric layer, the method for forming the nitride material layer is, for example, chemical vapor deposition or performing a nitriding process on the oxide material layer.

According to an embodiment of the present invention, in the method for manufacturing the gate dielectric layer, in the nitridation process, 10% to 30% of the oxide material layer can be nitrided into a nitride material layer.

Based on the above, in the manufacturing method of the gate dielectric layer proposed by the present invention, in the step of forming the first dielectric layer on the substrate in the non-low-voltage device region by oxidation process, since the barrier layer covers the low-voltage device region The substrate, so the formation of the first dielectric layer on the substrate in the low-voltage element region can be suppressed. Therefore, the influence of the oxidation process for forming the first dielectric layer on the low-voltage device region can be reduced, thereby independently and freely adjusting the corner rounding degree of the active region in the low-voltage device region, and reducing the low-voltage device region. The depth of the recess on the isolation structure near the region. In this way, the active region of the low-voltage device region can maintain a sufficient flat area, and can prevent large variations in the depressions on the isolation structure near the low-voltage device region, thereby improving the quality of the low-voltage device subsequently formed in the low-voltage device region. electrical performance.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

1A to 1G are cross-sectional views of a manufacturing process of a gate dielectric layer according to an embodiment of the present invention. 2A , 3A and 4A are cross-sectional views of barrier material layers according to other embodiments of the present invention. 2B , 3B and 4B are cross-sectional views of barrier layers according to other embodiments of the present invention.

Referring to FIG. 1A , a substrate 100 is provided. The substrate 100 includes a low voltage device region R1 and a non-low voltage device region R2. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. The non-low voltage component region R2 can be a medium voltage component region or a high voltage component region. In this embodiment, the non-low voltage component region R2 is an example of the medium voltage component region, but the present invention is not limited thereto. In addition, the active area AA1 in the low-voltage device region R1 and the active area AA2 in the non-low-voltage device region R2 can be respectively isolated by an isolation structure (eg, shallow trench isolation (STI)) in the substrate 100 (not shown). out) defined.

Next, a barrier material layer 102 may be formed on the substrate 100 . The barrier material layer 102 can be a single-layer structure or a multi-layer structure. In this embodiment, the barrier material layer 102 can be a single layer of oxide material layer 104 , but the invention is not limited thereto. The oxide material layer 104 can be formed by performing an oxidation process on the substrate 100 . The oxidation process is, for example, a thermal oxidation process. In some embodiments, during the oxidation process on the substrate 100 , part of the substrate 100 may be oxidized to form the oxide material layer 104 . In some embodiments, the oxide material layer 104 may be a sacrificial oxide layer. The sacrificial oxide layer can be used to control the ion implantation depth and protect the surface of the substrate 100 when forming a desired doped region (eg, well region) (not shown) in the substrate 100 by an ion implantation process. . The material of the oxide material layer 104 is, for example, silicon oxide.

In some other embodiments, as shown in FIG. 2A , FIG. 3A and FIG. 4A , the barrier material layer 102 may be a multi-layer structure. Referring to FIG. 2A , the barrier material layer 102 may include an oxide material layer 104 and an oxide material layer 106 on the substrate 100 in sequence. In addition, compared with the method for forming the barrier material layer 102 in FIG. 1A , the method for forming the barrier material layer 102 in FIG. 2A may further include the following steps in addition to the step of forming the oxide material layer 104 on the substrate 100 . An oxide material layer 106 is formed on the oxide material layer 104 . The method for forming the oxide material layer 106 is, for example, chemical vapor deposition. The material of the oxide material layer 106 is, for example, silicon oxide.

Referring to FIG. 3A , the barrier material layer 102 may include an oxide material layer 104 , an oxide material layer 106 and a nitride material layer 108 on the substrate 100 in sequence. In addition, compared with the method for forming the barrier material layer 102 in FIG. 2A , the method for forming the barrier material layer 102 in FIG. 3A may further include the following steps. A nitride material layer 108 is formed on the oxide material layer 106 . The method for forming the nitride material layer 108 is, for example, chemical vapor deposition or nitriding the oxide material layer 106 . During the nitridation process, 10% to 30% of the oxide material layer 106 may be nitrided into the nitride material layer 108 . The material of the nitride material layer 108 is, for example, silicon nitride or silicon oxynitride.

Referring to FIG. 4A , the barrier material layer 102 may include an oxide material layer 104 and a nitride material layer 108 on the substrate 100 in sequence. In addition, compared with the method for forming the barrier material layer 102 in FIG. 1A , the method for forming the barrier material layer 102 in FIG. 4A may further include the following steps in addition to the step of forming the oxide material layer 104 on the substrate 100 . A nitride material layer 108 is formed on the oxide material layer 104 . The method for forming the nitride material layer 108 is, for example, a chemical vapor deposition method or a nitriding process for the oxide material layer 104 . In the nitridation process, 10% to 30% of the oxide material layer 104 may be nitrided into the nitride material layer 108 . The material of the nitride material layer 108 is, for example, silicon nitride or silicon oxynitride.

Referring to FIG. 1B , a patterned mask layer 110 may be formed on the barrier material layer 102 . The patterned mask layer 110 covers the barrier material layer 102 in the low voltage device region R1 and exposes the barrier material layer 102 in the non-low voltage device region R2. In some embodiments, the patterned mask layer 110 can be a patterned photoresist layer, and the patterned photoresist layer can be formed by a lithography process.

Referring to FIG. 1C , the patterned mask layer 110 can be used as a mask to remove the barrier material layer 102 in the non-low voltage device region R2 to form a barrier layer 102 a on the substrate 100 . The barrier layer 102a covers the substrate 100 in the low voltage device region R1 and exposes the substrate 100 in the non-low voltage device region R2. The removal method of the barrier material layer 102 in the non-low voltage device region R2 is, for example, a wet etching method.

Then, the patterned mask layer 110 can be removed. When the patterned mask layer 110 is a patterned photoresist layer, the removal method of the patterned mask layer 110 is, for example, dry stripping or wet stripping.

In addition, the barrier layer 102a may be a single-layer structure or a multi-layer structure. In this embodiment, the barrier layer 102a can be a single-layer oxide layer 104a ( FIG. 1C ), but the invention is not limited thereto. In other embodiments, the barrier layer 102a can be a multi-layer structure. For example, as shown in FIG. 2B , FIG. 3B and FIG. 4B , the barrier layer 102 a formed by performing the above steps on the barrier material layer 102 in FIG. 2A , FIG. 3A and FIG. 4A may be a multi-layer structure. Referring to FIG. 2B , the barrier layer 102a may include an oxide layer 104a and an oxide layer 106a on the substrate 100 in sequence. Referring to FIG. 3B , the barrier layer 102a may include an oxide layer 104a , an oxide layer 106a and a nitride layer 108a sequentially located on the substrate 100 . Referring to FIG. 4B , the barrier layer 102a may include an oxide layer 104a and a nitride layer 108a on the substrate 100 in sequence.

Referring to FIG. 1D, after forming the barrier layer 102a, a dielectric layer 112 is formed on the substrate 100 in the non-low voltage device region R2 by an oxidation process. The dielectric layer 112 in the non-low voltage device region R2 can be used as a gate dielectric layer of the non-low voltage device. In the step of forming the dielectric layer 112 on the substrate 100 in the non-low voltage device region R2 by an oxidation process, since the barrier layer 102a covers the substrate 100 in the low voltage device region R1, the substrate in the low voltage device region R1 can be suppressed. Dielectric layer 112 is formed on 100 . In some embodiments, during the oxidation process on the substrate 100 , a portion of the substrate 100 may be oxidized to form the dielectric layer 112 . The oxidation process is, for example, a thermal oxidation process. The material of the dielectric layer 112 is, for example, oxide, such as silicon oxide.

Referring to FIG. 1E , a patterned mask layer 114 may be formed in the non-low voltage device region R2 . The patterned mask layer 114 covers the dielectric layer 112 in the non-low voltage device region R2 and exposes the barrier layer 102a. The patterned mask layer 114 can be a patterned photoresist layer, and the patterned photoresist layer can be formed by a lithography process.

Referring to FIG. 1F , the patterned mask layer 114 can be used as a mask to remove the barrier layer 102 a to expose the substrate 100 in the low voltage device region R1 . The removal method of the barrier layer 102a is, for example, a wet etching method.

Next, the patterned mask layer 114 can be removed. When the patterned mask layer 114 is a patterned photoresist layer, the removal method of the patterned mask layer 114 is, for example, a dry stripping method or a wet stripping method.

Referring to FIG. 1G , a dielectric layer 116 is formed on the substrate 100 in the low voltage device region R1 . The dielectric layer 116 in the low voltage device region R1 can be used as a gate dielectric layer of the low voltage device. In some embodiments, the thickness of the dielectric layer 116 may be less than the thickness of the dielectric layer 112 . The material of the dielectric layer 116 is, for example, oxide, such as silicon oxide. The dielectric layer 116 can be formed by performing an oxidation process on the substrate 100 . The oxidation process is, for example, a thermal oxidation process. In some embodiments, during the oxidation process on the substrate 100 , a portion of the substrate 100 may be oxidized to form the dielectric layer 116 .

Based on the above embodiment, it can be seen that in the above method of manufacturing the gate dielectric layer, in the step of forming the dielectric layer 112 on the substrate 100 in the non-low voltage device region R2 by an oxidation process, since the barrier layer 102a covers the low voltage device region The substrate 100 in R1, therefore, the formation of the dielectric layer 112 on the substrate 100 in the low-voltage device region R1 can be suppressed. Therefore, the influence of the oxidation process for forming the dielectric layer 112 on the low-voltage device region R1 can be reduced, so that the degree of corner rounding of the active region AA1 in the low-voltage device region R1 can be adjusted independently and freely. The depth of the recess on the isolation structure near the low-voltage element region R1 is reduced. For example, the degree of corner rounding of the active region AA1 in the low-voltage device region R1 can be controlled by an oxidation process used to form the oxide material layer 104 . In this way, the active area AA1 of the low-voltage element region R1 can maintain a sufficient flat area, and can prevent large variations in the depressions on the isolation structure near the low-voltage element region R1, so that the subsequent formation in the low-voltage element region R1 can be improved. The electrical performance of low-voltage components.

In addition, the characteristics of the low-voltage device and the non-low-voltage device can be individually adjusted by the method for manufacturing the gate dielectric layer of the above-mentioned embodiment. For example, in the low-voltage device region R1, since the active region AA1 can maintain a sufficient flat area (that is, the corner rounding degree of the active region AA1 is small), and can prevent the generation of depressions on the isolation structure near the active region AA1 Larger variation, so high saturation current (saturation current) can be obtained, and the variation of threshold voltage (threshold voltage, Vt) can be reduced. Meanwhile, in the non-low voltage device region R2 , since the active region AA2 can have a sufficient degree of corner rounding, the subthreshold hump effect can be suppressed.

To sum up, in the method for manufacturing the gate dielectric layer in the above embodiment, in the oxidation process for forming the gate dielectric layer in the non-low voltage device region, since the barrier layer covers the substrate in the low voltage device region, Therefore, the impact of the oxidation process on the low-voltage device area can be reduced. Thereby, the degree of corner rounding of the active region in the low-voltage device region can be independently and freely adjusted, and the recess depth on the isolation structure near the low-voltage device region can be reduced. In this way, the active area of the low-voltage element region can maintain a sufficient flat area, and can prevent large variations in the depressions on the isolation structure near the low-voltage element region, thereby improving the electrical resistance of the low-voltage element subsequently formed in the low-voltage element region. sexual performance.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100: base 102: barrier material layer 102a: barrier layer 104, 106: oxide material layer 104a, 106a: oxide layer 108: Nitride material layer 108a: Nitride layer 110, 114: Patterned mask layer 112, 116: Dielectric layer AA1, AA2: active area R1: low voltage component area R2: Non-low voltage component area

1A to 1G are cross-sectional views of a manufacturing process of a gate dielectric layer according to an embodiment of the present invention. 2A , 3A and 4A are cross-sectional views of barrier material layers according to other embodiments of the present invention. 2B , 3B and 4B are cross-sectional views of barrier layers according to other embodiments of the present invention.

100: base

102a: barrier layer

104a: oxide layer

112: dielectric layer

AA1,AA2: active area

R1: low voltage component area

R2: Non-low voltage component area

Claims (10)

A method for manufacturing a gate dielectric layer, comprising: providing a substrate, wherein the substrate includes a low-voltage element region and a non-low-voltage element region; forming a barrier layer on the substrate, wherein the barrier layer covers the low-voltage element region the substrate, and expose the substrate in the non-low voltage device region; after forming the barrier layer, form a first dielectric layer on the substrate in the non-low voltage device region by an oxidation process ; removing the barrier layer to expose the substrate in the low voltage device region; and forming a second dielectric layer on the substrate in the low voltage device region. The method for manufacturing a gate dielectric layer as claimed in claim 1, wherein the barrier layer comprises a single-layer structure. The method for manufacturing a gate dielectric layer as claimed in claim 1, wherein the barrier layer comprises a multi-layer structure. The method for manufacturing a gate dielectric layer according to claim 1, wherein the forming method of the barrier layer comprises: forming a barrier material layer on the substrate; forming a patterned mask layer on the barrier material layer, wherein The patterned mask layer covers the barrier material layer in the low voltage device region and exposes the barrier material layer in the non-low voltage device region; and using the patterned mask layer as a mask , removing the barrier material layer in the non-low voltage component region, and forming the barrier layer on the substrate. The method for manufacturing a gate dielectric layer as claimed in claim 4, wherein the barrier material layer includes an oxide material layer. The method for manufacturing a gate dielectric layer according to claim 4, wherein the method for forming the barrier material layer includes: forming a first oxide material layer on the substrate; and forming a first oxide material layer on the first oxide material layer A second layer of oxide material is formed. The method for manufacturing a gate dielectric layer according to claim 6, wherein the method for forming the barrier material layer further includes: forming a nitride material layer on the second oxide material layer. The method for manufacturing a gate dielectric layer according to claim 4, wherein the method for forming the barrier material layer includes: forming an oxide material layer on the substrate; and forming a nitride material on the oxide material layer layer. The method for manufacturing a gate dielectric layer according to claim 8, wherein the method for forming the nitride material layer includes chemical vapor deposition or performing a nitriding process on the oxide material layer. The method for manufacturing a gate dielectric layer according to claim 9, wherein in the nitridation process, 10% to 30% of the oxide material layer is nitrided into the nitride material layer.

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