TWI746094B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A method of forming a semiconductor structure includes sequentially forming an epitaxial layer and a semiconductor layer on a substrate. A patterned hard mask layer is formed on the semiconductor layer. The semiconductor layer and the epitaxial layer are etched with the patterned hard mask layer as an etching mask, so that the epitaxial layer has a recess. The patterned hard mask layer is removed. A first electrode dielectric layer is formed on the sidewall and bottom surface of the recess and on the semiconductor layer, so that the first electrode dielectric layer has a trench. A first electrode is formed in the trench. A pair of second electrodes is formed on the first electrode, so that the pair of second electrodes is arranged corresponding to each other along a horizontal direction. A third electrode is formed on the pair of second electrodes.

Description

Semiconductor structure and its forming method

The present invention relates to a semiconductor structure and its forming method, and more particularly to a semiconductor structure containing a mask electrode arranged in a horizontal direction and its forming method.

Due to the trench structure in the trench MOSFET, it has a smaller unit cell pitch and a lower gate-drain capacitance (C _gd ) Therefore, it is possible to effectively reduce the on-resistance (R _on ) and reduce the switching loss. However, with the increase in user demand, transistors are expected to have smaller sizes, faster response speeds and lower switching losses. It is necessary to reduce the size of the transistors. Even so, the gate drain charge (Q _gd ) Or the gate and drain capacitance still cannot be effectively reduced, resulting in no significant improvement in the switching speed.

Therefore, a shielded gate trench (SGT) MOSFET has been developed. The SGT-MOSFET is provided with a source electrode as a shielding electrode, that is, a source shielding structure is provided in the SGT-MOSFET. Therefore, SGT-MOSFET can obtain lower on-resistance and better switching performance based on charge balancing technology.

However, the existing semiconductor structures and their formation methods have gradually met their intended uses, but they have not yet fully met the requirements in all aspects. Therefore, there are still some problems to be overcome regarding the semiconductor structure that can be used as an SGT-MOSFET after further processing and its formation method.

In view of the above problems, the present invention provides a shielding structure by providing a plurality of electrodes as shielding electrodes. In particular, the provided plurality of electrodes further includes a pair of electrodes arranged horizontally, that is, a structure of separate spacer electrodes arranged in the horizontal direction, so that the electric field and the charge in the semiconductor structure More uniform, to obtain better electrical characteristics.

According to some embodiments, a method of forming a semiconductor structure is provided. The method for forming the semiconductor structure includes: sequentially forming an epitaxial layer and a semiconductor layer on a substrate. A patterned hard mask layer is formed on the semiconductor layer. The patterned hard mask layer is used as an etching mask, and the semiconductor layer and the epitaxial layer are etched so that the epitaxial layer has grooves. Remove the patterned hard mask layer. A first electrode dielectric layer is formed on the sidewall and bottom surface of the groove and on the semiconductor layer, so that the first electrode dielectric layer has a groove. A first electrode is formed in the trench. A pair of second electrodes is formed on the first electrode so that the pair of second electrodes are arranged corresponding to each other along the horizontal direction. A third electrode is formed on the pair of second electrodes.

According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a substrate, an epitaxial layer, a semiconductor layer, a first electrode dielectric layer, a first electrode, a second electrode, and a third electrode. The substrate has a first conductivity type. The epitaxial layer has the first conductivity type. The epitaxial layer is arranged on the substrate and has a groove. The semiconductor layer has a second conductivity type different from the first conductivity type. The semiconductor layer is arranged on the epitaxial layer. The first electrode dielectric layer is arranged on the sidewall and bottom surface of the groove and on the semiconductor layer. The first electrode dielectric layer has a trench. The first electrode is arranged in the groove. A pair of second electrodes are arranged on the first electrode. The pair of second electrodes correspond to each other along the horizontal direction. The third electrode is arranged on the pair of second electrodes.

The semiconductor structure of the present invention can be applied to various types of semiconductor devices. In order to make the features and advantages of the present invention more comprehensible, preferred embodiments are listed below in conjunction with the accompanying drawings, which are described in detail as follows.

The following disclosure provides many different embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of each element and its configuration are described below in order to simplify the embodiment of the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. , So that they do not directly touch the embodiment. In addition, the embodiment of the present invention may repeat reference numbers and/or letters in different examples. Such repetition is for conciseness and clarity, and is not used to indicate the relationship between the different embodiments and/or forms discussed.

In the different drawings and illustrated embodiments, similar component symbols are used to designate similar components. It can be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or deleted for other embodiments of the method.

In this article, each direction is not limited to the three axes of the rectangular coordinate system, such as the x-axis, the y-axis, and the z-axis, and can be explained in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For ease of description, hereinafter, when viewed in a cross-sectional view, the y-axis direction is referred to as the vertical direction D1, and the x-axis direction is referred to as the horizontal direction D2.

FIGS. 1-12 are schematic cross-sectional views illustrating the formation of the semiconductor structure 1 at various stages according to some embodiments of the present invention.

Referring to FIG. 1, an epitaxial layer 200 and a semiconductor layer 300 are sequentially formed on the substrate 100. The epitaxial layer 200 may be disposed on the substrate 100. The semiconductor layer 300 may be disposed on the epitaxial layer 200. The substrate 100, the epitaxial layer 200, and the semiconductor layer 300 may each extend. The substrate 100, the epitaxial layer 200, and the semiconductor layer 300 may be parallel to each other.

The substrate 100 may be a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate. The substrate 100 may be a wafer, such as a silicon wafer. Generally speaking, an insulating overlying semiconductor substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer or similar materials, which provide an insulating layer on a silicon or glass substrate. Other types of substrates include, for example, multi-layer or gradient substrates.

The substrate 100 may be an element semiconductor, which includes silicon and germanium; the substrate 100 may also be a compound semiconductor, which includes: for example, silicon carbide, gallium arsenide, and phosphorous. Gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide, but not limited thereto; the substrate 100 may also be an alloy semiconductor, which includes: examples In particular, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP or any combination thereof, but not limited thereto.

The epitaxial layer 200 may include silicon, germanium, silicon and germanium, III-V compounds, or a combination of the above. The epitaxial layer 200 may be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition (MOCVD), metal-organic chemical vapor deposition (MOCVD), and metal-organic chemical vapor deposition (MOCVD). phase epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma chemical vapor deposition (RPCVD), molecular beam epitaxy ( molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl -VPE) or similar methods.

In some embodiments, the substrate 100 and the epitaxial layer 200 have a first conductivity type, and the semiconductor layer 300 has a second conductivity type different from the first conductivity type. For example, if the first conductivity type of the substrate 100 and the epitaxial layer 200 is N-type, the second conductivity type of the semiconductor layer 300 is the P-type; on the contrary, if the substrate 100 and the epitaxial layer 200 have the The first conductivity type is P type, and the second conductivity type of the semiconductor layer 300 is N type. The first conductivity type and the second conductivity type can be adjusted according to requirements. At the same time, the doping concentration, doping depth, and size of the doped region can also be adjusted according to requirements. In some embodiments, the substrate 100 and the epitaxial layer 200 have an N-type conductivity type; and the semiconductor layer 300 has a P-type conductivity type. In some embodiments, the semiconductor layer 300 can also be formed after the third electrode is subsequently formed.

Referring to FIG. 2, a patterned hard mask layer 400 is formed on the semiconductor layer 300. The patterned hard mask layer 400 includes openings OP. The opening OP of the patterned hard mask layer 400 exposes a part of the upper surface of the semiconductor layer 300.

The patterned hard mask layer 400 may include oxide, nitride, or a combination thereof. In some embodiments, the oxide layer may include, for example, an oxide using tetraethyl orthosilicate (TEOS) as a precursor or other suitable oxides. The nitride may include (SiN), silicon oxynitride (SiON), titanium nitride (TiN), tantalum nitride (TaN) or other suitable nitrides. It is understandable that suitable hard mask materials can be matched according to process conditions, so the embodiments of the present invention are not limited thereto.

In some embodiments, the patterned hard mask layer 400 is oxide. In some embodiments, the step of forming a patterned hard mask layer 400 on the semiconductor layer 300 may further include: depositing an oxide layer as a hard mask layer on the semiconductor layer 300, and then forming a photoresist layer on the above oxide. And then expose the photoresist layer as required to obtain a patterned photoresist layer. After that, the patterned photoresist layer is used as an etching mask, and the oxide layer is etched to form a patterned oxide layer. Next, the patterned photoresist layer is removed to obtain the patterned hard mask layer 400 on the semiconductor layer 300. The above-mentioned oxide layer can be obtained by chemical vapor deposition (CVD) deposition or other suitable processes. The photoresist layer can be removed using an ashing and/or wet strip process.

Referring to FIG. 3, the patterned hard mask layer 400 is used as an etching mask, and the semiconductor layer 300 and the epitaxial layer 200 are etched so that the epitaxial layer 200 has a groove 210. In an embodiment, the portion of the semiconductor layer 300 corresponding to the opening OP is removed, so that the etched semiconductor layer 300 is penetrated. Furthermore, the part of the epitaxial layer 200 corresponding to the opening OP is removed, but the etched epitaxial layer 200 is not penetrated, so that the epitaxial layer 200 can have a groove 210. In an embodiment, although the semiconductor layer 300 is disposed on the epitaxial layer 200, it is not disposed on the groove 210. In one embodiment, the semiconductor layer 300 shields a part of the upper surface of the epitaxial layer 200. The removed part of the semiconductor layer 300 corresponding to the opening OP exposes another part of the upper surface of the epitaxial layer 200 so that the epitaxial layer 200 has a groove 210.

The groove 210 may correspond to the opening OP of the patterned hard mask layer 400. The groove 210 may be located below the opening OP. The groove 210 may be recessed toward the substrate 100. In the epitaxial layer 200, the bottom surface of the groove 210 is closest to the substrate 100. It should be understood that the depth of the etching epitaxial layer 200 can be adjusted, that is, the depth of the groove 210 can be adjusted. Here, by adjusting the depth of the groove 210, the relative depth of the first electrode, the second electrode, and the third electrode subsequently disposed in the groove 210 in the SGT-MOSFET subsequently formed can be adjusted. Therefore, the present invention can increase the number of shielding electrodes and the depth of the drift region by providing multiple shielding electrodes and adjusting the depth of the multiple shielding electrodes, and also enable the shielding electrodes to be arranged in the vertical and horizontal directions at the same time. In the direction, the charge balance effect is further improved, so that the charge can be distributed more uniformly to achieve the purpose of reducing the on-resistance.

Referring to FIG. 4, the patterned hard mask layer 400 is removed. The patterned hard mask layer 400 can be removed by performing an etching process or other suitable processes. The etching process may include dry etching, wet etching, or other suitable etching methods. Dry etching may include, but is not limited to, plasma etching, plasma-free gas etching, sputter etching, ion milling, and reactive ion etching (RIE). Wet etching may include, but is not limited to, using an acidic solution, an alkaline solution, or a solvent to remove at least a part of the structure to be removed. In addition, the etching process can also be pure chemical etching, pure physical etching, or any combination thereof.

Referring to FIG. 5, a first electrode dielectric layer 500 is formed on the sidewall and bottom surface of the groove 210 of the epitaxial layer 200 and on the semiconductor layer 300, so that the first electrode dielectric layer 500 has a trench T. The first electrode dielectric layer 500 can be silicon dioxide, silicon oxynitride, or any other suitable oxide layer material, or a combination of the above.

The first electrode dielectric layer 500 can be formed by CVD or thermal oxidation. CVD can be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD) ), PECVD, atomic layer deposition (ALD) or other suitable CVD processes.

In some embodiments, the first electrode dielectric layer 500 is compliantly formed on the epitaxial layer 200 and the semiconductor layer 300. Specifically, the first electrode dielectric layer 500 is disposed on the top surface and sidewalls of the semiconductor layer 300 and on the sidewalls and bottom surface of the groove 210 of the epitaxial layer 200. In some embodiments, the trench T has a substantially flat bottom surface, and the bottom surface of the trench T is substantially parallel to the bottom surface of the groove 210.

Referring to FIGS. 6 and 7, the first electrode 600 is formed in the trench T. In detail, in one embodiment, as shown in FIG. 6, a conductive material is filled in the trench T of the first electrode dielectric layer 500 to form the first electrode 600. A conductive material is used as the electrode material for forming the first electrode 600. The aforementioned conductive material may include amorphous silicon, polysilicon, metal, metal nitride, conductive metal oxide, or other suitable materials. In some embodiments, the conductive material used to form the first electrode 600 may be polysilicon. The method of filling the conductive material includes: CVD, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process, but it is not limited thereto. In addition, after the conductive material is filled, a chemical mechanical polishing (CMP) process may be further performed to make the top surface of the first electrode 600 and the top surface of the first electrode dielectric layer 500 substantially coplanar.

As shown in FIG. 7, the first electrode 600 is etched back so that the top surface of the first electrode 600 is lower than the top surface of the first electrode dielectric layer 500. The top surface of the first electrode 600 and the sidewall of the first electrode dielectric layer 500 form a shape similar to the trench T. Here, since the second electrode and the third electrode will be further formed later, the depth of the etch back of the first electrode 600 may depend on the shape and quantity of the second electrode and the third electrode formed later. In other words, the thickness of the first electrode 600 and the thickness of the first electrode dielectric layer 500 can be adjusted according to the shape and quantity of the second electrode and the third electrode to be formed later. In one embodiment, if a larger number of second electrodes and/or a larger size or a special shape need to be formed, the depth of the etch back of the first electrode 600 is deeper, that is, the first electrode 600 has Smaller thickness.

Referring to FIGS. 8 to 10, a pair of second electrodes 700 are formed on the first electrode 600 so that the pair of second electrodes 700 are arranged corresponding to each other along the horizontal direction D2. In other words, for those skilled in the art, the substrate 100, the epitaxial layer 200, and the semiconductor layer 300 are arranged along the vertical direction D1, while the pair of second electrodes 700 are arranged along the horizontal direction D2. set up. In other words, one second electrode 700 of the pair of second electrodes 700 and the other second electrode 700 of the pair of second electrodes 700 face each other. In an embodiment, one second electrode 700 of the pair of second electrodes 700 may be disposed on one side surface of the trench T, and the other second electrode 700 of the pair of second electrodes 700 may be disposed on the trench T. On the other side surface of the groove T, that is, on the opposite side surface, so that the pair of second electrodes 700 are arranged corresponding to each other along the horizontal direction D2. In detail, in one embodiment, as shown in FIG. 8, the second electrode dielectric layer 510 is formed on the first electrode 600 in compliance. The second electrode dielectric layer 510 is disposed between the first electrode 600 and the second electrode formed subsequently. The top surface of the second electrode dielectric layer 510 and the sidewall of the first electrode dielectric layer 500 form a trench-like shape. In one embodiment, the second electrode dielectric layer 510 is formed only on the first electrode dielectric layer 500 in the groove 210. In one embodiment, the second electrode dielectric layer 510 can be formed on the first electrode dielectric layer 500 and the first electrode 600 simultaneously. In some embodiments, the second electrode dielectric layer 510 and the first electrode dielectric layer 500 may be formed of the same or different materials. In some embodiments, the second electrode dielectric layer 510 may be silicon oxide, silicon oxynitride, low-k dielectric material, or any other suitable dielectric material, or a combination of the foregoing. In some embodiments, the second electrode dielectric layer 510 may include oxide. In some embodiments, the second electrode dielectric layer 510 and the first electrode dielectric layer 500 may be formed by the same or different processes.

As shown in FIG. 9, a conductive material is filled in the trench T and disposed on the second electrode dielectric layer 510 to conformally form the electrode material layer 710 on the second electrode On the dielectric layer 510. The electrode material layer 710 may have grooves. A conductive material is used as an electrode material for forming the second electrode 700. In some embodiments, the conductive material used to form the second electrode 700 and the conductive material used to form the first electrode 600 may be the same or different. In some embodiments, the second electrode 700 and the first electrode 600 can be formed by the same or different processes. In some embodiments, the conductive material used to form the second electrode 700 may be polysilicon.

As shown in FIG. 10, the electrode material layer 710 is etched to expose a part of the upper surface of the second electrode dielectric layer 510 to form the pair of second electrodes 700 with a gap therebetween. The minimum distance of the gap between the pair of second electrodes 700 may substantially correspond to the thickness of the electrode material layer 710 that is formed compliantly. In an embodiment, the shape of the pair of second electrodes 700 depends on the etching method, such as etching time, etching type, etching selectivity, and etching rate, but is not limited thereto. For example, when performing anisotropic etching, the pair of second electrodes 700 may have a narrow top and a wide bottom shape. That is, the distance S1 of the gap close to the substrate is smaller than the distance S2 of the gap far from the substrate 100. In an embodiment, the pair of second electrodes 700 may have a shape similar to a spacer.

In one embodiment, the steps of forming the second electrode 700 as described in FIGS. 8 to 10 may be repeated to form more than one pair of the second electrode 700 required to further adjust the subsequent formation. Electrical characteristics of SGT-MOSFET.

Referring to FIGS. 11 and 12, a third electrode 800 is formed on the pair of second electrodes 700 to obtain a semiconductor structure 1 according to an embodiment of the present invention. In detail, in one embodiment, as shown in FIG. 11, a third electrode dielectric layer 520 is conformably formed on the pair of second electrodes 700. The third electrode dielectric layer 520 is disposed between the pair of second electrodes 700 and the third electrode 800. In one embodiment, The third electrode dielectric layer 520 has a uniform thickness, so the third electrode subsequently formed on the third electrode dielectric layer 520 may have a shape corresponding to the pair of second electrodes 700. In this case, in addition to the third electrode 800 having a shape corresponding to the pair of second electrodes 700, a part of the third electrode 800 may extend into the gap between the pair of second electrodes 700. Furthermore, a part of the third electrode 800 can be in contact with the second electrode dielectric layer 510, that is, the third electrode 800 can be in contact with the second electrode not covered by the pair of second electrode 700 and the third electrode dielectric layer 520 A part of the upper surface of the two-electrode dielectric layer 510 is in contact with each other. In one embodiment, the third electrode dielectric layer 520 is formed only on the pair of second electrodes 700, so the third electrode dielectric layer 520 can expose a part of the upper surface of the second electrode dielectric layer 510.

In one embodiment, the third electrode dielectric layer 520 may be formed on the second electrode dielectric layer 510 and the pair of second electrodes 700 at the same time. In an embodiment, the third electrode dielectric layer 520 may have an uneven thickness, so the third electrode 800 subsequently formed on the third electrode dielectric layer 520 may not have a shape corresponding to the pair of second electrodes 700. In addition, in one embodiment, compared to the pair of second electrodes 700, the entire third electrode 800 is farther away from the substrate 100.

In some embodiments, the third electrode dielectric layer 520, the second electrode dielectric layer 510, and the first electrode dielectric layer 500 may be formed of the same or different materials. In some embodiments, the third electrode dielectric layer 520 may be silicon oxide, silicon oxynitride, low-k dielectric material, or any other suitable dielectric material, or a combination of the foregoing. In some embodiments, the third electrode dielectric layer 520 may include oxide. In some embodiments, the third electrode dielectric layer 520, the second electrode dielectric layer 510, and the first electrode dielectric layer 500 can be formed by the same or different processes.

Referring to Figure 12, fill conductive material in the trench T to form a third Electrode 800. A conductive material is used as the electrode material for forming the third electrode 800. In some embodiments, the conductive material used to form the third electrode 800 and the conductive material used to form the second electrode 700 and the conductive material used to form the first electrode 700 may be the same or different. In some embodiments, the third electrode 800 and the second electrode 700 and the first electrode 600 can be formed by the same or different processes. In some embodiments, the conductive material used to form the third electrode 800 may be polysilicon.

In one embodiment, after the conductive material is filled in the trench T, a planarization process can be further performed to planarize the conductive material until the upper surface of the first electrode dielectric layer 500 is exposed to form the third electrode 800. Furthermore, the semiconductor structure 1 including one embodiment of the first electrode 600, a pair of second electrodes 700, and a third electrode 800 of the present invention is obtained. The above-mentioned planarization process may include the use of, for example, a CMP process.

Referring to FIG. 13 to FIG. 18, the semiconductor structure of the present invention can form an SGT-MOSFET of one embodiment of the present invention by performing further processes.

As shown in FIG. 13, the first doped region 310 is formed on the surface of the semiconductor layer 300 away from the substrate 100. The method of forming the first doped region 310 includes, for example, ion implantation or diffusion process, but it is not limited thereto. In addition, the implanted dopants can also be activated by a rapid thermal annealing (RTA) process.

As shown in FIG. 14, an interlayer dielectric layer 900 is formed on the third electrode 800 and the first electrode dielectric layer 500. In some embodiments, the interlayer dielectric layer 900 and the third electrode dielectric layer 520 may be formed of the same material. In some embodiments, the interlayer dielectric layer 900 and the third electrode dielectric layer 520 can be formed by the same or different processes.

As shown in Fig. 15, a contact via CT is formed. Contact through hole CT can penetrate Pass through the first doped region 310, the first electrode dielectric layer 500, and the interlayer dielectric layer 900. The contact via CT does not penetrate the semiconductor layer 300. The contact via CT exposes a part of the semiconductor layer 300 provided on the epitaxial layer 200.

As shown in FIG. 16, a second doped region 320 is formed under the contact via CT and in the semiconductor layer 300. The first doped region 310 and the second doped region 320 have different conductivity types. As shown in FIG. 17, the through hole material is filled in the contact through hole CT to form a contact plug 330. In some embodiments, the via material may include metal materials, conductive materials, or other suitable materials. As shown in FIG. 18, a metal layer 910 is formed on the interlayer dielectric layer 900 so that the metal layer 910 and the contact plug 330 are in contact with each other to obtain an SGT-MOSFET of one embodiment of the present invention.

In some embodiments, the substrate 100, the epitaxial layer 200, and the first doped region 310 have the first conductivity type. The doping concentration of the first doped region 310 may be higher than the doping concentration of the substrate 100 and the epitaxial layer 200. The semiconductor layer 300 and the second doped region 320 have a second conductivity type different from the first conductivity type. The doping concentration of the second doping region 320 may be higher than the doping concentration of the semiconductor layer 300. Specifically, when the substrate 100 and the epitaxial layer 200 are of N type and the semiconductor layer 300 is of P type, the first doped region 310 may be a heavily doped N+ type, and the second doped region 320 may be heavily doped The P+ type.

It should be noted that, generally speaking, SGT-MOSFETs can be divided into left and right split gate SGT-MOSFETs and up and down split gate SGT-MOSFETs. When the upper and lower gate SGT-MOSFETs are to be formed, the semiconductor structure forming method of the present invention can simultaneously form a pair of shielding electrodes corresponding to each other in the horizontal direction in the same step, and only a few steps can be changed. In the case of the circumstance, simply add more shielding structures according to the demand to increase the charge balance effect to further improve Electrical characteristics of SGT-MOSFET.

In some embodiments of the present invention, the semiconductor structure may include a first electrode 600, a pair of second electrodes 700 arranged in a horizontal direction, and a third electrode 800. Wherein, the first electrode 600 and the pair of second electrodes 700 can serve as source electrodes of shielding electrodes. Therefore, the SGT-MOSFET in one of the embodiments of the present invention may have multiple shielding electrodes. The electrical performance of the SGT-MOSFET is improved by changing the capacitance between the gate electrode and the drain electrode by further disposing the pair of second electrodes 700.

In summary, according to some embodiments of the present invention, the present invention further improves the electrical performance by arranging multiple source shielding structures at the same time. For example, the gate and drain capacitance can be reduced, the on-resistance can be reduced, and the switching loss can be reduced.

In addition, because the present invention adjusts the process of setting the source shielding structure, the forming method of the present invention can be widely used in the improvement of various transistors, and is a kind of material that can form horizontally arranged spacers in a single step. A method of forming a pair of shielded electrodes. Therefore, the purpose of simplifying the manufacturing process and improving the electrical characteristics of the transistor can be achieved.

Although the embodiments of the present disclosure and their advantages have been disclosed as above, it should be understood that any person with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the manufacturing processes, machines, manufacturing, material composition, devices, methods, and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can implement some implementations from this disclosure. The disclosed content of the examples understands the current or future developed processes, machines, manufacturing, material composition, devices, methods, and steps, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. Book Some examples are disclosed for use. Therefore, the protection scope of the present disclosure includes the above-mentioned manufacturing processes, machines, manufacturing, material composition, devices, methods, and steps. In addition, each patent application scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes each patent application scope and a combination of embodiments.

Several embodiments are summarized above so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can design or modify other manufacturing processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field of the present invention should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention. Make all kinds of changes, substitutions and replacements.

1: Semiconductor structure

100: substrate

200: epitaxial layer

210: Groove

300: semiconductor layer

310: the first doped region

320: second doped region

330: contact plug

400: Patterned hard mask layer

500: first electrode dielectric layer

510: second electrode dielectric layer

520: third electrode dielectric layer

600: first electrode

700: second electrode

710: Electrode material layer

800: third electrode

900: Interlayer dielectric layer

910: Metal layer

CT: contact through hole

D1: vertical direction

D2: horizontal direction

OP: opening

S1, S2: Spacing

T: groove

Through the following detailed description and the accompanying drawings, we can better understand the viewpoints of the embodiments of the present invention. It is worth noting that, according to industry standard conventions, some features may not be drawn to scale. In fact, in order to be able to discuss clearly, the size of different components may be increased or decreased. Figures 1 to 12 are schematic cross-sectional views illustrating the formation of a semiconductor structure at various stages according to some embodiments of the present invention; and FIGS. 13 to 18 are cross-sectional schematic diagrams showing the formation of an SGT-MOSFET in various stages based on the semiconductor structure shown in FIG. 12 according to some embodiments of the present invention.

1: Semiconductor structure

100: substrate

200: epitaxial layer

300: semiconductor layer

500: first electrode dielectric layer

510: second electrode dielectric layer

520: third electrode dielectric layer

600: first electrode

700: second electrode

800: third electrode

D1: vertical direction

D2: horizontal direction

T: groove

Claims (13)

A method for forming a semiconductor structure includes: Sequentially forming an epitaxial layer and a semiconductor layer on a substrate; Forming a patterned hard mask layer on the semiconductor layer; Using the patterned hard mask layer as an etching mask, and etching the semiconductor layer and the epitaxial layer, so that the epitaxial layer has a groove; Removing the patterned hard mask layer; Forming a first electrode dielectric layer on the sidewall and bottom surface of the groove and on the semiconductor layer, so that the first electrode dielectric layer has a trench; Forming a first electrode in the trench; Forming a pair of second electrodes on the first electrode, so that the pair of second electrodes are arranged corresponding to each other along the horizontal direction; and A third electrode is formed on the pair of second electrodes. The forming method of claim 1, wherein the step of forming the pair of second electrodes on the first electrode further comprises: Forming a second electrode dielectric layer on the first electrode; Forming an electrode material layer on the second electrode dielectric layer; and The electrode material layer is etched to expose a part of an upper surface of the second electrode dielectric layer to form the pair of second electrodes with a gap therebetween. According to the forming method of claim 1, wherein the step of forming the third electrode on the pair of second electrodes further comprises: A part of the third electrode is extended into a gap between the pair of second electrodes. The forming method of claim 1, wherein before the step of forming the third electrode on the pair of second electrodes: A third electrode dielectric layer is formed on the pair of second electrodes. Such as the formation method of claim 4, where: The third electrode dielectric layer has a shape corresponding to the pair of second electrodes, and the third electrode dielectric layer exposes a part of the upper surface of the second electrode dielectric layer. Such as the formation method of claim 1, which further includes: Forming a first doped region on the semiconductor layer; Forming an interlayer dielectric layer on the first electrode dielectric layer; Forming a contact through hole, the contact through hole exposing a part of the semiconductor layer disposed on the epitaxial layer; Forming a second doped region under the contact via and in the semiconductor layer; Filling a through hole material in the contact through hole to form a contact plug; and A metal layer is formed on the interlayer dielectric layer so that the metal layer and the contact plug are in contact with each other. Such as the formation method of claim 6, where: The substrate, the epitaxial layer, and the first doped region have a first conductivity type, and the semiconductor layer and the second doped region have a second conductivity type different from the first conductivity type . A semiconductor structure comprising: A substrate having a first conductivity type; An epitaxial layer having the first conductivity type, disposed on the substrate, and having a groove; A semiconductor layer having a second conductivity type different from the first conductivity type and disposed on the epitaxial layer; A first electrode dielectric layer, arranged on the sidewall and bottom surface of the groove and on the semiconductor layer, with a groove; A first electrode arranged in the groove; A pair of second electrodes arranged on the first electrode, the pair of second electrodes corresponding to each other along the horizontal direction; and A third electrode is arranged on the pair of second electrodes. Such as the semiconductor structure of claim 8, which further includes: A second electrode dielectric layer disposed between the first electrode and the pair of second electrodes; and A third electrode dielectric layer is arranged between the pair of second electrodes and the third electrode. The semiconductor structure of claim 8, wherein a part of the third electrode extends into a gap between the pair of second electrodes. The semiconductor structure of claim 8, wherein a part of the third electrode is in contact with the second electrode dielectric layer. The semiconductor structure of claim 8, wherein the shape of a part of the third electrode corresponds to the shape of the pair of second electrodes. Such as the semiconductor structure of claim 8, which further includes: A first doped region having the first conductivity type and disposed on the semiconductor layer; An interlayer dielectric layer disposed on the first electrode dielectric layer; A contact plug that penetrates the interlayer dielectric layer, the first electrode dielectric layer, and the first doped region, but does not penetrate the semiconductor layer; A second doped region having the second conductivity type, disposed on the semiconductor layer, and in contact with the contact plug; and A metal layer is arranged on the interlayer dielectric layer and is in contact with the contact plug.

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