TWI740271B - Interated circuit structures and methods for forming the same - Google Patents

Abstract

An integrated circuit structure includes a bulk semiconductor region, a first semiconductor strip over and connected to the bulk semiconductor region, and a dielectric layer including silicon oxide therein. Carbon atoms are doped in the silicon oxide. The dielectric layer includes a horizontal portion over and contacting a top surface of the bulk semiconductor region, and a vertical portion connected to an end of the horizontal portion. The vertical portion contacts a sidewall of a lower portion of the first semiconductor strip. A top portion of the first semiconductor strip protrudes higher than a top surface of the vertical portion to form a semiconductor fin. The horizontal portion and the vertical portion have a same thickness. A gate stack extends on a sidewall and a top surface of the semiconductor fin.

Description

Integrated circuit structure and manufacturing method thereof

The embodiments of the present invention are related to semiconductor technology, and particularly related to integrated circuit structures and manufacturing methods thereof.

With the increasing miniaturization of integrated circuits and the increasingly demanding requirements for the speed of integrated circuits, transistors with smaller and smaller sizes need to have larger drive currents. Therefore, Fin Field-Effect Transistor (FinFET) has been developed. The fin-type field effect transistor includes a vertical semiconductor fin above the substrate. The semiconductor fin is used to form a source region and a drain region, and a channel region between the source region and the drain region. A Shallow Trench Isolation (STI) region is formed to define the semiconductor fin. The fin-type field effect transistor also includes a gate stack, which is formed on the sidewall and top surface of the semiconductor fin.

When forming the shallow trench isolation region and the corresponding fin field effect transistor, the shallow trench isolation region is formed first, and then the shallow trench isolation region is recessed to form a semiconductor fin, and a fin field effect transistor is formed based on this. The formation of the shallow trench isolation region may include forming an isolation liner, and then forming an oxide region on the isolation liner by using flowable chemical vapor deposition.

In some embodiments, an integrated circuit structure is provided. The integrated circuit structure includes a bulk semiconductor region; a first semiconductor strip is above the bulk semiconductor region and connected to the bulk semiconductor region; and the dielectric layer includes silicon oxide, wherein Carbon atoms are doped in silicon oxide, and the dielectric layer includes: a horizontal portion above and in contact with the top surface of the bulk semiconductor region; and a vertical portion connecting the ends of the horizontal portion, where the vertical portion Partially contacting the sidewall of the lower portion of the first semiconductor strip, wherein the top of the first semiconductor strip protrudes higher than the top surface of the vertical portion to form a semiconductor fin; and a gate stack extending on the sidewall and top surface of the semiconductor fin.

In some other embodiments, an integrated circuit structure is provided, and the integrated circuit structure includes a bulk semiconductor substrate; and an isolation region over and in contact with the bulk semiconductor substrate, wherein the isolation region includes a dielectric pad, It includes silicon oxide, in which carbon atoms are doped in the silicon oxide; and a dielectric region, which is filled in the area between the vertical portions on both sides of the dielectric liner, wherein the dielectric region contains silicon oxide and does not contain carbon.

In some other embodiments, a method for manufacturing an integrated circuit structure is provided. The method includes etching a semiconductor substrate to form a trench; forming a first dielectric layer through an atomic layer deposition cycle, wherein the first dielectric layer extends into the trench , And the atomic layer deposition cycle includes: pulsing hexachlorodisilane to the semiconductor substrate; removing hexachlorodisilane; after removing the hexachlorodisilane, pulsing triethylamine to the semiconductor substrate; and removing triethylamine; An annealing process is performed on a dielectric layer; and a planarization process is performed on the first dielectric layer, wherein the remaining part of the annealed first dielectric layer forms a part of the isolation region.

It should be understood that the following disclosure provides many different embodiments or examples to implement different components of the main body provided. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the present invention. For example, the following disclosure describes that a first part is formed on or above a second part, which means that it includes an embodiment in which the formed first part and the second part are in direct contact, and also includes This is an embodiment in which an additional component can be formed between the first component and the second component, and the first component and the second component may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and/or words. These repeated symbols or words are for the purpose of simplification and clarity, and are not used to limit the relationship between the various embodiments and/or the appearance structure.

Furthermore, in order to facilitate the description of the relationship between one element or component and another (plural) element or (plural) component in the drawings, space-related terms can be used, such as "under", "below", and "lower part". ", "upper", "upper" and similar terms. In addition to the orientation shown in the diagram, space-related terms also cover different orientations of the device in use or operation. The device can also be positioned separately (for example, rotated 90 degrees or located in another orientation), and correspondingly interpret the description of the used spatially related terms.

Provide shallow trench isolation (STI) regions and fin field effect transistors (FinFET) and manufacturing methods thereof. The intermediate stages of forming shallow trench isolation regions and fin-type field effect transistors according to some embodiments are shown. Discuss some variations of some embodiments. In the various views and displayed embodiments, similar reference symbols are used to label similar elements. According to some embodiments of the present invention, the formation of the shallow trench isolation region includes forming a SiOCN film (which may be a SiOCNH film), and then performing an annealing process to convert the SiOCN film into a silicon oxide layer. The SiOCN film and the final silicon oxide layer have good oxidation resistance and can protect the semiconductor strips between the shallow trench isolation regions from oxidation. The concepts of the discussed embodiments can also be applied to structures including any other gap filling processes for filling silicon oxide and any other processes for forming silicon oxide and processing of other structures, but is not limited thereto. The embodiments discussed herein provide examples of the main body capable of manufacturing or using the embodiments of the present invention, and those skilled in the art to which the present invention pertains will understand that modifications can be made while still being considered in the scope of different embodiments. Similar reference symbols and words in the following figures refer to similar components. Although the discussed method embodiments can be performed in a specific order, other method embodiments can be performed in any logical order.

Figures 1, 2, 3A, 3B, 4, 5A, 5B, 6A, 6B, 6C, 7-12, 13A, 13B, and 13C show the formation of shallow trench isolation regions and fin field effect transistors according to some embodiments Part of the perspective view and cross-sectional schematic diagram of the intermediate stage. The corresponding manufacturing process is schematically compared to the manufacturing process 200 shown in FIG. 30.

Figure 1 shows a perspective view of the initial structure. The initial structure includes a wafer 10, which includes a substrate 20 (sometimes referred to as a semiconductor substrate). The substrate 20 may further include a substrate (portion) 20-1. The substrate 20-1 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20-1 may also be a bulk substrate or a semiconductor substrate overlying an insulating layer.

According to some embodiments of the present invention, the displayed area is a p-type device area, in which a p-type transistor will be formed, such as a p-type fin field effect transistor (FinFET). The epitaxial semiconductor layer 20-2 (sometimes referred to as the epitaxial layer for short) is epitaxially grown on top of the substrate 20-1. The corresponding process is shown as process 202 in the process flow 200 in FIG. 30. Throughout this specification, the epitaxial semiconductor layer 20-2 and the substrate 20-1 are collectively referred to as the substrate 20. The epitaxial semiconductor layer 20-2 may be formed of silicon germanium (SiGe) or germanium (without silicon). The atomic percentage of germanium in the epitaxial semiconductor layer 20-2 may be higher than the atomic percentage of germanium in the substrate 20-1 (if any). According to some embodiments of the present invention, the atomic percentage (when formed of SiGe) in the epitaxial semiconductor layer 20-2 is in a range between about 30% and about 100%. The epitaxial semiconductor layer 20-2 may also be formed of SiP, SiC, SiPC, SiGeB, or III-V compound semiconductors (for example, InP, GaAs, AlAs, InAs, InAlAs, InGaAs) or the like, or may be formed of a layer containing the foregoing materials. Formation. The epitaxial semiconductor layer 20-2 may also be substantially free of silicon, for example, having a silicon percentage of less than about 1%.

According to some embodiments of the present invention, the displayed device region is a p-type device region, in which a p-type transistor, such as a p-type fin field effect transistor, will be formed. Therefore, the epitaxial semiconductor layer 20-2 can be formed. On the same wafer and in the same device die, n-type fin field effect transistors can be formed, and the corresponding device region used to form the n-type fin field effect transistor may not have the epitaxial semiconductor layer 20-2. In it.

A cushion layer 22 (sometimes referred to as a pad oxide layer) and a mask layer 24 (sometimes referred to as a hard mask) may be formed on the substrate 20. The cushion layer 22 may be a thin film formed of silicon oxide. According to some embodiments of the present invention, the underlayer 22 is formed in a thermal oxidation process, in which the top surface layer of the substrate 20 is oxidized. The cushion layer 22 serves as an adhesive layer between the base 20 and the mask layer 24. The underlayer 22 can also serve as an etch stop layer for etching the mask layer 24. According to some embodiments of the present invention, the mask layer 24 is made of silicon nitride formed by, for example, Low-Pressure Chemical Vapor Deposition (LPCVD). According to other embodiments of the present invention, the mask layer 24 is formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) or similar methods. The mask layer 24 is used as a hard mask during the subsequent photolithography process.

Please refer to FIG. 2, the mask layer 24 and the cushion layer 22 are etched to expose the substrate 20 below. Next, the exposed substrate 20 is etched to form a trench 31. The corresponding process is shown as process 204 in the process flow 200 in FIG. 30. The portion of the substrate 20 between the adjacent trenches 31 is later referred to as a semiconductor strip 30, and the semiconductor strip 30 covers the lower square-shaped portion connected to the substrate 20. The grooves 31 may have a strip shape parallel to each other (when viewed from the top view of the wafer 10). Although FIG. 2 shows one semiconductor strip 30, a plurality of semiconductor strips 30 can be formed parallel to each other (please refer to FIG. 3B), wherein the trench 31 separates the plurality of semiconductor strips 30 from each other. According to some embodiments of forming the epitaxial semiconductor layer 20-2 of the present invention, the bottom of the trench 31 can be lower than the interface 23 between the substrate 20-1 and the epitaxial semiconductor layer 20-2.

According to some embodiments, referring to FIGS. 3A and 3B, the silicon layer 32 is deposited. The corresponding process is shown as process 205 in the process flow 200 in FIG. 30. According to other embodiments, the step of depositing the silicon layer 32 is omitted. The deposition can be performed through a compliant deposition process, such as low pressure chemical vapor deposition (LPCVD), chemical vapor deposition (Chemical Vapor Deposition, CVD) or similar methods. The silicon layer 32 may contain no or substantially no other elements such as germanium, carbon or the like. For example, the atomic percentage of the silicon layer 32 may be greater than about 95%. The silicon layer 32 can be formed as a crystalline silicon layer or a polysilicon layer, which can be achieved, for example, by adjusting the temperature and growth rate of the deposition process. The thickness of the silicon layer 32 may be in the range between about 10 Å and about 25 Å.

When the epitaxial semiconductor layer 20-2 is formed in the foregoing steps, the silicon layer 32 is formed. In a region where the epitaxial semiconductor layer 20-2 is not formed and the entire semiconductor strip 30 is formed of silicon, the silicon layer 32 may or may not be formed. According to various embodiments, in FIG. 3A, the silicon layer 32 is shown by a dotted line to indicate that the silicon layer 32 may or may not be formed.

3A and 3B also respectively show a perspective view and a schematic cross-sectional view of the intermediate stage of the growth/deposition of the dielectric layer 34. The corresponding process is shown as process 206 in the process flow 200 in FIG. 30. The wafer 10 is placed in an atomic layer deposition (ALD) chamber (not shown), and an atomic layer deposition cycle is performed in the atomic layer deposition chamber to grow the dielectric layer 34. The atomic layer deposition process is a compliant deposition process. Therefore, the thickness T1 of the horizontal portion of the dielectric layer 34 (FIG. 3B) is equal to the thickness T2 of the vertical portion of the dielectric layer 34. According to some embodiments, the thickness T1 and the thickness T2 may be in a range between about 15 Å and about 50 Å.

FIG. 3B shows a schematic cross-sectional view of the reference cross-section 3B-3B of FIG. 3A, in which a plurality of closely spaced semiconductor strips 30 are formed as a group, and the semiconductor strips 30 are separated from each other by a narrow trench 31A. According to some embodiments, the narrow trench 31A has a small width W1, and the width W1 may be less than about 160 Å, or in a range between about 100 Å and about 250 Å. It is also possible to have wide trenches 31B, for example, on both outer sides of the group of closely arranged semiconductor strips 30. The width W2 of the wide trench 31B is greater than the width W1, for example, the ratio of W2/W1 is greater than about 2.0. The width W2 can also be greater than about 150Å. The grooves 31A and 31B are collectively referred to as grooves 31.

The intermediate chemical structure of the dielectric layer 34 (shown in Figures 3A and 3B) during formation is shown in Figures 14 and 15. FIG. 14 shows the first atomic layer deposition process to deposit the dielectric layer 34. The intermediate structure shown in Fig. 14 is distinguished from each other by using reference symbols 112, 114, 116, and 118. The structures produced through different steps are distinguished from each other. The wafer 10 includes a base layer 110. The base layer 110 may represent an exposed component. It includes the base 20, the semiconductor strip 30 and the silicon layer 32 of FIGS. 3A and 3B (if the silicon layer 32 is not formed, or the pad layer 22 and Mask layer 24). The initial structure in Figure 14 is referred to as structure 112. In the example shown, the base layer 110 is shown to contain silicon, which may be in the form of crystalline silicon, amorphous silicon, polycrystalline silicon, or the like. The base layer 110 may also include other types of silicon-containing compounds, such as silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, or the like. According to some embodiments of the present invention, since the native oxide is formed and exposed to moisture, the Si-OH bond is formed on the surface of the silicon-containing base layer 110.

Please refer to Figure 14, in the process 130, hexachlorodisilane (HCD) is introduced/pulsed into the atomic layer deposition chamber, and the wafer (Figures 3A and 3B) is placed in the atomic layer deposition chamber. The corresponding process is shown as process 208 in the process flow 200 in FIG. 30. Hexachlorodisilane has the chemical formula (SiCl ₃ ) ₂ , and Figure 18 shows the chemical formula of the hexachlorodisilane molecule. The chemical formula shows that the hexachlorodisilane molecule contains a chlorine atom bonded to two silicon atoms, and the silicon atoms are bonded to each other. When the hexachlorodisilane pulse enters the atomic layer deposition chamber, the wafer 10 can be heated, for example, to a temperature in a range between about 550°C and about 670°C. The OH bond shown in the structure 112 is broken, and the silicon atom and the chlorine atom bonded to the silicon atom are bonded to the oxygen atom to form an O-Si-Cl bond. The resulting structure is called structure 114. According to some embodiments of the present invention, when hexachlorodisilane is introduced, the plasma is not turned on. The hexachlorodisilane gas can remain in the atomic layer deposition chamber for a time between about 20 seconds and about 25 seconds. According to some embodiments, the pressure of the atomic layer deposition chamber may be in a range between about 100 Pa and about 150 Pa.

Next, remove the hexachlorodisilane in the atomic layer deposition chamber. The corresponding process is shown as process 208 in the process flow 200 in FIG. 30. In the process 132, a process gas containing nitrogen atoms bonded with alkyl groups may be pulsed into the atomic layer deposition chamber. For example, triethylamine can be pulsed. The corresponding process is shown as process 210 in the process flow 200 in FIG. 30. Triethylamine may have the chemical formula N(CH ₂ CH3) ₃ , which contains a nitrogen atom bonded to three ethyl groups (CH ₂ CH ₃ ). According to some embodiments, Figure 19 shows the symbol for triethylamine. This symbol shows that triethylamine contains a nitrogen atom bonded to three ethyl groups, and the symbol ">" each connected to a nitrogen (N) atom represents an ethyl group (CH ₂ CH ₃ , or CH ₂ molecule is bonded to CH ₃ molecule). With the introduction/pulse of triethylamine, the temperature of the wafer 10 can also be kept elevated, for example, in the range between about 550°C and about 670°C. The temperature can also be kept the same as during the pulsed hexachlorodisilane process. According to some embodiments of the present invention, when triethylamine is introduced, the plasma is not turned on. During the pulse of triethylamine, the atomic layer deposition chamber may have a pressure in a range between about 800 Pa and about 1000 Pa.

Structure 114 reacts with triethylamine. The resulting structure is referred to as structure 116, as shown in Figure 14. During the reaction, the Si-Cl bond in structure 114 is broken so that nitrogen atoms (such as in triethylamine) can be bonded to silicon atoms. Silicon atoms can be bonded to three nitrogen atoms, and each nitrogen atom can be bonded to two ethyl groups. The triethylamine can remain in the atomic layer deposition chamber for a time between about 5 seconds and about 15 seconds, and then the triethylamine in the atomic layer deposition chamber is removed. The corresponding process is shown as process 210 in the process flow 200 in FIG. 30.

Next, as shown in the process 134 in Figure 14, oxygen (O ₂ ) is pulsed into the atomic layer deposition chamber. The corresponding process is shown as process 212 in the process flow 200 in FIG. 30. During process 212, structure 116 reacts with oxygen to produce structure 118. Alkyl groups such as the ethyl group in structure 116 help to convert Si-N bonds into Si-O bonds, for example, break some of the Si-N bonds in structure 116, and silicon atoms are bonded to oxygen atoms. Some nitrogen atoms and ethyl groups bonded to nitrogen atoms can also remain bonded to silicon atoms. Some oxygen atoms can bond two silicon atoms to create cross-links between some silicon atoms. According to some embodiments of the present invention, when oxygen is introduced, the plasma is not turned on. During pulsed oxygen, the atomic layer deposition chamber may have a pressure in a range between about 800 Pa and about 1000 Pa. The time that oxygen can remain in the atomic layer deposition chamber is between about 5 seconds and about 15 seconds, and then the oxygen in the atomic layer deposition chamber is removed. The corresponding process is shown as process 212 in the process flow 200 in FIG. 30.

In the above process, the processes 130 and 132 can be collectively referred to as an atomic layer deposition cycle 136. The atomic layer deposition cycle 136 results in the growth of an atomic layer, which contains silicon atoms and correspondingly bonded nitrogen atoms and ethyl groups. Furthermore, the processes 130, 132, and 134 can also be referred to as the atomic layer deposition cycle 138. The atomic layer deposition cycle 138 leads to the growth of an atomic layer. The atomic layer includes silicon atoms and correspondingly bonded nitrogen atoms and ethyl groups, and is bonded Oxygen atom. According to some embodiments, the atomic layer resulting from the atomic layer deposition cycle 138 has a thickness of about 1 Å.

After the process 134 is completed, the atomic layer deposition cycle 138 is repeated, so that a plurality of atomic layers are deposited to form the dielectric layer 34, as shown in FIGS. 3A and 3B. In the subsequent atomic layer deposition cycle, the Si-O bond and Si-N bond formed in the previous atomic layer deposition cycle can be broken, and the Si-Cl bond can be formed due to the pulsed hexachlorodisilane. Then, the Si-N bond and the corresponding ethyl group can be substituted for the Si-Cl bond. Next, oxygen can be used to form Si-O bonds, with Si-O bonds replacing some of the Si-N bonds. Figure 15 shows the resulting chemical structure of the dielectric layer 34.

The atomic layer deposition cycle 138 is repeated until the dielectric layer 34 has the desired thickness. It is understood that, depending on the thickness of the dielectric layer 34 desired, many atomic layers can be deposited. According to some embodiments of the present invention, the thickness of the dielectric layer 34 may be, for example, in a range between about 15 Å and about 50 Å. The deposited dielectric layer 34 is a SiOCN layer. Since hydrogen is present in the ethyl group, the dielectric layer 34 is also a SiOCNH layer.

According to some embodiments of the present invention, after the atomic layer deposition cycle 138, the resulting dielectric layer 34 has a carbon (atomic) percentage in the range between about 1% and about 15%. The atomic percentage of nitrogen in the dielectric layer 34 cannot be too high or too low. If the nitrogen atom percentage is too high, the semiconductor strip 30 may be bent in the subsequent manufacturing process. If the nitrogen atom percentage is too low, the resulting dielectric layer 34 and the final silicon oxide layer may not have sufficient oxidation resistance, and the semiconductor strip 30 cannot be properly protected from oxidation during the subsequent annealing process. For example, the nitrogen (atomic) percentage in the dielectric layer 34 may be in a range between about 5% and about 20%. Most of the remaining elements in the dielectric layer 34 are silicon and oxygen, which may have an atomic ratio of silicon to oxygen of about 1.5:2 to about 1:2.5, and may be, for example, about 1:2. For example, the atomic percentage of silicon may be in the range between about 20% and about 40%. The atomic percentage of oxygen may be in the range between about 50% and about 70%.

After the dielectric layer 34 is deposited (grown), an annealing process is performed. The corresponding process is shown as process 214 in the process flow 200 in FIG. 30. According to some embodiments of the present invention, the annealing process includes a low temperature wet annealing process, a high temperature wet annealing process, and a dry annealing process. The low temperature wet annealing process and the high temperature wet annealing process can be performed by using steam (H ₂ O) as the process gas. The dry annealing process can be performed by using nitrogen (N ₂ ), argon or the like as a carrier gas. The annealing process is discussed below with reference to Figures 16 and 17.

According to some embodiments of the present invention, the low temperature wet annealing process is first performed. The corresponding process is shown as process 216 in the process flow 200 in FIG. 30. The low temperature wet annealing process is performed at a relatively low temperature, for example, in a range between about 300°C and about 450°C. The duration of the low temperature wet annealing process may be in the range between about 3 hours and about 5 hours. The pressure during the low temperature wet annealing process may be about 1 atmosphere. The low temperature wet annealing process has two functions. The first function is to drive water/vapor (H ₂ O) molecules into the dielectric layer 34. The second function is to partially convert Si-NC bonds, Si-CH ₃ bonds, and Si-N-Si bonds in the dielectric layer 34 into Si-OH bonds. The temperature is controlled high enough to cause at least a partial transformation. On the other hand, the temperature of the low temperature wet annealing process cannot be too high. Otherwise, the surface layer of the dielectric layer 34 will expand to prevent water molecules from entering the inside of the dielectric layer 34. Therefore, the temperature range is selected between about 300°C and about 450°C according to the experimental results.

After the low temperature wet annealing process, a high temperature wet annealing process is performed. The corresponding process is shown as process 218 in the process flow 200 in FIG. 30. The high temperature wet annealing process is performed at a relatively high temperature higher than the temperature of the low temperature wet annealing process. For example, the temperature of the high temperature wet annealing process may be in the range between about 450°C and about 650°C. The duration of the high temperature wet annealing process may be in the range between about 1.5 hours and about 2.5 hours. The pressure during the high temperature wet annealing process may be about 1 atmosphere. The temperature is high enough to effectively convert the Si-C-N bonds in the dielectric layer 34 into Si-OH bonds, as shown schematically in FIG. 16. On the other hand, the temperature cannot be too high to cause excessive oxidation of the semiconductor material. For example, the semiconductor strip 30 includes SiGe, and the temperature of the high temperature wet annealing process is lower than about 650°C. Otherwise, SiGe can be oxidized. Although the rate is lower, silicon can also be oxidized above about 650°C. Therefore, the temperature of the high temperature wet annealing process can be in the range between about 500°C and about 650°C, or in the range between about 500°C and about 600°C for high conversion efficiency and still have some Process margin.

The high temperature wet annealing process breaks the Si-N bond and Si-O bond. In addition to the nitrogen atom, the alkyl group attached to the nitrogen atom is also broken together. The OH group is attached to the broken bond. The obtained chemical structure can be schematically shown in Figure 16. During the high temperature wet annealing process, the dielectric layer 34 expands, and the volume expansion rate can be as high as about 10%.

After the high temperature wet annealing process, a dry annealing process is performed to form silicon oxide. The corresponding process is shown as process 220 in the process flow 200 in FIG. 30. As the process gas, an oxygen-free process gas can be used, such as nitrogen (N ₂ ), argon, or the like. The temperature of the dry annealing process cannot be too high or too low. If the temperature is too low, the OH bond may not be sufficiently broken, and the conversion rate of Si-OH to Si-O-Si is low. If the temperature is too high, the semiconductor strip 30 (e.g., SiGe) can be mixed with surrounding materials. According to some embodiments of the present invention, the dry annealing process is performed in a temperature range between about 600°C and about 800°C. The duration of the dry annealing process may be in the range between about 0.5 hours and about 1.5 hours. The pressure can be about 1 atmosphere. A carrier gas can be used to take away the generated H ₂ O vapor. The carrier gas can be nitrogen, argon or the like.

In the dry annealing process, the OH bond and the Si-O bond are broken (Figure 16), and the broken H and OH combine to form H ₂ O molecules. Due to the loss of hydrogen atoms, the dangling oxygen atom bonds can bond with Si to form Si-O-Si bonds and form silicon oxide (SiO ₂ ). The resulting dielectric layer is later referred to as a silicon oxide layer 34', which is shown in FIG. 4. After the dry annealing process, a small percentage of carbon atoms and nitrogen atoms may remain in the silicon oxide layer 34'. The atomic percentage of carbon atoms and nitrogen atoms is less than about 1%, and may be between about 0.5% and about 1.0%. between. This is different from the shallow trench isolation region formed by the traditional method, and the shallow trench isolation region formed by the traditional method does not have carbon. Furthermore, since carbon and nitrogen atoms are the remaining atoms of the deposited dielectric layer 34, the distribution of carbon and nitrogen atoms is approximately uniform. Furthermore, since the hexachlorodisilane includes chlorine atoms, the dielectric layer 34 includes chlorine atoms, and therefore the silicon oxide layer 34' may also include a small amount of chlorine atoms therein, for example, less than about 1%, and may be Between about 0.5% and about 1.0%.

Please refer to FIGS. 5A and 5B to fill the remaining trenches 31 with a dielectric layer (region) 40. The corresponding process is shown as process 222 in the process flow 200 in FIG. 30. The dielectric layer 40 may be a deposited silicon nitride layer formed by using, for example, atomic layer deposition, high-density plasma chemical vapor deposition (High-Density Plasma Chemical Vapor Deposition, HDPCVD) or chemical vapor deposition (CVD). Carbon dielectric or similar. The dielectric layer 40 can also be formed by using Flowable Chemical Vapor Deposition (FCVD), spin coating or similar methods. The dielectric layer 40 is deposited to a level higher than the top surface of the silicon oxide layer 34'. The dielectric layer 40 may contain no carbon, no chlorine, and may or may not contain nitrogen atoms. When the dielectric layer 40 includes nitrogen, the atomic percentage of nitrogen in the dielectric layer 40 is higher than the atomic percentage of nitrogen in the silicon oxide layer 34'. For example, the atomic percentage of nitrogen in the dielectric layer 40 may be higher than about 30%. Furthermore, due to the formation method, the dielectric layer 40 may have a density lower than that of the silicon oxide layer 34'.

The formation of the dielectric layer 40 may include an annealing process, which may also involve, for example, wet annealing using water vapor. During the aforementioned annealing process including the annealing process for converting the dielectric layer 34 into the silicon oxide layer 34', the dielectric layer 34 and the finally transformed silicon oxide layer 34' have the ability to prevent the semiconductor strip 30 from oxidizing. This ability is called oxidation resistance.

Then, a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical polishing process) is performed to remove the excess portion of the dielectric material including the silicon oxide layer 34' and the dielectric layer 40. The corresponding process is shown as process 222 in the process flow 200 in FIG. 30. The remaining part of the dielectric material is the shallow trench isolation region. The planarization process can be performed by using the mask layer 24 as a chemical mechanical polishing stop layer.

In the subsequent process, as shown in FIGS. 6A, 6B, and 6C, the shallow trench isolation region 42 formed in the foregoing process is recessed, so that the top of the semiconductor strip 30 protrudes higher than the top surface 34S of the silicon oxide layer 34' (Figures 6B and 6C) to form protruding fins 44. The corresponding process is shown as process 224 in the process flow 200 in FIG. 30. The recess of the dielectric layer can be performed by using a dry etching process, in which HF ₃ and NH _{3 are} used as etching gases. According to other embodiments of the present invention, the recess of the dielectric layer 34 can be performed by using a wet etching process. For example, the etching chemistry may include an HF solution. The mask layer 24 and the cushion layer 22 can also be removed (Figures 5A and 5B). According to some embodiments of the present invention, the bottom of the protruding fin 44 is at a level higher than the bottom surface (ie, the interface 23) of the epitaxial semiconductor layer 20-2 (if formed).

According to some embodiments, as shown in FIG. 6B, both the silicon oxide layer 34' and the dielectric layer 40 are recessed. According to other embodiments, as shown in FIG. 6C, the silicon oxide layer 34' is recessed and the dielectric layer 40 is not etched, so that the dummy dielectric fin 45 protrudes higher than the top surface 34S of the remaining part of the silicon oxide layer 34' . When the silicon oxide layer 34' is thick enough, the dummy dielectric fin 45 can be formed, so that the gate stack and the gate spacer formed later fill the space between the protruding fin 44 and the dummy dielectric fin 45. According to some embodiments, the thickness T3 of the silicon oxide layer 34' can be increased, for example, greater than about 30 Å, and may be in a range between about 10 Å and about 100 Å. Due to the conformal deposition of the dielectric layer 34, when the narrow trench 31A is filled with the dielectric layer 34, the wide trench 31B is not completely filled (Figure 2B). This makes it possible to fill the dielectric layer 40 when the silicon oxide layer 34' is thick enough, and makes it possible to form a dummy dielectric fin 45. When the size of the fin-type field effect transistor is very small, generating dummy fins helps to improve the device performance of the fin-type field effect transistor.

In the above embodiment, the semiconductor fin can be formed by any suitable method. For example, semiconductor fins can be patterned by using one or more photolithography processes (including double patterning or multiple patterning processes). Generally speaking, a double patterning or multiple patterning process combines photolithography and self-alignment processes to create patterns with smaller pitches. For example, this pattern has better performance than that obtained using a single direct photolithography process. Patterns with smaller spacing. For example, in one embodiment, the sacrificial layer is formed on the substrate and patterned by using a photolithography process. The spacer is formed beside the patterned sacrificial layer by using a self-aligned process. Next, the sacrificial layer is removed, and the remaining spacers or mandrels can then be used to pattern the fins.

Please refer to FIG. 7, a dummy gate stack 46 is formed across the protruding fin 44. The dummy gate stack 46 may include a dummy gate dielectric 48 and a dummy gate electrode 50 above the dummy gate dielectric 48. The dummy gate dielectric 48 may be formed of silicon oxide or other dielectric materials. The dummy gate electrode 50 can be formed by using polysilicon or amorphous silicon, and other materials can also be used. Each dummy gate stack 46 may also include one (or more) hard mask 52 above the dummy gate electrode 50. The hard mask 52 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or the foregoing multiple layers. The dummy gate stack 46 may span a single or a plurality of protruding fins 44 and/or shallow trench isolation regions 42. The dummy gate stack 46 also has a length direction perpendicular to the length direction of the protruding fin 44. The formation of the dummy gate stack 46 may include depositing a dummy gate dielectric layer, depositing a gate electrode layer over the dummy gate dielectric layer, depositing a hard mask layer, and patterning the stacked layer to form the dummy gate stack物46.

Next, referring to FIG. 8, the gate spacer 54 is formed on the sidewall of the dummy gate stack 46. The formation of the gate spacer 54 may include depositing a blanket dielectric layer, and performing anisotropic etching to remove the horizontal portion of the dielectric layer, leaving the gate spacer on the sidewall of the dummy gate stack 46 54. According to some embodiments of the present invention, the gate spacer 54 is formed of an oxygen-containing dielectric material (oxide), such as SiO ₂ , SiOC, SiOCN or the like. According to some embodiments of the present invention, the gate spacer 54 may also include a non-oxide dielectric material, such as silicon nitride.

Next, an etching process is performed to etch the portion of the protruding fin 44 that is not covered by the dummy gate stack 46 and the gate spacer 54 to obtain the structure shown in FIG. 9. The recessing of the protruding fin 44 can be performed through an anisotropic etching process, and thus the portion of the protruding fin 44 directly below the dummy gate stack 46 and the gate spacer 54 is protected from being etched. According to some embodiments, the top surface of the recessed semiconductor strip 30 may be lower than the top surface 42A of the shallow trench isolation region 42. The space previously occupied by the etched portion of the protruding fin 44 is later referred to as the notch 60. The notches 60 include some portions between the shallow trench isolation regions 42 (as shown in FIG. 9), and some portions are higher than the shallow trench isolation regions 42 and between the dummy gate stacks 46. During the recessing process, the portion of the silicon layer 32 higher than the bottom surface 60A of the recess 60 is also etched, so that the sidewall of the silicon oxide layer 34' can be exposed. If the silicon oxide layer 34' is very thin, the exposed portion of the silicon oxide layer 34' may also be consumed during the formation of the notch 60. The bottom surface 60A can also be higher, flush, or lower than the interface 23. Therefore, there may or may not be the remaining part of the epitaxial semiconductor layer 20-2 directly under the notch 60.

Next, the epitaxial region 62 (source/drain region) is formed by selectively growing a semiconductor material from the recess 60 to obtain the structure shown in FIG. 10. According to some embodiments of the present invention, the epitaxial region 62 includes silicon germanium, silicon, or silicon carbon. Depending on whether the final fin-type FET is a p-type fin-type FET or an n-type fin-type FET, the p-type or n-type impurities can be doped in situ as the epitaxial process is performed. For example, when the final fin field effect transistor is a p-type fin field effect transistor, silicon germanium boron (SiGeB), GeB, or the like can be grown. Conversely, when the final fin-type FET is an n-type fin-type FET, silicon-phosphorus (SiP), silicon-carbon-phosphorus (SiCP) or the like can be grown. According to other embodiments of the present invention, the epitaxial region 62 is formed of a group III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination of the foregoing, or the foregoing multiple layers. After the epitaxial region 62 completely fills the notch 60, the epitaxial region 62 starts to expand horizontally, and can form a multi-faceted surface.

After the epitaxial process, the epitaxial region 62 can be further implanted with p-type or n-type impurities to form a source/drain region, and the source/drain region is also marked with a reference symbol 62. According to other embodiments of the present invention, when the epitaxial region 62 is doped with p-type or n-type impurities in situ during the epitaxy period, the implantation process is omitted.

FIG. 11 shows a perspective view of the structure after forming a Contact Etch Stop Layer (CESL) 66 and an Inter-Layer Dielectric (ILD) 68. The contact etch stop layer 66 may be formed of silicon nitride, silicon carbide nitride, or the like. For example, the contact etch stop layer 66 can be formed by using a compliant deposition process, such as atomic layer deposition or chemical vapor deposition. The interlayer dielectric 68 may include a dielectric material formed by using flowable chemical vapor deposition, spin coating, chemical vapor deposition, or other deposition methods. The interlayer dielectric 68 may also be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as silicon oxide, Tetra Ethyl Ortho Silicate (TEOS) oxide, plasma-assisted chemical vapor deposition ( PECVD) Oxide (SiO ₂ ), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho -Silicate Glass, BPSG) or similar. A planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical polishing process) is performed to make the top surfaces of the interlayer dielectric 68, the dummy gate stack 46, and the gate spacer 54 flush with each other. When forming the interlayer dielectric 68, an annealing process can be used.

Then, in one or more etching processes, the dummy gate stack 46 including the hard mask 52, the dummy gate electrode 50 and the dummy gate dielectric 48 is etched to form portions on both sides of the gate spacer 54 The groove 70 between is as shown in Figure 12. The etching process can be performed using dry etching, for example.

Next, referring to FIG. 13A, a gate stack 72 is formed (replaced). The gate stack 72 includes a gate dielectric 74 and a (replaced metal) gate electrode 76. The formation of the gate stack 72 includes forming/depositing a plurality of layers, and then performing a planarization process, such as a chemical mechanical polishing process or a mechanical polishing process. The gate dielectric 74 extends into the trench 70 (Figure 12). According to some embodiments of the present invention, the gate dielectric 74 includes Interfacial Layers (ILs) as its lower part. The interface layer is formed on the exposed surface of the protruding fin 44. The interface layer may include an oxide layer, such as a silicon oxide layer. The gate dielectric 74 may also include a high-k dielectric layer formed above the interface layer. High-k dielectric layer may comprise a high k dielectric material, such as _{HfO 2, ZrO 2, HfZrO x} , HfSiO x, HfSiON, ZrSiO x, HfZrSiO x, Al 2 O 3, HfAlO x, HfAlN, ZrAlO x , La ₂ O ₃ , TiO ₂ , Yb ₂ O ₃ , silicon nitride or the like. The gate electrode 76 may include a plurality of layers, including a titanium silicon nitride (TSN) layer, a tantalum nitride (TaN) layer, a titanium nitride (TiN) layer, a titanium aluminum (TiAl) layer, additional TiN and/or TaN Layer and filler metal, but not limited to this. Some of these layers define the work function of the corresponding fin field effect transistor. Furthermore, the metal layer of the p-type fin field effect transistor and the metal layer of the n-type fin field effect transistor can be different from each other, so that the work function of the metal layer is suitable for the corresponding p-type fin field effect transistor or the n-type fin Type field effect transistor. The filler metal may include aluminum, copper, or cobalt. Therefore, a fin-type field effect transistor 80 is formed.

13B shows a schematic cross-sectional view of the fin field effect transistor 80, in which the gate stack 72 including the gate dielectric 74 and the gate electrode 76 overlaps the shallow trench isolation region 42 and directly contacts the silicon oxide layer 34'顶surface 34S. 13C shows a schematic cross-sectional view of the fin-type field effect transistor 80, in which the gate stack 72 including the gate dielectric 74 and the gate electrode 76 overlaps the shallow trench isolation region 42 and the dummy dielectric fin 45, and is in direct contact The top surface 34S of the silicon oxide layer 34'.

Figures 20-22 show perspective views of the intermediate stages of forming shallow trench isolation regions and fin-type field effect transistors according to other embodiments. These embodiments are similar to the embodiments previously shown in Figures 1, 2, 3A, 3B, 4, 5A, 5B, 6A, 6B, 6C, 7-12, 13A, 13B, and 13C, except that the entire shallow trench isolation region It is formed of a silicon oxide layer 34', and no isolation liner is formed. Unless otherwise specified, the materials and forming processes of the components in these embodiments are substantially the same as those of similar components, and these components are marked with reference symbols similar to those in the previous embodiments. Therefore, the details of the forming process and materials of the components shown in FIGS. 20-22 (and FIGS. 23-26) can be seen in the discussion of the previous embodiment.

The initial steps of these embodiments are roughly the same as those in FIGS. 1, 2, 3A, and 3B, in which a part of the dielectric layer 34 has been formed. The formation continues until the trench 31 is completely filled with the dielectric layer 34. Then, an annealing process (process 214 in FIG. 30) is performed to convert the deposited dielectric layer 34 into a silicon oxide layer 34', as shown in FIG. 20. The formation process of the silicon oxide layer 34' is substantially the same as that discussed in the previous embodiment, and will not be repeated here. The silicon oxide layer 34' fills the entire trench 31 (Figures 2, 3A, and 3B). As shown in FIG. 20, the top surface 34S' of the silicon oxide layer 34' is higher than the top surface of the mask layer 24. When forming the silicon oxide layer 34', the low-temperature annealing process can make water molecules penetrate into the dielectric layer 34, and the high-temperature annealing process makes the final dielectric layer 34 expand. Since the dielectric layer 34 will completely fill the trench 31 (Figure 3B), the portion of the dielectric layer 34 grown from the adjacent semiconductor strips 30 will eventually contact each other, and a gap can be formed therebetween. The high-temperature annealing process makes the portions where the dielectric layer 34 grows from the adjacent protruding semiconductor fins closely contact each other when the dielectric layer 34 expands. In the subsequent dry etching process, cross-linking is more effectively established, so that the dielectric layer 34 is cross-linked from the portion where the adjacent protruding semiconductor fin grows. Therefore, in the final portion of the silicon oxide layer 34' in the trench 31, there are substantially no gaps or voids.

Next, a planarization process is performed on the structure shown in FIG. 20, and a shallow trench isolation region 42 is formed. Therefore, the entire shallow trench isolation region 42 is formed by the silicon oxide layer 34'. Next, the shallow trench isolation region 42 is recessed, and a protruding fin 44 is formed on the top of the semiconductor strip 30, as shown in FIG. 21. Figure 22 shows the formation of the dummy gate stack 46. The subsequent manufacturing process is roughly the same as the structure shown in Figs. 8-12, 13A, 13B, and 13C, and is not repeated here. The resulting structure is also similar to that shown in Figures 13A, 13B, and 13C, except that the entire shallow trench isolation region 42 is formed of a homogenous silicon oxide layer 34' with a small amount of carbon (for example, less than about 1 atomic percent) in it.

Figures 23-26 show perspective views of the intermediate stages of forming shallow trench isolation regions and fin-type field effect transistors according to other embodiments. These embodiments are similar to the embodiments previously shown in Figures 1, 2, 3A, 3B, 4, 5A, 5B, 6A, 6B, 6C, 7-12, 13A, 13B, and 13C, except that the isolation liner is formed by deposition , And the silicon oxide layer 34' is formed on the isolation liner. The initial steps of these embodiments are roughly the same as in Figures 1 and 2. Next, as shown in FIG. 23, a silicon layer 32 may be formed (or may not be formed). Next, an isolation liner 35 is formed. The isolation liner 35 may be formed of silicon oxide formed by using atomic layer deposition, chemical vapor deposition, low pressure chemical vapor deposition, or the like. The isolation liner 35 can be formed of silicon oxide (as deposited) without undergoing transformation and annealing processes. The isolation liner 35 may also be formed of other materials, such as silicon nitride.

Next, as shown in FIG. 24, a silicon oxide layer 34' is formed on the isolation liner 35. The forming process is substantially the same as discussed in the previous embodiment, and is not repeated here. The silicon oxide layer 34' fills the entire remaining trench 31 (Fig. 23). As shown in FIG. 24, the top surface 34S' of the silicon oxide layer 34' is higher than the top surface of the mask layer 24. When forming the silicon oxide layer 34', the low-temperature annealing process can make water molecules penetrate into the dielectric layer 34, and the high-temperature annealing process makes the final dielectric layer 34 expand. This makes the compliant dielectric layers 34 grown from the protruding semiconductor fins come into close contact with each other, and makes the cross-linking in the subsequent dry annealing process more effective. Therefore, there are no gaps or voids in the final shallow trench isolation region 42 including the silicon oxide layer 34' and the isolation liner 35.

Next, a planarization process is performed on the structure shown in FIG. 24, and shallow trench isolation regions 42 are formed. Next, the shallow trench isolation region 42 is recessed, and a protruding fin 44 is formed on the top of the semiconductor strip 30, as shown in FIG. 25. Figure 26 shows the formation of the dummy gate stack 46. The subsequent manufacturing process is roughly the same as shown in Figures 8-12, 13A, 13B, and 13C, and will not be repeated here. The resulting structure is also similar to the structure shown in FIGS. 13A, 13B, and 13C, except that the shallow trench isolation region 42 includes an isolation liner 35 and an upper silicon oxide layer 34'. Furthermore, the silicon oxide layer 34' may have a small amount of carbon (for example, less than about 1 atomic percent) in it.

Figures 27, 28, and 29 are the experimental results obtained from the sample wafer, where the Y axis represents the signal intensities (quantities) of the elements Si, Ge, O, N, and C, which are represented by lines 150, 152, 154, 156 and 158 said. The X axis represents the different areas in the example. These examples are measured after the flowable chemical vapor deposition process and the annealing process to form the dielectric layer 40 (Figure 5B). Figure 27 shows the results obtained from the first example with a 17Å silicon layer 32 deposited by using low pressure chemical vapor deposition and a 30Å silicon oxide layer formed by using conventional low pressure chemical vapor deposition. The marked areas 140, 142, and 144 correspond to the semiconductor strip 30 (for example, FIG. 3B), the silicon layer 32, and the deposited silicon oxide layer, respectively. Figure 28 shows a silicon layer 32 with a 17Å deposited by low-pressure chemical vapor deposition and a dielectric layer 34 with a 30Å formed by using the process 206 of Figure 30 (including an atomic layer deposition cycle but no annealing process) The result of the second example. The marked areas 140, 142, and 146 correspond to the semiconductor strip 30 (for example, FIG. 3B), the silicon layer 32, and the dielectric layer 34 (FIG. 3A), respectively. Figure 29 shows the third from a silicon oxide layer 34' with a 17Å silicon layer 32 deposited using low pressure chemical vapor deposition and a 30Å silicon oxide layer 34' formed according to some embodiments of the present invention (including an atomic layer deposition cycle and annealing process). The result of the example. The marked areas 140, 142, and 148 correspond to the semiconductor strip 30 (e.g., Figure 3B), the silicon layer 32, and the silicon oxide layer 34' (Figure 5A), respectively. The second example is obtained after the dielectric layer 34 is formed and before the annealing process turns it into the silicon oxide layer 34', and the third example is obtained after the annealing process.

The thicknesses of the silicon layers in Figures 27, 28, and 29 are labeled T4, T5, and T6, respectively. It can be observed that the thickness T5 is equal to the thickness T6, which means that the thickness of the silicon layer 32 will not be reduced during the annealing process and subsequent flowable chemical vapor deposition. This proves that the dielectric layer 34 and the transformed silicon oxide layer 34' have good oxidation resistance, and can prevent the silicon layer 32 and the underlying semiconductor strip 30 (for example, SiGe, FIG. 3B) from being oxidized. In contrast, the thickness T4 (Figure 27) is less than the thickness T6, which means that the oxidation resistance of the silicon oxide layer formed by using traditional low pressure chemical vapor deposition is not as good as the dielectric layer 34 and the silicon oxide layer 34 in the embodiment of the present invention. 'Good job.

The embodiments of the present invention have some advantageous features. In the embodiment of the present invention, the shallow trench isolation region is formed by forming an SiOCN layer (which is also a SiOCNH layer) and converting the SiOCN layer into a silicon oxide layer. The SiOCN layer and the final silicon oxide layer formed according to the embodiment of the present invention are dense and have excellent oxidation resistance. Therefore, it is possible to eliminate or at least reduce the undesirable oxidation of the semiconductor strips caused by the formation of shallow trench isolation regions.

According to some embodiments of the present invention, the integrated circuit structure includes a bulk semiconductor region; the first semiconductor strip is above the bulk semiconductor region and connected to the bulk semiconductor region; the dielectric layer includes silicon oxide, in which carbon atoms are doped in the silicon oxide And wherein the dielectric layer includes: a horizontal portion above the top surface of the bulk semiconductor region and contacting the top surface of the bulk semiconductor region; and a vertical portion connected to the end of the horizontal portion, wherein the vertical portion contacts the lower portion of the first semiconductor strip Wherein the top of the first semiconductor strip protrudes higher than the top surface of the vertical portion to form a semiconductor fin; and the gate stack extends on the sidewall and top surface of the semiconductor fin. In one embodiment, the integrated circuit structure includes a dielectric layer with a carbon atom percentage of less than about 1%. In one embodiment, the integrated circuit structure includes the dielectric layer and further includes chlorine therein. In one embodiment, the integrated circuit structure further includes a dielectric region overlapping and contacting the horizontal portion, wherein the dielectric region includes silicon oxide and does not contain carbon therein. In one embodiment, the integrated circuit structure includes the top surface of the dielectric region protruding higher than the top surface of the vertical portion to form a dummy dielectric fin, and the gate stack further extends to the sidewall and top surface of the dummy dielectric fin . In one embodiment, the integrated circuit structure further includes a second semiconductor strip and a third semiconductor strip above the bulk semiconductor region and connecting the bulk semiconductor region; and the isolation region is between the second semiconductor strip and the third semiconductor strip The strips are in contact with the second semiconductor strip and the third semiconductor strip, wherein the entire isolation region is formed of the same homogeneous dielectric material as the dielectric layer, and the isolation region does not contain gaps therein.

According to some embodiments of the present invention, the integrated circuit structure includes a bulk semiconductor substrate; and the isolation region is above the bulk semiconductor substrate and contacts the bulk semiconductor substrate, wherein the isolation region includes: the dielectric liner includes silicon oxide, wherein the silicon oxide Carbon atoms are doped in the medium; and the dielectric region is filled in the region between the vertical portions on both sides of the dielectric liner, wherein the dielectric region includes silicon oxide and does not contain carbon therein. In one embodiment, the integrated circuit structure including the dielectric region further includes atoms selected from the group consisting of nitrogen atoms, chlorine atoms, and combinations of the foregoing. In one embodiment, the integrated circuit structure further includes a semiconductor strip having sidewalls contacting the dielectric pad, wherein the top of the semiconductor strip protrudes higher than the top surface of the isolation region to form a semiconductor fin. In one embodiment, the integrated circuit structure includes the isolation region and further includes a protruding portion above the dielectric region and connected to the dielectric region, and the protruding portion and the dielectric region are formed of the same dielectric material. In an embodiment, the integrated circuit structure further includes a semiconductor fin on one side of the isolation region, wherein the top surface of the protruding portion is substantially coplanar with the top surface of the semiconductor fin. In one embodiment, the integrated circuit structure further includes a contact etch stop layer above and in contact with the protruding area; and an interlayer dielectric overlapping and contacting the etch stop layer.

According to some embodiments of the present invention, a method includes etching a semiconductor substrate to form a trench; forming a first dielectric layer through an atomic layer deposition cycle, wherein the first dielectric layer extends into the trench, and wherein the atomic layer deposition cycle includes: Pulse hexachlorodisilane to the semiconductor substrate; remove hexachlorodisilane; after removing the hexachlorodisilane, pulse triethylamine to the semiconductor substrate; and remove triethylamine; perform an annealing process on the first dielectric layer; and A planarization process is performed on the first dielectric layer, wherein the remaining part of the annealed first dielectric layer forms a part of the isolation region. In one embodiment, the atomic layer deposition cycle further includes: after removing the triethylamine, _{pulsing oxygen (O 2} ) to the semiconductor substrate; and removing the oxygen. In one embodiment, the method further includes repeating an atomic layer deposition cycle including pulsed oxygen. In one embodiment, the annealing process includes: performing a low temperature wet annealing process at a first temperature; performing a high temperature wet annealing process at a second temperature higher than the first temperature; and performing dry annealing at a third temperature higher than the first temperature Process. In one embodiment, the method further includes forming a second dielectric layer above the first dielectric layer, wherein the method of forming the second dielectric layer is different from the method of forming the first dielectric layer. In one embodiment, flowable chemical vapor deposition is used to form the second dielectric layer. In one embodiment, the method further includes depositing the isolation liner to extend into the trench using a method different from forming the first dielectric layer before depositing the first dielectric layer. In one embodiment, the first dielectric layer fills the entire trench.

The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on the embodiments of the present invention, so as to achieve the same purpose and/or achieve the same purpose as the embodiments described herein. The same advantages. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Without departing from the spirit and scope of the invention, various changes, substitutions or modifications can be made to the embodiments of the invention.

10: Wafer 20, 20-1: base 20-2: Epitaxy semiconductor layer 22: Cushion 23: Interface 24: Mask layer 30: Semiconductor strip 31, 70: groove 31A: Narrow groove 31B: Wide groove 32: Silicon layer 34, 40: Dielectric layer 34S, 34S’, 42A: Top surface 34’: Silicon oxide layer 35: isolation liner 42: Shallow trench isolation area 44: protruding fins 45: dummy dielectric fin 46: dummy gate stack 48: dummy gate dielectric 50: dummy gate electrode 52: hard mask 54: Gate spacer 60: Notch 60A: bottom surface 62: Epitaxy zone 66: Contact etch stop layer 68: Interlayer dielectric 72: Gate stack 74: gate dielectric 76: gate electrode 80: fin field effect transistor 110: basal layer 112, 114, 116, 118: structure 136, 138: Atomic layer deposition cycle 140, 142, 144, 146, 148: area 150, 152, 154, 156, 158: line 200: Process flow 130, 132, 134, 202, 204, 205, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224: process T1, T2, T3, T4, T5, T6: thickness W1, W2: width

The embodiments of the present invention can be better understood according to the following detailed description and the accompanying drawings. It should be noted that, according to the standard practice of this industry, the various features in the illustration are not necessarily drawn to scale. In fact, it is possible to arbitrarily enlarge or reduce the size of various components to make a clear description. Figures 1, 2, 3A, 3B, 4, 5A, 5B, 6A, 6B, 6C, 7-12, 13A, 13B, and 13C show the formation of shallow trench isolation (STI) regions and fin field effects according to some embodiments The perspective view and cross-sectional schematic diagram of the intermediate stage of the transistor (FinFET). FIG. 14 shows an Atomic Layer Deposition (ALD) cycle for forming a SiNOC film according to some embodiments. Figure 15 shows an intermediate structure formed by a plurality of atomic layer deposition cycles according to some embodiments. Figure 16 shows a schematic structure after performing a low temperature wet annealing process and a high temperature wet annealing process according to some embodiments. Figure 17 shows a schematic chemical structure of silicon oxide after a dry annealing process according to some embodiments. Figures 18 and 19 respectively show the chemical structure of hexachlorodisilane (HCD) and the symbol of triethylamine (triethylamine) according to some embodiments. FIGS. 20-22 are perspective views of an intermediate stage of forming shallow trench isolation regions and fin-type field effect transistors according to some embodiments. FIGS. 23-26 are perspective views of intermediate stages of forming shallow trench isolation regions and fin-type field effect transistors according to some embodiments. Figures 27-29 show some experimental results according to some examples. FIG. 30 shows a process flow of forming shallow trench isolation regions and fin-type field effect transistors according to some embodiments.

20: Base

30: Semiconductor strip

40: Dielectric layer

34S: Top surface

34’: Silicon oxide layer

42: Shallow trench isolation area

44: protruding fins

66: Contact etch stop layer

68: Interlayer dielectric

72: Gate stack

74: gate dielectric

76: gate electrode

80: fin field effect transistor

Claims (14)

An integrated circuit structure includes: a block-shaped semiconductor region; a first semiconductor strip above the block-shaped semiconductor region and connected to the block-shaped semiconductor region; a dielectric layer including silicon oxide, in which carbon atoms are doped In silicon oxide, and wherein the dielectric layer includes: a horizontal portion above and in contact with the top surface of the bulk semiconductor region; and a vertical portion connecting the ends of the horizontal portion, Wherein the vertical part contacts the sidewall of the lower part of the first semiconductor strip, wherein the top of the first semiconductor strip protrudes higher than the top surface of the vertical part to form a semiconductor fin; a dielectric region overlaps and contacts the horizontal Part, wherein the dielectric region includes silicon oxide and does not contain carbon therein, wherein the top of the dielectric region protrudes higher than the top surface of the vertical portion to form a dummy dielectric fin; and a gate stack extending On the sidewall and top surface of the semiconductor fin. According to the integrated circuit structure described in claim 1, wherein the gate stack further extends to the sidewall and top surface of the dummy dielectric fin. The integrated circuit structure described in item 1 or 2 of the scope of the patent application further includes: a second semiconductor strip and a third semiconductor strip, which are above and connected to the bulk semiconductor region; and An isolation region between the second semiconductor strip and the third semiconductor strip and in contact with the second semiconductor strip and the third semiconductor strip, wherein the entire isolation region is composed of the same dielectric layer The homogeneous dielectric material is formed, and the isolation region does not contain gaps therein. An integrated circuit structure, including: A bulk semiconductor substrate; and an isolation region above and in contact with the bulk semiconductor substrate, wherein the isolation region includes: a dielectric liner including silicon oxide, wherein carbon is doped in the silicon oxide Atoms; and a dielectric region filled in a region between the vertical portions on both sides of the dielectric pad, wherein the dielectric region includes silicon oxide, and does not contain carbon in which, wherein the isolation region further includes a protrusion Part is above and connected to the dielectric region. The integrated circuit structure described in item 4 of the scope of patent application further includes a semiconductor strip having a sidewall contacting the sidewall of the dielectric pad, wherein the top of the semiconductor strip protrudes higher than the top surface of the isolation region, To form a semiconductor fin. The integrated circuit structure described in item 4 or 5 of the scope of the patent application, wherein the protruding portion and the dielectric region are formed of the same dielectric material. The integrated circuit structure described in item 6 of the scope of the patent application further includes a semiconductor fin on one side of the isolation region, wherein the top surface of the protruding portion is substantially coplanar with the top surface of the semiconductor fin. A manufacturing method of an integrated circuit structure includes: etching a semiconductor substrate to form a trench; forming a first dielectric layer through an atomic layer deposition cycle, wherein the first dielectric layer extends into the trench, and The atomic layer deposition cycle includes: pulsing hexachlorodisilane to the semiconductor substrate; removing hexachlorodisilane; after removing hexachlorodisilane, pulsing triethylamine to the semiconductor substrate; and removing triethylamine; Performing an annealing process on the first dielectric layer; A second dielectric layer is formed above the annealed first dielectric layer. The second dielectric layer is filled in an area between the two vertical portions of the first dielectric layer. The second dielectric layer It includes silicon oxide and does not contain carbon, and the second dielectric layer further includes a protruding portion above the area and connected to the area; and flattening the first dielectric layer and the second dielectric layer Chemical process, wherein the annealed remaining part of the first dielectric layer and the second dielectric layer forms an isolation region. According to the manufacturing method of the integrated circuit structure described in item 8 of the scope of the patent application, the atomic layer deposition cycle further includes: after the triethylamine is removed, oxygen is pulsed to the semiconductor substrate; and the oxygen is removed. The manufacturing method of the integrated circuit structure described in item 9 of the scope of the patent application further includes repeating the atomic layer deposition cycle including pulsed oxygen. According to the manufacturing method of the integrated circuit structure described in item 8 or 9 of the scope of patent application, the annealing process includes: performing a low temperature wet annealing process at a first temperature; and at a second temperature higher than the first temperature Performing a high temperature wet annealing process; and performing a dry annealing process at a third temperature higher than the first temperature. According to the manufacturing method of the integrated circuit structure described in item 8 or 9 of the scope of patent application, the method of forming the second dielectric layer is different from the method of forming the first dielectric layer. The manufacturing method of the integrated circuit structure as described in item 8 or 9 of the scope of the patent application further includes depositing an isolation liner extension using a method different from forming the first dielectric layer before depositing the first dielectric layer Into the groove. According to the manufacturing method of the integrated circuit structure described in item 8 or 9 of the scope of patent application, the first dielectric layer fills the entire trench.

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