TWI622151B - Carrier substrate for semiconductor packaging and package structure thereof, and method for fabricating semiconductor package - Google Patents

Abstract

A carrier substrate for a semiconductor package includes a carrier sheet, a substrate, and a reinforcement layer. The base body is disposed on the carrier sheet and includes a line area and a non-line area located outside the line area. The reinforcing layer is disposed on the non-line area, wherein the reinforcing layer reverses a top surface of the carrier sheet higher than the line area to reverse a surface of the carrier sheet. The present invention also provides a semiconductor package structure having the aforementioned carrier substrate, and a method of fabricating the semiconductor package component.

Description

Carrier substrate for semiconductor package and package structure thereof, and method for fabricating semiconductor package component

The present invention relates to a semiconductor package substrate and a method of fabricating the same, and more particularly to a carrier substrate for a semiconductor package, a semiconductor package structure, and a method of fabricating the semiconductor package device.

Existing electronic products are gradually becoming more versatile, high-performance, and miniaturized. In order to meet the high-density density and miniaturized package, the structure of a carrier substrate used in the packaging process gradually evolves from a two-layer substrate to a multi-layer substrate. To expand the available area in a limited space; or to further develop a circuit-growth technique to stack multiple layers of dielectric layers or circuit layers to improve wiring precision; or, to integrate three-dimensional stacking of wafers into three dimensions Related packaging technologies such as structured wafer stack packaging are becoming increasingly important.

In the foregoing packaging process, it is often required to form a substrate having a wiring layer and a solder resist layer on a temporary carrier substrate, and then mounting a wafer on the substrate and a package encapsulating the wafer. Subsequently, The carrier substrate having the wafer is subjected to a subsequent electrical connection by stripping the temporary carrier substrate. However, when the carrier substrate is stripped, the thickness of the outer periphery of the substrate is often thin (about 40 um). It is easy to be stripped together with the carrier substrate, but generally the outer periphery of the substrate is often used as a fixture for a subsequent process to be clamped or fixed. Therefore, if the outer periphery of the substrate is along with the carrier substrate The stripping is likely to cause subsequent processing such as ball placement and singulation of the wafer, and there is no post-flow transfer problem due to the absence of the clamping zone.

Accordingly, it is an object of the present invention to provide a carrier substrate having a reinforced structure for use in a semiconductor package.

Therefore, the carrier substrate for a semiconductor package of the present invention comprises a carrier sheet, a substrate, and a reinforcing layer.

The base body is disposed on the carrier sheet and includes a line area and a non-line area located outside the line area. The strengthening layer is disposed on the non-line area. In the present invention, the reinforcing layer reverses a top surface of the carrier sheet above the line region and reverses a surface of the carrier sheet.

Further, another object of the present invention is to provide a semiconductor package structure.

Therefore, the semiconductor package structure comprises a carrier substrate for the semiconductor package, at least one wafer, and an encapsulant. The at least one wafer is electrically connected to the line region. The encapsulant covers a portion of the line region and encapsulates the wafer.

It is still another object of the present invention to provide a method of fabricating a semiconductor package component.

Thus, the method of fabricating the semiconductor package component includes a preparation step, a transfer step, a reinforcement layer formation step, and a conductive layer removal step.

The preparation step prepares a carrying unit, the carrying unit includes a first carrier sheet, a conductive layer on the first carrier sheet, and a base body on the conductive layer, the base body includes a line area, and a The non-line area on the outside of the line area.

The transferring step connects the substrate opposite to a surface of the first carrier sheet to a second carrier sheet, and removes the first carrier sheet to expose the conductive layer.

The strengthening layer forming step forms a strengthening layer on the conductive layer of the non-line region such that a top surface of the reinforcing layer opposite to the second carrier sheet is higher than a surface of the second carrier sheet opposite to the substrate.

The conductive layer removing step removes a portion of the conductive layer on which the reinforcing layer is not formed, exposing the surface of the wiring region.

The effect of the present invention is to enhance the structural strength of the non-line region of the substrate by providing a reinforcing layer having a thickness higher than the line region in the non-line region, so that the substrate can be made when the carrier sheet is peeled off. The non-wire region of the substrate has sufficient structural strength resistance and is not stripped with the carrier sheet.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 1 , a first embodiment of a carrier substrate 2 for a semiconductor package includes a carrier 21 , a substrate 22 disposed on the carrier 21 , and a reinforcement layer 23 disposed on the substrate 22 . And a conductive layer 24 between the substrate 22 and the reinforcing layer 23.

Specifically, the substrate 22 includes a solder resist layer 221 and a circuit layer 222. The solder resist layer 221 has an inner solder resist portion 223 defining a line space 220, and a solder mask portion 223 outside the inner solder resist portion 223. The outer soldering portion 224 is formed in the line space 220. The inner soldering portion 223 and the circuit layer 222 together form a line region A, and the outer soldering portion 224 constitutes a non-line region B. The line area A is mainly used for the subsequent connection and packaging of the external wafer, and the non-line area B is used to assist the carrier substrate 2 in performing the transfer and peeling of the carrier sheet 21.

The conductive layer 24 is formed on the outer soldering portion 224. The reinforcing layer 23 is disposed on the conductive layer 24 and located in the non-line region B, and a top surface 231 of the reinforcing layer 23 is higher than the inner solder mask portion. A surface 225 of the carrier sheet 21 is reversed from 223. Since the thickness of the substrate 22 is generally extremely thin (only about 40 to 50 um), the present invention increases the overall thickness of the non-line region B by using the reinforcing layer 23 by providing the reinforcing layer 23 on the non-line region B. The structural strength of the non-line region B is enhanced. Therefore, when the substrate 22 needs to be peeled off from the carrier sheet 21 in a subsequent process, the outer soldering portion 224 located in the non-line region B can be provided by the reinforcing layer 23. Sufficient structural strength is resisted without being stripped with the carrier sheet 21. Preferably, in this embodiment, the height of the reinforcing layer 23 is greater than 20 μm, and the width is not less than 25 μm, and the reinforcing layer 23 and the conductive layer 24 suitable for the embodiment may be made of a metal material such as copper. Therefore, the strengthening layer 23 can be formed on the conductive layer 24 by electroplating, and the related manufacturing process will be described later.

Referring to FIG. 2, a second embodiment of the carrier substrate 2 for a semiconductor package of the present invention is substantially the same as the first embodiment, except that the outer solder resist portion 224 has a recessed structure in the embodiment. A conductor layer 25 is formed in the recess structure. The conductor layer 25 has a top surface 251 that is flush with a surface 226 of the outer solder resist 224, so that the reinforcing layer 23 can be directly formed on the conductor layer 25. On, the relevant production process is explained later.

Referring to FIG. 3, a third embodiment of the carrier substrate 2 for a semiconductor package of the present invention is substantially the same as the first embodiment, except that the reinforcing layer 23 is made of a non-metal material and directly formed thereon. On the outer soldering portion 224. In detail, in the present embodiment, the reinforcing layer 23 is made of a molding material such as an insulating polymer, and the reinforcing layer 23 can be formed directly on the outer solder portion 224 by a stamping method instead of the plating process. The reinforcing layer 23 is formed separately on the outer soldering portion 224. However, in actual production, the reinforcing layer 23 can be integrally formed with the encapsulating layer for subsequently packaging the wafer, and the related manufacturing process will be described later.

The carrier substrate 2 of the present invention is applicable to a semiconductor chip package to obtain a semiconductor package structure, and the semiconductor obtained by using the carrier substrate 2 of the first to third embodiments described above for semiconductor chip packaging will be described in the following embodiments. Package structure.

Referring to FIG. 4, a first embodiment of the semiconductor package structure 3 of the present invention includes the carrier substrate 2 of the first embodiment, and a wafer 31 formed on the line region A and electrically connected to the circuit layer 222. And an encapsulant 32 covering the portion of the line region A and covering the wafer 31 and having a height greater than the reinforcing layer 23, and spacing the encapsulant 32 and the reinforcing layer 23 to each other to have a spacing D, so as to follow The periphery of the base 22 of the outer encapsulant 32 can be easily performed. It should be noted that the materials of the wafer 31 and the encapsulant 32 which are suitable for the present embodiment are selected by those skilled in the art, and are not the focus of the present invention, and will not be further described herein.

Referring to FIG. 5, a second embodiment of the semiconductor package structure 3 of the present invention is substantially the same as the first embodiment, except that the semiconductor package structure 3 of the present embodiment is the same as the second embodiment. The carrier substrate 2, that is, the conductor layer 25 is a recessed structure formed in the outer solder mask 224 such that the conductor layer 25 is equal to the surface 226 of the outer solder resist 224.

Referring to FIG. 6, a third embodiment of the semiconductor package structure 3 of the present invention is substantially the same as the first embodiment, except that the semiconductor package structure 3 of the present embodiment is the same as the third embodiment. The substrate 2 is carried, and the encapsulant 32 and the reinforcing layer 23 are made of the same material and are integrally connected to each other and completely covered on the substrate 22.

In order to more clearly illustrate the structure of the embodiments, a fabrication flow of such embodiments of the semiconductor package structure is further described below.

Referring to FIG. 7 and FIG. 8, the first embodiment of the semiconductor package structure of the present invention includes a preparation step 401, a transfer step 402, a enhancement layer formation step 403, a conductive layer removal step 404, and a wafer. Step 405, a packaging step 406, and a carrier removal step 407 are provided.

The preparation step 401 is to prepare a carrier unit 41. Specifically, the carrier unit 41 is first provided with a first carrier sheet 411 having a conductive layer 24 on one surface thereof, wherein the first carrier sheet 411 is provided. It may be a general metal printed circuit board (MCPCB), a copper foil substrate (CCL), or a glass fiber substrate (FR4), and the conductive layer 24 may be the copper foil on the substrate. It should be noted that the opposite surfaces of the first carrier sheet 411 can also have the conductive layer 24 at the same time, and the double-sided electrical connection lines can be formed in the same process, and are used in subsequent processes. In this embodiment, the conductive layer is used. 24 is formed on one of the surfaces as an example. Then, a photoresist is formed on the conductive layer 24, and part of the photoresist is removed by exposure and development to expose a portion of the conductive layer 24, and the exposed conductive layer 24 is electroplated on the wiring layer 222. Finally, a portion of the circuit layer 222 is covered with a photoresist such that the photoresist resists the solder resist layer 221, and the wiring layer 222 and the solder resist layer 221 together form the substrate 22, and the substrate The line area A is defined on 22, and the non-line area B located outside the line area A.

The transferring step 402 is to connect the surface of the substrate 22 opposite to the first carrier sheet 411 to a second carrier sheet 412, and remove the first carrier sheet 411 to expose the conductive layer 24 completely.

The strengthening layer forming step 403 is performed by plating a thick copper structure on the conductive layer 24 corresponding to the non-line region B to obtain the reinforcing layer 23.

The conductive layer removing step 404 is to remove a portion of the conductive layer 24 on which the reinforcing layer 23 is not formed, so that the surface 225 of the wiring region A is exposed to obtain the carrier substrate 2 as shown in FIG. .

The wafer setting step 405 is then performed to electrically connect the wafer 31 to the line region 222 of the carrier substrate 2.

The encapsulating step 406 covers a portion of the line region A with an insulating polymer material to coat the wafer 31 to obtain the semiconductor package structure 3 of FIG.

Finally, the carrier removal step 407 is further performed to peel off the second carrier sheet 412 connected to the substrate 22, so that the circuit layer 222 that is opposite to the portion of the wafer 31 is exposed, and at the same time the exposed portion A conductive portion 413 capable of external electrical connection, such as a conductive bump or a conductive post, is formed on the wiring layer 222 to obtain a semiconductor package component 4.

After the semiconductor package component 4 is obtained, the portion of the substrate 22 located in the non-line region B may be further removed along the periphery of the encapsulant 32 (not shown), and the subsequent process or application may be performed as needed.

Since the reinforcing layer 23 having the thickness enhancement is provided in the non-line region B, the structural strength of the periphery of the substrate 22 is enhanced, so that the non-line region B of the substrate 22 can be made when the second carrier sheet 412 is peeled off. It will not be removed with the peeling of the second carrier sheet 412, and the subsequent process can be easily continued.

Referring to FIG. 9 and FIG. 10, the manufacturing method of the second embodiment of the semiconductor package structure of the present invention is substantially the fabrication method of the first embodiment of the same semiconductor package structure, and the difference is that the preparation step 401 and the implementation For example, the conductive layer removing step 404 is performed first, and then the strengthening layer forming step 403 is performed. In detail, in the embodiment, the preparation step 401 removes a portion of the photoresist by exposure and development to expose a portion of the conductive layer 24, and simultaneously allows the conductive layer 24 on the outer periphery of the first carrier sheet 411. Exposed, so that the conductive layer 24 is plated on the exposed conductive layer 24, and the conductor layer 25 having the same height as the circuit layer 222 is formed on the outer periphery; after the transfer step 402 is completed, The conductive layer removal step 404 is performed to remove the exposed conductive layer 24 while leaving the outer peripheral edge of the conductor layer 25 in the non-line region B (see FIG. 8), and then in the reinforcement layer formation step 403 The strengthening layer 23 can be directly plated on the conductor layer 25 of the non-line region B. Therefore, after the wafer setting step 405, the packaging step 406, and the carrier removal step 407, the semiconductor can be obtained. Package component 4.

Referring to FIG. 11 and FIG. 12, the manufacturing method of the third embodiment of the semiconductor package structure of the present invention is substantially the fabrication method of the first embodiment of the same semiconductor package structure, and the difference is that the enhancement layer is in this embodiment. The forming step 403 is integrated in the encapsulating step 406. That is, after performing the transferring step 402, the third embodiment proceeds to perform the conductive layer removing step 404 and the wafer setting step 405, and after setting the wafer. When the encapsulating step 406 is performed, the insulating polymer material is integrally molded to cover the wafer 31, and the insulating polymer material is extended to the periphery to cover the surface of the substrate 22, and the non-line is The reinforcing layer 23 having the same material as the encapsulant 32 is formed at the region B (see FIG. 8). In other words, in the embodiment, the reinforcing layer 23 is formed by replacing the metal material with a molding material instead of using the copper plating process. This strengthening layer 23 is formed.

In summary, the carrier substrate 2 for a semiconductor package of the present invention enhances the structure of the non-line region B of the substrate 22 by providing the reinforcing layer 23 having a thickness higher than the line region A in the non-line region B. The strength can prevent the non-line region B of the base 22 from having sufficient structural strength resistance when the base 22 is peeled off, so that the non-line region B is not removed with the peeling of the carrier sheet 21, so The object of the invention can indeed be achieved.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the simple equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still Within the scope of the invention patent.

2‧‧‧Semiconductor package substrate
21‧‧‧ Carrying film
22‧‧‧ base
220‧‧‧ line space
221‧‧‧ solder mask
222‧‧‧Line layer
223‧‧‧Internal welding department
224‧‧‧External welding department
32‧‧‧Package
4‧‧‧Semiconductor package components
41‧‧‧ Carrying unit
401‧‧‧Preparation steps
402‧‧‧Transfer steps
403‧‧‧ Strengthening layer formation steps
404‧‧‧ Conductive layer removal steps
405‧‧‧ wafer setup steps
225‧‧‧ surface
226‧‧‧ surface
23‧‧‧ Strengthening layer
231‧‧‧ top surface
24‧‧‧ Conductive layer
25‧‧‧Conductor layer
251‧‧‧ top surface
3‧‧‧Semiconductor package structure
31‧‧‧ wafer
406‧‧‧Packaging steps
407‧‧‧ Carrier removal steps
411‧‧‧First carrier
412‧‧‧Second carrier
413‧‧‧Electrical Department
A‧‧‧ line area
B‧‧‧Non-line area
D‧‧‧ spacing

Other features and advantages of the present invention will be apparent from the embodiments of the present invention, wherein: FIG. 1 is a partial cross-sectional view illustrating a first embodiment of a carrier substrate for a semiconductor package of the present invention; 2 is a partial cross-sectional view showing a second embodiment of the carrier substrate for a semiconductor package of the present invention; FIG. 3 is a partial cross-sectional view showing a third embodiment of the carrier substrate for a semiconductor package of the present invention; 4 is a partial cross-sectional view showing a first embodiment of the semiconductor package structure of the present invention; FIG. 5 is a partial cross-sectional view showing a second embodiment of the semiconductor package structure of the present invention; FIG. 6 is a partial cross-sectional view illustrating A third embodiment of the semiconductor package structure of the present invention; FIG. 7 is a schematic flow chart showing the manufacturing method of the first embodiment of the semiconductor package structure of the present invention and a carrier removal step; FIG. A fabrication flow of the first embodiment of the semiconductor package structure of the present invention is illustrated; FIG. 9 is a flow diagram illustrating The manufacturing method of the second embodiment of the semiconductor package structure and the carrier removal step; FIG. 10 is a schematic view of the fabrication process, illustrating the fabrication process of the second embodiment of the semiconductor package structure of the present invention; FIG. 12 is a flow chart showing the fabrication of the third embodiment of the semiconductor package structure of the present invention; and FIG. 12 is a schematic view showing the fabrication of the third embodiment of the semiconductor package structure of the present invention. Process.

Claims (14)

A carrier substrate for a semiconductor package, comprising: a carrier sheet that can be removed; a substrate disposed on the carrier sheet and including a line region and a non-line region located outside the line region; and And a reinforcing layer disposed on the non-line area; wherein the reinforcing layer reverses a top surface of the carrier sheet higher than the line area to reverse a surface of the carrier sheet. The carrier substrate for a semiconductor package according to claim 1, wherein the substrate comprises a solder resist layer and a circuit layer, the solder resist layer having an inner solder resist portion defining a line space, and an outer layer In the solder resist portion, the circuit layer is formed in the line space, the inner solder resist portion and the circuit layer together constitute the line region, and the outer solder resist portion constitutes the non-line region. The carrier substrate for a semiconductor package according to claim 2, further comprising a conductive layer disposed on the outer solder mask, the reinforcing layer being disposed on the conductive layer. The carrier substrate for a semiconductor package according to claim 3, wherein the outer solder mask is opposite to a surface of the carrier sheet opposite to the circuit layer by a surface of the carrier sheet. The carrier substrate for a semiconductor package according to claim 3, wherein the conductive layer is opposite to a surface of the carrier sheet opposite to the circuit layer by a surface of the carrier sheet. The carrier substrate for a semiconductor package according to claim 3, wherein the reinforcing layer and the conductive layer are made of a metal. The carrier substrate for a semiconductor package according to claim 2, wherein the reinforcing layer is disposed on the outer solder mask, and the reinforcing layer is made of an insulating polymer material. A semiconductor package structure comprising: a carrier substrate for a semiconductor package according to any one of claims 1 to 7; at least one wafer electrically connected to the line region; and an encapsulant covering a portion of the line region And coating the wafer. The semiconductor package structure of claim 8, wherein the reinforcement layer and the encapsulant are spaced apart from each other. The semiconductor package structure of claim 8, wherein the reinforcing layer and the encapsulant are connected to each other. A manufacturing method of a semiconductor package component, comprising: a preparation step of preparing a carrier unit, the carrier unit comprising a first carrier sheet, a conductive layer on the first carrier sheet, and a substrate on the conductive layer, The substrate includes a line region and a non-line region located outside the circuit region; a transfer step of connecting the substrate to a surface of the first carrier sheet to a second carrier and removing the first a carrier sheet exposing the conductive layer; a strengthening layer forming step of forming a strengthening layer on the conductive layer of the non-line region, such that the reinforcing layer is reversed from a top surface of the second carrier sheet higher than the substrate To a surface of the second carrier sheet; and a conductive layer removing step, removing a portion of the conductive layer on which the reinforcing layer is not formed to expose the surface of the wiring region. The method for fabricating a semiconductor package component according to claim 11, further comprising a wafer setting step performed after the conductive layer removing step, electrically connecting at least one of the wafers to the wiring region. The method of fabricating a semiconductor package component according to claim 12, further comprising a packaging step performed after the step of disposing the wafer, covering a portion of the wiring region with an insulating polymer material and coating the wafer. The method for fabricating a semiconductor package component according to claim 13, further comprising a carrier removal step performed after the packaging step, removing the second carrier sheet attached to the substrate.