TWI622150B - Electronic device package and circuit layout structure - Google Patents

Abstract

The invention discloses an electronic package component and a circuit layout structure. The electronic package member has a plurality of ground solder balls and a plurality of signal solder balls corresponding to an array of arrangement points. The configuration point array includes a plurality of grounding configuration points for carrying ground solder balls, a plurality of signal configuration points for carrying signal solder balls, and a plurality of vacancy configuration points. Configuring a dot array by a plurality of the grounding configuration points, a plurality of the signal configuration points, and a plurality of the vacancy arrangement points arranged in m columns along a first direction and n rows along a second direction The outermost row 1 of the arrangement point array or the plurality of ground configuration points in the first column are alternately arranged with the plurality of vacancy configuration points.

Description

Electronic package component and circuit layout structure

The present invention relates to an electronic package member and a circuit layout structure, and more particularly to an electronic package member and a circuit layout structure using the ball grid array package technology.

The integrated circuit package member formed by the ball grid array packaging technique is provided with an array of solder ball pads on the bottom surface. In addition, the board typically includes a plurality of pads corresponding to the array of solder ball pads and a plurality of traces respectively connected to the pads. When the integrated circuit package member is mounted on the circuit board, the integrated circuit package member is soldered to the corresponding pad through the solder ball pad, and is connected to the circuit board by a plurality of traces connecting the pads. Other components establish signal connections.

In general, some of the solder ball pads are grounded by a trace to provide ground shielding for other traces and solder ball pads for transmitting signals, thereby making the integrated circuit package components and other components It has better signal transmission quality. As the size of the integrated circuit package member becomes smaller and smaller, the number of pads of the board set per unit area is also increasingly dense.

Although the pads and traces are located on the same layer of the board, the signal transmission loss or signal coupling can be reduced, but because the distance between the plurality of pads disposed on the board is smaller and smaller, Only pads located on the first or second turn of the outermost edge of the pad array can be connected directly to another component through the same layer of traces. Other pads located inside the pad array must be connected to another component through conductive vias and traces placed on the inner or bottom layer of the board.

When the integrated circuit package component transmits signals through the lower layer traces, the traces located on the lower layer and used for transmitting signals are difficult to achieve a complete ground shield, thereby meeting the requirements of high frequency signal transmission.

The technical problem to be solved by the present invention is to provide an electronic package component and a circuit layout structure for the deficiencies of the prior art, which can increase the line space usage rate of the circuit board and take into account the signal transmission quality.

In order to solve the above technical problem, one of the technical solutions adopted by the present invention is to provide an electronic package member having a plurality of ground solder balls and a plurality of signal solder balls corresponding to an array of arrangement points. The configuration point array includes a plurality of grounding configuration points for carrying ground solder balls, a plurality of signal configuration points for carrying signal solder balls, and a plurality of space configuration points, wherein the configuration point array is configured by multiple grounding configuration points and multiple signals The dot and the plurality of vacancy arrangement points are arranged in m rows along a first direction and n rows along a second direction, and are located in a first row or a first column of the outermost side of the array of arrangement points The grounding configuration point is alternately disposed with a plurality of the vacancy configuration points.

Another technical solution adopted by the present invention is to provide a circuit layout structure formed in a circuit board to match the electronic package member. The circuit layout structure comprises an array of pads, the pad array is disposed on a surface of one of the pads, the pad array comprises a plurality of ground pads, a plurality of signal pads and a plurality of padless regions . The pad array is composed of a plurality of ground pads, a plurality of signal pads and a plurality of pad-free regions arranged in a m row along a first direction and n rows along a second direction, and located in the pad A plurality of the ground pads and a plurality of the padless regions in the outermost first row or the first column of the array are alternately disposed.

One of the beneficial effects of the present invention is that the electronic package member and circuit layout structure provided by the present invention can be configured by "a plurality of grounding arrangements in at least the outermost row or the outermost column of the ball grid array of the electronic package member" The technical solution of alternately setting points with multiple vacancy configuration points, so that the corresponding ball grid array on the circuit board The pad array and each signal line can be completely shielded by the ground line.

For a better understanding of the features and technical aspects of the present invention, reference should be made to the accompanying drawings.

1‧‧‧Electronic package components

10‧‧‧Ball ball configuration area

100‧‧‧Configure point array

100S‧‧‧ signal configuration point

100G‧‧‧ Grounding configuration point

100R‧‧‧ Vacancy configuration point

110G‧‧‧Ground solder ball

110S‧‧‧Signal solder balls

N1‧‧‧ first line configuration point group

N2‧‧‧ second line configuration point group

M1‧‧‧lower wiring configuration point group

M2‧‧‧lower wiring configuration point group

2‧‧‧ boards

20‧‧‧pad configuration area

20A‧‧‧ surrounding area

20B‧‧‧Internal area

200‧‧‧Circuit layout structure

210‧‧‧pad array

A1‧‧‧Top-level wiring pad group

A2‧‧‧lower wiring pad group

210G‧‧‧Ground pad

210S‧‧‧ Signal pad

210R‧‧‧No pad area

L1‧‧‧ top layer

L2‧‧‧lower circuit layer

S1‧‧‧first signal line

G1‧‧‧First grounding line

S2‧‧‧second signal line

G2‧‧‧Second grounding line

D1‧‧‧ first direction

D2‧‧‧ second direction

1 is a partial bottom plan view of an electronic package member according to an embodiment of the invention.

2 is a top plan view showing a circuit layout structure according to an embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a partial top plan view of an electronic package member according to an embodiment of the invention. The electronic package component 1 of the present embodiment is formed by a semiconductor wafer through a ball grid array encapsulation technique, wherein the semiconductor wafer may be an integrated circuit wafer, a dynamic random memory wafer or other semiconductor components.

The bottom of the electronic package member 1 has a solder ball arrangement area 10, and the solder ball arrangement area 10 has an array of arrangement points 100 therein. In addition, the electronic package member 1 has a ball grid array (not labeled), and the ball grid array includes a plurality of ground balls 110G corresponding to the arrangement point array 100 and a plurality of signal solder balls 110S. After the electronic package member 1 is disposed on the circuit board, the ground ball 110G of the electronic package member 1 is electrically grounded.

In this embodiment, the configuration point array 100 includes a plurality of signal configuration points 100S for carrying the signal solder balls 110S, a plurality of ground configuration points 100G for carrying the ground solder balls 110G, and a plurality of vacancy configuration points 100R. It should be noted that, in the embodiment of the present invention, no solder balls are disposed on the vacancy arrangement point 100R.

In addition, as shown in FIG. 1 , the arrangement point array 100 is a matrix array, and is arranged by a plurality of ground arrangement points 100G, a plurality of signal arrangement points 100S, and a vacancy arrangement point 100R along a m column and along a first direction D1. A n line of a second direction D2 is drawn. In other words, the configuration point array 100 includes m×n configuration points.

In the present embodiment, the plurality of ground arrangement points 100G located in the outermost first row or the first column of the arrangement point array 100 are alternately arranged with the plurality of vacancy arrangement points 100R. In the embodiment of FIG. 1, the display is located at the outermost side of the array of configuration points 100. The arrangement of the plurality of ground arrangement points 100G and the plurality of vacancy arrangement points 100R in the first column (m=1) will be described. In other words, in the arrangement point array 100 of the present embodiment, in the outermost first column, a part of the position is not provided with any solder balls. Further, in the outermost first column (m=1) of the arrangement point array 100, one vacancy arrangement point 100R is provided between every two adjacent ground arrangement points 100G.

Therefore, the peripheral contour of the ball grid array (excluding the vacancy arrangement point 100R) of the present embodiment has a waveform structure. It is worth mentioning that a plurality of signal configuration points 100S and a plurality of vacancy configuration points 100R in the outermost second column (m=2) of the arrangement point array 100 are also alternately arranged. As shown in FIG. 1, a vacancy arrangement point 100R is provided between every two adjacent signal arrangement points 100S in the second outermost column (m=2) of the arrangement point array 100.

Further, one of the vacancy arrangement points 100R located in the outermost first column (m=1) of the arrangement point array 100 and one vacancy arrangement point located in the outermost second column (m=2) of the arrangement point array 100 The 100R bits are on the same line. In other words, in the present embodiment, the plurality of vacancy arrangement points 100R in the outermost first column are aligned with each other in the second direction D2 with the plurality of vacancy arrangement points 100R located in the second column.

As shown in FIG. 1, the configuration point array 100 includes a first row configuration point group N1. The first row of configuration point groups N1 includes a plurality of grounding configuration points 100G and a plurality of signal configuration points 100S that are alternately disposed, and two signal configuration points 100S are disposed between each two adjacent grounding configuration points 100G. In other words, the plurality of ground configuration points 100G and the plurality of signal configuration points 100S located in one of the rows of the arrangement point array 100 (such as the first row in FIG. 1) are alternately arranged in the second direction D2. Thus, a grounded solder ball 110G is disposed before and after each of two adjacent signal solder balls 110S.

In addition, the configuration point array 100 includes a second row configuration point group N2. As shown in FIG. 1, the second row configuration point group N2 includes a plurality of adjacent vacancy configuration points 100R, a plurality of signal configuration points 100S adjacent to each other, and at least one ground configuration point 100G, and a plurality of adjacent ones are adjacent to each other. The signal configuration point 100S is located between one of the slot configuration points 100R and the at least one ground configuration point 100G.

In this embodiment, in another row (such as the second row in FIG. 1) of the configuration point array 100, two vacancy configuration points 100R, four signal configuration points 100S, and a ground configuration point are sequentially disposed. 100G. In addition, one of the signal configuration points 100S in the second row configuration point group N2 and one of the first row configuration point groups N1 are in the same column. In addition, at least one grounding configuration point 100G of the second row of configuration point groups N2 is in the same column as one of the first row of configuration point groups N1.

For example, the first row and the fourth column of the arrangement point array 100 and the second row and the fourth column of the arrangement point array 100 are respectively provided with the ground solder ball 110G and the signal solder ball 110S. The ground ball 110G is disposed in the first row and the seventh column of the arrangement point array 100 and the second row and the seventh column of the arrangement point array.

Further, the configuration point array 100 of the present embodiment is composed of a plurality of first row configuration point groups N1 and a plurality of second row configuration point groups N2 that are alternately arranged in the first direction, and each A second row configuration point group N2 is disposed between every two adjacent first row configuration point groups N1.

The configuration point array 100 includes a lower layer wiring configuration point group M1, and the lower layer wiring configuration point group M1 includes a plurality of ground configuration points 100G, a plurality of signal configuration points 100S, and a plurality of space configuration points 100R. In the lower layer wiring arrangement point group M1, the ratio of the number of signal arrangement points 100S to the number of ground arrangement points 100G is 2:1, and the ratio of the number of signal arrangement points 100S to the number of slot configuration points 100R is also 2:1.

Corresponding to the arrangement of the first row configuration point group N1, the two ground configuration points 100G and the two signal configuration points in the lower layer wiring configuration point group M1 are located in the same row (for example, the first row of the configuration point array) And the two signal configuration points 100S are located between two adjacent ground configuration points 100G.

In addition, corresponding to the arrangement manner of the second row configuration point group N2, the two signal configuration points 100S and the two vacancy configuration points 100R are located in the same row (for example, the second row of the configuration point array), and two vacancies The configuration points 100R are in close proximity to each other.

It should be noted that since the first row and the second side of the outermost point of the array array 100 are arranged The row has a vacancy arrangement point 100R. When the electronic package component 1 is disposed on the circuit board, the grounding solder balls 110G on the plurality of grounding arrangement points 100G of the lower layer wiring arrangement point group M1 and the plurality of signal arrangement points 100S The signal solder ball 110S can be connected to the corresponding contact through the circuit board surface, and the signal solder ball 110S and the connected circuit can be completely shielded by the ground solder ball 110G and the connected circuit.

In the embodiment of FIG. 1, the lower layer wiring arrangement point group M1 includes a plurality of ground configuration points 100G, a plurality of signal configuration points 100S, and a plurality of vacancy configuration points in the first to fourth columns of the outermost side of the arrangement point array 100. 100R. That is to say, the ground solder balls 110G and the signal solder balls 110S of the first to fourth columns (m=1 to 4) located at the outermost side of the ball grid array can be connected to the lines on the surface of the board. Thus, compared with the prior art, the ball grid array of the electronic package component 1 of the embodiment of the present invention can improve the line space utilization rate of the circuit board surface.

The configuration point array 100 of the embodiment of the present invention further includes a lower layer wiring configuration point group M2. The lower layer wiring arrangement point group M2 includes a plurality of grounding configuration points 100G and a plurality of signal configuration points 100S. The ratio of the number of signal configuration points 100S to the number of grounding configuration points 100G is 2:1, and the plurality of grounding configuration points 100G in the lower layer wiring configuration point group M2 are in the same column, as shown in the seventh column of FIG. .

When the electronic package component 1 is disposed on the circuit board, the ground connection point 100G located at the lower layer wiring arrangement point group M2 and the ground solder ball 110G and the signal solder ball 110S on the signal arrangement point 100S are through the conductive holes of the circuit board. And the lines below the board are connected to the corresponding contacts. The aforementioned conductive holes may be conductive blind holes or conductive through holes. The circuit under the board can be a line buried inside the board or a line at the bottom of the board.

It should be noted that when the electronic package component 1 is mounted on the circuit board, the ground solder ball 110G located in the top wiring arrangement point group M1 and the connected circuit thereof can shield the signal solder ball on the signal configuration point 100S. 110S and the line to which it is connected.

In addition, the ground ball 110G located on the grounding arrangement point 100G of the lower layer wiring arrangement point group M2 and the line connected thereto can also be shielded from the signal configuration point 100S. The signal solder ball 110S and the line to which it is connected to avoid mutual coupling between the lines. In this way, the requirements for high-frequency signal transmission can be satisfied without increasing the circuit complexity of the circuit board.

Referring to FIG. 2, a partial top view of the circuit layout structure of the embodiment of the present invention is shown. The circuit layout structure 200 is formed in a circuit board 2 to fit the electronic package member 1 as described above. First, in this embodiment, one surface of the circuit board 2 is provided with a pad arrangement area 20, and the pad arrangement area 20 can be divided into a peripheral area 20A and an inner area 20B.

The circuit layout structure 200 includes a pad array 210, a top wiring layer L1 connected to the pad array 210, and a lower wiring layer L2 connected to the pad array 210. The top wiring layer L1 and the pad array 210 are on the same side of the circuit board 2, and the lower wiring layer L2 and the pad array 210 are located on opposite sides of the circuit board 2, respectively. Therefore, the circuit layout structure 200 further includes a plurality of conductive vias (not shown) such that the pad array 210 and the underlying wiring layer L2 are connectable through the conductive vias.

As shown in FIG. 2, the pad array 210 is disposed in the pad arrangement area 20 and includes a plurality of ground pads 210G, a plurality of signal pads 210S, and a plurality of padless regions 210R. Further, the pad array 210 is a configuration dot array 100 corresponding to the electronic package member 1 and a ball grid array. Similar to the arrangement point array 100, the pad array 210 is arranged by a plurality of ground pads 210G, a plurality of signal pads 210S, and a plurality of padless regions 210R along a m column along a first direction D1 and along a n rows of the second direction D2.

The pad array 210 of the present embodiment includes a top-level wiring pad group A1 located in the peripheral region 20A. The top-level wiring pad group A1 of the present embodiment includes a plurality of ground pads 210G in the first column (m=1) to the fourth column (m=4) of the outermost side of the pad array 210, and a plurality of signals. Pad 210S and a plurality of padless regions 210R. The aforementioned padless region 210R is a vacant arrangement point 100R corresponding to the electronic package member 1, and no pad is provided. In the top-level wiring pad group A1, the ratio of the number of signal pads 210S to the number of ground pads 210G is 2:1, and the signal pads 210S The ratio of the number to the number of pads-free regions 210R is 2:1.

Furthermore, in the present embodiment, a plurality of ground pads 210G and a plurality of padless regions 210R located in the outermost first column (m=1) of the pad array 210 are alternately disposed. As shown in FIG. 2, in the outermost column 1 of the pad array 210, a padless region 210R is disposed between every two adjacent ground pads 210G.

In addition, in the embodiment, the plurality of signal pads 210S located in the outermost second column (m=2) of the pad array 210 are alternately disposed with the plurality of padless regions 210R, and each two adjacent A solderless pad region 210R is disposed between the signal pads 210S. In detail, the padless region 210R in the outermost column 1 of the pad array 210 and the padless region 210R in the second column located at the outermost side of the pad array 210 are in the same row. For example, the second row and the fourth row shown in FIG.

The top-level wiring pad group A1 further includes a plurality of signal pads 210S located at the outermost third column of the pad array 210, and a plurality of signal pads 210S and a plurality of alternately disposed in the fourth outermost row of the pad array 210. Ground pad 210G.

Compared to the number of pads located in the third column, the number of pads in the outermost first row of the pad array 210 is small, so that each two adjacent ground pads located in the first column 210G and each of the two adjacent signal pads 210S in the second column have a wider spacing.

In addition, in this embodiment, the plurality of ground pads 210G and the plurality of signal pads 210S in the top layer wiring pad group A1 are all connected to the top layer circuit layer L1. Further, the padless region 210R located in the outermost row of the pad array 210 can be used as a wiring routing region to set the top wiring layer L1.

As shown in FIG. 2, the top layer circuit layer L1 includes a plurality of first signal lines S1 and a plurality of first ground lines G1. The plurality of first signal lines S1 are respectively connected to the plurality of signal pads 210S in the top layer wiring pad group A1, and the plurality of first ground lines G1 are respectively connected to the plurality of ground pads 210G in the top layer wiring pad group A1. . A no-wiring area is defined between each two adjacent first signal lines S1 and the first ground line G1.

In other words, there is no other first signal line S1 passing through the area between every two most adjacent first signal lines S1 and the first ground line G1. Therefore, each of the first signal lines S1 is provided with a first ground line G1, thereby providing a complete ground shield for each of the first signal lines S1.

As can be seen from FIG. 2, the first signal line S1 connected to the signal pad 210S in the first row and the third column and the first ground line G1 connected to the ground pad 210G in the first row and the fourth column are Pass through the padless region 210R.

Accordingly, the signal pad 210S and the ground pad 210G located in the first to fourth columns of the pad array 210 can be electrically connected to another element on the circuit board 2 through the top layer circuit layer L1. Therefore, in the pad array 210 of the embodiment of the present invention, the line space utilization rate of the surface of the circuit board 2 can be effectively improved by the arrangement of the padless region 210R.

In addition, the pad array 210 further includes a lower layer wiring pad group A2 located in an inner region 20B of the pad arrangement region 20. The lower layer wiring pad group A2 includes a plurality of signal pads 210S and a plurality of ground pads 210G. In this embodiment, the ratio between the number of signal pads 210S and the number of ground pads 210G is 2:1, and the plurality of ground pads 210G in the lower layer wiring pad group A2 are arranged in the first direction D1. In the same column.

The signal pad 210S and the ground pad 210G in the lower layer wiring pad group A2 are respectively connected through a plurality of conductive holes and the lower wiring layer L2.

The lower circuit layer L2 includes a plurality of second signal lines S2 and a plurality of second ground lines G2. The plurality of second signal lines S2 are respectively connected to the plurality of signal pads 210S in the lower layer wiring pad group A2. In addition, the plurality of second ground lines G2 are respectively connected to the plurality of ground pads 210G in the lower layer wiring pad group A2. Similar to the top layer L1, a non-wiring area is defined between each two adjacent second signal lines S2 and the second ground line G2, so that each second ground line G2 can shield the second signal adjacent thereto. Line S2.

In general, in the circuit layout structure 200 of the embodiment of the present invention, for each For the signal pad 210S, at least one of the plurality of pads adjacent to the signal pad 210S has a ground pad 210G or is adjacent to a ground line G1 (or G2).

In detail, for the plurality of ground pads 210G and the signal pads 210S located in the peripheral region 20A, if the signal pads 210S (position coordinates m=3, n=3) are centered, the signal pads 210S are located. (Position coordinates m=3, n=3) The pads of the next column are the ground pads 210G (position coordinates m=4, n=3).

In addition, for the signal pad 210S located in the second row of the third column (position coordinates m=3, n=2), the signal pads 210S (position coordinates m=3, n=2) are up, down, left, and right. The pad is not the ground pad 210G, but the signal pad 210S (position coordinate m=3, n=2) is next to a first ground connected to the ground pad 210G (position coordinates m=4, n=1). Line G1.

Similarly, the same is true in the plurality of ground pads 210G and the signal pads 210S in the inner region 20B. Hereinafter, the signal pad 210S (position coordinate m=5, n=2) and the other signal pad 210S (position coordinate m=6, n=2) will be described in detail as an example. For the signal pad 210S (position coordinate m=6, n=2), at least one of the four pads on the top, bottom, left and right of the signal pad 210S (position coordinate m=6, n=2) is at least one grounded. Pad 210G (located in row 2, row 2 (position coordinates m=7, n=2)).

For the other signal pad 210S (position coordinates m=5, n=2), although the four pads of the signal pad 210S (position coordinates m=5, n=2) are not grounded. Pad 210G, but next to the signal pad 210S (position coordinates m=5, n=2), a second ground line G2 connected to the ground pad 210G (position coordinates m=7, n=1) is disposed.

Accordingly, the circuit layout structure 200 of the embodiment of the present invention can provide a complete ground shield for each of the signal pads 210S, the first signal line S1, and the second signal line S2.

Specifically, the circuit layout structure 200 provided by the embodiment of the present invention can ensure that each signal of the electronic package component 1 passes through the corresponding first signal line S1 (or the second message). After the line S2) is transmitted to another component, the signal is returned from the first signal line S1 (or the second signal line S2) and the immediately adjacent first ground line G1 (or the second ground line G2). That is to say, the first ground line G1 (or the second signal line S2) adjacent to each of the first signal lines S1 (or the second signal line S2) is a return path of the signal.

In view of the above, one of the advantageous effects of the present invention is that the electronic package member 1 and the circuit layout structure 200 thereof provided by the present invention can pass the "configuration point array 100 and the circuit layout structure 200 of the electronic package member 1 respectively". The at least one outer row or the outermost column of the pad array is provided with a vacancy arrangement point and a padless region", so that the pad array 210 has more rows or columns of pads directly connected to the top layer Layer L1, thereby increasing the usage of the line space of the circuit board 2.

In addition, in the circuit layout structure 200 on the circuit board 2, in the top-layer wiring pad group A1, a plurality of ground pads 210G and a plurality of first ground lines G1 connected thereto are grounded, and a plurality of first ground lines are connected. G1 can completely shield all of the signal pads 210S located in the top wiring pad group A1 and the first signal line S1 to which they are connected. Similarly, the plurality of ground pads 210G in the lower layer wiring pad group A2 and the plurality of second ground lines G2 connected thereto are grounded, and all the signal pads 210S in the lower layer wiring pad group A2 can be shielded. And the second signal line S2 connected thereto, thereby avoiding interference when transmitting high frequency signals.

That is to say, with the circuit layout structure 200 provided by the embodiment of the present invention, even if the number of the ground pads 210G is smaller than the number of the signal pads 210S, the signal pad 210S can be provided with good ground shielding.

The above disclosure is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, any equivalent technical changes made by using the present specification and the contents of the drawings are included in the application of the present invention. Within the scope of the patent.

Claims (10)

An electronic package component having a plurality of ground solder balls and a plurality of signal solder balls disposed corresponding to an array of arrangement points, wherein the array of arrangement points includes a plurality of grounding configuration points for carrying the ground solder balls, a plurality of signal configuration points carrying the signal solder balls and a plurality of vacancy configuration points, the arrangement point array being arranged by a plurality of the ground configuration points, a plurality of the signal configuration points, and a plurality of the vacancy configuration points Forming m columns along a first direction and n rows along a second direction, a plurality of the grounding configuration points and a plurality of the first row or the first column located in the outermost side of the array of arrangement points The vacancy configuration points are alternately set. The electronic package member according to claim 1, wherein a plurality of the grounding arrangement points located in the outermost column 1 of the arrangement point array are alternately arranged with the plurality of the vacancy arrangement points, and each two One of the vacancy arrangement points is disposed between the adjacent grounding configuration points. The electronic package component of claim 2, wherein a plurality of the signal configuration points located in the outermost second column of the arrangement point array are alternately disposed with the plurality of the space configuration points, and are located in the One of the slot configuration points in the outermost first column of the arrangement point array is in the same row as one of the slot configuration points located in the outermost second column of the arrangement point array. The electronic package component of claim 1, wherein the array of configuration points comprises: a first row of configuration point groups, the first row of configuration point groups comprising a plurality of the grounded configuration points and a plurality of the signal configuration points, and two of the signal configuration points are disposed between each two adjacent ground configuration points; and a second row configuration point group, the second line configuration point group The group includes a plurality of adjacent vacancy configuration points, a plurality of adjacent signal configuration points, and at least one ground configuration point, and the plurality of signal configuration points adjacent to each other are located at one of the Between the vacancy configuration points and at least one of the ground configuration points; wherein the configuration point array is composed of a plurality of the first row configuration point groups and a plurality of alternately arranged in the first direction The second row configuration point group is configured, and each of the second row configuration point groups is disposed between every two adjacent first row configuration point groups. The electronic package component of claim 4, wherein at least one of the grounding configuration point of the second row of configuration point groups and one of the first row of configuration point groups is the grounding configuration point In the same column. A circuit layout structure formed in a circuit board to match the electronic package component of claim 1, wherein the circuit layout structure includes an array of pads, and the array of pads is disposed on the circuit board a pad arrangement area on one surface, the pad array includes a plurality of ground pads, a plurality of signal pads, and a plurality of padless regions, the pad array comprising a plurality of the ground pads, The plurality of signal pads and the plurality of pad regions are arranged in m rows along a first direction and n rows along a second direction, and are located at an outermost side of the pad array A plurality of the ground pads in the row or the first column and a plurality of the pads-free regions are alternately disposed. The circuit layout structure of claim 6, wherein the pad array comprises a top wiring pad group located in a peripheral region of the pad arrangement region, the top layer wiring pad group including a ground pad, a plurality of signal pads, and a plurality of padless regions, and in the group of top wiring pads, the ratio of the number of signal pads to the number of ground pads is 2: 1, and the ratio of the number of signal pads to the number of the padless regions is 2:1. The circuit layout structure of claim 6, further comprising a top circuit layer, the top circuit layer and the top wiring pad group being the same on the circuit board a side, wherein the top layer circuit layer comprises: a plurality of first signal lines, wherein the plurality of first signal lines are respectively connected to a plurality of the signal pads in the top layer wiring pad group; and a plurality of a plurality of the first ground lines connected to the plurality of the ground pads in the top layer wiring pad group, wherein each of the two adjacent first signal lines and the first A no-wiring area is defined between a ground line. The circuit layout structure of claim 8, wherein the pad array further comprises a lower layer wiring pad group located in an inner region of the pad arrangement region, the lower layer wiring pad group including a plurality of the signal pads and a plurality of ground pads arranged in a plurality of rows along the second direction, and the ratio between the number of the signal pads and the number of the ground pads is 2:1, And a plurality of the ground pads in the lower layer wiring pad group are arranged in the same row in the first direction. The circuit layout structure of claim 9, further comprising a lower circuit layer, wherein the lower circuit layer and the lower layer wiring pad group are respectively located on opposite sides of the circuit board, wherein the lower circuit layer The method includes: a plurality of second signal lines, wherein the plurality of second signal lines are respectively connected to a plurality of the signal pads in the lower layer wiring pad group; and a plurality of second ground lines, and the plurality of Two grounding lines are respectively connected to the plurality of the grounding pads in the lower layer wiring pad group, wherein a definition is defined between each two adjacent second signal lines and the second grounding line Wiring area.