TWI621242B - Aluminum nitride (ain) devices with infrared absorption structural layer - Google Patents

Abstract

A microelectromechanical system device is disclosed, comprising: a first germanium substrate, the first germanium substrate comprising: an operating layer, the operating layer comprising a first surface and a second surface, the second surface comprising a cavity; an insulating layer deposited thereon Above the second surface of the handle layer; the device layer having a third surface and a fourth surface, wherein the third surface is bonded to the insulating layer; the piezoelectric layer is deposited over the fourth surface of the device layer; a conductive layer disposed over the piezoelectric layer; a bonding layer disposed over a portion of the metal conductive layer; and a spacer formed on the first germanium substrate; wherein the first germanium substrate is bonded to the second germanium substrate The second germanium substrate comprises: a metal electrode configured to form an electrical connection between the metal conductive layer formed on the first germanium substrate and the second germanium substrate.

Description

Aluminum nitride (AIN) device with infrared absorbing structure layer

The present disclosure relates to a micro-electro-mechanical (MEMS) device, a MEMS device for radio frequency (RF) and low parasitic applications, and an aluminum nitride having an infrared absorbing structure layer ( AlN) method of device.

Microelectromechanical systems (MEMS) are a widely used technology that combines microelectronic circuits and mechanical structures on a single wafer, significantly reducing manufacturing costs and die size. There is a strong need for cost effective solutions that can be utilized in low parasitic applications.

A simplified summary of the specification is presented below to provide a basic understanding of some aspects of the specification. This Summary is not an extensive overview of the specification, and is not intended to identify a critical or critical element of the specification, nor is it intended to describe any scope of any embodiment or claim. Its sole purpose is to present some concepts of the specification in a

MEMS devices for low parasitic applications are disclosed. In the first In one aspect, the MEMS device includes a MEMS wafer and an insulating layer, the MEMS wafer including an operational wafer having one or more vias, the operational wafer having a first surface and a second surface, the insulating layer deposited On the second surface of the wafer. The MEMS device also includes a device layer having third and fourth surfaces bonded to the insulating layer of the second surface of the handle wafer; and a metal conductive layer on the fourth surface . The MEMS device also includes a complementary metal oxide semiconductor (CMOS) wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode to form an electrical connection between the at least one metal electrode and at least a portion of the metal conductive layer.

In the second aspect, the MEMS device comprises a MEMS based A slab comprising a movable portion and one or more spaces extending from the substrate; an aluminum layer deposited on the one or more spaces. The MEMS substrate includes an electrically conductive diffusion barrier layer disposed on top of the aluminum layer, and a germanium layer disposed on top of the electrically conductive diffusion barrier layer. The MEMS device further includes a CMOS substrate coupled to the MEMS substrate and including at least one electrode and one or more aluminum pads. The one or more spaces are bonded to the one or more aluminum pads using a eutectic point between the one or more aluminum pads and the tantalum layer.

In a third aspect, the device includes a first substrate having a MEMS device. The MEMS device includes a crucible movable element and a piezoelectric element such that when a voltage is applied, strain is induced on the piezoelectric element. The device also includes a second substrate having at least one electronic circuit, and An electrical connection is provided by the bonding of the first substrate and the second substrate. An electrical connection from the MEMS device to the electronic circuit provides a voltage to the piezoelectric element.

In another embodiment, a MEMS is disclosed and described The device, the MEMS device can include a first germanium substrate, the first germanium substrate can include: an operating layer comprising a first surface and a second surface, wherein the second surface can comprise a cavity; an insulating layer deposited on the operation Above the second surface of the layer; the device layer having a third surface and a fourth surface, wherein the third surface is bonded to the insulating layer; the piezoelectric layer is deposited over the fourth surface of the device layer; the metal is electrically conductive a layer disposed over the piezoelectric layer; a bonding layer disposed over a portion of the metal conductive layer; and a spacer formed on the first germanium substrate; wherein the first germanium substrate is bonded to the second germanium substrate, The second germanium substrate comprises: a metal electrode configured to form an electrical connection between the metal conductive layer formed on the first germanium substrate and the second germanium substrate.

According to yet another embodiment, the machine/processor is disclosed The method comprises: depositing an insulating layer above the operating layer, the operating layer comprising a first surface and a second surface, wherein the second surface comprises a cavity, and the insulating layer is formed on the operating layer Bonding a first layer of the device layer to the insulating layer; depositing a piezoelectric layer on the second surface of the device layer; depositing a metal conductive layer over the piezoelectric layer; partially depositing a bonding layer on the metal Above the conductive layer; forming a space on the second surface of the device layer; and establishing an electrical connection between the metal conductive layer and the germanium substrate.

According to another aspect and/or embodiment, a method is disclosed The MEMS device includes: a first germanium substrate bonded to the second germanium substrate, the second germanium substrate comprising: an electrode on the second germanium substrate and electrically contacting the conductive layer disposed on the first germanium substrate; The conductive layer on the first germanium substrate is disposed over the piezoelectric layer on the first germanium substrate; the piezoelectric layer on the first germanium substrate is deposited over the device layer, and the device layer includes a spacer Formed on the first germanium substrate; and the device layer on the first germanium substrate is bonded to a dielectric layer, the dielectric layer being a surface of an operating layer deposited on the first germanium substrate, the surface Contains cavities.

The following description and additional drawings present the specification Specific examples. However, these aspects are only some of the various ways in which the principles of the specification may be employed. Other advantages and novel features of the specification will become apparent from the following detailed description.

100, 100', 200, 300, 400, 600, 700, 800, 900, 934‧‧‧ MEMS structures

102, 102', 102", 936‧‧‧ CMOS wafers

104, 104', 104", 942‧‧‧ MEMS wafers

106, 106'''‧‧‧矽 device layer

108‧‧‧Operating wafer

109‧‧‧Oxide layer

110, 110', 110", 110'''‧‧‧ MEMS aluminum

111, 206, 206'‧‧‧锗

112‧‧‧ interval

112a, 112b, 402‧‧‧ insulation

113, 204, 204', 204" ‧ ‧ CMOS aluminum

114‧‧‧ spacers

117‧‧‧ bottom metal layer

302, 302"‧‧‧ barrier layer

502, 504, 506, 508, 510, 512 ‧ ‧ steps

602‧‧‧Piezoelectric layer

604, 604', 604", 920‧‧‧ bottom electrode

606‧‧‧Top electrode

608‧‧‧CMOS aluminum pad

610‧‧‧Interconnection

702, 1404‧‧‧ cerium oxide layer

902, 938‧‧‧ cavity

904‧‧‧Operation Wafer/Layer/Substrate

906‧‧‧2 Oxide layer/substrate

908‧‧‧矽 substrate/layer (structure layer)

910‧‧‧Aluminum nitride seed layer

912‧‧‧ molybdenum layer

914‧‧‧Aluminum nitride stack

916‧‧‧2O2 interval

918, 1312‧‧‧ cerium oxide hard mask

922‧‧‧Bottom electrode contacts

924‧‧‧Aluminum nitride top joint

926, 1306‧‧‧aluminum and titanium layers

928, 1308‧‧‧锗 pads

930‧‧‧electrode

932‧‧‧ photoresist layer

934, 1314‧‧‧ release structure

940‧‧‧MEMS Operating Wafer

944, 1318‧‧‧ interface

1002‧‧‧ Partial etching

1102‧‧‧Infrared absorption layer

1202‧‧‧Piezo stack layer

1302‧‧‧Aluminum nitride layer

1304‧‧‧Aluminum nitride layer pattern

1310‧‧‧Aluminum and titanium pads

1316‧‧‧MEMS device wafer

1402‧‧‧ side wall

1406‧‧‧ Sidewall protection

The various aspects, embodiments, objects, and advantages of the present invention will be apparent from the description of the accompanying drawings. : Figure 1A illustrates a cross-sectional view of a MEMS structure in accordance with a first embodiment.

Fig. 1B illustrates a cross-sectional view of a MEMS structure in accordance with a second embodiment.

Figure 2 illustrates a cross-sectional view of a MEMS structure in accordance with a third embodiment.

Figure 3 illustrates a cross-sectional view of a MEMS structure in accordance with a fourth embodiment.

Figure 4 illustrates a cross-sectional view of a MEMS structure in accordance with a fifth embodiment.

Figure 5 is a flow diagram of a procedure for adding a piezoelectric layer to a MEMS structure.

Fig. 6 is a cross-sectional view showing the MEMS structure according to the sixth embodiment.

Figure 7 illustrates a cross-sectional view of a MEMS structure in accordance with a seventh embodiment.

Figure 8 illustrates a cross-sectional view of a MEMS structure in accordance with an eighth embodiment.

9A to 9K are cross-sectional views illustrating a MEMS structure according to a ninth embodiment.

Figure 10 illustrates a cross-sectional view of a MEMS structure in accordance with a tenth embodiment.

Fig. 11 is a cross-sectional view showing the MEMS structure according to the eleventh embodiment.

Sections 12(a)(i), 12(a)(ii), 12(b)(i), and 12(b)(ii) illustrate cross-sectional views of a MEMS structure in accordance with a twelfth embodiment.

13A to 13H are cross-sectional views showing a MEMS structure according to a thirteenth embodiment.

14A to 14C are cross-sectional views illustrating a MEMS structure according to a fourteenth embodiment.

One or more embodiments will now be described with reference to the drawings In the above, the same numbers are used to denote the same components throughout. In the following description, for the purposes of illustration However, it will be apparent that different embodiments may be practiced without these specific details, for example, without application to any particular network environment or standard. In other examples, known structures and devices are shown in the form of block diagrams for additional detail Sections to facilitate the description of this embodiment.

The main disclosure relates to a microelectromechanical system (MEMS) device, and more particularly to a MEMS device for radio frequency (RF) and low parasitic applications. The following description is presented to enable one of ordinary skill in the art to make and use the invention, Different modifications to the described embodiments and the general principles and features described herein will become apparent to those skilled in the art. Therefore, the present invention is not intended to be limited to the embodiments shown, but is to be accorded to the broad scope of the principles and features described herein.

In the described embodiment, a microelectromechanical system (MEMS) refers to a structure or device that is fabricated using a program such as a semiconductor and exhibits mechanical properties (eg, the ability to move or deform). MEMS usually, but not always, interact with electrical signals. MEMS devices include, but are not limited to, gyroscopes, accelerometers, magnetometers, pressure sensors, and radio frequency components. A germanium wafer containing a MEMS structure is called a MEMS wafer.

In the described embodiment, a MEMS device can refer to a semiconductor device implemented as a microelectromechanical system. A MEMS structure can refer to any feature that can be a component of a larger MEMS device. An engineered over-insulator (ESOI) wafer may refer to an SOI wafer having a cavity below the germanium device layer or substrate. Operating a wafer generally refers to a thicker substrate used as a carrier for a thinner germanium device substrate in a germanium on insulator. The operating substrate and the operating wafer are interchangeable.

In the described embodiment, the cavity means a recess in the aperture or substrate wafer, and the enclosure may be completely enclosed. space. A bond chamber refers to an enclosure in a piece of bonding apparatus in which the wafer bonding process is performed. The atmosphere in the bonding chamber determines the atmosphere sealed in the bonded wafer.

Furthermore, a system and method in accordance with the present invention describes a RF MEMS devices, sensors, and actuators, including but not limited to switches, resonators, and tunable capacitors that are sealable and engageable with integrated circuits that can use capacitive sensing and static electricity Sexual, magnetic, or piezoelectric actuation.

FIG. 1A illustrates a MEMS structure according to the first embodiment Sectional view of 100. Figure 1A shows that the MEMS structure has additional metal in the germanium structure layer. The structure includes a CMOS wafer 102 bonded to the MEMS wafer 104. The MEMS wafer 104 includes a germanium device layer 106 that is melt bonded to the handle wafer 108 through the oxide layer 109. A MEMS aluminum 110 metal layer is added to the germanium device layer 106. Adding a metal layer is more than the germanium device layer 106, which reduces the electrical resistance of the MEMS structure, making it more useful for applications requiring low parasitic (eg, RF MEMS, Lorentz force sensors, etc.). Attractive. In this embodiment, the connection between CMOS wafer 102 and MEMS wafer 104 is created by the stand-off 112, which uses aluminum-germanium formed by germanium 111 and aluminum 113. Crystal bonding. In addition to the spacing 112, the metal layer 117 carries most of the current. In an embodiment, a spacer 114 composed of an insulating material (for example, hafnium oxide or tantalum nitride) may be placed on the bottom metal layer 117 to reduce static friction and thereby control the top metal layer 110 and the bottom metal layer. The gap between 117.

FIG. 1B illustrates a cross-sectional view of a MEMS structure 100' in accordance with a second embodiment. 1B shows a MEMS structure having an additional insulating layer 112a deposited on the MEMS aluminum 110, and an insulating layer 112b deposited on the bottom electrode 117 to prevent short circuits and further When the movable MEMS structure (which is composed of the germanium device layer 106, the MEMS aluminum 110, and the insulating layer 112a) is in contact with the electrode on the CMOS wafer 102, a good capacitive gap is created.

FIG. 2 illustrates a cross-sectional view of a MEMS structure 200 in accordance with a third embodiment. Figure 2 shows a MEMS structure similar to Figure 1A. However, in this embodiment, the electrical connection between the CMOS wafer 102' and the MEMS wafer 104' is transmitted through the CMOS aluminum 204 and the MEMS wafer 104' on the CMOS wafer 102'. The physical contact between the MEMS aluminum 110' occurs, wherein the CMOS aluminum 204 and the MEMS aluminum 110' are formed on the CMOS wafer 102' by 锗 206 and CMOS aluminum 204 and the MEMS wafer 104' The aluminum-germanium layer created by the eutectic reaction between the MEMS aluminum 110' is connected. One possible risk of this embodiment is the selective oxidation of the crucible 206 to the MEMS aluminum 110' (since it is deposited directly on the layer), which may have insufficient reaction with the CMOS aluminum 204. This insufficient response can result in poor bonding and critical electrical connections.

Figure 3 illustrates a cross-sectional view of a MEMS structure 300 in accordance with a fourth embodiment. Figure 3 shows the same MEMS structure as in Figure 2, except that barrier layer 302 is deposited between the MEMS aluminum 110" and the crucible 206'. The barrier layer 302 is electrically conductive and is in contact with the physical Aluminum battery Sexual contact. The purpose of the barrier layer 302 is to prevent eutectic reaction between the MEMS aluminum 110" and the germanium 206', leaving the germanium 206' eutectic reaction with the CMOS aluminum 204. One such barrier layer can be nitrided. Titanium. During the eutectic reaction, the CMOS aluminum 204 will be mixed with the crucible 206' to create electrical and physical bonds with the barrier layer 302 on the MEMS aluminum 110", thereby forming the CMOS wafer 102. Create electrical contact between "with MEMS wafer 104".

Figure 4 illustrates a cross-sectional view of a MEMS structure 400 in accordance with a fifth embodiment. Figure 4 shows the same MEMS structure as in Figure 3, but with an insulating layer 402 deposited between the MEMS aluminum 110"" and the germanium device layer 106"" to electrically insulate the germanium from the metal. . The insulating layer 402 is desirable in cases where it is undesirable to carry any electrical signals in the germanium layer (e.g., in RF applications where signal transmission in the germanium can create energy losses). In this embodiment, the MEMS aluminum 110"" is still permeable to the insulating layer 402 at the RF frequency and capacitively coupled to the germanium device layer 106"". In order to achieve sufficient insulation, the insulating layer must be sufficiently thick to minimize capacitance, or the crucible must have sufficient electrical resistance to minimize the electrical signals coupled thereto.

Figure 5 is a flow diagram of the procedure for adding metal and piezoelectric layers to the MEMS structure. The program begins with the engineered SOI 502. The first metal layer (metal 1) is deposited on the surface of the device via step 504, and then patterned and etched by the piezoelectric layer deposition (eg, aluminum nitride or PZT) through step 506. Next, through step 508, a second metal layer (metal 2) is deposited on the wafer as the top electrode of the piezoelectric layer and provides electrical contact between the metal 1 and the CMOS substrate. Through the steps 510, a layer of germanium is deposited on the metal 1 and patterned to define the germanium pad in the region where bonding with CMOS occurs. Next, through step 512, the MEMS wafer is bonded to the CMOS wafer to eutectic the germanium pad with the aluminum pad on the CMOS to create electrical and physical contact between the CMOS aluminum and the MEMS metal 2.

Fig. 6 illustrates a sixth embodiment according to the use of a piezoelectric layer A cross-sectional view of MEMS structure 600. The addition of the piezoelectric layer 602 allows the range of applications to include acoustic resonators and screening programs as well as piezo-actuated devices. In order to operate, the piezoelectric layer 602 typically requires a bottom electrode 604 and a top electrode 606. The bottom electrode 604 can comprise a first metal layer (metal 1) (eg, aluminum, tantalum, tungsten, molybdenum, or platinum). In other embodiments, the germanium device layer can be used as the bottom electrode 604. The top electrode 606 and interconnect 610 are comprised of a second metal layer (metal 2) (eg, aluminum). The top electrode 606 and interconnect 610 are bonded using an aluminum crucible to make physical and electrical contact with the CMOS aluminum pad 608. The bottom electrode 604 can be in physical and electrical contact with the interconnect 610 to connect to the CMOS wafer. A potential can be applied between the top electrode 606 and the bottom electrode 604, or between the individual top electrodes 606. These potentials create an electric field to induce strain in the piezoelectric material.

FIG. 7 illustrates a MEMS structure according to a seventh embodiment Sectional view of 700. Fig. 7 shows the same structure as in Fig. 6, and additionally has a ceria layer 702 between the device layer 106 and the metal layer 604". The ceria layer 702 serves as a temperature stabilizing layer to have Improvement of the Young's modulus temperature coefficient of yttrium oxide to compensate for 矽 with a positive Young's temperature coefficient to improve The frequency stability of the resonator or screening program for temperature.

Figure 8 illustrates a MEMS structure according to an eighth embodiment Sectional view of 800. Fig. 8 shows the same structure as in Fig. 7 and additionally has a patterned bottom electrode 604". By patterning the bottom electrode 604", a plurality of potentials can be applied to the bottom surface of the piezoelectric material 602. The area guides more design flexibility and more efficient devices. For resonator applications, for example, the ability to input electrical signals at the bottom and top of the piezoelectric structure can result in higher coupling efficiency. In a further embodiment, the subject application discloses a microelectromechanical system (MEMS) integration process to incorporate aluminum nitride (AlN) on an engineered substrate and a top electrode bonded to aluminum telluride (AlGe) to complement each other Metal oxide semiconductor (CMOS) wafer/layer/substrate.

In addition to the above, this application also describes MEMS Process, which includes starting wafer/layer/substrate (eg, complementary metal oxide semiconductor (CMOS) wafer/layer/substrate, MEMS operational wafer/layer/substrate, and/or MEMS device wafer/layer/ a substrate) and a plurality of mask layers, for example, a 10-layer mask layer, although one of ordinary skill in the art will appreciate that a smaller or larger number of mask layers may be used without unduly departing from the general disclosure. Sex and scope.

In general, the MEMS handle wafer/layer/substrate can The backside alignment mark layer is patterned while the backside alignment mark layer is used for front-to-back alignment after fusion bonding. A cavity defining a suspended MEMS structure can also be etched on the front side of the MEMS handle wafer/layer/substrate. The MEMS operating layer/wafer/substrate can be followed by Oxidized and then melt bonded to the MEMS device layer/wafer/substrate.

For example, the MEMS device layer/wafer/substrate can be packaged a germanium-containing (Si) structural layer that can be ground to a target thickness at which point an aluminum nitride seed layer can be disposed on a surface of the germanium structural layer, and a molybdenum layer can be deposited over the aluminum nitride seed layer An aluminum nitride stacked layer may be deposited over the molybdenum layer, and/or a ceria spacer layer may be disposed on the aluminum nitride stack layer.

The ceria spacer layer can be in the MEMS device layer/crystal Etching on the circle/substrate to provide separation between the MEMS structure and the complementary metal oxide semiconductor wafer/layer/substrate. The aluminum nitride (AlN) stacked layer can then be patterned by a ruthenium dioxide hard mask having a structure, a bottom contact, and/or an aluminum nitride top contact mask. In addition, aluminum, titanium, and tantalum may then be sequentially deposited from bottom to top and patterned to have mats and electrodes. The germanium device layer can then be used to create deep penetration, steep-sided holes, and trenches in the layer/wafer/substrate, for example, using an anisotropic etch process, typically having a high aspect ratio For example, deep reactive ion etch (DRIE) is patterned and etched to define a release structure. In general, the engagement of the structure with the release layer defining the entire release structure is formed on the upper bore.

The bottom cavity is available in the complementary metal oxide semiconductor The layer/wafer is etched to form a gap for out-of-plane movement of the MEMS structure (e.g., bonding germanium and aluminum nitride stacked layers) or damping control. The MEMS and complementary metal oxide semiconductor wafer/layer/substrate can then be bonded using an aluminum-germanium (Al-Ge) eutectic bonding to A perimeter seal of the MEMS structure and an electrical interconnection between the MEMS structure and the complementary metal oxide semiconductor circuit are created. Thereafter, the bonded wafer/layer can be thinned to a desired thickness on the MEMS side, and a port can be formed on the polished side of the MEMS wafer/layer to create a connection to the surrounding environment Access. Thereafter, a silicon tab on the MEMS wafer layer can be removed using, for example, a dicing process to expose the complementary metal oxide semiconductor wire-bond pad.

MEMS device 900 is illustrated in accordance with previous and with reference to FIG. Sectional view. The MEMS 900 can include an operational wafer/layer/substrate 904 that can be patterned to have a backside alignment mark layer that will be used for front-to-back alignment after fusion bonding. Additionally, the front side of the handle wafer/layer/substrate 904 can be etched to form the cavity 902. As illustrated, the handle wafer/layer/substrate 904 can be formed from a tantalum layer/substrate that has been etched into it. For the handle wafer/layer/substrate 904 containing the via 902, a hafnium layer/substrate 906 can be deposited over the germanium layer/substrate 904 to cover the germanium layer/substrate 904 and the cavity formed therein Hole 902. A substrate/layer formed of 矽 908 may be disposed and/or deposited over the yttria layer/substrate 906 and melt bonded to the yttria layer/substrate 906. Depending on the embodiment, the handle wafer/layer/substrate 904 containing the formed vias 902 and ceria layer 906 may be referred to as an engineered substrate, and may be referred to as the MEMS handle layer for purposes of this disclosure.

Referring to FIG. 9B, the MEMS device 900 is shown One-step cross-sectional view, in addition to the above-mentioned layer containing the etched cavity 902 Substrate 904, ruthenium dioxide layer/substrate 906 (layer/substrate 904 containing etched via 902 and yttria layer/substrate 906 may be formed and may be referred to as the MEMS handle layer/wafer/substrate), and The substrate/layer 908 formed by the ruthenium, the ruthenium dioxide spacer 916 may be deposited by continuously depositing an aluminum nitride seed layer 910, a molybdenum layer 912 over the germanium substrate/layer 908, for example, prior to etching and/or forming the germanium dioxide spacer 916, and Aluminum nitride stacked layer 914. The additional deposition or placement layer (which includes the aluminum nitride seed layer 910, the molybdenum layer 912, the aluminum nitride stack layer 914, and the ceria spacer 916) over the germanium substrate/layer 908 may be referred to as the MEMS device. Layer/wafer/substrate and/or piezoelectric layer/wafer/substrate.

The germanium substrate layer 908 can be the germanium of the MEMS device layer The MEMS operational layer (eg, tantalum layer/substrate 904 containing etched vias 902 and yttria layer/substrate 906) may have been melt bonded to the MEMS device layer/wafer/substrate (eg, germanium structure) Substrate/layer 908, aluminum nitride seed layer 910, molybdenum layer 912, aluminum nitride stack layer 914, and spacer 916). It should be noted that the MEMS operating layer may typically have been oxidized prior to fusing the MEMS operating layer to the MEMS device layer, and depositing the aluminum nitride seed layer 910, the molybdenum layer 912, the aluminum nitride stack layer 914, and Prior to the spacing 916 formed by the cerium oxide, the 矽 structural layer/substrate 908 of the MEMS device layer may have been ground to a target or predetermined thickness. Spacer 916 is typically formed on the MEMS device layer to provide separation between the MEMS structure and the CMOS wafer/layer/substrate.

Figures 9C through 9E provide illustrations of MEMS device 900 In a further cross-sectional view, the MEMS device 900 includes the layers described above in Figures 9A-9B. In Figure 9C, the structure can be defined and accessible A ceria hard mask 918 is deposited or disposed over the aluminum nitride stack layer 914 and the spacer 916, and then etched through the ceria hard mask 918 to define the structure and engrave to separate the bottom electrode 920. As observed, the etch process etch layer/substrate (which is formed of ceria hard mask 918, aluminum nitride 914, molybdenum 912, and aluminum nitride seed layer 910, respectively) to the germanium structure layer/substrate 908 . In Figure 9D, a bottom electrode contact 922 can be created. In Figure 9E, an etch of openings in the yttria layer 918 can be implemented to define the aluminum nitride top contact 924 and avoid unnecessary HBAR resonance from the pad. As illustrated in FIGS. 9C-9E, the structure can be defined and the bottom electrode 920 can be engraved by creating a bottom electrode contact by patterning the aluminum nitride stack layer by the ruthenium dioxide hard mask 918. 922, and defines an aluminum nitride top contact 924.

As illustrated in Figure 9F, for the top electrode material For the purpose of deposition, an aluminum and titanium layer 926 is deposited, and then a tantalum layer 928 is deposited over the aluminum and titanium layer 926 such that the mat 928 and electrode 930 can be patterned as illustrated in Figures 9G-9H. . The device layer can be covered by a photoresist layer 932 and patterned and etched using deep reactive ion etching (DRIE) to define a release structure, as depicted in Figure 9I. Only the combination of the structure and the release layer can define the complete release structure 934 in the bore 902 (see Figure 9J).

As shown in FIG. 9J, the etching cavity 938 enters CMOS wafer 936 to form a gap for out-of-plane moving MEMS structure 934 and/or amplitude reduction control, and then CMOS wafer 936 and MEMS device wafer 940 are bonded using aluminum-germanium eutectic bonding to the MEMS structure A seal is created around 934 and the CMOS circuit, and bond wafer 942 is formed. The eutectic bonded wafer 942 can then be thinned to a predetermined or desired thickness, for example, on the MEMS wafer side, and an interface can be formed on the abrasive side of the MEMS wafer 942 to create access to the surrounding environment. (access), as depicted in Figure 9K. In addition, the tabs on the MEMS wafer 942 are removed using a singulation process to expose the complementary metal oxide semiconductor wire bond pads.

According to an additional embodiment previously and illustrated in FIG. 10, after defining the structure and engraving the separated bottom electrode 920, as illustrated in FIG. 9C, but before creating the bottom electrode contact 922, as in FIG. 9D Illustrated, a partial germanium etch can be performed, wherein the structural germanium layer 908 (eg, the structural germanium layer of the MEMS device wafer) can be partially etched 1002. The partial etch 1002 can be implemented to partially thin the germanium device layer (e.g., structural germanium layer 908). The partial etch 1002 can be structured with a layer mask and completed by germanium etching or deep reactive ion etching. It should be noted that for that previous implementation to define the structure and engrave the separate bottom electrode 920 (as explained above with reference to Figure 9C), the partial etch 1002 is an additional etch. Additionally and/or additionally, the partial etching 1002 and defining the structure and engraving the etch performed by the separate bottom electrode 920 (as depicted in FIG. 9C) may be accomplished in a single action without undue and/or It is necessary to deviate from the intention and generality of the subject disclosure.

In further additional aspects or embodiments, as illustrated in FIG. 11, additional actions may be performed after etching the interface 944 on the abrasive side of the MEMS wafer 942 (see, for example, FIG. 9K). According to this In an aspect, an infrared (IR) absorber layer 1102 can be deposited on the back of the MEMS handle wafer 940. As exemplified, the infrared absorbing layer 1102 can be disposed not only on the back of the MEMS handle wafer 940, but also in the previously etched interface 944.

According to further disclosed aspects or embodiments, such as the 12th Additional and/or additional spacing 916 forming techniques may be employed as illustrated in the figures. As illustrated in FIG. 12(a)(i), a germanium layer 908 can be deposited on the MEMS handle layer/wafer/substrate (eg, germanium layer/wafer/substrate 904 containing vias 902 and germanium dioxide) Above layer/substrate 906), and thereafter the deposited germanium layer 908 may be partially etched to form spacers 916, thus, with reference to Figure 9A and illustrated in Figure 12(a)(i), the spacing 916 may already The structural germanium layer 908 is formed from the MEMS device layer or piezoelectric layer/wafer/substrate. Alternatively, as illustrated in Fig. 12(a)(ii), the structural germanium layer 908 is not partially etched, and the structural germanium layer 908 may be covered by a layer of germanium dioxide, and thereafter, the deposited layer of germanium dioxide may be Patterning to create or form an interval 916 as illustrated in Figure 12(a)(ii).

After that, and still refer to Figure 12, deposition can be achieved The piezoelectric stack layer 1202, as described and illustrated with reference to Figures 9C through 9K, is shown in Figures 12(b)(i) and 12(b)(ii), respectively. In the context of Fig. 12(b)(i), the next piezoelectric stack layer 1202 will be observed, as described with reference to Figures 9C to 9K, covering the germanium spacer 916, and including the piezoelectric The continuous layer of stacked layer 1202 (as disclosed with reference to Figures 9C-9K) overlies the cerium oxide spacer 916, see Figure 12(b)(ii).

Figure 13 illustrates the description and reference to Figures 9A through 9K. Explain different additional and/or additional program flows. In this case, and as depicted in Figure 13(a), and as already described with reference to Figure 12(a)(i), the structural layer 908 can be patterned and/or partially etched, To form a 矽 interval 916. Thereafter, the piezoelectric layer stack (eg, aluminum nitride seed layer 910, molybdenum layer 912, and aluminum nitride stack layer 914) previously described with reference to FIG. 9B can be reduced to only the aluminum nitride layer 1302, wherein nitrogen The aluminum layer 1302 is the top of the structural layer 908 that covers the formed germanium space S916 and is patterned. As illustrated in Figures 13B through 13H, the structural germanium layer 908 containing germanium spacers 916 can be used as the bottom electrode. In FIG. 13C, the aluminum nitride layer 1302 can be covered by the aluminum and titanium layers 1306. As will be noted with reference to FIG. 13C, the pattern 1304 in the aluminum nitride layer 1302 will be filled with the aluminum and titanium layers 1306.

In FIG. 13D, a mattress 1308 can be defined, wherein The tantalum layer may cover the aluminum and titanium layers 1306 to form the mat 1308. Moreover, in FIG. 13E, the previously deposited aluminum and titanium layers 1306 can be selectively patterned to define aluminum and titanium pads 1310 and expose the underlying aluminum nitride layer 1302. In FIG. 13F, the ceria hard mask 1312 can be deposited over the defined crucible pad 1308, the aluminum and titanium pads 1310, and the exposed aluminum nitride layer 1302, and etched or patterned to define the structure 1314. .

Once structure 1314 has been defined, CMOS wafer 936 The MEMS device wafer 1316 can be eutectic bonded to the manner illustrated in the context of FIG. 9J and illustrated in FIG. 13G. In addition, the CMOS wafer 936 is eutectic bonded to the MEMS device wafer. After 1316, interface 1318 can be formed on the abrasive side or surface of the MEMS device wafer 1316, as illustrated in Figure 13H.

Now refer to Figures 14A through 14C and start with Referring to Figure 14A, in order to provide protection to the sidewalls 1402 at different etch and/or patterning stages (which may be employed to construct the microelectromechanical device described in accordance with the embodiments), and as illustrated in Figure 14B The cerium oxide layer 1404 can be deposited to cover the layer described in the context of Figure 9E. Upon inspection of Figure 14B, it will be observed that the ceria layer 1404 has been deposited and covers the sidewall 1402 along with the bottom electrode 920 and the bottom electrode contact 922. In addition, when examining Figure 14B, it will be observed that the deposited ceria layer 1404 will also have covered the aluminum nitride top contact 924. The deposition and patterning of the cerium oxide layer 1404 provides isolation. Once the yttria layer 1404 has been deposited as illustrated in FIG. 14B, the yttria layer 1404 can be subjected to a blank reactive ion etch to create sidewall protection 1406.

In accordance with the prior application in one or more different embodiments And a MEMS device, comprising: a first germanium substrate comprising: an operating layer comprising a first surface and a second surface, the second surface comprising a cavity; an insulating layer deposited on the second of the operating layer a device layer having a third surface and a fourth surface, wherein the third surface is bonded to the insulating layer; a piezoelectric layer deposited over the fourth surface of the device layer; and a metal conductive layer disposed thereon Above the piezoelectric layer; a bonding layer disposed over a portion of the metal conductive layer; and a spacer formed on the first germanium substrate; wherein the first germanium substrate is bonded to the second germanium substrate, the second germanium substrate package And comprising: a metal electrode configured to form an electrical connection between the metal conductive layer formed on the first germanium substrate and the second germanium substrate.

According to the previously described, the interval can be formed at the pressure On the electrical layer, a layer of tantalum or germanium dioxide deposited as on the layer of the device may be formed. Additionally and/or additionally, the spacing may be formed by cerium oxide deposited on the piezoelectric layer.

Additionally, the piezoelectric layer can be patterned and etched to A sidewall is formed in the piezoelectric layer, wherein a first dielectric layer can be interposed between the piezoelectric layer and the metal conductive layer, and a second dielectric layer can be disposed on the sidewall of the piezoelectric layer. Additionally, an opening may be formed in the operating layer to expose the device layer, the holes in the device layer may be used to expose the piezoelectric layer, and the device layer may comprise voids.

Depending on the aspect of the disclosure, it may be selectively or partially removed The device layer, which in one embodiment may comprise aluminum nitride, or in another embodiment may comprise an aluminum nitride (AlN) seed layer, a bottom metal layer, and an aluminum nitride layer. Further, an infrared absorbing layer may be deposited on a portion of the device layer, and/or the infrared (IR) absorbing layer may be deposited on a portion of the piezoelectric layer.

According to another embodiment, a method is described and disclosed. The method can include a sequence of machine-executable operations, the operation comprising depositing an insulating layer over the operating layer, the operating layer comprising a first surface and a second surface, wherein the second surface comprises a cavity and the insulating layer Formed on the second surface of the handle layer; bonding the first surface of the device layer to the insulating layer; depositing the piezoelectric layer on the second surface of the device layer; depositing a metal guide An electrical layer is above the piezoelectric layer; a bonding layer is partially deposited over the metal conductive layer; a second surface is formed on the device layer; and an electrical connection is established between the metal conductive layer and the germanium substrate.

Additional machine-executable method operations may include: deposition a germanium layer or a hafnium oxide layer to form the spacer; depositing a hafnium oxide layer to form a space positioned on the piezoelectric layer; patterning and etching the piezoelectric layer to form a sidewall; interposing the first dielectric layer in the Between the piezoelectric layer and the metal conductive layer; depositing a second dielectric layer on the sidewall of the piezoelectric layer; exposing the device layer through a first opening in the operating layer; and, through the first opening And a second opening in the device layer exposes the piezoelectric layer.

Additional machine executable method actions can also include: Optionally removing a portion of the device layer; depositing an infrared (IR) absorbing layer over selected portions of the device layer; and depositing an infrared (IR) absorbing layer over selected portions of the piezoelectric layer.

According to a further embodiment, the disclosure describes a microcomputer An electrical device, comprising: a first germanium substrate bonded to the second germanium substrate, the second germanium substrate comprising: an electrode on the second germanium substrate and electrically contacting the conductive layer disposed on the first germanium substrate The conductive layer on the first germanium substrate is disposed above the piezoelectric layer on the first germanium substrate; the piezoelectric layer on the first germanium substrate is deposited over the device layer, and the device layer includes formation a space on the first germanium substrate; and the device layer on the first germanium substrate is bonded to a piezoelectric layer, the piezoelectric layer being deposited on a surface of the operating layer on the first germanium substrate, The surface contains a cavity.

The term "or" as used in this application is intended to mean the package. Contains "or" rather than exclusive "or". That is, "X employs A or B" is intended to mean any natural inclusive permutation unless otherwise indicated or clear from the context. That is, if X employs A; X employs B; or X combines A and B, then "X employs A or B" is satisfied in any previous case. In addition, the article "a" or "an" or "an" Furthermore, the word "coupled" as used herein refers to either direct or indirect electrical or mechanical coupling. Furthermore, "example" and/or "example" as used herein is intended to mean an example, a case, or an illustration. Any aspect or design described herein as "example" and/or "example" need not be construed as preferred or advantageous over other aspects or designs. Instead, the use of the word is intended to present concepts in a streamlined manner.

The examples described above contain examples of the present disclosure. of course, It is not possible to describe every desired combination of elements or methods in order to describe the subject matter, but it should be appreciated that there may be many additional combinations and permutations of the present disclosure. Accordingly, the subject matter of the claims is intended to cover all such changes, modifications, and variations that fall within the spirit and scope of the appended claims.

In particular and for the components, devices, The terms used to describe such elements (including references to "means") are intended to correspond (unless otherwise indicated) to the specified functions of the described elements. Any element (e.g., a functional equivalent), even if it is not structurally equivalent to the disclosed structure, the element performs the exemplary embodiment of the subject matter of the request Features.

The previously mentioned systems are already between several components The interactive aspects are described. It will be appreciated that such systems and/or components may include those elements or specified sub-elements, some of those specified or sub-elements, and/or additional elements, and depending on the various arrangements of the combination. The secondary component can also be implemented as a component that is communicatively coupled to other components rather than included in the parent component (architectural). Furthermore, it should be noted that one or more elements may be combined into a single element that provides a collective function, or divided into several individual sub-elements, and any one or more intermediate layers may be provided to interact with such sub-elements. Communication is coupled to provide integrated functionality. Any of the elements described herein can also interact with one or more other elements not specifically described herein.

In addition, although the special features revealed by the theme are already in the One aspect of the implementation is disclosed, but such features may be combined with one or more other features of other implementations that are desired and advantageous for a given or particular application. In addition, "including" "has", "contains", its variants, and other similar words are used in the detailed description or claims, which are intended to be similar to "including" "(comprising) is included as an open-ended word without excluding other additional or other elements.

Claims (25)

A microelectromechanical system device comprising: a first germanium substrate comprising: an operating layer comprising a first surface and a second surface, the second surface comprising a cavity; an insulating layer deposited over the second surface of the operating layer; a device layer having a third surface and a fourth surface, wherein the third surface is bonded to the insulating layer; an oxide layer is formed on the fourth surface; a piezoelectric layer is deposited on the oxide layer; and the metal is electrically conductive a layer disposed over the piezoelectric layer; a bonding layer disposed over a portion of the metal conductive layer; and a spacer formed on the first germanium substrate, the spacer comprising a germanium layer or a hafnium oxide layer; wherein the first layer The germanium substrate is bonded to the complementary metal oxide semiconductor substrate, and the complementary metal oxide semiconductor substrate comprises: a metal electrode configured to oxidize the metal conductive layer formed on the first germanium substrate and the complementary metal oxide Electrical connections are made between the semiconductor substrates. The MEMS device of claim 1, wherein the spacer is formed on the piezoelectric layer. The MEMS device of claim 1, wherein the spacer is formed by ruthenium dioxide deposited on the piezoelectric layer. The MEMS device of claim 1, wherein the piezoelectric layer is patterned and etched to form sidewalls in the piezoelectric layer. The MEMS device of claim 4, further comprising a first dielectric layer between the piezoelectric layer and the metal conductive layer. The MEMS device of claim 5, further comprising a second dielectric layer disposed on the sidewall of the piezoelectric layer. The MEMS device of claim 6, further comprising an opening in the operating layer to expose the device layer. The MEMS device of claim 7, further comprising a hole in the device layer to expose the piezoelectric layer. The MEMS device of claim 7, further comprising a void in the device layer. The MEMS device of claim 1, wherein the device layer is selectively or partially removed. The MEMS device of claim 1, wherein the piezoelectric layer comprises aluminum nitride. The MEMS device of claim 1, wherein the piezoelectric layer comprises: an aluminum nitride seed layer, a bottom metal layer, and an aluminum nitride layer. The MEMS device of claim 1, further comprising an infrared absorbing layer deposited on a portion of the device layer. The MEMS device of claim 1, further comprising an infrared absorbing layer deposited on a portion of the piezoelectric layer. A method for fabricating a MEMS device, comprising: Depositing an insulating layer over the operating layer, the operating layer comprising a first surface and a second surface, wherein the second surface comprises a cavity, and the insulating layer is formed on the second surface of the operating layer; a first surface bonded to the insulating layer; an oxide layer formed on the second surface of the device layer; a piezoelectric layer deposited on the oxide layer; a metal conductive layer deposited over the piezoelectric layer; and a partial deposition bond Laying over the metal conductive layer; forming a second surface on the device layer, the space comprising a germanium layer or a hafnium oxide layer; and establishing electricity between the metal conductive layer and the complementary metal oxide semiconductor substrate Sexual connection. The method of claim 15, further comprising depositing a layer of hafnium oxide to form a space positioned on the piezoelectric layer. The method of claim 15, further comprising patterning and etching the piezoelectric layer to form sidewalls. The method of claim 17, further comprising interposing a first dielectric layer between the piezoelectric layer and the metal conductive layer. The method of claim 18, further comprising providing a second dielectric layer on the sidewall of the piezoelectric layer. The method of claim 19, further comprising exposing the device layer by a first opening in the operating layer. The method of claim 20, further comprising exposing the piezoelectric layer via the first opening and the second opening in the device layer. The method of claim 15, further comprising selectively removing a portion of the device layer. The method of claim 15, further comprising depositing an infrared absorbing layer on a selected portion of the device layer. The method of claim 15, further comprising depositing an infrared absorbing layer on the selected portion of the piezoelectric layer. A microelectromechanical device comprising: a first germanium substrate bonded to a complementary metal oxide semiconductor substrate, the complementary metal oxide semiconductor substrate comprising: an electrode on the complementary metal oxide semiconductor substrate, and electrically contacting a conductive layer on the first germanium substrate; the conductive layer on the first germanium substrate is deposited over the piezoelectric layer of the first germanium substrate; the piezoelectric layer on the first germanium substrate is Deposited on the oxide layer, and the oxide layer is formed on the device layer, the device layer comprising a space formed on the first germanium substrate, wherein the spacer comprises a germanium layer or a hafnium oxide layer; The device layer on the first germanium substrate is bonded to a dielectric layer that is deposited on the surface of the handle layer on the first germanium substrate, the surface comprising a cavity.