TWI610414B - Ic substrate, packaging structure of the ic substrate and manufacturing same - Google Patents

Abstract

A method for fabricating an IC carrier board includes the steps of: providing a first carrier substrate; Pressing a substrate on the carrier substrate, the substrate comprising opposite upper and lower surfaces, the upper surface being attached to the first carrier substrate, and at least one first blind hole is formed in the lower surface; Forming a first conductive circuit layer on the lower surface and forming the conductive hole in the at least one first blind via; removing the first carrier substrate on the substrate to expose the upper surface; on the upper surface Opening at least one second blind hole corresponding to a position of the conductive hole formed by the at least one first blind hole; forming a second conductive circuit layer on the upper surface and At least one second blind hole is formed to form a conductive hole.

Description

IC carrier board, package structure having the same, and manufacturing method thereof

The present invention relates to an IC carrier board, a method of manufacturing the IC carrier board, and a package structure having the IC carrier board and a method of fabricating the same.

With the increasing development of wafer technology, IC carrier boards are gradually moving toward a thin and light direction. However, the thin plate is prone to cause abnormal phenomena such as breakage and bending during the manufacturing process, and the same problem occurs in the packaging process, resulting in serious loss of yield.

In view of the above, it is necessary to provide an IC carrier board that overcomes the above problems, a package structure having the IC carrier board, and a method of fabricating the same.

A method for fabricating an IC carrier board includes the steps of: providing a first carrier substrate; pressing a substrate on the first carrier substrate, the substrate comprising opposite upper and lower surfaces, the upper surface and the The first carrier substrate is attached to each other, and at least one first blind hole is formed on the lower surface; a first conductive circuit layer is formed on the lower surface; and the at least one first blind hole is formed into a conductive hole; The first carrier substrate on the substrate exposing the upper surface; opening at least one second blind hole on the upper surface, the at least one second blind hole and the at least one first blind The positions of the conductive holes formed by the holes are corresponding to each other; the second conductive circuit layer is formed on the upper surface and the conductive holes are formed by forming the at least one second blind hole.

A manufacturing method of a package structure includes the steps of: providing an electronic component, a solder ball, and an IC carrier board fabricated by the above manufacturing method; fixing the electronic component on the IC carrier board; electrically connecting the electronic component Go to the IC carrier board.

An IC carrier board includes a first solder resist layer, a first conductive circuit layer, a substrate, a second conductive wiring layer, and a second solder resist layer that are sequentially contacted. A first conductive hole and a second conductive hole corresponding to each other are formed on the substrate, and the second conductive hole is electrically connected to the first conductive hole. The first conductive circuit layer and the second conductive circuit layer are electrically connected by the first conductive via and the second conductive via. The second carrier substrate is in contact with the first solder resist layer and the first conductive trace layer.

A package structure includes electronic components and an IC carrier as described above. The electronic component is fixed on the IC carrier and electrically connected to the IC carrier.

The IC carrier board provided by the invention is fabricated by matching the first carrier substrate and the second carrier substrate, thereby avoiding problems such as breakage and bending in the process. And the ultra-thin board can be made using the previous IC carrier production equipment without additional investment equipment. In addition, the package structure is fabricated by removing the second carrier substrate after the chip package, which reduces the probability of the IC carrier 100 appearing to be bent.

10‧‧‧Package structure

100‧‧‧IC carrier board

110‧‧‧First carrier substrate

112‧‧‧First copper foil layer

114‧‧‧First basal layer

116‧‧‧Second copper foil layer

120‧‧‧Substrate

122‧‧‧ upper surface

1220‧‧‧ first blind hole

1225‧‧‧First conductive hole

124‧‧‧ lower surface

1240‧‧‧ second blind hole

1245‧‧‧Second conductive hole

130‧‧‧First seed layer

140, 240‧‧‧ patterned dry film

150‧‧‧First plating

160‧‧‧First conductive circuit layer

165‧‧‧ solder pads

170‧‧‧First solder mask

200‧‧‧IC substrate

210‧‧‧Second carrier substrate

212‧‧‧Second basal layer

2122‧‧‧ first surface

2124‧‧‧ second surface

214‧‧‧ Third copper foil layer

230‧‧‧Second seed layer

250‧‧‧Second plating

260‧‧‧Second conductive circuit layer

265‧‧‧Contact pads

270‧‧‧Second solder mask

300‧‧‧ wafer

400‧‧‧ underfill

500, 600‧‧‧ solder balls

1 is a cross-sectional view of a first carrier substrate provided by an embodiment of the present invention.

2 is a cross-sectional view of a press-bonded substrate on the first copper foil layer of FIG. 1.

Figure 3 is a cross-sectional view of the substrate after the first blind via is formed in Figure 2.

4 is a cross-sectional view showing the first seed layer formed on the lower surface of the substrate of FIG. 3.

Figure 5 is a cross-sectional view of the first seed layer shown in Figure 4 after patterning the dry film, exposure and development steps by stamping.

Figure 6 is a cross-sectional view showing the first conductive wiring layer formed on the first seed layer shown in Figure 5.

Fig. 7 is a cross-sectional view showing the formation of a first solder resist layer on the first conductive wiring layer shown in Fig. 6.

8 is a view showing that after the first copper foil layer shown in FIG. 7 is separated from the first carrier substrate, the second carrier substrate is pressed on the first solder resist layer and the pad, and the second blind hole is formed on the upper surface of the substrate. Cutaway view.

Figure 9 is a cross-sectional view showing the substrate shown in Figure 8 after the second seed layer is formed on the second blind via wall and the upper surface.

Figure 10 is a cross-sectional view showing the second seed layer shown in Figure 9 after a cross-sectional view of the patterned dry film, exposure and development steps.

Figure 11 is a cross-sectional view showing the second conductive wiring layer formed on the second seed layer shown in Figure 10.

Figure 12 is a cross-sectional view showing the removal of the second solder resist layer formed on the second conductive wiring layer shown in Figure 11 to form a second solder resist layer.

Figure 13 is a cross-sectional view showing a package structure obtained by mounting a wafer in the IC carrier shown in Figure 12 .

Figure 14 is a cross-sectional view showing the package structure shown in Figure 13 after the cross-sectional view of the package structure is detached from the second carrier substrate, and the solder balls are implanted on the pads.

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

The invention provides an IC carrier board 100 and a manufacturing method of the package structure 10 having the IC carrier board. The specific steps are as follows:

In the first step, referring to FIG. 1, a first carrier substrate 110 is provided.

The first carrier substrate 110 includes a first copper foil layer 112 , a first base layer 114 , and a second copper foil layer 116 . The first copper foil layer 112 and the second copper foil layer 116 are respectively adhered to opposite sides of the first base layer 114.

In the second step, referring to FIG. 2, a substrate 120 is provided and the substrate 120 is pressed against the first carrier substrate 110. The substrate 120 is a glass-free substrate (excluding a fiberglass cloth), and is made of Ajinomoto Build-up Film ABF (Ajinomoto Build-up Film) material, and has a thickness of 15-30 um, which is favorable for making fine lines. The substrate 120 includes opposing upper and lower surfaces 122, 124. The substrate 120 is press-bonded onto the first copper foil layer 112, and the upper surface 122 is attached to the first copper foil layer 112.

In the third step, referring to FIG. 3 and FIG. 4, a plurality of first blind holes 1220 are formed on the lower surface 124, and a first crystal is formed on the lower surface 124 and the wall of the plurality of first blind holes 1220. Layer 130.

The plurality of first blind vias 1220 are formed by laser ablation. The plurality of first blind holes 1220 extend through the substrate 120. The first seed layer 130 is formed by electrolessly depositing copper. The thickness of the first seed layer 130 is about 0.5 um.

In the fourth step, referring to FIG. 5, the patterned dry film 140 is pasted on the first seed layer 130. The patterned dry film 140 is formed into a dry film pattern by an exposure and development process.

In the fifth step, referring to FIG. 5 and FIG. 6, the first seed layer 130 formed with the dry film pattern is plated with copper, and the first plating layer is formed on a portion of the first seed layer 130. 150. At the same time, copper plating is formed in the plurality of first blind vias 1220 to form a first conductive via 1225. After the plating is completed, a film removing process is performed to remove the patterned dry film attached to the first seed layer 130. 140. And quickly etching away the first seed layer 130 not covered by the first plating layer 150, so that the remaining first seed layer 130 and the first plating layer 150 together form a first conductive line Layer 160.

In the sixth step, referring to FIG. 7, the surface of the first conductive circuit layer 160 is subjected to a solder resist process to form a first solder resist layer 170. A portion of the first conductive wiring layer 160 is exposed in the first solder resist layer 170 to form a plurality of pads 165. A surface treatment is performed on the plurality of pads 165 to prevent surface oxidation of the pad 165, thereby affecting electrical characteristics thereof. The surface treatment may be performed by forming a protective layer (not shown) by means of electroless gold plating, electroless nickel plating, or the like, or forming an organic solder resist (OSP) (not shown) on the pad 165.

And rapidly etching the surface of the first conductive circuit layer 160 before forming the first solder resist layer 170, so that the first conductive circuit layer 160 presents a rough microstructure to facilitate the first conductive line. The surface of layer 160 is solder resisted and surface treated.

In the seventh step, referring to FIG. 7 and FIG. 8 , the second carrier substrate 210 is pressed onto the first solder resist layer 170 and the pad 165 of the first conductive circuit layer 160 . The second carrier substrate 210 may be a copper foil substrate, a resin substrate, a plastic substrate, or a supporting substrate made of a glass fiber material. In the embodiment, the second carrier substrate 210 is a copper foil substrate.

The second carrier substrate 210 includes a second substrate layer 212 and a third copper foil layer 214. The second substrate layer 212 includes a first surface 2122 and a second surface 2124 opposite to each other. The third copper foil layer 214 is formed on the second surface 2124. The first surface 2122 is a pressing surface of the second carrier substrate 210. The first carrier substrate 110 on the substrate 120 is removed to expose the upper surface 122.

In an eighth step, referring to FIG. 9 , the first conductive via 1225 is quickly etched such that a portion of the copper plating layer in the first conductive via 1225 is etched away, thereby facing away from the upper surface 122 . A plurality of second blind holes 1240 are formed in the direction. Thereafter, a second seed layer 230 is formed on the upper surface 122 and the wall of the plurality of second blind holes 1240.

The plurality of second blind holes 1240 correspond to the positions of the plurality of first conductive holes 1225. The plurality of second blind vias 1240 do not extend through the plurality of first conductive vias 1225. The second seed layer 230 is formed by electroless copper plating. The thickness of the second seed layer 230 is about 0.5 um.

In a ninth step, referring to FIG. 10, a patterned dry film 240 is attached to the second seed layer 230. The patterned dry film 240 is formed into a dry film pattern by an exposure and development process.

In the tenth step, referring to FIG. 10 and FIG. 11, the second seed layer 230 formed with the dry film pattern is plated with copper, and the second plating layer 250 is formed on the second seed layer 230. . At the same time, copper plating is formed in the plurality of second blind holes 1240 to form a second conductive hole 1245. The second conductive via 1245 is electrically connected to the first conductive via 1225. After the plating is completed, a film removing treatment is performed to remove the patterned dry film 240 attached to the second seed layer 230. And rapidly etching away the second seed layer 230 not covered by the second plating layer 250, so that the remaining second seed layer 230 and the second plating layer 250 together form a second conductive line Layer 260.

In the eleventh step, referring to FIG. 12, the surface of the second conductive circuit layer 260 is solder-proofed to form a second solder resist layer 270, and the IC carrier 100 is obtained. A part of the second conductive circuit layer 260 is exposed in the second solder resist layer 270 to form a plurality of contact pads 265. Surface treatment is performed on the plurality of contact pads 265 to avoid surface oxidation of the contact pads 265, thereby affecting electrical characteristics. The surface treatment may be formed by a chemical plating, an electroless nickel plating or the like to form a protective layer (not shown), or an organic solder resist (OSP) (not shown) may be formed on the contact pad 265.

The surface of the second conductive circuit layer 260 is also quickly etched before the second solder resist layer 270 is formed, so that the second conductive circuit layer 260 exhibits a rough microstructure to facilitate the second conductive line. The surface of layer 260 is solder masked and surface treated.

The IC carrier 100 includes a second carrier substrate 210 and an IC substrate 200 carried on the second carrier substrate 210.

In a twelfth step, referring to FIG. 13, the electronic component is soldered on the IC carrier 100 to obtain a package structure 10. In the embodiment, the electronic component is the wafer 300.

Referring to FIG. 13 , the technical solution further provides a package structure 10 including an IC carrier 100, a wafer 300 and a solder ball 500 obtained by the above method.

The wafer 300 and the plurality of contact pads 265 are electrically connected by the solder balls 500 to electrically connect the wafers 300 to the IC carrier 100. The wafer 300 and the IC carrier are fixed by an underfill 400.

The IC carrier 100 includes a second carrier substrate 210 and an IC substrate 200. The second carrier substrate 210 includes a second substrate layer 212 and a third copper foil layer 214. The IC substrate 200 is located on the second carrier substrate 210. The IC substrate 200 includes a first solder resist layer 170, a first conductive circuit layer 160, a substrate 120, a second conductive circuit layer 260, and a first contact layer. Two solder mask layer 270. The substrate 120 is made of an ABF material. A first conductive hole 1225 and a second conductive hole 1245 corresponding to each other are formed on the substrate 120. The second conductive via 1245 is electrically connected to the first conductive via 1225. The first conductive circuit layer 160 and the second conductive circuit layer 260 are electrically connected by the first conductive via 1225 and the second conductive via 1245. The second base layer 212 of the second carrier substrate 210 is in contact with the first solder resist layer 170 and the first conductive trace layer 160. A portion of the second conductive wiring layer 260 is exposed to the second solder resist layer 270 to form a contact pad 265. The contact pad 265 is electrically connected to the wafer 300.

Referring to FIG. 13 and FIG. 14 , the package structure 10 and the manufacturing method provided by the technical solution may further include removing the second carrier substrate 210 , forming the solder ball 600 on the pad 165 and The solder ball 600 is electrically connected to the electrical component or the package, thereby obtaining the package structure 10 without the second carrier substrate 210.

The IC carrier board 100 provided by the present invention is completed by being matched with the first carrier substrate 110 and the second carrier substrate 210, thereby avoiding problems such as breakage and bending during the process. And the ultra-thin board can be made using the previous IC carrier production equipment without additional investment equipment. In addition, the package structure 10 is fabricated by removing the second carrier substrate 210 after the wafer 300 is packaged, which reduces the probability of the IC carrier 100 being bent.

It is to be understood that a person skilled in the art can make various other changes and modifications in accordance with the technical concept of the present invention, and all such changes and modifications are intended to fall within the scope of the present invention.

10‧‧‧Package structure

100‧‧‧IC carrier board

120‧‧‧Substrate

1225‧‧‧First conductive hole

1245‧‧‧Second conductive hole

160‧‧‧First conductive circuit layer

170‧‧‧First solder mask

200‧‧‧IC substrate

210‧‧‧Second carrier substrate

212‧‧‧Second basal layer

214‧‧‧ Third copper foil layer

260‧‧‧Second conductive circuit layer

265‧‧‧Contact pads

270‧‧‧Second solder mask

300‧‧‧ wafer

400‧‧‧ underfill

500‧‧‧ solder balls

Claims (9)

A method for fabricating an IC carrier board includes the steps of: providing a first carrier substrate, wherein the first carrier substrate comprises a first copper foil layer, a first substrate layer and a second copper foil layer, and the first copper foil layer Forming a second copper foil layer on opposite sides of the base layer; pressing the substrate on the first carrier substrate, the substrate including opposite upper and lower surfaces, the upper surface and the The first carrier substrate is attached to each other, and at least one first blind hole is formed on the lower surface; a first conductive circuit layer is formed on the lower surface; and the at least one first blind hole is formed into a conductive hole; The first carrier substrate on the substrate exposing the upper surface; opening at least one second blind hole on the upper surface, and electrically forming the at least one second blind hole and the at least one first blind hole The positions of the holes correspond; forming a second conductive circuit layer on the upper surface and forming the conductive holes in the at least one second blind hole. The method for fabricating an IC carrier board according to claim 1, wherein after the step of forming the first conductive wiring layer on the lower surface and forming the conductive via in the at least one first blind via, removing the substrate The first carrier substrate, before the step of exposing the upper surface, further includes the step of: pressing the second carrier substrate on the first conductive circuit layer. The method of fabricating an IC carrier board according to claim 2, wherein the second carrier substrate comprises a second substrate layer and a third copper foil layer. The method for fabricating an IC carrier board according to claim 2, wherein the second carrier substrate is made of any one of glass fiber, resin and plastic. The method of fabricating an IC carrier board according to claim 1, wherein the at least one first blind hole corresponds to a position of the at least one second blind hole, the first conductive hole and the second conductive The hole phase is turned on. A manufacturing method of a package structure, comprising the steps of: providing an electronic component and a solder ball, and manufacturing an IC carrier board by using the manufacturing method according to any one of claims 1 to 5; fixing the electronic component to the IC a board; electrically connecting the electronic component to the IC carrier board. An IC carrier board comprising a first solder resist layer, a first conductive circuit layer, a substrate, a second conductive circuit layer, a second solder resist layer and a second carrier substrate which are sequentially contacted, and a position is formed on the substrate Corresponding first conductive holes and second conductive holes, the second conductive holes are electrically connected to the first conductive holes, and the first conductive circuit layer and the second conductive circuit layer are The first conductive via and the second conductive via are electrically connected, and the second carrier substrate is in contact with the first solder resist layer and the first conductive trace layer. The IC carrier board according to claim 7, wherein a portion of the second conductive circuit layer is exposed in the second solder resist layer to form a contact pad, and the contact pad is electrically connected to the electronic component, and the portion is A conductive wiring layer is exposed in the first solder resist layer to form a solder pad for connecting to an external circuit. A package structure comprising an electronic component and an IC carrier board according to any one of claims 7-8, wherein the electronic component is fixed on the IC carrier board and electrically connected to the IC carrier board.